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Riscv Isa

The document provides an overview of RISC-V architecture, detailing its operands, including 32 registers and memory access methods. It also outlines various RISC-V assembly language instructions categorized into arithmetic, data transfer, logical operations, and branching. Each instruction is accompanied by examples and comments explaining their functionality and usage.

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7 views1 page

Riscv Isa

The document provides an overview of RISC-V architecture, detailing its operands, including 32 registers and memory access methods. It also outlines various RISC-V assembly language instructions categorized into arithmetic, data transfer, logical operations, and branching. Each instruction is accompanied by examples and comments explaining their functionality and usage.

Uploaded by

अखिलेश यादव
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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RISC-V operands

Name Example Comments


Fast locations for data. In RISCV, data must be in registers to perform arithmetic.
32 registers x0-x31 Register x0 always equals 0.

ACCessed only by data


30 memory Memory[0J, Memoryl4), ... Oniy oy data ranster instructions. RISCV uses byte addresses, so
words Memory[4,294,967,292] sequential word accesses differ by 4. Memory holds data structures, arrays,
and spilled registers.

RISC-V assembly language


Category Instruction Example Meaning Comments
Add add x5, x6, x7 X5 = x6 + x7 Three register operands; add
|Arithmetic Subtract sub x5, x6. x7 x5 = x6 x7 | Three register operands; subtract
x6 + 20
Add immediate addi x5, x6. 20 x5 |Used to add constants
Load word lw x5, 40(x6) X5 Memory[x6 + 40] Word from memory to register
Load word, unsigned Iwu x5. 40(x6) x5 - Memory[x6 + 40] Unsigned word frorn memory to register
Store word SW X5, 40(x6) Memory[x6 + 40]- x5 Word from register to memory
Load halfword lh x5. 40(x6) x5 = Memory [x6 + 40] Halfword from memory to register
Load halfword, lhu x5, 40(x6) X5Memory[x6 + 40] Unsigned halfword from memory
Data transfer unsigned to register
Store halfword sh x5, 40(x6) Memory[x6 + 40]- x5 Halfword from register to memory
Load byte lb x5, 40(x6) X5- Memory[x6 + 40] Byte from memory to register
Load byte, unsigned l bu x5, 40(x6) x5 Memory [x6 + 40] Byte unsigned from memory to register
Store byte sb x5, 40(x6) Memory[x6 + 40] - x5 Byte from register to memory
Load reserved Ir.d x5, (x6) x5Memory Lx6]J Load; 1st half of atonic swap
Store conditional sc.d x7, x5, (x6) Memory [x6] = x5: x7 = 0/1 Store; 2nd half of atomic swap
Load upper lui x5, 0x12345 X5 0x12345000 Loads 20-bit constant shifted left
immediate 12 bits
And and x5, x6. x7 X 5 X 6 & x7
Three reg. operands; bit-by-bit AND
Inclusive or or x5, x6, X8 X5 - X6 X8 Three reg. operands; bit-by-bit OR
Exclusive or xor x5. x6. x9 X5 x6 ^ x9 Three reg. operands; bitby bit XOR
Logical andi x5, x6. 20
And immediate x5 x6 & 20 Bit-bybit AND reg. with constant
Inclusive or immediate ori x5, x6, 20 x5- x6 | 20 Bit-by-bit OR reg. with constant
Exclusive or immediate Xori x5, x6, 20 X5 x6 ^ 20 Bit-by bit XOR reg. with constant
Shift left logical sll x5, x6, x7 X5 X6 << x7 Shift left by register
Shift right logical Srl x5, x6, x7 X5x6 >> x7 Shift right by register
Shift right arithmetic sra x5, x6, x7 x5 X6 >> x7 Arithmetic shift right by register
Shift left logical s111 x5, x6, 3 X5 X6 << 3 Shift left by immediate
Shift immediate
Shift right logical srli x5, x6, 3 x5 = x6 >> 3 | Shift right by immediate
immediate

Shift right arithmetic Srai x5, x6, 3 X5= x6 >> 3 Arithmetic shift right by immediate
immediate

Branch if equal beq x5, x6, 100 if (x5X6) go to PC+100 PC-relative branch if registers equal
Branch if not equal bne x5. x6. 100 |if (x5 !- x6) go to PC+100PC-relative branch if registers not equal
Branch if less than blt x5, x6. 100 |if (x5 < x6) go to PC+100 |PC-relative branch if registers less
Branch if greater or bge x5. x6, 100 1f (x5 = x6) go to PC+100 PC-relative branch if registers greater
Conditionalequal or equal
branch Branch if less, unsigned bltu x5, x6. 00 1f (x5 < x6) go to PC+100 PC-relative branch if registers less,
unsigned
Branch if greater or bgeu x5, x6 100 if (x5 = x6) go to PC+100 PC-relative branch if registers greater
equal, unsigned or equal, unsigned
Unconditionall Junp and link | Jal xl. 100 x1 PC+4: go to PC+100 PC-relative procedure call
branch Junp and link register |jalr xl, 100(x5)x1 - PC+4: go to x5+100 Procedure retum; indirect calI

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