HPC Questions

Module-2 MIPS ORGANIZATION,PIPELINE HAZARDS

1. MIPS instruction set follows register, immediate and relative addressing modes. How
direct addressing mode can be realized by MIPS? Explain with example.
2. Explain the use of NPC and LMD register in MIPS architecture.
3. Explain the R, I and J MIPS instruction format with one example from each type.
4. Enlist any two addressing modes that the MIPS instruction set follows. Explain with
example.
5. ”Fixed length encoding in MIPS simplifies instruction decoding”, Justify it by taking the
example of load and store instruction
6. Discuss the characteristics of MIPS instruction set architecture that makes MIPS
suitable for RISC.
7. Discuss the MIPS pipeline stages with the help of data path.
8. Derive the expression for pipeline speed up, efficiency and throughput.
9. Prove that how the throughput in a pipelined processor increases than the non pipelined
processor with example.
10. A 5 stage pipeline separated by a 10ns clock. If the non pipeline clock is also having
same duration and the pipeline efficiency is 90%, then calculate the speed up factor.
11. How Havard architecture is used to prevent structural hazard in a pipelined processor?
Explain with example.
12. Consider a 4 stage pipeline processor . The no of cycles needed by 4 instructions
I1,I2,I3 and I4 in segments S1,S2 , S3 and S3 is given below

S1 S1 S1 S1

I1 2 1 1 1
I2 1 3 2 2

What is the no. for cycles needed to execute the following loop ignoring loop control
instructions
For ( i=1 to 2)
I1; I2;I3;I4;
13. What is structural hazard? Explain the techniques to resolve the structural hazard.
14. How Havard architecture is used to prevent structural hazard in a pipelined processor?
Explain with example.
15. Assume a pipelined processor has single shared memory for data and instruction.What
type of hazard this may lead to and why?
16. State a situation when there may be resource hazard between IF and MEM segment of
pipeline.
17. Discuss different techniques to overcome data hazard.
18. Explain the operation of each MIPS pipeline line segments while executing the following
instructions stored at memory location 1000 and 2000 respectively
i. LD R1, 30(R2)
ii. SD R3,40(R4)
19. Assume a pipeline processor has shared a single memory pipeline for data and
instruction. What type of hazard it may leads to:
A) Structural Hazard
B) Data Hazard
C) Control Hazard
D) Instruction Hazard
20. Processor A supports X type of instruction set and processor B supports Y type of
instruction set. It has been observed that to do a task machine A uses 5 stage pipeline and B
uses 7 stage pipeline . If the clock rate of A is 2 times faster than B. Ideal CPI of both the
machines supporting pipeline is 1. Find out which machine is faster?
21. Consider the execution of a program of 15000 instructions by a pipeline processor with a
clock rate of 25MHz. Assume that the instruction pipeline has 5 stages and that one
instruction is issued per clock cycle. What are the efficiency and throughput of this pipelined
processor?
22. A 4 stage pipeline has stage delays as 150, 120, 160,140 ns respectively. There is a latch
delay of 5ns each. Assuming constant clock rate, the total time taken to process 1000 data
items on this pipeline will be
A) 120.5 µs
B) 160.5 µs
C) 165.5 µs
D) 190 µs
23. A 4 stage pipeline has stage delays as 300, 240, 320,280 ns respectively. There is a latch
delay of 10 ns each. Assuming constant clock rate, the total time taken to process 1000 data
items on this pipeline will be
A)241.5 µs
B)331 µs
C)298 µs
D)340 µs
24. A 4 stage pipeline has stage delays as 150, 120, 160,140 ns respectively. There is a latch
delay of 5ns each. What is the speedup ratio?
A) 3.45
B) 4.25
C) 2.8
D) 4.5
25.
A 4 stage pipeline has stage delays as 300, 240, 320,280 ns respectively. There is a
latch delay of 10 ns each.What is the speedup ratio?
A) 3.45
B) 4.25
C) 2.8
D) 4.5
26. A 4 stage pipeline has stage delays as 300, 240, 320,280 ns respectively. There is a
latch delay of 10 ns each. Assuming constant clock rate, the total time taken to process
1000 data items on this pipeline will be
A)241.5 µs
B)331 µs
C)298 µs
D)340 µs
27.
A 7stage pipeline separated by a clock 6ns along with a latch delay of 1ns.If the non-
pipeline clock is also having the same duration and the pipeline efficiency is 50%
then calculate the speed up factor.

A) 2
B) 4
C) 6
D) 3
28. We have 2 designs D1 and D2 for a pipeline processor. D1 has 6 stage pipeline with
execution time of 6 ns, 5 ns, 4 ns, 7 ns and 3 ns. While the design D2 has 8 pipeline
stages each with 5 ns execution time. How much time can be saved using design D2
over design D1 for executing 100 instructions?
(A) 300 ns
(B) 270 ns
(C) 200 ns
(D)340 ns
29. A 7 stage pipeline separated by a clock 6ns along with a latch delay of 1ns. If the non-
pipeline clock is also having the same duration and the pipeline efficiency is 50% then
calculate the speed up factor.
(A) 2
(B) 4
(C) 6
(D) 3
30.
We have 2 designs D1 and D2 for a pipeline processor. D1 has 5 stage pipelines with
execution time of 3 ns, 2 ns, 4 ns, 2 ns and 3 ns. While the design D2 has 8 pipeline stages
each with 2 ns execution time. How much time can be saved using design D2 over design D1
for executing 100 instructions?(hints: assume latch delay time is 0).
A.214 ns
B .202 ns
C. 86 ns
D. 200 ns
31. Consider an instruction pipeline with 5 stages that take 7 nsec, 4nsc, 3 nsec, 8 nsec,
and 5 nsec respectively. The delay of an inter-stage register stage of the pipeline is 2 nsec.
What is the approximate speedup of the pipeline in the steady state under ideal conditions as
compared to the corresponding non-pipelined implementation?
(A) 2.7
(B) 3.5
(C) 2.5
(D) 3.7
32. Consider the following sequence of instructions:
Add R3, R2, R1
Mul R5, R4, #3
Sub R5, R2, R3
Add R5, R2, #20
Show the content of different stages at different clock pulses in a 4 stage pipelined processor,
by considering the Space Time diagram. Show the content of inter-stage buffers from clock
pulse 3 to 7. The contents of registers R1, R2 and R4 are 50, 75 and 90 respectively.

33. Find out the total number of clock cycles required to execute the following instructions
without and with operand forwarding?
LD R1, 10(R2)
LD R1,10(R3)
DSUB R5,R1,#20
SD R5, 0(R2)
DADDIU R2,R3,#4
DSUB R5,R3,R2
34. A five stage pipeline processor has IF, ID, EXE, MEM, WB. The IF, ID, WB stages
takes 1 clock cycles each for any instruction. The execution of different instructions takes
more than ideal time as given:- 3 clock cycle for an ADD instruction, 2 clock cycles for SUB
instruction, 3 clock cycles for MUL instructions, 3 clock cycles for DIV instructions and 1
clock cycles for LOAD instruction respectively.

Consider the following instructions:-

ADD R2, R3, R4
LOAD R4, (02)R1
SUB R6, R4, R2
LOAD R4, (02)R6
ADD R1, R6, R4
MUL R1, R1, R4

For the above sequence of instructions draw time and space diagram in order to find
out total number of clock cycles required to complete their execution without using
operand forwarding?

35. A five stage pipeline processor has IF, ID, EXE, MEM, WB. The IF, ID, WB stages
takes 1 clock cycles each for any instruction. The execution of different instructions
takes more than ideal time as given:- 2 clock cycle for an ADD instruction, 2 clock
cycles for SUB instruction, 4 clock cycles for MUL instructions, 4 clock cycles for DIV
instructions and 2 clock cycles for LOAD instruction respectively.

Consider the following instructions:-

SUB R1, R2, R4
LOAD R2, (02)R1
ADD R7, R1, R2
LOAD R4, (02)R7
DIV R1, R7, R4
MUL R1, R7, R4
For the above sequence of instructions draw time and spacediagram in order to find
out total number of clock cycles required to complete their execution using operand
forwarding

36.
Find out the total no of clock cycles required to execute the following instructions
without and with operand forwarding?
LD R1, 0(R2)
LD R1, 0(R3)
DADDIU R1,R1,#1
SD R1, 0(R2)
DADDIU R2,R2,#4
DSUB R4,R3,R2

37. Consider the following MIPS instructions:-

LD R1, 09(R10)
LD R2,10(R9)
DADD R3,R1,R2
SD R3,08(R8)
LD R4,11(R7)
OR R5,R4,R6
SD R5,12(R11)
For the above sequence, find out total number of clock cycles required to complete the
execution . And also find total no cycles required if operand forwarding is used.

38. Consider the following high level statements

a=a+1;
c=a+b;
Write down the necessary MIPS code. Find out the no of clock cycles required to execute
without and with operand forwarding techniques and also with rescheduling.

39. Consider the following MIPS instructions:-

LD R1, 09(R10)
LD R2,10(R9)
DADD R3,R1,R2
SD R3,08(R8)
LD R4,11(R7)
OR R5,R4,R6
SD R5,12(R11)
For the above sequence, find out total number of clock cycles required to complete the
execution . And also find total no cycles required if operand forwarding is used.

40. Consider an unpipelined processor takes 4 cycles for ALU and other operations and 5
cycles for memory operations. Assume the relative operation frequencies like ALU and
other operations are 60% and memory operations 40%.Ignore the effect of branching
operations. If the cycle time is 1ns and the pipeline overhead is 0.2ns , then calculate
the speed up due to pipeline.

41. Consider the following MIPS instructions:-

DADD R2,R3,R4
DADD R5,R2,R6
OR R7,R2,R8
AND R9,R2,R6
XOR R8,R2 ,R9
For the above sequence, find out total number of clock cycles required to complete the
execution . And also find total no cycles required if operand forwarding is used.

42.
Consider the following MIPS assembly code.
LD R10, 38(R12)
DSUB R7, Rl0, R5
DADD R8, R10, R6
XOR R9, R5, R10
DMUL R6, R4, R8
Enlist different types of data dependency in the above code.
43.
Consider a 5-stage pipeline and we wish to execute instructions I1,I2,……I17 in
program order. Find out the no of clock cycles required to complete the execution
of those instructions in the following cases
Case-1 : Find out the no of clock cycles required to complete the execution of I1 to
I17.
Case-2 : Find out the no of clock cycles required to complete the execution of I1 to
I17 where I4 is a unconditional branch instruction and I12 is the target
instruction.
Case-3 : Find out the no of clock cycles required to complete the execution of I1 to
I17 where I4 is a conditional branch instruction and I12 is the target instruction.