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 Table of Contents
Before you Begin .......................................................................................................................... 4

Lab2 Configuring Scan Chains/Test Logic ................................................................................... 5

Introduction ................................................................................................................................ 5
Objectives .................................................................................................................................. 5
Exercise 1: Basic Scan Insertion.................................................................................................. 6
Exercise 2: Setting-Up Scan Pins ...............................................................................................17
Exercise 3: Balancing Scan Chains and Multiple Clock Domains .................................................21

Lab Answers ................................................................................................................................24

Lab 2.........................................................................................................................................24

NOTES:.........................................................................................................................................26
 Before you Begin

You will need to:

1. Obtain lab data if you have not already done so.

2. Set environment variables.

Obtaining Lab Data

If the atpg_data directory, with lab subdirectories, is located in the home directory (e.g. cd ~), please
proceed to the lab exercises as you have already set up the lab database on this VM.

If this is the first time you are starting a session for this VM, the atpg_data directory will not be in the
home directory and you will need to download and extract it using the following instructions.

1. Double click on the Desktop icon Download_lab_data, . This launches a web browser.

2. On the resulting web page, select the file named tessent_atpg_data_v2020.1_20200611.tgz,

3. In the resultant window, select the Download button, enable the Save File button, then select the
OK button to download the file.

Move the file in the Downloads directory to the home directory. If you are using the terminal
(Applications>Favorites>Terminal) you can use the following command:

mv ./Downloads/tessent_atpg_data_v2020.1_20200611.tgz .

4. In a terminal window, extract the files from the compressed tar file using the command:

tar xzvf ./tessent_atpg_data_v2020.1_20200611.tgz

You should now have a directory named atpg_data in your $HOME directory. That directory contains all
the files you need to perform the exercises, in this learning path.

Setting Environment Variables

The environment uses bash and is ready to use for the labs with all needed environment variables already
setup.

You are now ready to proceed with lab exercises.

Configuring Scan Chains/Test Logic 4

 Lab2
Configuring Scan Chains/Test Logic

Introduction
The exercises in this lab provide experience using Tessent Scan to insert full scan, create internal scan
chains, balance scan chains with lockup latches, and write out a scan-inserted netlist and ATPG setup
files.

Objectives
Upon completing this lab, you should be able to:

• Insert basic scan into a netlist

• Create dofiles and test procedure files

• Set up new and existing scan pins (internal or external)

• Create, configure, and balance scan chains

Configuring Scan Chains/Test Logic 5

Exercise 1: Basic Scan Insertion
Setup Instructions
1. Log in to your workstation if you are not already logged in.
2. Change to the $ATPG_LABS/Lab2/Exercise1 directory.
shell> cd $ATPG_LABS/Lab2/Exercise1
3. Invoke Tessent Shell to perform scan insertion on the design.
Design: design/ex1_design.v
Library: ../../libs/adk.atpg
Log file: logs/scan.log
shell> tessent –shell –logfile logs/scan.log –replace
Tessent Shell invokes and displays the SETUP> prompt.
Tessent tools have various modes of operation called system modes. Each system mode facilitates
a specific task. The tool is now in SETUP mode, which is the default system mode. In SETUP
mode, you can specify or set up circuit, scan, and tool behavior.
In this lab, default configurations are used to minimize complexity in the tool setup. The primary
goal for this exercise is to familiarize you with the traditional scan insertion and the ATPG flow.
4. Set the correct context and get the design loaded into the tool.
SETUP> set_context dft –scan
SETUP> read_verilog design/ex1_design.v
SETUP> read_cell_library ../../libs/adk.atpg
SETUP> set_current_design

5. Define control signals.

In this exercise, there are no requirements to hold pins at constant values. However, setting pin
constraints is something you often do when setting up control signals.
What command would you use to hold a pin to a constant value?
____________________________________________________________________________
___________________________________

6. Define clocks.
SETUP> analyze_control_signals -auto_fix
The default scan configurations are used for this exercise, so we are finished defining the
design and are ready to go to the next stage, analysis mode, where scan/test circuitry is
identified and inserted.

Configuring Scan Chains/Test Logic 6

 7. Check design rules and go to Analysis mode.
SETUP> check_design_rules

When you exit SETUP mode, DFT tools automatically run DRC. You should not encounter any
DRC failures in this run.

8. Report how many design instances can be made scan cells.

ANALYSIS> report_scan_elements

How many scannable cells are identified?_____________________

9. Set up scan insertion options.

ANALYSIS> set_scan_insertion_options \

-port_index_start_value 1 –single_clock_edge_chains on

ANALYSIS> set_insertion_options \

-module_uniquification_suffix _scan#
Here we indicate to use separate scan chains for different clock edges. Review the Tessent
Shell Reference Manual for the details and options for these two commands.

10. Define a single scan mode and how many chains to create. Then analyze the scan chains that will
be created.
ANALYSIS> add_scan_mode unwrapped –chain_count 1
ANALYSIS> analyze_scan_chains
Create Scan-Inserted Netlist and ATPG Setup Files
11. Perform test synthesis and setup the scan circuitry.
The next step is to insert 1 scan chain into the scan logic.
ANALYSIS> insert_test_logic
A scan-inserted netlist is created. Note that this takes you to the Insertion system mode.

12. Display the results of the process you just performed.

INSERTION> report_test_logic
INSERTION> report_scan_chains
What is the number of sequential instances? ____________________
Number of inserted scan chains? _____________________________
Number of new pins inserted? _______________________________

Configuring Scan Chains/Test Logic 7

 13. View the scan cells and chains you inserted with the Report Scan Cells command.
INSERTION> report_scan_cells

14. Save a Verilog netlist and the ATPG setup files.

INSERTION> write_design -output_file results/ex1_scan.v \
-replace
INSERTION> write_atpg_setup results/ex1_scan -replace
View the files Tessent Scan created in the local results directory:

o ex1_scan.v — Verilog netlist

o ex1_scan.dofile — dofile

o ex1_scan.testproc — test procedure file

o ex1_scan_verify_scan_modes.dofile — verification dofile

The dofile and test procedure file are used with Tessent FastScan ™ to do the design setup before
creating test patterns. If you want to verify the scan insertion that just happened you can set the
system mode to Setup and run the verification dofile like this:
INSERTION> set_system_mode setup
SETUP> dofile results/ex1_scan_verify_scan_modes.dofile

Remember, you do not have to type out the commands in their

entirety. Full commands are used in lab exercises to help you
Note understand which commands are being used. You can use the Tab
key for command completion while typing.

15. Exit Tessent Scan.

ANALYSIS> exit -d

Configuring Scan Chains/Test Logic 8

Exercise 2: Setting-Up Scan Pins
In this exercise you use Tessent Scan to:

• Insert full-scan test circuitry into your design

• Connect existing internal pins as scan inputs and outputs for scan chains

• Create an internal scan chain

• Write a scan-inserted netlist file and ATPG setup files

• Set up new and existing scan pins (internal and external) and insert test logic as shown in Figure 2-
1.

Figure 2-1. Test Logic Example

Setup Instructions
1. Log in to your workstation if you are not already logged in.

2. Change to the $ATPG_LABS/Lab2/Exercise2 directory.

shell> cd $ATPG_LABS/Lab2/Exercise2

Invoke Tessent Scan and Define the Design

3. Invoke Tessent Shell to perform scan insertion on the design.
Design: design/ex2_design.v
Library: ../../libs/adk.atpg
 Logfile: logs/ex2.log
shell> tessent –shell –logfile logs/ex2.log –replace

4. Set the correct context and get the design loaded into the tool.
SETUP> set_context dft –scan
SETUP> read_verilog design/ex2_design.v
SETUP> read_cell_library ../../libs/adk.atpg
SETUP> set_current_design

5. Define the control signals automatically using the command analyze_control_signals -

auto_fix:
shell> analyze_control_signals -auto_fix

6. Check design rules and go to Analysis mode.

SETUP> check_design_rules

Setup/Run Test Synthesis

Looking at the diagram in Figure 2-1, set the scan insertion options to create 2 scan chains and connect
them to the pins shown.

7. Set up scan insertion options.

ANALYSIS> set_scan_insertion_options \
-port_index_start_value 1 –si_timing any_edge \
-so_timing any_edge –single_clock_edge_chains on \
-single_clock_domain_chains on
ANALYSIS> set_insertion_options \
-module_uniquification_suffix _scan#

8. Define a single scan mode and how many chains to create. Also, specify which design pins to
connect to the scan inputs and outputs. Then analyze the scan chains that will be created.
ANALYSIS> add_scan_mode unwrapped –chain_count 2 \
-si_connections {{/d[10]} {/d[0]}} \
-so_connections {{/q[15]} {/q[0]}}
ANALYSIS> analyze_scan_chains

9. After you have defined the scan chains, the next step is to insert them into the design.
ANALYSIS> insert_test_logic
A scan-inserted netlist is created. Note that this takes you to the Insertion system mode.

Configuring Scan Chains/Test Logic 18

 10. Display the results of the process you just performed.
INSERTION> report_test_logic
INSERTION> report_scan_chains
Number of inserted scan chains? _____________________________
Number of additional gates inserted? __________________________

11. View the scan cells and chains you inserted with the Report Scan Cells command.
INSERTION> report_scan_cells
Why are there only 2 cells in scan chain 2?
____________________________________________________________________________
____________________________________________________________________________
_____

Save the Netlist and ATPG Setup Files

12. Save a new netlist in Verilog format to the file results/ex2_scan.v.
INSERTION> write_design -output_file results/ex2_scan.v –replace

13. Save a test procedure ATPG setup file with a base name of results/ex2_scan (no file
extension)
INSERTION > write_atpg_setup results/ex2_scan -replace
The following files are created:
o ex2_scan.v — Verilog netlist
o ex2_scan.dofile — dofile
o ex2_scan.testproc — test procedure file
o ex2_scan_verify_scan_modes.dofile — verification dofile

14. Exit from Tessent Scan.

INSERTION> exit –d

You have created a scan inserted netlist. The next stage is to generate the test patterns that are
used with the netlist (which you do not do for this exercise.)

Option to Save the Completed Files to the Tessent Shell Data Base
The traditional method of using Tessent Scan that you have just used in this lab exercise has the user
specify the file names and locations of the completed files that are written to disk. In this exercise files
were written into the ./results directory. There is a newer option starting with tool version 2016.4 where you
can specify to use the TSDB, or Tessent Shell Data Base structure, to store and use the files. The TSDB
details are found in a chapter of the Tessent Shell Reference Manual.

Configuring Scan Chains/Test Logic 19

Compare the two dofiles named insert_scan.do and insert_scan_tsdb.do in the solutions directory. With
the TSDB method dofile you’ll notice two differences:

o The design level needs to be set with the set_design_level command

o The insert_test_logic command uses the option –write_in_tsdb on

This second command and option inserts the test logic and automatically creates the TSDB directory and
writes the files into it. If you are interested, invoke Tessent Shell and execute the dofile
./solutions/insert_scan_tsdb.do, then examine the results in the tool created directory
tsdb_outdir/dft_inserted_designs/counter16_gate.dft_inserted_design. You’ll see it contains the scan
inserted netlist file, a scan definition file (.scandef), and the tcd file that can be used for the ATPG pattern
creation setup. The tcd file does what the scan dofile and testproc file do in the traditional method when
used with Tessent FastScan to define the clocks and scan logic.

Configuring Scan Chains/Test Logic 20

Exercise 3: Balancing Scan Chains and Multiple Clock
Domains
This version of the design has multiple clock domains and a requirement to balance the chains so test
pattern generation and application is more efficient. In order to avoid skew issues during shift, a lockup
latch needs to be inserted between the scan cells where the clock domains cross.

Figure 2-2. Test Logic Example – Balanced Chains

Note: This is not a complete post-insertion diagram. Similar to what you saw in exercise 2, there will be
muxes inserted at the scan_out of both chains in this version of the design.

Setup Design, and Add Clocks

1. Change directory into $ATPG_LABS/Lab2/Exercise3
shell> cd $ATPG_LABS/Lab2/Exercise3

2. Invoke Tessent Shell and set the context for scan insertion.

shell> tessent -shell -logfile results/ex3.log -replace

SETUP> set_context dft -scan

3. Read Verilog netlist, ATPG cell library and set design level you are working on. Get the clocks
defined.

SETUP> read_verilog design/ex3_design.v

Configuring Scan Chains/Test Logic 21

 SETUP> read_cell_library ../../libs/adk.atpg
SETUP> set_current_design
SETUP> analyze_control_signals –auto_fix

Define Latch to Use for Lockup

The APTG library does not have a predefined cell to use as a lockup latch. So you will identify the latch
and inverter that will be used for the lockup.

4. Identify a latch and an inverter from the ATPG cell library for use as test structures.

SETUP> add_cell_models latch -type dlat CLK D

SETUP> add_cell_models inv01 -type inv

5. You will also add additional test logic to control the "reset" control signal in this design.

SETUP> set_test_logic -reset on

Perform DRC and Circuit Learning

6. SETUP> check_design_rules

Setup and Perform Scan Insertion

7. Using the commands from the previous exercise as an example, define the two scan chains using the
scan_in and scan_out pins. Notice that the chain2 scan_out pin is different in this exercise. Allow for
scan chain balancing by using two clocks with a single chain. Define a scan mode and analyze scan
chains.

What commands did you use?

_________________________________________________________
_________________________________________________________

8. Insert the test structures, allowing for scan balancing and using two clocks for a single chain.

ANALYSIS> insert_test_logic

9. How many scan cells are reported by:

INSERTION> report_scan_chains

chain1: __________
chain2: __________

Configuring Scan Chains/Test Logic 22

 10. What test logic and new pins were inserted?
INSERTION> report_test_logic
___________________________________________________
___________________________________________________
___________________________________________________

11. Save the scan inserted netlist and ATPG setup files as in previous exercises.

This is the end of exercise 3. Exit the tool.

Configuring Scan Chains/Test Logic 23

 Lab Answers

These labs were qualified using Tessent 2020.1 and ModelSim 2020.2,
if other Tessent versions were used, results contained in tables in these
Note labs may differ slightly from those shown in this Lab Answers section.

Lab 2
Exercise 1

Setup Instructions
Step 5

• What command would you use to hold a pin to a constant value? add_input_constraints
<pin_name> [C0|C1]

Step 8

• How many scannable cells are identified? 17

Create Scan-Inserted Netlist and ATPG Setup Files

Step 12

• What is the number of sequential instances? 2

• Number of inserted scan chains? 1

• Number of new pins inserted? 3 [new pins: ts_si[1], ts_so[1], scan_en]

Exercise 2

Setup/Run Test Synthesis

Step 10

• Number of inserted scan chains? 2

• Number of additional gates inserted? 6

Configuring Scan Chains/Test Logic 24

 Step 11

• Why are there only 2 cells in scan chain 2? Because clk 2 is controlling only 2 scannable
elements and the –single_clock_domain_chains option was set to ON, which restricts
a scan chain to a single clock domain.

Exercise 3

Setup and Perform Scan Insertion

Step 7

What commands did you use?

“set_scan_insertion_options -port_index_start_value 1 -si_timing any_edge -so_timing

any_edge -single_clock_edge_chains on -single_clock_domain_chains off”

“set_insertion_options -module_uniquification_suffix _scan#”

“add_scan_mode unwrapped -chain_count 2 -si_connections {{/d[10]} {/d[0]}} -

so_connections {{/q[15]} {/q[1]}}”

“analyze_scan_chains”

Step 9

• chain1: 9

• chain2: 8

Step 10

• What test logic and new pins were inserted?

New pins: scan_en

Instance module
----------------------------------------- --------------
Counter16/tessent_persistent_cell_buf_extso1_i buf02
Counter16/tessent_persistent_cell_buf_extso10_i buf02
Counter16/ts_lockup_latchn_clkc0_intno16_i nlatch
Counter16/tessent_persistent_cell_buf_intsi17_i buf02
Counter16/tessent_persistent_cell_buf_intsi18_i buf02
Counter16/ts_mux_sea0_atsource17__intno17_i mux21
Counter16/ts_mux_sea0_atsource18__intno18_i mux21

Configuring Scan Chains/Test Logic 25

 NOTES:

Configuring Scan Chains/Test Logic 26