Sequential Circuit Timing

• The correct functioning of sequential circuits involves several timing issues.

• Propagation delays of flip-flops, The propagation delay can depend on
whether the output is changing from high to low or vice versa
• gates and wires;
• setup times and
• hold times of flip-flops;
• clock synchronization;
• clock skew;
These are the important issues in designing sequential circuits
Propagation Delays, Setup, and Hold Times
• Static timing analysis (STA) is a method of validating the timing
performance of a design by checking all possible paths for timing violations
under worst-case conditions.
• A static analysis path starts at a source flip-flop (or at a primary input) and
terminates at a destination flip-flop (or primary output).
• A static timing path between two flip-flops starts at the input to the source
flip-flop and terminates at the input of the destination flip-flop.
• It does not go through the destination flipflop. The path terminates when
it encounters a clocked device. If a signal goes from register (flip-flop) A to
register B and then to register C, the signal contains two paths
• The timing paths in a synchronous digital system can be classified into
4 types:
I. Register to register paths (i.e., flip-flop to flip-flop)
II. Primary input to register paths (i.e., input to flip-flop)
III. Register to primary output paths (i.e., flip-flop to output)
IV. Input to output paths (i.e., no flip-flop)
A Circuit to Illustrate Timing Paths
Imp definitions
• A setup time violation occurs if the data changes just before the clock without pro- viding
enough setup time for the flip-flop.
• A hold-time violation occurs if the data changes just after the clock without providing
enough hold time for the flip-flop.
• Slack is the amount of time still left before a signal will violate a setup or hold-time
constraint.
• Paths must have a positive or zero slack in order to have no violations.
• Paths that have a zero or very small slack are the speed-limiting paths in the design,
because any small changes in clock or gate delays will lead to violations in such circuits.
• Paths that have a negative slack time have already violated a setup or hold constraint.
• Static timing analysis considers the worst possible timing scenarios, but not the logical
operation of the circuit. In comparison with circuit simulation, static timing analysis is
faster because it doesn’t need to simulate multiple test vectors.
Timing Rules for Flip-Flop to Flip-Flop Paths
• Rule No. 1: Setup time rule for flip-flop to flip-flop path: Clock period
should be long enough to satisfy flip-flop setup time.
• Rule No. 2 Hold-time rule for flip-flop to flip-flop path: Minimum
circuit delays should be long enough to satisfy flip-flop hold time.
• Rule No. 3 Setup time rule for input to flip-flop path: External input
changes to the circuit should satisfy flip-flop setup time.
• Rule No. 4 Hold-time rule for input to flip-flop path: External input
changes to the circuit should satisfy flip-flop hold times.
Design flow for ASIC and FPGA
• The design flow for ASIC (Application-Specific Integrated Circuit) and FPGA
(Field Programmable Gate Array) development includes a series of similar
steps, but the tools, objectives, and final implementations differ
significantly between the two. Here’s a breakdown of the design flows for
each:
• FPGA Design Flow
• FPGAs are reprogrammable devices with an array of logic blocks, so their
design flow is generally more iterative and flexible.
1.Design Entry: The design is created using Hardware Description Languages
(HDLs) like VHDL or Verilog, or via schematic entry and block design tools.
2.Simulation & Functional Verification: The initial design is tested through
simulations to verify its functionality and correctness, using software like
ModelSim or Vivado.
1.Synthesis: The HDL code is converted into a gate-level netlist that can be mapped onto
FPGA resources. This process is handled by synthesis tools like Xilinx Vivado or Intel
Quartus.
2.Implementation (Place and Route):
1. Mapping: Maps the netlist onto FPGA logic blocks.
2. Placement: Determines where each block will be placed on the FPGA.
3. Routing: Connects the blocks based on the design.
3.The output is a bitstream file that configures the FPGA hardware.
4.Timing Analysis and Optimization: Ensure the design meets timing requirements (e.g.,
clock constraints) to prevent signal delays.
5.Configuration and Testing: The bitstream is loaded onto the FPGA, and the design is
tested on the actual hardware. Modifications are easy at this stage, as the FPGA can be
reprogrammed with a new bitstream.
6.Debugging and Iteration: Tools like ChipScope or SignalTap allow for real-time debugging
on the FPGA, and changes can be implemented quickly.
• ASIC Design Flow
• ASICs are fixed hardware devices once manufactured, so the design process is
more extensive and focused on optimization to meet performance, power, and
area (PPA) constraints.
1.Design Specification: Define detailed requirements and constraints, including
functionality, performance, and power objectives.
2.Design Entry: Similar to FPGA, using HDL or schematic entry, but with a focus on
defining constraints for optimal silicon use.
3.Functional Verification: Extensive verification using simulation tools and formal
verification to ensure all aspects of the design meet the functional specifications.
4.Synthesis: The HDL is synthesized into a gate-level netlist optimized for the target
technology. Power, performance, and area optimization are prioritized.
1. Floorplanning and Physical Design:
1. Floorplanning: Organize the layout of the circuit blocks on the chip.
2. Placement: Place the logic cells and blocks onto the physical design.
3. Clock Tree Synthesis (CTS): Ensure the clock signal is distributed with minimal skew.
4. Routing: Connects the placed cells based on the netlist.
2. Design Rule Check (DRC) & Layout Versus Schematic (LVS): Ensure the design adheres to manufacturing
rules and that the layout matches the intended schematic.
3. Static Timing Analysis (STA): Verify that all timing requirements are met to prevent delays or setup/hold
violations.
4. Power Analysis: Analyze power consumption and optimize to meet the target.
5. Verification: Includes more thorough testing like gate-level simulation, and Design-for-Test (DFT) structures
are added for manufacturing testing.
6. Sign-Off: The design undergoes final checks, including formal verification and tape-out preparation.
7. Fabrication: The design is sent to a foundry for manufacturing, which produces the actual ASIC hardware.
8. Testing and Validation: Once fabricated, the chip is tested extensively to ensure it functions as intended.
Comparison of ASIC and FPGA Design Flows

• Flexibility: FPGAs allow reprogramming and are well-suited for

iterative design, while ASICs are one-time programmable and require
higher initial investment.
• Cost: FPGA development has lower initial costs, but ASICs become
more cost-effective for large production volumes.
• Performance: ASICs can be highly optimized for specific applications,
often achieving better performance and lower power consumption
than FPGAs.
• In summary, FPGA design flow is more iterative and allows for
flexibility and reconfiguration, while ASIC design flow is more rigorous
and targeted toward final, optimized silicon.
Compiler directives
• Timescale
• Syntax: \timescale <time_unit> / <time_precision>
• `Purpose: Specifies the time unit and precision for simulation timing.
• Example: \timescale 1ns / 1ps` sets the time unit to 1 nanosecond
and the precision to 1 picosecond.
• Use Case: Useful for defining timing resolution in testbenches and
simulation models.
• Define
• Syntax: \define <macro_name> <value>`
• Purpose: Defines macros, which act as constants or shorthand for
specific values or expressions.
• Example: \define DATA_WIDTH 8 creates a constantDATA_WIDTH`
with a value of 8.
• Use Case: Enables easy modification of parameters (like data widths
or constants) throughout the code by changing a single line.
• Include
• Syntax: \include "filename"`
• Purpose: Imports the content of another Verilog file.
• Example: \include "definitions.v"will include the code from
definitions.v`.
• Use Case: Organizes code by separating common definitions or
module parameters into separate files.
• ifdef, ifndef, elsif, else, and endif
• Syntax:Verilog
`ifdef <macro_name>//
code if macro_name is defined
`else
// code if macro_name is not defined
`endif
• Purpose: Conditionally includes code based on whether a macro is
defined.Example:verilogCopy code`define DEBUG`ifdef DEBUG initial
$display("Debugging enabled");`endif
• Use Case: Controls which parts of the code are included, useful for creating different
configurations or enabling debug code without affecting the main functionality.
Coding guidelines
Slack
In digital circuit design, slack is a term used to describe the difference
between the required timing of a signal and its actual arrival time. It's an
essential concept in timing analysis and helps determine whether a circuit can
meet its timing requirements.
•Positive Slack: Indicates that the design meets the timing requirement.
•Negative Slack: Indicates a timing violation, requiring design optimization.
•Setup Slack: Ensures data arrives before the next clock edge.
•Hold Slack: Ensures data remains stable after a clock edge.
Analyzing and managing slack is crucial for ensuring a design's performance,
stability, and reliability.