Computer Structure &

Language:
MIPS Instructions (Part One)
Hossein Asadi (asadi@sharif.edu)
Department of Computer Engineering
Sharif University of Technology
Fall 2024
Copyright Notice
• Some Parts (text & figures) of this Lecture
adopted from following:
– Computer Organization & Design, The
Hardware/Software Interface, 4th Edition, by D.
Patterson and J. Hennessey, MK pub., 2012.
– “Intro to Computer Architecture” handouts, Dept of
ECE, CMU, by James Hoe, 2009.
– “Computer Organization I” handouts, Dept of Computer
Science, FSU, by X. Liu, Fall 2007.
– “Computer Organization & Design” handouts, by Prof.
Kumar, UIUC, Fall 2007.
– “Machine Structures” handouts, by Prof. D. Garcia,
UCB, Spring 2010.

Slide 2
Our Lectur Today

Slide 3
Topics Covered Today
• MIPS Instructions
– Arithmetic
– Logical
– Data transfer
• Memory Organization
– MIPS memory organization
• Endianness

Slide 4
Copyright Notice
• Parts (text & figures) of this lecture adopted from:
– Computer Organization & Design, The
Hardware/Software Interface, 3rd Edition, by D.
Patterson and J. Hennessey, Morgan Kaufmann
publishing, 2005.
– “Computer Organization & Design” handouts, by Prof.
Kumar, UIUC, Fall 2007.
– “Computer Organization I” handouts, FSU, Fall 2007.

Slide 5
MIPS-32 Processor
• 32-Bit Processor
– Registers 32 bits
– Arithmetic & logical operations 32 bits
• Load/Store ISA
– Only load/store instructions can access memory
• Arithmetic/logical instructions no access to memory
• 32-Bit Instruction Length

Slide 6
Why Coding in Assembly?
• Primary Reasons
– When speed or size of code is critically
important
• Compilers often introduce uncertainty
• Assembly programmer has tight control over
instructions & their execution time
– Applications
• Embedded applications
• Knowledge needed for compiler designers
• Core modules in operating system

Slide 7
Why Coding in Assembly? (cont.)
• Pros
– Code size very efficient
– Higher performance
• Cons
– Very time-consuming for large size codes
– Processor-specific
– Low readability
– Not easy to debug
• Solution?

Slide 8
Why Coding in Assembly? (cont.)
• Hybrid Programming
– Have your main code in high-level language
– Time-critical sections written in assembly
language
• Locality in Execution Time
– Programs typically spend most of their time
executing a small fraction of program’s source
code

Slide 9
Writing Functions with Inline Assembly
// Power2_inline_asm.c
// processor: x86
#include <stdio.h>
int power2( int num, int power );
int main( void )
{
printf_s( "3 times 2 to the power of 5 is %d\n", power2( 3, 5) );
} ISA Independent
int power2( int num, int power )
{
__asm
{ © msdn.microsoft.com
mov eax, num ; Get first argument
mov ecx, power ; Get second argument
shl eax, cl ; EAX = EAX * ( 2 to the power of CL )
} // Return with result in EAX
} ISA Dependent

Slide 10
MIPS Instructions
• Arithmetic
• Data Transfer
• Logical
• Control
– Conditional branch
– Unconditional branch

Slide 11
MIPS Registers
• $s0-$s7
– General registers
– Must be saved when calling subroutine
• $t0-$t9
– Temporary registers
– Local to each subroutine
• $v0-$v1
– Values for results of a subroutine call
• $a0-$a3
– Arguments for subroutine call

Slide 12
MIPS Registers (cont.)

Slide 13
MIPS Instructions
• Arithmetic
– add r1, r2, r3
• Example: add $t0, $s2, $s4
• Meaning: $t0 = $s2 + $s4
– sub r1, r2, r3
• Example: sub $t0, $s2, $s4
• Meaning: $t0 = $s2 - $s4

Slide 14
MIPS Instructions (cont.)
• Logical and Shift Instructions
– Operate on bits individually
• Unlike arithmetic, which operate on entire
word
– Use to isolate fields
• Either by masking or by shifting back and
forth

Slide 15
MIPS Instructions: Logical
• and r1, r2, r3
– Example: and $t0, $s2, $s4
– Meaning: $t0 = $s2 & $s4
• or r1, r2, r3
– Example: or $t0, $s2, $s4
– Meaning: $t0 = $s2 | $s4
• nor r1, r2, r3
– Example: nor $t0, $s2, $s4
– Meaning: $t0 = ~($s2 | $s4)

Slide 16
MIPS Instructions: Data Transfer
• lw address
– Example: lw $s1, 100($s2)
– Meaning: $s1 = Memory[$s2 + 100]
• sw address
– Example: sw $s1, 100($s2)
– Meaning: Memory[$s2 + 100] = $s1
• Address
– 16-bit, signed
– Signed extended to 32-bits

Slide 17
Load and Store
• Base Addressing
– Memory address in load and store specified by a
base register and offset

Slide 18
MIPS Instructions (cont.)
• Example 1: compute f = (g+h) – (i+j)
– Assumptions
• g in $t0
• h in $t1
• i in $t2
• j in $t3
– Answer
• add $s0, $t0, $t1
• add $s1, $t2, $t3
• sub $s2, $s0, $s1

Slide 19
Memory Organization
• Memory Organized as an Array of Bytes
– One Byte = 8 bits
– Byte is smallest addressable entry in memory
• Possible Organizations
– Byte addressable, byte accessible
– Byte addressable, word accessible
– Word addressable, word accessible

Slide 20
Memory Organization (cont.)
• MIPS Uses Words (4 bytes)
– Words start at addresses that are multiples of 4
– This is called alignment restriction
– Addresses are byte-based addressing

Slide 21
MIPS Instructions (cont.)
• Example 2: A[12] = h + A[8]
– Assumptions
• Address of A in $s3
• Variable h is in $s2

lw $t0, 32($s3) # A[8]

Slide 22
MIPS Instructions (cont.)
• Example 3:
– compute A[4]
• A[4] = (A[0]+A[1]) – (A[2]+A[3])
– Assumptions
• A is in an array in main memory
– Four-byte each entry
– Starting address of array A in $s0

Slide 23
MIPS Instructions (cont.)
• A[4] = (A[0]+A[1]) – (A[2]+A[3])
• Answer
• lw $t0, 0($s0)
• lw $t1, 4($s0)
• lw $t2, 8($s0)
• lw $t3, 12($s0)
• add $s1, $t0, $t1
• add $s2, $t2, $t3
• sub $s3, $s1, $s2
• sw $s3, 16($s0)

Slide 24
Endianness
• Byte Ordering
– How a multiple byte data word stored in memory
• Endianness
– Big Endian
• Most significant byte of a multi-byte word is stored at
lowest memory address
– e.g. Sun Sparc, PowerPC
– Little Endian
• Least significant byte of a multi-byte word is stored at
lowest memory address
– e.g. Intel x86
• LLL (Little endian: Least significant in Lowest
address)
Slide 25
Example of Endianness
• Store 0x87654321 at address 0x0000, byte-
addressable

Slide 26
Example of Endianness
• Store 0x87654321 at address 0x0000, byte-
addressable

Slide 27
Endianness (cont.)
• Why to Worry about Endianness?
– Two computers with different byte orders
may be communicating
– Failure to account for varying endianness
è a hard to detect bug

Slide 28
Endianness (cont.)
• Endianness Misconceptions
– Read a 32-bit value and store it in a 32-bit
register
• Do I need to know Endianness?
– No
– Endianness only makes sense when you are
breaking up a multi-byte quantity

Slide 29
Endianness (cont.)
• How Do I know Endianness in Processor?
• Try running this Code:
main()
{
int num = 1;
if(*(char *)&num == 1)
printf("\nLittle-Endian\n");
else
printf("Big-Endian\n");
}

Slide 30
Organization of MIPS Program
• Text Segment
– Code
• Static Data
– Static variables
• Dynamic Data
– Dynamic variables

Slide 31
Stack Example
• $sp
– Contains address of
word on top of stack

• lw $s0, 4($sp)
– Meaning?
• lw $s1, 0($sp)
– Meaning?

Slide 32
MIPS Assembly Program
• MIPS Assembly Code
– Consists of MIPS instructions and data
– Instructions given in .text segments
• A program may have multiple .text segments
– Data defined in .data segments using MIPS
assembly directives
• .word, for example, defines following
numbers in successive memory words
• See your book Appendices

Slide 33
MIPS Assembly Program (cont.)
• First MIPS assembly program
– Compute sum of first five homework
assignment scores
– Scores are in memory

– We need to:
• Load address of scores to a register
• Load first two scores
• Add them
• Then load third score and add it to the sum and
so on
Slide 34
First MIPS Assembly Program

Slide 35
What We Learned in this Lecture?
• MIPS Registers
• MIPS Arithmetic Instructions
• MIPS Logical Instructions
• MIPS Data Transfer Instructions
• Base Addressing Mode in MIPS
• MIPS Memory Organization
• Endianness
• First MIPS Assembly Program

Slide 36
Thanks for Your Attention!