555 Timers

Shafrin Sultana
Lecturer
Department of Electronics and Communication Engineering
Khulna University of Engineering & Technology, Khulna

1. Ramakant A. Gayakward, “Op-Amps and Linear Integrator Circuits,” Pearson. Chapter 9

2. Albert Malvino, “Electronic Principle -7th edition,” MC Graw Hill India. Chapter 23
 Chapter Summary

1. The 555 timer 21.7

2. Monostable multivibrator applications 9.4.2
3. Astable multivibrator applications 9.4.4, 21.8
4. Phase locked loops 9.5. 21.10
Mathematical Problems 21.6 – 21.9, 9.5, 9.7
 Introduction
The 555 timer IC is an integrated circuit used in a variety of timer, delay, pulse generation, and
oscillator applications.

In 555 timer is called so because of its internal circuit. There are three 5k resistors used in the IC
and hence the name 555. It helps to design timing counter.

Eg: NE555, SE555, LM555

Multivibrator: It is a two-state circuit that has zero, one or two stable output states.
a) When 555 timer is used in the monostable mode, called monostable multivibrator. At the same
time, it is called one-shot multivibrator because it provides only one output pulse for each input
trigger. The duration of output pulse can be precisely controlled with external R & C.
b) Astable multivibrator, no stable states means it cannot remain indefinitely in either state. Also
called a free-running multivibrator as no input trigger is needed.
c) Bistable multivibrator. Such as RS flip-flop.
 Internal Block Diagram of 555 timer
 It consists of a voltage divider, two

comparators, an RS flip-flop and an npn

transistor.

Fig. 555 timer PIN diagram

555 timer simplified functional block diagram
 Monostable Multivibrator
 Initially the Q output is high, this saturates the transistor and clamps the capacitor voltage at ground. This
will remain in the state until a trigger arrives
𝑉𝑐𝑐
 When trigger input falls less than , the comparator 2 resets the flipflop Q changed to low and the
3

transistor goes into cut-off operation, this allow the capacitor to charge exponentially and output Q is
high
2𝑉𝑐𝑐
 When capacitor voltage is greater than , the comparator 1 sets the flipflop Q changed to high and the
3

transistor turns on, this allow the capacitor to discharge instantly and remain until another trigger
 Monostable Timer Circuit

Fig. Monostable Timer

Circuit Simplified form

555 timer connected for monostable operation

 Application of Monostable Multivibrator
❑ Frequency divider: Based on the concept that the output
will not change it’s state even if an input trigger is applied

again during the capacitor’s charging interval. To use the

monostable multivibrator as a divide-by-2 circuit, the capacitor

charging interval must be slightly large than the time period T

of the trigger input signal.

❑ Pulse stretcher: Output pulse width can be stretched longer

Input and output waveforms of the monostable
than the input trigger pulse width. Narrow pulse width signals multivibrator as a divider-by-2 network

are not suitable for driving an LED display.

 Astable Operation
2𝑉 𝑉
As previous UTP = 𝑐𝑐 and LTP = 𝑐𝑐
3 3
When Q is low and the transistor is in cut-off region, the
capacitor charge through the total resistance
𝑹 = 𝑹𝟏 + 𝑹𝟐
Charging time, 𝒕𝒄 = 𝟎. 𝟔𝟗𝟑(𝑹𝟏 +𝑹𝟐 )𝑪
Discharging time, 𝒕𝒅 = 𝟎. 𝟔𝟗𝟑𝑹𝟐 𝑪
Hence the pulse width, 𝐖 = 𝟎. 𝟔𝟗𝟑(𝑹𝟏 +𝑹𝟐 )𝑪
The period of the output pulse, 𝐓 = 𝟎. 𝟔𝟗𝟑(𝑹𝟏 +𝑹𝟐 )𝑪
𝑹 +𝑹
Duty cycle, 𝐃 = 𝟏 𝟐
𝑹𝟏 +𝟐𝑹𝟐

Capacitor and output waveforms for astable operation 555 timer connected for astable operation
 Application of Astable Operation

Astable multivibrator s square wave

oscillator with 50% duty cycle by connecting
diode across the resistor 𝑹𝟐

Astable timer circuit simplified form

 Voltage Controlled Oscillator
Another application for a 555 timer.

Also called voltage to frequency converter as it changes the output frequency in according to

change in input voltage.

Voltage controlled oscillator

Transistor Astable Multivibrator

Transistor Astable Multivibrator Circuit

 Transistor Astable Multivibrator
When circuit is switched ON, one transistor is ON and the other is OFF. Consider Q1 is ON and Q2 is OFF.
 During this time capacitor C2 is charging to Vcc through R.
 Q2 is OFF due to the negative voltage from the discharging capacitor C1 during the previous cycle. Output
voltage at Q1 collector is low and output voltage at Q2 collector is high.

 After a time period, C1 discharge completely and starts charging in reverse direction through R1.
 When reverse charge of C1 = 0.7 V to the base of Q2, it turns ON and capacitor C2 starts discharging.

 The negative voltage from C2 turns OFF the Q1 and capacitor C1 starts charging through R.
 Likewise in the previous state, when the capacitor C2 discharge completely it starts charging towards opposite
direction through R2.

 When it’s reverse voltage cross 0.7 V, it turns ON transistor Q1 and C1 starts discharging.
 This process continue.
Transistor Astable Multivibrator
T1 = ON period of Q1 = OFF period of Q2 = 0.693 R1C1

T2 = OFF period of Q1 = ON period of Q2 = 0.693 R2C2

Waveforms across transistor’s collector and base

 Phase Locked Loop (PLL)
A phased locked loop (PLL) contains a phase detector, a dc amplifier, a low pass filter and a voltage

controlled oscillator (VCO).

When a PLL has an input signal with a frequency of 𝑓𝑖𝑛 , its VCO will produce an output frequency of

𝑓𝑜𝑢𝑡 that equals to 𝑓𝑖𝑛

Applications related to communication:

• Cleaning up a noisy input signal because of a low-pass filter will remove high-frequency noise.
• The output is stable as the output comes from the VCO.
• FM demodulator (taking out of phase detector).
• Frequency multiplier (using frequency divider at the feedback path).
 Phase Locke Loop (PLL)
Phase Detector: It is the first stage in a PLL. This circuit produces an output voltage proportional to the

phase difference between two input signals.

(a) Phase detector, (b) Equal frequency sine waves with phase difference, (c) Transfer curve

The typical phase detector produces a linear response between -90° to +90°. When ∆Ø is between 0° and

+90°, the output is a positive voltage. When ∆Ø is between 0° and -90°, the output is a negative voltage.
 Phase Locke Loop (PLL)

(a) VCO block, (b) Output frequency is proportional to input voltage

Phase Locke Loop (PLL)
THANK YOU