Centre for Distance & Online Education

NAME SIMON PETER

ROLL NO. 2314520879
SESSION FEBRUARY/MARCH 2024
PROGRAM BACHELOR OF COMPUTER
APPLICATIONS (BCA)
SEMESTER II
COUIRSE CODE & NAME DCA1205 DIGITAL LOGIC

SET-I

Q.No1.

Ans. Certainly! Boolean algebra plays a crucial role in the design of digital logic circuits, with a
set of important laws that aid in simplifying Boolean expressions. Here are the primary Boolean
laws explained with the help of logic diagrams.
1. The Identity Law
A OR 0 = A OR A AND 1 = A Interpretation:

A AND 1: The value of A is unaffected by the AND operation with 1. The outcome is true (1) if
A is true (1). The outcome is false (0) if A is false (0).
A OR 0: The value of A is unaffected by the OR operation with 0. The outcome is true (1) if A is
true (1). The outcome is false (0) if A is false (0).

2. Domination Law, also known as Null Law

• A OR 1 = 1; A AND 0 = 0
Justification
• A AND 0: Using 0 in the AND operator yields 0. If one of the inputs is 0, the outcome is
always 0, regardless of what A is.
• A OR 1: 1 is the outcome of the OR operation with 1. If one input is 1, the outcome is always 1
regardless of what A is.

3. Complement Law

Where A DOES NOT equal 0

• A OR NOT A = 1.
Justification

• A AND NOT A: Since A and NOT A cannot both be true at the same time, a variable ANDed
with its complement always yields 0.
• A OR NOT A: When one multiplies a variable by its complement, the outcome is always 1
because either A or NOT A is true.

4. Idempotent Law

states that: A AND A = A OR A OR A = A

Justification
• A AND A: The variable is the result of an AND operation between a variable and itself. The
outcome remains the same.
• A OR A: The variable is the result of an OR operation between it and itself. The outcome
remains the same.

5. Distributive law
states that:
• A AND (B OR C) = (A AND B) OR (A AND C) • A OR (B AND C) = (A OR B) AND (A
OR C)
Justification
• A AND (B OR C): This assigns A to the OR function. The combination of (A AND B) OR (A
AND C) is the outcome.
• Distributes A over the AND operation using A OR (B AND C). The combination of (A OR B)
AND (A OR C) is the outcome.
6. Absorption law: A OR (A AND B) = A
• B OR A AND A = A
Justification
• An OR (A AND B): An AND is absorbed by an OR operation. The outcome is just an A.
The AND operation absorbs the OR operation in the expression A AND (A OR B). The outcome
is just an A.

7. Theorems of De Morgan
• Not in A AND B = Not in A OR Not in B; Not in A OR B = Not in A AND Not in B
Justification
• NOT (A AND B): The OR of the complements is the complement of an AND operation.
• NOT (A OR B): The AND of the complements is the complement of an OR operation.

Q.No2.

Ans. Logic gates are fundamentally constructed from logic gates. They carry out fundamental
logical operations that are necessary for designing digital circuits. Truth tables and symbols can
be used to represent each gate, which implements a distinct Boolean function. Below is a
summary of the fundamental logic gates:

1. AND Gate

 Symbol: A --| AND |-- Q B --|_______|

- **Purpose:** The AND gate carries out a logical operation of multiplication. It only returns
true (1) if every input is true (1).

- **Table showing logical values:**

| True | True | True |

| True | False | False |
| False | True | False |
| False | False | False |

Original text: The cat quickly ran across the street before the car arrived.

Paraphrased text: The cat swiftly dashed over the road prior to the car's arrival.

- **Clarification:** In an AND gate, the result \( Q \) is only 1 when both inputs A and B are
also 1. If not, the result will be a minimal value of zero (0).

### 2. **OR Gate**

This is a text about **OR Gate**.

- **Representation:**

A --| OR |-- Q B --|_______|

**Purpose:** The OR gate carries out a logical sum. It will output true (1) if at least one of the
inputs is true (1).
**Table of Truth:**

| False | False | False |

| False | True | True |
| True | False | True |
| True | True | True |
The text should be paraphrased using the same input language and maintaining the same word
count.
- **Clarification:** In the case of the OR gate, the result \( Q \) will be a 1 when A is high, B is
high, or both A and B are high. If both the inputs are at a low level (0), then the output will also
be at a low level (0).
### 3. **Inverter Gate (NOT Gate)**
- **Representation:**

Q.No3.

Ans. Karnaugh maps (K-maps) are a graphical tool used to simplify Boolean expressions and
minimize the number of terms in a logic function. When dealing with Boolean expressions,
sometimes certain input combinations are not relevant to the function’s operation; these are
known as "don't care" conditions. These don't care conditions can be used strategically to
simplify the expression further. Here’s a step-by-step explanation of how to use Karnaugh maps
with don’t care conditions, along with an example.

Steps for Karnaugh Map Simplification with Don’t Care Conditions

1. Build the Karnaugh Map: Determine the amount of variables in the Boolean function to
construct a Karnaugh map. There will be cells on the map that correspond to every
possible combination of the input variables.Plot the Function on the Karnaugh Map:
o Place the output values of the Boolean function into the cells corresponding to
each combination of inputs.
2. Determine Which Situations Don't Care: oMark the Karnaugh map's non-caring
conditions. Usually, a 'X' or another symbol is used to indicate these cells, meaning that
the function does not care about the value of the cell.
3. Assemble the 1s and Don't Care Conditions: o Assemble groupings of 1s and, if
desired, cells that indicate no concern. Every group ought to be as big as it can be and a
power of two (1, 2, 4, 8, etc.). The objective is to use the fewest groups possible to cover
all 1s..
4. Write the Simplified Expression: o Determine the simplified Boolean expression based
on the groups that were generated. Each group in the simplified expression corresponds
to a product word.

Example:

Given Boolean Function: F(A,B,C,D)=∑(0,1,2,5,7,8,9,12,13)F(A, B, C, D) = \sum(0, 1, 2, 5, 7,

8, 9, 12, 13)F(A,B,C,D)=∑(0,1,2,5,7,8,9,12,13) Don’t Care Conditions:
Don’t Care=∑(3,4,6,10,11)\text{Don’t Care} = \sum(3, 4, 6, 10, 11)Don’t Care=∑(3,4,6,10,11)

Step-by-Step Solution:
 1. Construct the Karnaugh Map: For a function with four variables (A, B, C, D), create a
4x4 Karnaugh map.
2. Plot the Function Values: Place the output values (1s) in the Karnaugh map. Mark don’t
care conditions with ‘X’.

Identify and Group the 1s and Don’t Care Conditions:

 Group the adjacent 1s and optionally include don’t care conditions to form larger groups.
Each group should be rectangular and contain a number of cells that is a power of 2.
 In the map:
o Group 1: Covers all cells with 1 in the last row and column (Cells 8, 9, 12, 13).
o Group 2: Covers cells 0, 1, 4, and 5.

SET-II

Q.No4.

Ans. One popular and adaptable kind of flip-flop in digital electronics is the JK flip-flop. It bears
the names of Jack Kilby and Robert Noyce, its creators. The JK flip-flop is an edge-triggered
device that, depending on its inputs, can be set to execute a variety of functions, such as setting,
resetting, and toggling. Here's a thorough breakdown of how it functions:

JK Flip-Flop Synopsis
A kind of sequential circuit having two inputs (J and K) and two outputs (Q and Q') is the JK
flip-flop. Additionally, it features a clock input (CLK) that regulates the flip-flop's timing.
Fundamental attributes:
• Sources:
o J (Set Input): Chooses whether to set the output to 1 by the flip-flop.

o K (Reset Input): Indicates if the output of the flip-flop should be reset to 0.

o CLK (Clock Input): Regulates when states change. Because the JK flip-flop is edge-
triggered, it alters its state when the clock signal transitions, usually on the rising edge.

• Results:

Q: The primary result.

o Q': Q in its complement.

Truth Table

The JK flip-flop’s behavior is governed by its inputs and the clock signal. The truth table below
shows how the flip-flop responds to different combinations of the J and K inputs on the clock’s
edge:
J K Q(t) Q'(t) Description
0 0 Q(t) Q'(t) No Change (Hold State)
0 1 0 1 Reset (Q = 0)
1 0 1 0 Set (Q = 1)
1 1 ~Q(t) ~Q'(t) Toggle (Q switches state)

Legend:

 Q(t): The state of the output before the clock edge.

 Q'(t): The complement of Q(t).
 ~Q(t): The complement of Q(t) (i.e., if Q was 1 before the clock edge, it becomes 0, and
vice versa).

State Transition Diagram

The state transition diagram provides a visual representation of the JK flip-flop’s behavior. It
shows how the flip-flop transitions between different states based on the J and K inputs:

 J = 0, K = 0: The output state remains unchanged.

 J = 0, K = 1: The flip-flop resets the output to 0.
 J = 1, K = 0: The flip-flop sets the output to 1.
 J = 1, K = 1: The output toggles from its current state (if it was 1, it becomes 0, and if it
was 0, it becomes 1).

Circuit Diagram

The JK flip-flop can be implemented using NAND or NOR gates. A typical circuit diagram for
the JK flip-flop using NAND gates is shown below:

Q.No5.

Ans. Binary data is stored and managed using a kind of digital storage device called a shift
register. It is made up of a chain of connected flip-flops that allow data to be sequentially moved
from one flip-flop to the next. Applications for shift registers include data storage, data transfer,
and data manipulation. Shift registers are explained in detail below:

1. Fundamental Idea
A shift register is made up of a series of flip-flops, each of which is used to represent a single bit
of data. A shift register's main job is to move the data through the flip-flops on each clock pulse,
either left or right. Numerous activities, including data storage and serial-to-parallel and parallel-
to-serial conversion, can be carried out with this process.

2. Types of Shift Registers

Shift registers can be classified based on their shifting operations and data handling methods:
 a. Serial-In Serial-Out (SISO) Shift Register
b. Serial-In Parallel-Out (SIPO) Shift Register
c. Parallel-In Serial-Out (PISO) Shift Register
d. Parallel-In Parallel-Out (PIPO) Shift Register

3. Shift Register Operation

Shifting Data:

• Clock Signal: A clock signal is what drives the shift register. Data is moved from one flip-flop
to the next on each clock pulse.
• Direction of Shifting: Depending on how the shift register is made, data may be shifted to the
left or right.

Types of Shifts:

• Left Shift: Every bit in the shift register is shifted to the left, and the rightmost location is filled
with a new bit.
• Right Shift: Every bit is shifted to the right, and the leftmost location is filled with a new bit.

4. Applications of Shift Registers

• Data Storage: When temporary data storage is needed, shift registers are employed in memory
devices and data storage applications.
• Data Conversion: They are used to convert different formats of data such as parallel-to-serial
and serial-to-parallel conversions.

•Data Manipulation: Utilizing data transformation and manipulation in digital signal processing
and control systems.

• Counters: Counters and other sequential circuits can be designed using shift registers.

5. Example Circuit:
4. Bit Serial-In Parallel-Out Shift Register
Think of a 4-bit shift register that has parallel output and serial input. The data would be
loaded and retrieved as follows:

Bit-by-bit serial data 1101 is the input data.

Four clock pulses are needed to move all of the data into the register.
Parallel Output: 1101 would be the parallel output following four clock pulses.

Q.No6.

Ans. The Master and Slave flip-flops are a pair of linked flip-flops, forming part of the Master-
Slave flip-flop, a type of sequential logic circuit. This setup aims to prevent timing hazards and
race conditions to enhance the performance of flip-flops. By utilizing edge-triggering, the
Master-Slave flip-flop functions based on the clock signal, ensuring a reliable method for storing
and transferring data.

The Master-Slave Flip-Flop's operation.

The Master-Slave flip-flop operates in two stages.

First Phase:

Activity in the Master flip-flop happens when the clock signal is at its high phase.

The flip-flop receives the incoming data (D) during this phase and stores it in its internal
memory. The inputs that the Master flip-flop receives determine its state.

Slavery stage.

The Slave flip-flop operates when the clock signal is low.

The state is transferred from the Master flip-flop to the Slave flip-flop and sent to the output (Q).
During this phase, the outcome doesn't change.

By guaranteeing that the data is only sent to the output during the clock's transition from high to
low, this configuration helps to avoid race situations and guarantee synchronized operation.

Timing Diagram

The following timing diagram shows the evolution of the Master-Slave flip-flop's response to the
input data and clock signal:

Time Pulse:

High Phase: The input data is captured by the active Master flip-flop.
Low Phase: The data from the Master flip-flop is captured by the active Slave flip-flop.
Input of Data (D):

The data input is read by the Master flip-flop when the clock signal is high.
The Slave flip-flop adjusts its output in response to the low clock signal by using the Master flip-
flop's state as a guide.

Advantages of Master-Slave Flip-Flop

Race condition problems that might arise in simpler flip-flop designs are avoided by the Master-
Slave flip-flop by isolating the data capturing (Master stage) from the output updating (Slave
stage).
Cutting-Edge: With its edge-triggered operation, which transfers data only on the clock edge,
timing and synchronization are guaranteed to be more accurate.
Enhanced Stability

Compared to basic flip-flops, it provides superior timing control and stability, which makes it
appropriate for more intricate digital circuits.