EE-222 Microprocessor Systems

Introduction to CPU Architecture

Week1-Lecture2/3
Dr. Sara Shakil Qureshi
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Outline
• Microprocessor vs Microcontroller
• Program loading and execution
• Memory and I/O interfacing with CPU
▫ Memory read and write operations
• CPU Architectures
▫ Harvard architecture
▫ Von-Neumann architecture
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Affordable
Space & power efficient
Not Versatile

Bulky
Expensive
Versatility
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Program loading and execution

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Parts of a Microprocessor-based system

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CPU connecting to memory

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Memory Characteristics
• Location
• Capacity
• Organization
• Access Method
• Physical type
• Unit of transfer
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Memory Characteristics
• Capacity
▫ Word size – n
▫ Number of words - 𝟐𝒌

• Organization
▫ How memory is
arranged/organized

• Access time
▫ Time taken to access the
memory
Memory size = 𝟐𝒌 ∗ 𝒏
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Memory Pin Connections

• Data lines
▫ n-bits data is accessed in
every clock cycle

• Address lines
▫ k-bits address lines

• Control lines
▫ R/OE – read enable
▫ W/WE - write enable

• Voltage connections
▫ Ground
▫ 𝑽𝑪𝑪
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Try this!
• 1Kbytes memory
▫ i.e. Word size is 1 bytes

Calculate the size of address line??

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Try this!
• 1Kbytes memory
▫ i.e. Word size is 2 bytes

Calculate the size of address line??

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Try this!
• Memory addresses
▫ i.e. 0-255

• Word Size
▫ i.e. 16 bits

Calculate the size of Memory??

256x16 = 𝟐𝟖 𝒙𝟏𝟔
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Try this!
• Size of address bus
▫ i.e. 8-bits

• Size of data bus

▫ i.e. 4-bits

Calculate the size of Memory??

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Try this!

Calculate the size of Memory??

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Interfacing Memory to CPU

Read operation Write operation

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Interfacing Memory & I/O (using bus)

to CPU

Read/Write enable
IO/Mem Enable
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Interfacing Memory & I/O (using bus)

to CPU

𝐴0
𝐴1
𝐴2
𝐴3
𝐴4
.
.
.
.
.
IO/𝑴𝑬𝑴 .
.
I/O Devices 𝐴15
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Interfacing Memory & I/O (using bus)

to CPU
𝐴7 𝐴6 𝐴5 𝐴4 𝐴3 𝐴2 𝐴1 𝐴0
0 0 0 0 0 0 0 0
0 0 0 0 1 1 1 1

Fixed Part
𝐴0
𝐴1
𝐴2
𝐴3
𝐴4 IO/𝑴𝑬𝑴
.
.
.
.
.
IO/𝑴𝑬𝑴 . Address decoder
.
I/O Devices 𝐴15 for addresses 0-15
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Try this!

Design an address decoder for addresses 200 (HEX) to 2FF (HEX)??

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CPU execution of program

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Microcontroller retains program in

memory
CPU Architecture
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- ALU
- Program counter (PC)
Components of a CPU has address of next
instruction.
- Instruction decoder
- Registers

𝐴0 = 22h
𝐴1 = 33ℎ
𝐴2 = 41ℎ
𝐴3 = 24ℎ
𝐴4 = 88ℎ
.
R
.
ALU
PC
e
g .
i
s
t
.
Instruction
e
r
.
decoder s
IO/𝑴𝑬𝑴 .
.
I/O Devices 𝐴15 = 01h
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Instruction Current
Number CPU Instr
- ALU
- ---
- Program counter (PC)
0 A<-[16]
- Instruction decoder
1
- Registers
2

𝐴0 = 22h
PC Instruction 𝐴1 = 33ℎ
pointed by 𝐴2 = 41ℎ
PC 𝐴3 = 24ℎ
0 A<-[16] 𝐴4 = 88ℎ
.
1 A<-[3] R
.
ALU
PC
e
g .
3 B=[16]+[3] i
s .
0 t

7 A<-[17] Instruction
e
r
.
decoder s

D<-B
IO/𝑴𝑬𝑴 .
.
I/O Devices 𝐴15 = 01h
IO (1-4)

A refers to address bus, D refers to data bus, [ ] refers to an address

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Instruction Current
Number CPU
Instruction
- ALU
- --- - Program counter (PC)
0 A<-[16] - Instruction decoder
1 - Registers
2
𝐴0 = 22h
PC Instruction 𝐴1 = 33ℎ
pointed by 𝐴2 = 41ℎ
PC 𝐴3 = 24ℎ
0 A<-[16] 𝐴4 = 88ℎ
.
1 A<-[3] R
.
ALU
PC
e
g .
3 B=[16]+[3] i
s .
1 t

7 A<-[17] Instruction
e
r
.
decoder s

D<-B
IO/𝑴𝑬𝑴 .
.
I/O Devices 𝐴15 = 01h
IO (1-4)

A refers to address bus, D refers to data bus, [ ] refers to an address

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Instruction Current
Number CPU
Instruction
- ALU
- --- - Program counter (PC)
0 A<-[16] - Instruction decoder
1 A<-[3] - Registers
2
𝐴0 = 22h
PC Instruction 𝐴1 = 33ℎ
pointed by 𝐴2 = 41ℎ
PC 𝐴3 = 24ℎ
0 A<-[16] 𝐴4 = 88ℎ
.
1 A<-[3] R
.
ALU
PC
e
g .
3 B=[16]+[3] i
s .
3 t

7 A<-[17] Instruction
e
r
.
decoder s

D<-B
IO/𝑴𝑬𝑴 .
.
I/O Devices 𝐴15 = 01h
IO (1-4)

A refers to address bus, D refers to data bus, [ ] refers to an address

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Instruction Current
Number/A
ddress
CPU
Instruction
- ALU
- --- - Program counter (PC)
0 A<-[16] - Instruction decoder
1 A<-[3] - Registers
3 B=[16]+[3]
𝐴0 = 22h
PC Instruction 𝐴1 = 33ℎ
pointed by 𝐴2 = 41ℎ
PC 𝐴3 = 24ℎ
0 A<-[16] 𝐴4 = 88ℎ
.
1 A<-[3] R
.
ALU
PC
e
g .
3 B=[16]+[3] i
s .
7 t

7 A<-[17] Instruction
e
r
.
decoder s

D<-B
IO/𝑴𝑬𝑴 .
.
I/O Devices 𝐴15 = 01h
IO (1-4)

A refers to address bus, D refers to data bus, [ ] refers to an address

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Decoding Instructions
• CPU understands binary language.
• Machine code is a binary format of an instruction.
▫ Two parts: Op-code and Operand
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Von-Neumann Vs Define how CPU is separated

from the memory.
Harvard Architectures

Harvard Architecture
More space, fast, complex, more efficient, high cost

Von-Neumann Architecture
Less, space, slow, simple,less efficient, low cost
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Conclusion
• Microprocessor has ALU, CU and registers.
Microcontroller has memory, I/O ports and CPU on chip.
• CPU loads the program and executes the instructions
sequentially.
• Memory and I/O interfacing with CPU
▫ CPU shares the address, data and control lines/bus as it interfaces memory
and I/O devices.
▫ Memory read and write operations are controlled using the read enable,
write enable and chip select bits.
• CPU Architecture
▫ Harvard vs Von-Neumann Architecture
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Reading Material
• Textbook:
▫ Chapter 1, Section 1.2
▫ Chapter 2, Section 2.1-2.4
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Questions?