Ch 3

A Top-Level View of Computer

Function and Interconnection

CO, Lecture4 Eng. manal A.al-Areqi

 Computer Components

Contemporary computer designs are based on concepts

developed by John von Neumann.
Referred to as the von Neumann architecture and is
based on three key concepts:
◦Data and ◦The contents of ◦Execution occurs
instructions this memory are in a sequential
are stored in addressable by fashion (unless
a single location, without explicitly
read-write regard to the type modified) from
memory. of data contained one instruction to
there. the next.
 Computer Components

Memory

Memory address Memory buffer

register (MAR) register (MBR)
• Specifies the address in • Contains the data to be
memory for the next written into memory or
read or write receives the data read
from memory

I/O address register I/O buffer register

(I/OAR) (I/OBR)
• Specifies a particular • Used for the exchange
I/O device of data between an I/O
module and the CPU
 Computer Function

Action Categories
• Data transferred • Data transferred
The from processor to to or from a
processor memory or from
memory to
peripheral device
by transferring
interprets processor between the
processor and an
the I/O module
instruction Processor- Processor-
memory I/O
and
performs
the
required Data
action. Control
processing
These
actions fall • An instruction • The processor
may specify that may perform
into four the sequence of
execution be
some arithmetic
or logic operation
categories: altered on data
 Instruction Cycle State Diagram Computer Function

Read instruction from

its memory location
into the processor. Fetch the operand Write the result

Analyze instruction
to determine the Perform the
type of operation to operation
be performed and indicated in the
operand(s) to be
instruction.
used.

determine the
address of the
operand.
 Computer Function

Instruction Cycle State Diagram

• Instruction fetch (if): Read instruction from its memory location into the
processor.
• Instruction operation decoding (iod): Analyze instruction to determine the
type of operation to be performed and operand(s) to be used.
• Operand address calculation (oac): If the operation involves reference to
an operand in memory or available via I/O, then determine the address of
the operand.
• Operand fetch (of): Fetch the operand from memory or read it in from
I/O.
• Data operation (do): Perform the operation indicated in the instruction.
• Operand store (os): Write the result into memory or out to I/O.
• Instruction address calculation (iac): Determine the address of the next
instruction to be executed. Usually, this involves adding a fixed number
to the address of the previous instruction.
 Interrupts

• An interrupt is a signal that requests the

processor to suspend its current execution
and service the occurred interrupt.
• After the execution of the interrupt service
routine, the processor resumes the
execution of the suspended program.
Interrupts can be of two types hardware
interrupts and software interrupts.
 Classes of Interrupts
• Program: Generated by some condition that occurs as a result of
instruction execution, such as arithmetic overflow, division by
zero, attempt to execute an illegal machine instruction, or
reference outside a user’s allowed memory space.
• Timer: Generated by a timer within the processor. This allows
the operating system to perform certain functions on a regular
basis.
• I/O: is Generated by an I/O controller, to signal the normal
completion of an operation, request service from the processor,
or to signal a variety of error conditions.
• Hardware: Failure Generated by a failure such as power failure
or memory parity error.
Instruction Operand Operand
fetch fetch store

Multiple Multiple
operands results

Instruction Instruction Operand Operand

Data Interrupt
address operation address address Interrupt
Operation check
calculation decoding calculation calculation

No
Instruction complete, Return for string interrupt
fetch next instruction or vector data

Figure 3.12 Instruction Cycle State Diagram, With Interrupts

 Computer Function

Direct memory access (DMA)

• Allow I/O exchanges to occur directly
with memory.
• The processor grants an I/O module the
authority to read from or write to
memory so that the I/O memory transfer
can occur without tying up the processor.
• DMA relieves the processor of
responsibility for the exchange.
CO, LEC 5 ENG.MANAL ALAREQI
 Interconnection Structures

Computer Modules

CO, LEC 5 ENG.MANAL ALAREQI

 Interconnection Structures

The interconnection structure must

support the following types of transfers:
Memory Processor I/O to or
I/O to Processor
to to from
processor to I/O
processor memory memory
An I/O
module is
allowed to
Processor exchange
Processor reads an data directly
reads an Processor instruction Processor with
instruction writes a unit or data from sends data to memory
or a unit of of data to an I/O the I/O without
data from memory device via device going
memory an I/O through the
module processor
using direct
memory
access
CO, LEC 5 ENG.MANAL ALAREQI
Bus Interconnection

A communication Signals transmitted by any Typically

pathway connecting one device are available for consists of
reception by all other
two or more devices devices attached to the bus multiple
• If two devices transmit during communication
the same time period their lines
signals will overlap and
become garbled

Data
Computer systems contain
many different buses. Address

Control
CO, LEC 5 ENG.MANAL ALAREQI
 Bus Interconnection

Bus Interconnection

CO, LEC 5 ENG.MANAL ALAREQI

 Bus Interconnection

Data Bus

• Data lines that provide a path for moving data

among system modules
• May consist of 32, 64, 128, or more separate
lines
• The number of lines is referred to as the width of
the data bus
• The number of lines determines how many bits
can be transferred at a time
• The width of the data bus is a key factor in
determining overall system performance.
CO, LEC 5 ENG.MANAL ALAREQI
 Bus Interconnection

Address Bus

• Used to allocate the source or destination

of the data on the data bus
• Also the address lines are generally used
to address I/O ports.

CO, LEC 5 ENG.MANAL ALAREQI

 Bus Interconnection

Control Bus
◦Used to control the access and the use of the data and
address lines.
◦signals transmit both command and timing
information among system modules.
◦Timing signals indicate the validity of data and
address information.
◦Command signals specify operations to be
performed.

CO, LEC 5 ENG.MANAL ALAREQI

 Bus Interconnection

Typical control lines include:

❖Memory write: causes data on the bus to be

written into the addressed location.
❖Memory read: causes data from the addressed
location to be placed on the bus.
❖I/O write: causes data on the bus to be output to
the addressed I/O port.
❖I/O read: causes data from the addressed I/O port
to be placed on the bus.
❖Transfer ACK: indicates that data have been
accepted from or placed on the bus.
CO, LEC 5 ENG.MANAL ALAREQI
 Bus Interconnection

Typical control lines include:

❖Bus request: indicates that a module needs to

gain control of the bus.
❖Bus grant: indicates that a requesting module has
been granted control of the bus.
❖Interrupt request: indicates that an interrupt is
pending.
❖Interrupt ACK: acknowledges that the pending
interrupt has been recognized.
❖Clock: is used to synchronize operations.
❖Reset: initializes all modules.
CO, LEC 5 ENG.MANAL ALAREQI