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Dldlab 10

The document outlines Lab #10 for the course EEE240, focusing on the design and implementation of a BCD to 7-segment decoder. It details the objectives, introduction to the decoder, truth table, simulation, and modifications for handling invalid BCD inputs. The conclusion emphasizes the successful demonstration of the decoder's functionality and its relevance to digital system design.

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emanfatima2t8
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13 views7 pages

Dldlab 10

The document outlines Lab #10 for the course EEE240, focusing on the design and implementation of a BCD to 7-segment decoder. It details the objectives, introduction to the decoder, truth table, simulation, and modifications for handling invalid BCD inputs. The conclusion emphasizes the successful demonstration of the decoder's functionality and its relevance to digital system design.

Uploaded by

emanfatima2t8
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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EEE240 Fundamental of Digital Logic Design

Lab # 10: Design and Implementation of BCD to 7- Segment


Decoder

Eman Fatima
Name Safia Mahnoor
SP24-BAI-015
Registration No. SP24-BAI-046
BSAI-2
Class
Dr. Muhammad Rizwan Azam
Instructor’s Name

Lab Assessment
Post Lab Total
In-Lab
Data Presentation Data Analysis Writing Style

Page 1 of 7
Pre-Lab:
• Objectives:
The objective of this experiment is to understand Binary Coded
Decimal (BCD) representation and its use in digital electronics by designing a BCD
to 7-segment decoder. This involves creating a combinational logic circuit that
translates BCD inputs into signals to drive a 7-segment display and is verified using
simulation tools such as Xilinx.

• Introduction:
1) BCD to 7-segment decoder:
A BCD to 7-segment decoder is a digital circuit that converts a 4-bit BCD input
into the appropriate outputs to drive a 7-segment display. Each digit from 0 to 9 is
displayed using a specific combination of segments, controlled by the outputs of the
decoder.
➢ The display is widely used in digital clocks, calculators, and electronic meters.
Truth Table:
Z A B C D E F G Display
Digit
0000 1 1 1 1 1 1 0 0
0001 0 1 1 0 0 0 0 1
0010 1 1 0 1 1 0 1 2
0011 1 1 1 1 0 0 1 3
0100 0 1 1 0 0 1 1 4
0101 1 0 1 1 0 1 1 5
0110 1 0 1 1 1 1 1 6
0111 1 1 1 0 0 0 0 7
1000 1 1 1 1 1 1 1 8
1001 1 1 1 1 0 1 1 9
others 0 0 0 0 0 0 0 Blank

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In-Lab:
• Proteus Simulation:

• Gate-level Model:

Page 3 of 7
• Stimulus:

• Simulation:

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Post-Lab:
Modify the BCD to 7-segment decoder circuit to handle invalid BCD
inputs (1010 to 1111). Implement a mechanism to turn off the 7-segment display or
display a specific pattern (e.g., all segments off) for invalid inputs. Simulate the
modified circuit in Proteus and verify the error handling functionality.
• Proteus Simulation:

This figure shows that when we put an invalid input, all of the lights turned
off.
• Gate-level Model:

Page 5 of 7
• Stimulus:

• Simulation:

This module will give 0000_000, when invalid input is given.

Page 6 of 7
Conclusion:
The experiment successfully demonstrates the design and
implementation of a BCD to 7-segment decoder. The decoder converts a 4-bit BCD
input into accurate outputs for driving the display, showcasing the practical
application of combinational logic. This experiment enhances understanding of
digital system design, Boolean logic, and the integration of theoretical knowledge
into practical systems.
----------------------------------

Page 7 of 7

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