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An interrupt temporarily halts the microprocessor to address a different task, allowing peripheral devices to access the CPU. The 8086 microprocessor handles interrupts through an Interrupt Service Routine (ISR) and categorizes them into hardware and software interrupts. An interrupt vector table (IVT) associates interrupt handlers with requests, storing vectors in the lower 1024 bytes of memory.

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22 views2 pages

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An interrupt temporarily halts the microprocessor to address a different task, allowing peripheral devices to access the CPU. The 8086 microprocessor handles interrupts through an Interrupt Service Routine (ISR) and categorizes them into hardware and software interrupts. An interrupt vector table (IVT) associates interrupt handlers with requests, storing vectors in the lower 1024 bytes of memory.

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Interrupts

An interrupt is a condition that halts the microprocessor temporarily to work on a


different task and then returns to its previous task. An interrupt is an event or signal
that requests the CPU’s attention. This halt allows peripheral devices to access the
microprocessor. Whenever an interrupt occurs, the processor completes the current
instruction and starts the implementation of an Interrupt Service Routine (ISR) or
Interrupt Handler.

ISR is a program that tells the processor what to do when the interrupt occurs. After
the ISR execution, control returns to the main routine where it was interrupted.

Task Performed:
In the 8086 microprocessor following tasks are performed when the microprocessor
encounters an interrupt:

1. The value of the flag register is pushed into the stack. It means that first, the
value of SP (Stack Pointer) is decremented by two then the value of the flag
register is pushed to the memory address of the stack segment.
2. The value of starting memory address of CS (Code Segment) is pushed
into the stack.
3. The value of IP (Instruction Pointer) is pushed into the stack.
4. IP is loaded from word location (Interrupt type) * 04.
5. CS is loaded from the following word location.
6. Interrupt, and Trap flags are reset to 0.

Types of Interrupts

The different types of interrupts present in the 8086 microprocessor are given by:

1. Hardware Interrupts – Hardware interrupts are those interrupts that are


caused by any peripheral device by sending a signal through a specified pin
to the microprocessor. There are two hardware interrupts in the 8086
microprocessor. They are:
o NMI (Non-Maskable Interrupt): It is a single pin non-maskable
hardware interrupt that cannot be disabled. It is the highest priority
interrupt in the 8086 microprocessor. After its execution, this
interrupt generates a TYPE 2 interrupt. IP is loaded from word
location 00008 H, and CS is loaded from the word location 0000A
H.
o INTR (Interrupt Request): It provides a single interrupt request and
is activated by the I/O port. This interrupt can be masked or
delayed. It is a level-triggered interrupt. It can receive any interrupt
type, so the value of IP and CS will change on the interrupt type
received.
2. Software Interrupts – These are instructions inserted within the program to
generate interrupts. There are 256 software interrupts in the 8086
microprocessor. The instructions are of the format INT type, where the type
ranges from 00 to FF. The starting address ranges from 00000 H to 003FF
H. These are 2-byte instructions. IP is loaded from type * 04 H, and CS is
loaded from the following address given by (type * 04) + 02 H. Some
important software interrupts are:
o TYPE 0 corresponds to division by zero(0).
o TYPE 1 is used for single-step execution for debugging the
program.
o TYPE 2 represents NMI and is used in power failure conditions.
o TYPE 3 represents a break-point interrupt.
o TYPE 4 is the overflow interrupt.

Uses of Interrupts

Some common uses of interrupts include:

• Hardware Signals: Handling hardware events like keyboard input, mouse


movements, or incoming data from peripherals.
• Timer Interrupts: Facilitating time-related tasks, such as updating system time,
managing delays, or scheduling processes.
• Exception Handling: Dealing with exceptional conditions like divide-by-zero
errors, invalid memory accesses, or other faults.
• I/O Operations: Managing input and output operations, allowing the CPU to
perform other tasks while waiting for data transfer to or from devices.

interrupt vector table


An interrupt vector table (IVT) is a data structure that associates a list of interrupt
handlers with a list of interrupt requests in a table of interrupt vectors. Each entry of
the interrupt vector table, called an interrupt vector, is the address of an interrupt
handler (also known as ISR). For example, a dispatch table is one method of
implementing an interrupt vector table.
Interrupts are assigned a number between 0 to 255. The interrupt vectors for
each interrupt number are stored in the lower 1024 bytes of main memory. For
example, interrupt 0 is stored from 0000:0000 to 0000:0003, interrupt 1 from
0000:0004 to 0000:0007, and so on.

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