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MP Exp2

The document explains various addressing modes of the 8086 microprocessor, detailing how operands are identified and accessed during instruction execution. It also covers the block diagrams and functionalities of the 8255, 8257, and 8259 devices, including their operating modes and control signals. Additionally, it includes explanations of specific assembly instructions and provides example programs for finding the largest number in an array and reversing a string.

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0% found this document useful (0 votes)
8 views12 pages

MP Exp2

The document explains various addressing modes of the 8086 microprocessor, detailing how operands are identified and accessed during instruction execution. It also covers the block diagrams and functionalities of the 8255, 8257, and 8259 devices, including their operating modes and control signals. Additionally, it includes explanations of specific assembly instructions and provides example programs for finding the largest number in an array and reversing a string.

Uploaded by

nayosrkr
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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1.

Explain addressing modes of 8086


Addressing modes specify how an instruction identifies the data, or operands. It operates
on in assembly language. This field indicates whether the operand is a direct value, a
memory address, or stored in a register. Addressing modes are important during instruction
execution, as they define the form of an operand and the way data is accessed, making sure
proper data handling at the machine level.
Types of Addressing Modes
Register Mode: In this type of addressing mode both the operands are registers.
Example:
MOV AX, BX
XOR AX, DX
ADD AL, BL
Immediate Mode: In this type of addressing mode the source operand is a 8 bit or 16 bit data.
Destination operand can never be immediate data.
Example:
MOV AX, 2000
MOV CL, 0A
ADD AL, 45
AND AX, 0000
Displacement or Direct Mode: In this type of addressing mode the effective address is
directly given in the instruction as displacement.
Example:
MOV AX, [DISP]
MOV AX, [0500]
Register Indirect Mode: In this addressing mode the effective address is in SI, DI or BX.
Example: Physical Address = Segment Address + Effective Address
MOV AX, [DI]
ADD AL, [BX]
MOV AX, [SI]
Based Indexed Mode: In this the effective address is sum of base register and index register.
Base register: BX, BP
Index register: SI, DI
Indexed Mode: In this type of addressing mode the effective address is sum of index register
and displacement.
Example:
MOV AX, [SI+2000]
MOV AL, [DI+3000]
Based Mode: In this the effective address is the sum of base register and displacement.
Example:
MOV AL, [BP+ 0100]
Based Indexed Displacement Mode: In this type of addressing mode the effective
address is the sum of index register, base register and displacement.
Example:
MOV AL, [SI+BP+2000]
String Mode: This addressing mode is related to string instructions. In this the value of SI and
DI are auto incremented and decremented depending upon the value of directional flag.
Example:
MOVS B
MOVS W
Input/Output Mode: This addressing mode is related with input output operations.
Example:
IN A, 45
OUT A, 50
Relative Mode: In this the effective address is calculated with reference to instruction
pointer.
Example:
JNZ 8 bit address
IP=IP+8 bit address
2. Draw and explain block diagram of 8255.
PPI 8255 is a general purpose programmable I/O device designed to interface the CPU with its outside
world such as ADC, DAC, keyboard etc. We can program it according to the given condition. It can be
used with almost any microprocessor. It consists of three 8-bit bidirectional I/O ports i.e. PORT A, PORT
B and PORT C. We can assign different ports as input or output functions.

It consists of 40 pins and


operates in +5V regulated power supply. Port C is further divided into two 4-bit ports i.e. port C lower
and port C upper and port C can work in either BSR (bit set rest) mode or in mode 0 of input-output
mode of 8255. Port B can work in either mode 0 or in mode 1 of input-output mode. Port A can work
either in mode 0, mode 1 or mode 2 of input-output mode. It has two control groups, control group A
and control group B. Control group A consist of port A and port C upper. Control group B consists of port
C lower and port B. Depending upon the value if CS’, A1 and A0 we can select different ports in different
modes as input-output function or BSR. This is done by writing a suitable word in control register
(control word D0-D7).
CS’ A1 A0 Selection Address

0 0 0 PORT A 80 H

0 0 1 PORT B 81 H

0 1 0 PORT C 82 H

0 1 1 Control Register 83 H

1 X X No Seletion X
Pin diagram –

8255 pin diagram :


PA0 – PA7 – Pins of port A
PB0 – PB7 – Pins of port B
PC0 – PC7 – Pins of port C
D0 – D7 – Data pins for the transfer of data
RESET – Reset input
RD’ – Read input
WR’ – Write input
CS’ – Chip select
A1 and A0 – Address pins
Operating modes –
Bit set reset (BSR) mode – If MSB of control word (D7) is 0, PPI works in BSR mode. In this mode only
port C bits are used for set or reset.

Input-Output mode – If MSB of control word (D7) is 1, PPI works in input-output mode. This is further
divided into three modes:

Mode 0 –In this mode all the three ports (port A, B, C) can work as simple input function or simple
output function. In this mode there is no interrupt handling capacity.
Mode 1 – Handshake I/O mode or strobed I/O mode. In this mode either port A or port B can work as
simple input port or simple output port, and port C bits are used for handshake signals before actual
data transmission. It has interrupt handling capacity and input and output are latched. Example: A CPU
wants to transfer data to a printer. In this case since speed of processor is very fast as compared to
relatively slow printer, so before actual data transfer it will send handshake signals to the printer for
synchronization of the speed of the CPU and the peripherals.

Mode 2 – Bi-directional data bus mode. In this mode only port A works, and port B can work either in
mode 0 or mode 1. 6 bits port C are used as handshake signals. It also has interrupt handling capacity.
3. Draw and explain block diagram of 8257.
Suppose any device which is connected to input-output port wants to transfer data to memory, first of
all it will send input-output port address and control signal, input-output read to input-output port, then
it will send memory address and memory write signal to memory where data has to be transferred. In
normal input-output technique the processor becomes busy in checking whether any input-output
operation is completed or not for next input-output operation, therefore this technique is slow.
This problem of slow data transfer between input-output port and memory or between two memory is
avoided by implementing Direct Memory Access (DMA) technique. This is faster as the
microprocessor/computer is bypassed and the control of address bus and data bus is given to the DMA
controller.

HOLD – hold signal

HLDA – hold acknowledgment

DREQ – DMA request

DACK – DMA acknowledgment

Suppose a floppy drive that is connected at input-output port wants to transfer data to memory, the
following steps are performed:

Step-1: First of all the floppy drive will send a DMA request (DREQ) to the DMAC, it means the floppy
drive wants its DMA service.

Step-2: Now the DMAC will send a HOLD signal to the CPU.

Step-3: After accepting the DMA service request from the DMAC, the CPU will send hold
acknowledgment (HLDA) to the DMAC, it means the microprocessor has released control of the address
bus the data bus to DMAC and the microprocessor/computer is bypassed during DMA service.

Step-4: Now the DMAC will send one acknowledgement (DACL) to the floppy drive which is connected at
the input-output port. It means the DMAC tells the floppy drive be ready for its DMA service.

Step-5: Now with the help of input-output read and memory write signal the data is transferred from
the floppy drive to the memory.

Modes of DMAC:
1. Single Mode – In this only one channel is used, means only a single DMAC is connected to the
bus system.
2. Cascade Mode – In this multiple channels are used, we can further cascade more number of
DMACs.

4. Draw and explain block diagram of 8259.


8259 microprocessor can be programmed according to given interrupts condition and it can be provided
either with level or edge-triggered interrupt level.
It can be programmed to either work in 8085 or in 8086 microprocessors.
Individual interrupt bits can be masked.
By cascading Nine 8259’s in Master-Slave Configuration we can handle up to 64 interrupt pins.

It contains 3 registers commonly known as ISR, IRR, IMR & there is 1 priority resolver (PR).

Interrupt Request Register (IRR): It stores those bits which are requested for their interrupt services.
Interrupt Service Register (ISR): It stores the interrupt levels which is currently being served.
Interrupt Mask Register (IMR): It stores interrupt levels that have to be masked. These interrupt levels
are already accepted by the 8259 microprocessor.
Priority Resolver (PR): It examines all the 3 registers and sets the priority of interrupts and sets the
interrupt levels in ISR which has the highest priority and the rest of the interrupt bit is IRR which is
already accepted.
SP/EN (low active pin): If its value is 1 it works in master mode & if its value=e is 0 then it works in slave
mode.
Cascade Buffer: It is used to cascade more number of Programmable Interrupt Controller to increase the
interrupts handling capability up to 64 levels.
5. Explain following instructions: XLAT, XCHG, MOVSB, DAA,
CMC
1. XLAT (Translate)
Operation:
The XLAT instruction is used to perform a byte translation using the lookup table that is based on the
value of the AL register and an offset. The XLAT instruction translates the byte value in the AL register
using the table pointed to by the DS:BX register pair. After execution, the result of the translation is
stored back into the AL register.
Syntax:
nginx
Copy
XLAT
Explanation:
The AL register contains an index that is used to look up a byte in the table.
The address of the lookup table is pointed to by DS:BX.
The byte at the table address corresponding to the value in AL (as an index) is loaded into AL.
Example:
If DS:BX = 2000h, and AL = 5, the byte located at DS:BX + AL (which would be 2005h) is loaded into AL.

2. XCHG (Exchange)
Operation:
The XCHG instruction swaps the contents of two operands, which can be either registers or a register
and a memory location.
Syntax:
bash
Copy
XCHG destination, source
Explanation:
destination and source can either be two registers, or one register and a memory location.
The contents of the destination and source operands are exchanged.
Example:
objectivec
Copy
XCHG AX, BX
This swaps the contents of the AX and BX registers.
The XCHG instruction does not affect the flags except for the CF (Carry Flag) when used with memory
operands.

3. MOVSB (Move String Byte)


Operation:
The MOVSB instruction is used to move a byte from a source to a destination. It operates on strings, so
it moves the byte from the memory location addressed by SI (Source Index) to the memory location
addressed by DI (Destination Index). The SI and DI registers are automatically updated after each
operation.
Syntax:
nginx
Copy
MOVSB
Explanation:
MOVSB moves a byte from [DS:SI] to [ES:DI]. After the move, SI and DI are incremented or
decremented based on the direction flag.
If the DF (Direction Flag) is cleared (0), both SI and DI are incremented. If the DF is set (1), both SI and DI
are decremented.
Example:
nginx
Copy
MOVSB
If SI = 1000h and DI = 2000h, the byte at DS:1000h is copied to ES:2000h, and SI and DI are updated
accordingly (either incremented or decremented based on the DF flag).

4. DAA (Decimal Adjust AL After Addition)


Operation:
The DAA instruction is used after ADD or ADC operations when performing BCD (Binary-Coded Decimal)
arithmetic. It adjusts the contents of the AL register to make it a valid BCD number.
Syntax:
nginx
Copy
DAA
Explanation:
After adding two packed BCD numbers, DAA adjusts the AL register to ensure the result remains a valid
BCD number (i.e., a number where each nibble is in the range 0-9).
The DAA instruction only affects the AL register and the flags register (specifically CF, OF, AF).
Example:
Let's assume AL = 25h and AH = 23h (after an ADD operation).
The result would be 48h, which is not a valid BCD number.
After executing DAA, AL would be adjusted to 48h, which is a valid BCD result for 48.

5. CMC (Complement Carry Flag)


Operation:
The CMC instruction is used to complement the Carry Flag (CF) in the FLAGS register, meaning if CF is 0,
it becomes 1, and if CF is 1, it becomes 0.
Syntax:
objectivec
Copy
CMC
Explanation:
CMC simply flips the Carry Flag. It does not affect any other flags or registers.
Example:
If the CF is 0 before the CMC instruction is executed, it will be changed to 1 after executing CMC.
6. Write an assembly language programming to find the largest
number from a given array.
Problem – Determine largest number in an array of n elements. Value of n is stored at address 2050 and
array starts from address 2051. Result is stored at address 3050. Starting address of program is taken as
2000.
Example:

Algorithm:
We are taking first element of array in A
Comparing A with other elements of array, if A is smaller then store that element in A otherwise compare
with next element
The value of A is the answer
Program:

Memory Address Mnemonics Comment

2000 LXI H 2050 H←20, L←50

2003 MOV C, M C←M

2004 DCR C C←C-01

2005 INX H HL←HL+0001

2006 MOV A, M A←M

2007 INX H HL←HL+0001

2008 CMP M A-M

2009 JNC 200D If Carry Flag=0, goto 200D

200C MOV A, M A←M

200D DCR C C←C-1


Memory Address Mnemonics Comment

200E JNZ 2007 If Zero Flag=0, goto 2007

2011 STA 3050 A→3050

2014 HLT
Explanation:
Registers used: A, H, L, C
LXI 2050 assigns 20 to H and 50 to L
MOV C, M copies content of memory (specified by HL register pair) to C (this is used as a counter)
DCR C decrements value of C by 1
INX H increases value of HL by 1. This is done to visit next memory location
MOV A, M copies content of memory (specified by HL register pair) to A
INX H increases value of HL by 1. This is done to visit next memory location
CMP M compares A and M by subtracting M from A. Carry flag and sign flag becomes set if A-M is
negative
JNC 200D jumps program counter to 200D if carry flag = 0
MOV A, M copies content of memory (specified by HL register pair) to A
DCR C decrements value of C by 1
JNZ 2007 jumps program counter to 2007 if zero flag = 0
STA 3050 stores value of A at 3050 memory location
HLT stops executing the program and halts any further execution
7. Write an assembly language programming to reverse the string.
.MODEL SMALL
.STACK 100H
.DATA

; The string to be printed


STRING DB 'This is a sample string', '$'

.CODE
MAIN PROC FAR
MOV AX,@DATA
MOV DS,AX

; call reverse function


CALL REVERSE

; load address of the string


LEA DX,STRING

; output the string


; loaded in dx
MOV AH, 09H
INT 21H

; interrupt to exit
MOV AH, 4CH
INT 21H

MAIN ENDP
REVERSE PROC
; load the offset of
; the string
MOV SI, OFFSET STRING

; count of characters of the;


;string
MOV CX, 0H

LOOP1:
; compare if this is;
;the last character
MOV AX, [SI]
CMP AL, '$'
JE LABEL1

; else push it in the;


;stack
PUSH [SI]

; increment the pointer;


;and count
INC SI
INC CX

JMP LOOP1

LABEL1:
; again load the starting;
;address of the string
MOV SI, OFFSET STRING

LOOP2:
;if count not equal to zero
CMP CX,0
JE EXIT

; pop the top of stack


POP DX
; make dh, 0
XOR DH, DH

; put the character of the;


;reversed string
MOV [SI], DX

; increment si and;
;decrement count
INC SI
DEC CX

JMP LOOP2

EXIT:
; add $ to the end of string
MOV [SI],'$ '
RET

REVERSE ENDP
END MAIN

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