7 © BASIC PROCESSING UNIT CHAPTER inputs Decoder! encoder Condition : codes Control signals Figure 7.10 Control unit See ae To gain insight into the structure of the control unit, we start with a simplified view of the hardware involved. The decoder/encoder block in Figure 7.10 is a combinational circuit that generates the required control outputs, depending on the state of all its inputs. By separating the decoding and encoding functions, we obtain the more detailed block ram in Figure 7.11. The step decoder provides a separate signal line for each step, or time slot, in the control sequence. Similarly, the output of the instruction decoder consists of a separate line for each machine instruction. For any instruction loaded in the IR, one of the output lines INS, through INS,,, is set to 1, and all other lines are set to 0. (For design details of decoders, refer to Appendix A.) The input signals to the encoder block in Figure 7.11 are combined to generate the individual control signals Yin» PCow, Add, End, and so on, An example of how the encoder generates the Zin control signal for the processor organization in Figure 7.1 is given in Figure 7.12. This circuit implements the logic function Zin =T, +T5-ADD+T,-BR+--- 7. This signal is asserted during time slot T; for all instructions. during Ts for an Add instruction, during T, for an unconditional branch instruction, and so on. The logic function for Z;, is derived from the control sequences in Figures 7.6 and 7.7. As another example, Figure 7.13 give ircui 5 ~ . fineton gi Bives a circuit that generates the End control signal from the logi¢ End = 17 ADD +T;-BR+(Ts-N+T,-N).BRN+--. al The End signal starts a new ing truction fetch cycle by res a, ” to its starting value, Figure 7. fetch cycle by resetting the control step counter! 11 contains another control signal called RUN. Wheoe ENRDWIRED CONTROL aur Instruction IR : decoder Encoder figure 7.11 Separation of the decoding and encoding functions, Branch Add Figure 7.12 Gecnapran 7 * Bast PROCESSING UNIT Branch<0. Branch Add Ts Ts End Figure 7.13 Generation of the End control signal. set to 1, RUN causes the counter to be incremented by one at the end of every clock cycle. When RUN is equal to 0, the counter stops counting. This is needed whenever the WMEC signal is issued, to cause the processor to wait tor the reply from the memory. The control hardware shown in Figure 7.10 or 7.11 can be viewed as a state machine that changes from one state to another in every clock cycle, depending on the contents of the instruction register, the condition codes, and the external inputs. The outputs of the state machine are the control signals. The sequence of operations carried out by this machine is determined by the wiring of the logic elements, hence the name “hardwired. : A controller that uses this approach can operate at high speed. However, it has Tittle flexibility, and the complexity of the instruction set it can implement is limited. 741 A COMPLETE PRoc SOR A complete proces: ‘ocessor cz ; strcure has an insta can be designed using the structure shown in Figure 7.14. This from the main hemor eh unit that fetches instructions from an instruction cache oF has separate processing when the desired instructions are not already in the cache. It these unite coe ne ae its to deal with integer data and floating-po can be organize B c these units and the nae as shown in Figure 7.8. A data cache is inserted betwee! lemory. Using se = ena! y. Using separate caches for instructions and data 1s commons clice non practice in many processors today. Other wweikindagete 5 point data. Each o! y einela anche that130 or Micro inetuetion | ++ | 52 | $2 | ~ il iiote ol * 0 a 0 OO) 1 Olin Oi iio 2 1 ‘ 010 0/0'0 0 olvle : | i jolo 9 0folololrlolg 0/0 olofoltiolnlr ie 6 | 0/0/0/0 1,0, 0.0 1 lidiolg Q ma Of Of 010/910] 0;o! 1, olyin g , 7 | |olo | a de '9€ Figure 7.15 An example of microinstructions for Figure 7.6 First, we introduce some common terms. A control word (CW) is a word whose individual bits represent the various control signals in Figure 7.11 h of the contro} steps in the control sequence of an instruction. defines a unique combination of js and 0s in the CW. The CWs corresponding to the 7 steps of Figure 7.6 are shown in Figure 7.15. We have assumed that SelectY is represented by Select = 0 and Select by Select = I. A sequence of CWs corresponding to the control sequence of a machine instruction constitutes the microroutine for that instruction, and the individual control words in this microroutine are referred to as microinstruction’. - The microroutines for all instructions in the instruction set of a computer are stored ina special memory called the control store. The control unit can generate the control signals for any instruction by Sequentially reading the CWs of the corresponding mi- croroutine from the control store. This suggests organizing the control unit as shown in Figure 7.16. To read the control words sequentially trom the control store. a mim program counter (uPC) is used, Every time a new instruction is loaded into the IR. the output of the block labeled “starting address generator” is loaded into the PC The ueC is then automatically incremented by the clock, causing successive microin Structions to be read from the control store. Hence. the control signals are delivered to Various parts of the processor in the correct sequence. - ogni a fuseton of the control unit cannot be implemented by the simple gl -16. This is the situation that arises when the control unit Status of the condition codes or external inputs to choose ine as matin. In the case of hardwired control this situation is icroprogrammed comme function, as in Equation 7.2, in the encoder a " ‘ol, an alternative approach is to use conditional addition to the branch address. these microinstruction Codes. or. possibly, bits of the instructior He. instruction Branch =o Condition for branching to take pl “0 May now be implemented by a microroutine such as thal After loading this 2 . ie instruction into IR lace. 1 branch microinstructiControl Lv, cy store Figure 7.16 Basic organization of o microprogrammed control unit Address Microinstruction 0 PC out. MAR,,.. Read, Select 4, Add. Z, 1 Zot. PCin. Yin. WMEC 2 MDR, 2. IR. 3 Branch to starting address of appropriate microrontine 25 If N=0, then branch to micr 0 Offset-ficld-of TRae. Select, Add. 7 7 Zour PC... End Figure 7.17. Microroutine for the instruction Bronch - 0 transfers control to the corresponding microroutine, which ts assumed to start at location 25 in the control store. This address 1s the output of the starting address generator block in Figure 7.16. The microinstruction at location 25 tests the N bit of the condition codes. If this bit is equal to 0, a branch takes place to location 0 to fetch a new machine instruction, Otherwise, the microinstruction at locaton 26 1s executed to put the branch target address into register Z, as in step 4 in Figure 7.7. The microinstruction in locauion 27 loads this address into the PCprocessinG UNIT cuaprer 7 + Basic r External | inputs — | | Starting and Condition ie branch address codes generator Control store cw Figure 7.18 Organization of the control unit to allow conditional branching in the microprogram. To support microprogram branching, the organization of the control unit should be modified as shown in Figure 7.18. The starting address generator block of Figure 7.16 becomes the starting and branch address generator. This block loads a new address into the PC when a microinstruction instructs it to do so. To allow implementation of a conditional branch, inputs to this block consist of the external inputs and condition codes as well as the contents of the instruction register. In this control unit, the PC is incremented every time a new microinstruction is fetched from the microprogram memory, except in the following situations: |. When a new instruction is loaded into the IR, the zPC is loaded with the starting address of the microroutine for that instruction. 2 re sae 2. a 4 Branch microinstruction is encountered and the branch condition is satis- ed, the PC is loaded with the branch address, 3. Whey Fee eg often ee struction is encountered, the jzPC is loaded with the address in the mic Ben shia . . fi inFigure 71, ¢ microroutine for the instruction fetch cycle (this address is 0 me 5.1 Mic RONSTRUCT IONS Having des, escribed a so look at th 4 Scheme for sequence; at the formar ue ‘quencing microinstrucs micrsinse of individual icone Microinstructions, we now take a closer ics nstructions, A straightforward w Position to each control sienal ICtIONS is to g S (0 assign one ay to structure ne in Bn 1ethis scheme has one serious drawback — assigning individual bits to each nal results in long microinstructions because the number of required signals Moreover. only a few_ are _set to | (to be used for active gating) waldven microinstruction, which means the available bit space is poorly used. » sce again the simple processor of Figure 7.1, and assume that it contains only veral-purpose registers, RO, RI, R2, and R3. Some of the connections in this permanently enabled, such as the output of the IR to the decoding circuits s to the ALU. The remaining connections to various registers require a signals, Additional control signals not shown in the figure are also ‘cluding the Read, Write, Select, WMFC, and End signals. Finally, we must specify the function t0 be performed by the ALU. Let us assume that 16 fun provided, including Add, Subtract, AND, and XOR. These functions depe narticular ALU used and do not necessarily have a one-to-one correspondence with the hine instruction OP codes. In total, 42 control signals are needed.” \ Trwe use the simple encoding scheme described ezrlier, 42 bits woud be needed in cach microinstruction. Fortunately, the length of the microinstructions can be reduced Shily. Most signals are not needed simultaneously, and many signals are mutually jve(Gor example, only one function of the ALU can be activated at a timeyethe source for a data transfer must be unique because it is not possible to gate the contents of two different registers onto the bus at the same timeRead and Write signals to the memory cannot be active simultaneously) This suggests that signals can be grouped so that all mutually exclusive signals are placed in the same group. Thus, at most one niicrooperation per group is specified in any microinstruction. Then it is possible to sea binary coding scheme to represent the signals within a group. ‘For example{ four bits suffice to represent the 16 available functions in the ALU. Register output control signals can be placed in a group consisting of PCour, MDRow+ Zour Offsetour, RO ous Rl ours R2ous R3 ours and TEMPo,:.Any one of these can be selected by a unique 4-bit code. Further natural groupings can be made for the remaining signals. Figure 7.19 shows an example of a partial format for the microinstructions, in which each group occupies afield large enough to contain the required codes. Most fields must include one inactive codé for the case in which no. action is required. For example, the all-zero pattern in Fl indicates that none of the registers that may be specified in this field should have its contents placed on the bus. An inactive code is not needed in all fields. For example, F4 contains 4 bits that specify one of the 16 operations performed in the ALU. Since no spare code is included, the ‘ALUisactive during the execution of every microinstruction. However, its activity is monitored by the rest of the machine through register Z, which is loaded only when the Zj, signal is activated. Grouping control signals into fields requires a little more hardware because decod- ing circuits must be used to decode the bit patterns of each field into individual control signals. The cost of this additional hardware is more than offset by the reduced number of bitin each microinstruction, which results in a smaller control store. In Figure 7.19, only 20 bits are needed to store the patterns for the 42 signals. So far we have considered grouping and encoding only mutually exclusive control signals. We can extend this idea by enumerating the patterns of required signals in all possible microinstructions. Each meaningful combination of active control signals can plowevel vol sig « ysually Fa in ar ssor are proce dnd both inputs fotal of 20 gating needed, in maclMicroinstruction - = a] ca F3 (G bits) F4 (4 bits) FS (2 bits) 2 (3 bits) js FI (4 bits) 000: No transfer 0000: Add 00: No action . 00: io transfe (00; No wansfer 000: No ra a 001: MAR, 0001: Sub Ol: Read 001: PCy ; Coat DRin : 10: Write ae hon «010: IRin pe st ea Zyy LZ a. Y, ALE XOR 100: RO,, 1 100: ROjq a ye a 101: Rlin 16 ALU 1: Rl owe i rr Rout 110: R2jn functions OUT: R3 jay PUP RSin 1010: TEMP, LOM: OfF8et _ _ _ 0: SelectY No action 0: Continue 1: Select4 ls WMFC 1: End Figure 7.19 An example of a partial format for field-encoded microinstructions. then be assigned a distinct code that represents the microinstruction, Such full encoding is likely to further red luce the length of microwords but also to increase the complexity of the required decoder circuits. ee Highly encoded Schemes that use co; control fy mMpact codes to specify only a small number of tneach microinstruction are referred to as a vertical organization. On le minimally encoded Scheme of Figure 7.15, in which man: 'd with a single microinstruction, 1s called a hori: &pproach is useful when a higher o i arallel of resources. The y nore mi junctions een resources The ae zontal organization. ed is desired and when ertical approach resulis, Toinstructions are needed bits are required Tor each f bits in the control store is led to handle the execution eis need