JAYA ENGINEERING COLLEGE

Approved by AICTE & Affiliated to Anna University,

Chennai
(NAAC Accredited Institution)
CTH Road, Prakash Nagar, Thiruninravur, Chennai, Tamil Nadu
- 602024

DEPARTMENT OF COMPUTER SCIENCE ENGINEERING PRACTICAL RECORD

CS3351 – DIGITAL PRINCIPLES AND COMPUTER ORGANIZTIONLABORATORY

NAME :

REG NO. :

YEAR :

SEM :
 ANNA UNIVERSITY
JAYA ENGINEERING COLLEGE
Approved by AICTE & Affiliated to Anna University, Chennai
(NAAC Accredited Institution)
CTH Road, Prakash Nagar, Thiruninravur, Chennai, Tamil Nadu - 602024

BONAFIDE CERTIFICATE

This is to certify that this is a bonafide record of work done by

Mr./Ms.................................................................................Reg.No. ..............................................

of BE-Computer Science Engineering in CS3351-DIGITAL PRINCIPLES AND

COMPUTER ORGANIZTION LABORATORY in the III semester during AUGUST

2022 to JANUARY 2023.

Head of the Department Staff-In-Charge

Submitted For Practical Examination Held On .......................................

Internal Examiner External Examiner

 INDEX

PO’s &
EX.NO DATE NAME OF EXPERIMENT COs MARK SIGN
PSO’s
VISION AND MISSION OF THE INSTITUTE
Vision of the Institute
To achieve excellence in technical education through innovative teaching and multidisciplinary research with
professional is to serve the global society.

Mission of the Institute

Jaya Engineering College will Endeavor
M1-To provide state of art teaching and learning for Engineering and Technology, Research and Management
studies. M2-To provide quality education, self discipline and ethical values.
M3-To associate with R&D and industries to have connectivity with the society.
M4 –To impart knowledge to become empowered professionals in the field of Engineering and Management.

VISION AND MISSION OF THE DEPARTMENT

Vision of the Department
To achieve Excellence in Computer Science and Engineering by providing quality technical education to cater the
need of industry and society through research and development.

Mission of the Department

The Computer Science and Engineering Department is committed to:
M1: Provide strong fundamentals and technical skills in Computer Science Engineering through Effective teaching and
learning methods.
M2: Impart high quality experiential learning to get expertise in modern software tools and to procure the real-time
requirements of the industry.
M3: Inculcate problem solving and team building skills and promote lifelong learning with a sense of societal and
ethical responsibilities.

PROGRAM EDUCATIONAL OBJECTIVES

Graduates can
PEO1: Apply their technical competence in computer science to solve real world problems, with technical and people
leadership.
PEO2: Conduct cutting edge research and develop solutions on problems of social relevance.
PEO3: Work in a business environment, exhibiting team skills, work ethics, adaptability and lifelong learning.

PROGRAMSPECIFICOUTCOMES
Engineering Graduates will be able to
PSO1: Exhibit design and programming skills to build and automate business solutions using cutting edge
technologies
PSO2: Strong theoretical foundation leading to excellence and excitement towards research, to provide elegant
solutions to complex problems.
PSO3: Ability to work effectively with various engineering fields as a team to design, build and develop system
applications.
PROGRAMOUTCOMES
Engineering Graduates will be able to

PO1 - Engineering Knowledge: Apply the knowledge of mathematics, science, engineering fundamentals, and an
engineering specialization to the solution of complex engineering problems.

PO2 - Problem Analysis: Identify, formulate, review research literature, and analyze complex engineering
problems reaching substantiated conclusions using first principles of mathematics, natural sciences, and
engineering sciences.

PO3-Design/Development of Solutions: Design solutions for complex engineering problems and design system
components or processes that meet the specified needs with appropriate consideration for the public health and
safety, and the cultural, societal, and environmental considerations.

PO4 - Conduct investigations of complex problems: Use research-based knowledge and research methods
including design no of experiments, analysis and interpretation of data and synthes is of the information to provide
valid conclusions.

PO5 - Modern tool usage: Create, select, and apply appropriate techniques, resources, and modern engineering and
it tools including prediction and modeling to complex engineering activities with an understanding of the
limitations.

PO6 - the engineer and society: Apply reasoning informed by the contextual knowledge to assess societal, health,
safety, legal and cultural issues and the consequent responsibilities relevant to the professional engineering
practice.

PO7 - Environment and sustainability: Understand the impact of the professional

engineeringsolutionsinsocietalandenvironmentalcontexts,anddemonstratetheknowledgeof, and need for sustainable
development.

PO8-Ethics: Apply ethical principles and commit to professional ethics and responsibilities and norms of the
engineering practice.

PO9-Individual and team work: Function effectively as an individual, and as a member or leader in diverse teams,
and in multidisciplinary settings.

PO10 - Communication: Communicate effectively on complex engineering activities with the engineering
community and with society at large, such as, being able to comprehend and write effective reports and design
documentation, make effective presentations, and give and receive clear instructions.

PO11 - Project management and finance: Demonstrate knowledge and understanding of the engineering and
management principles and apply these to one’s own work, as a member and leader in a team, to manage projects
and in multi disciplinary environments.

PO12-Life-long learning: Recognize the need for, and have the preparation and ability to engage in independent
and life-long learning in the broadest context of technological change.

COURSE OUTCOMES

At the end of this course, the students will be able to

CO1: Design various combinational digital circuits using logic gates.
CO2: Design sequential circuits and analyze the design procedures.
CO3 : State the fundamentals of computer systems and analyze the execution of an instruction.
CO4 : Analyze different types of control design and identify hazards.
CO5 : Identify the characteristics of various memory systems and I/O communication.
 SYLLABUS

CS3351 DIGITAL PRINCIPLES AND COMPUTER ORGANIZATION LT PC30 24

OBJECTIVES:
 To analyze and design combinational circuits.
 To analyze and design sequential circuits

List of Experiments:

1. Verification of Boolean theorems using logic gates.

2. Design and implementation of combinational circuits using gates for arbitrary functions.
3. Implementation of 4-bit binary adder / Subtractor circuits.
4. Implementation of code converters.
5. Implementation of BCD adder, encoder and decoder circuits
6. Implementation of functions using Multiplexers.
7. Implementation of the synchronous counters
8. Implementation of a Universal Shift register.
9. Simulator based study of Computer Architecture

Experiments beyond the Syllabus:

10. Design of Hazard Free Circuits.

11. Simulator based study of Control Unit Design.
TOTAL: 30 PERIODS

COURSE OUTCOMES:

At the end of this course, the students will be able to:

CO1: Design various combinational digital circuits using logic gates.

CO2: Design sequential circuits and analyze the design procedures.

CO3 : State the fundamentals of computer systems and analyze the execution of an instruction.

CO4 : Analyze different types of control design and identify hazards.

CO5 : Identify the characteristics of various memory systems and I/O communication.
EXPT. NO.:1
STUDY OF LOGIC GATES
DATE:

AIM:

To study about logic gates and verify their truth tables.

APPARATUS REQUIRED:

SL.NO. COMPONENT SPECIFICATION QTY

1. AND GATE IC 7408 1
2. OR GATE IC 7432 1
3. NOT GATE IC 7404 1
4. NAND GATE 2 I/P IC 7400 1
5. NOR GATE IC 7402 1
6. X-OR GATE IC 7486 1
7. NAND GATE 3 I/P IC 7410 1
8. IC TRAINER KIT - 1
9. PATCH CORD - 14

THEORY:
Circuit that takes the logical decision and the process are called logic gates. Each gate
has one or more input and only one output. OR, AND and NOT are basic gates. NAND and
NOR known as universal gates. Basic gates form these gates.
AND GATE:
The AND gate performs a logical multiplication commonly known as AND function.
The output is high when both the inputs are high. The output is low level when any one of the
inputs is low.
OR GATE:
The OR gate performs a logical addition commonly known as OR function. The output
is high when any one of the inputs is high. The output is low level when both the inputs are
low.
NOT GATE:
The NOT gate is called an inverter. The output is high when the input is low. The
output is low when the input is high.
NAND GATE:
The NAND gate is a contraction of AND-NOT. The output is high when bothinputs
are low and any one of the input is low .The output is low level when both inputs are high.
NOR GATE:
The NOR gate is a contraction of OR-NOT. The output is high when both inputs are
low. The output is low when one or both inputs are high.

X- OR GATE:
The output is high when any one of the inputs is high. The output is lowwhen both
the inputs are low and both the inputs are high.

PROCEDURE:
(i) Connections are given as per circuit diagram.
(ii) Logical inputs are given as per circuit diagram.
(iii) Observe the output and verify the truth table.
 AND GATE

SYMBOL PIN DIAGRAM

OR GATE
 NOT GATE

SYMBOL PIN DIAGRAM

EX-OR GATE

SYMBOL PIN DIAGRAM

 2-INPUT NAND GATE

SYMBOL PIN DIAGRAM

INPUT NAND GATE

 NOR GATE

RESULT:

The logic gates are studied and its truth tables are verified.
 EXPERIMENT:2
DESIGN AND IMPLEMENTATION OF CODE CONVERTERS
DATE:

AIM:

To design and verify the truth table of the following code converters
a. Binary to Gray converter & vice versa
b. BCD to Excess-3 & vice versa.

REQUIREMENTS:

S. No. Components / Equipments Specifications Quantity

1. Digital IC trainer --- 1

2. Ex-OR Gate IC7486 2

3. AND , OR and NOT IC7408, IC7432 and IC7404 1 each

THEORY:
Binary to GRAY Converter:
By representing the ten decimal digits with a four bit Gray code, we have another form of
BCD code. The Gray code however can be extended to any number of bits and conversion between
binary code and Gray code is sometimes useful. The following rules apply for conversion:
1. The MSB in the Gray code is the same as the corresponding bit in the binary number.
2. Going from left to right, add each adjacent pair of binary bits to get the next Gray code bit.
Disregard carries.
GRAY to Binary Converter:
To convert from Gray code to binary code, A similar method is used, at there are some differences. The
following rules apply:
1. The MSB in the binary code is the same as the corresponding digit in the Gray code
2. Add each binary digit generated to the gray digit in the next adjacent position Disregard carries.
TRUTHTABLE FOR BINARY TO GRAY CODE CONVERTER:

Binary input Gray code output

B3 B2 B1 B0 G3 G2 G2 G0
0 0 0 0 0 0 0 0

0 0 0 1 0 0 0 1

0 0 1 0 0 0 1 1

0 0 1 1 0 0 1 0

0 1 0 0 0 1 1 0

0 1 0 1 0 1 1 1

0 1 1 0 0 1 0 1

0 1 1 1 0 1 0 0

1 0 0 0 1 1 0 0

1 0 0 1 1 1 0 1

1 0 1 0 1 1 1 1

1 0 1 1 1 1 1 0

1 1 0 0 1 0 1 0

1 1 0 1 1 0 1 1

1 1 1 0 1 0 0 1

1 1 1 1 1 0 0 0
K-Map for G3: K-Map for G2:

G3 = B 3 G2=B3+B2

K-Map for G1: K-Map for G0:

G0=B1+B0

Binary to GRAY Logic Diagram :

TRUTH TABLE FOR GRAY CODE TO BINARY CONVERTOR:

Gray code output Binary input

G3 G2 G2 G0 B3 B2 B1 B0
0 0 0 0 0 0 0 0

0 0 0 1 0 0 0 1

0 0 1 1 0 0 1 0

0 0 1 0 0 0 1 1

0 1 1 0 0 1 0 0

0 1 1 1 0 1 0 1

0 1 0 1 0 1 1 0

0 1 0 0 0 1 1 1

1 1 0 0 1 0 0 0

1 1 0 1 1 0 0 1

1 1 1 1 1 0 1 0

1 1 1 0 1 0 1 1

1 0 1 0 1 1 0 0

1 0 1 1 1 1 0 1

1 0 0 1 1 1 1 0

1 0 0 0 1 1 1 1
 K-Map for B3: K-Map for B2:

B3 = G3

K-Map for B1: K-Map for B0:

GRAY to Binary LOGIC DIAGRAM

TRUTH TABLE FOR BCD TO EXCESS-3 CONVERTOR:
BCD input Excess – 3 output
B3 B2 B1 B0 G3 G2 G2 G0
0 0 0 0 0 0 1 1
0 0 0 1 0 1 0 0

0 0 1 0 0 1 0 1

0 0 1 1 0 1 1 0

0 1 0 0 0 1 1 1

0 1 0 1 1 0 0 0

0 1 1 0 1 0 0 1

0 1 1 1 1 0 1 0

1 0 0 0 1 0 1 1

1 0 0 1 1 1 0 0

1 0 1 0 x X x x

1 0 1 1 x X x x

1 1 0 0 x X x x

1 1 0 1 x X x x

1 1 1 0 x X x x

1 1 1 1 x X x x
 K-Map for E3: K-Map for E2:

E3 = B3 + B2 (B0 + B1)

K-Map for E1: K-Map for E0:

BCD TO EXCESS-3 Convertor Logic Diagram

TRUTH TABLE FOR EXCESS-3 TO BCD CONVERTOR:

Excess – 3 Input BCD Output

B3 B2 B1 B0 G3 G2 G1 G0

0 0 1 1 0 0 0 0

0 1 0 0 0 0 0 1

0 1 0 1 0 0 1 0

0 1 1 0 0 0 1 1

0 1 1 1 0 1 0 0

1 0 0 0 0 1 0 1

1 0 0 1 0 1 1 0

1 0 1 0 0 1 1 1

1 0 1 1 1 0 0 0

1 1 0 0 1 0 0 1
 K-Map for A: K-Map for B:

A = X1 X2 + X3 X4 X1

K-Map for C: K-Map for D:

EXCESS-3 TO BCD convertor Logic diagram:

PROCEDURE:

1. Connections are given as per the circuit diagram (Binary to GRAY).

2. Switch on the power supply.
3. Verify the truth table given for different inputs.
4. Repeat the above procedures for other converters.

Results:
Thus the truth tables for Binary to Gray, Gray to Binary and BCD to Excess3 converters
were verified.
EXPERIMENT: DESIGN AND IMPLEMENTATION OF 4 BIT BINARY ADDER /
DATE: SUBTRACTOR USING IC 7483

AIM:
To study the 4 bit binary adder/subtractor using IC7483.

REQUIREMENTS:

S.No. Name of the apparatus Specifications Quantity

1 Digital Trainer kit - 1

2 OR gate IC 7432 1

3 AND gate IC 7408 1

4 Binary Adder / Subtractor IC 7483 2

5 Connecting wires - some

THEORY

The full adder/sub tractors are capable of adding/subtracting only two single digit binary
numbers along with a carry input. But in practice we need to add/subtract binary numbers, which are
much longer than just one bit. To add/subtract two n-bit binary numbers we need to use the n-bit
parallel subtractor/adder.

Binary adder: IC type 7483 is a 4-bit binary parallel adder/subtractor .The two 4-bit input binary
numbers are A1 through A4 and B1 through B4. The sum is obtained from S1 through S4. C0 is the
input carry and C4 the output carry. Test the 4-bit binary adder 7483 by connecting the power supply
and ground terminals. Then connect the four A inputs to a fixed binary numbers such as 1001 and the
B inputs and the input carry to five toggle switches. The five outputs are applied to indicator lamps.
Perform the addition of a few binary numbers and check that the output sum and output carry give the
proper values. Show that when the input carry is equal to 1, it adds 1 to the output sum.

Binary subtractor: The subtraction of two binary numbers can be done by taking the 2’s
complement of the subtrahend and adding it to the minuend. The 2’s complement can be obtained by
taking the 1’s complement and adding. To perform A-B, we complement the four bits of B, add them
to the four bits of A, and add 1 through the input carry. The four XOR gates complement the
bits of B when the mode select M=1(because x Θ 0 = x ) and leave the bits of B unchanged when
M=0(because x Θ 0 = x ) .Thus , when the mode select M is equal to 1, the input carry C0 is equal 1
and the sum output is A plus the 2’s complement of B. when M is equal to 0, the input carry is equal
to 0 and the sum generates A+B.
Functional symbol for IC 7483:

Operand1 Operand2

B3 B2 B1 B0 A3 A2 A1 A0

Cout 4 bit IC 7483 Cin

Output

Pin Diagram of IC7483:

Circuit Diagram for 4-bit Binary adder/subtractor:

3- BIT BINARY ADDER:

4- BIT BINARY SUBTRACTOR

PROCEDURE:
1. Connections are given as per the circuit diagram.
2. Set mode M =0 such that the circuit will operate in addition mode.
3. Set the Value of inputs A as 1001 and B as 1001 note the sum and output carry.
4. Repeat the same step in step 3 by keeping M=1 such that circuit will operate in subtraction mode.

RESULT:
Thus the 4 bit Binary Adder / Subtractor using IC7483 is been implemented for both addition
and subtraction and the corresponding truth tables are verified.
EXPERIMENT:
DESIGN AND IMPLEMENTATION OF BCD ADDER
DATE:

AIM:
To design and implement the BCD adder by using IC7483.

REQUIREMENTS:

S.No. Name of the apparatus Specifications Quantity

1 Digital Trainer kit - 1

2 OR gate IC 7432 1

3 AND gate IC 7408 1

4 Binary Adder / Subtractor IC 7483 2

5 Connecting wires - some

THEORY
The full adder/sub tractors are capable of adding/subtracting only two single digit binary
numbers along with a carry input. But in practice we need to add/subtract binary numbers, which are
much longer than just one bit. To add/subtract two n-bit binary numbers we need to use the n-bit
parallel subtractor/adder.
Binary adder: IC type 7483 is a 4-bit binary parallel adder/subtractor .The two 4-bit input binary
numbers are A1 through A4 and B1 through B4. The sum is obtained from S1 through S4. C0 is the
input carry and C4 the output carry. Test the 4-bit binary adder 7483 by connecting the power supply
and ground terminals. Then connect the four A inputs to a fixed binary numbers such as 1001 and the
B inputs and the input carry to five toggle switches. The five outputs are applied to indicator lamps.
Perform the addition of a few binary numbers and check that the output sum and output carry give the
proper values. Show that when the input carry is equal to 1, it adds 1 to the output sum.
Binary subtractor: The subtraction of two binary numbers can be done by taking the 2’s
complement of the subtrahend and adding it to the minuend. The 2’s complement can be obtained by
taking the 1’s complement and adding. To perform A-B, we complement the four bits of B, add them
to the four bits of A, and add 1 through the input carry. The four XOR gates complement the bits of B
when the mode select M=1(because x Θ 0 = x ) and leave the bits of B unchanged when M=0(because
x Θ 0 = x ) .Thus , when the mode select M is equal to 1, the input carry C0 is equal 1 and the sum
output is A plus the 2’s complement of B. when M is equal to 0, the input carry is equal to 0 and the
sum generates A+B.
Functional symbol for IC 7483:

Operand1 Operand2

B3 B2 B1 B0 A3 A2 A1 A0
Cout 4 bit IC 7483 Cin

Output

Pin Diagram of IC7483:

TRUTH TABLE FOR BCD ADDER:

K MAP

Y = S4 (S3 + S2)
LOGIC DIAGRAM OF BCD ADDER
PROCEDURE:
1. Connections are given as per the circuit diagram.
2. Set mode CE =0 such that the circuit will operate in addition mode.
3. Set the Value of inputs A as 1001 and B as 1001 note the sum and output carry.

RESULT:

Thus the BCD Adder using IC7483 is been implemented for and the corresponding truth
tables are verified.
EXPERIMENT:
DESIGN AND IMPLEMENTATION OF ENCODER
DATE:

AIM:

To construct and verify the 8 X 3 Encoder using logic gates.

REQUIREMENTS:

S. No Components / Equipments Specification Quantity

1. Digital IC trainer kit - 1

2. OR Gate IC7432 3

3. Connecting Wires - Sufficient Numbers

THEORY:

Digital Computers, Microprocessors and other digital systems are binary operated whereas
our language of communication is in decimal numbers and alphabetical characters only. Therefore,
the need arises for interfacing between digital system and human operators. To accomplish this task,
Encoder is used
Logic Diagram:

Truth Table:

INPUT OUTPUT

D0 D1 D2 D3 D4 D5 D6 D7 A B C

1 0 0 0 0 0 0 0 0 0 0

0 1 0 0 0 0 0 0 0 0 1

0 0 1 0 0 0 0 0 0 1 0

0 0 0 1 0 0 0 0 0 1 1

0 0 0 0 1 0 0 0 1 0 0

0 0 0 0 0 1 0 0 1 0 1

0 0 0 0 0 0 1 0 1 1 0

0 0 0 0 0 0 0 1 1 1 1

Outputs:

A = D4 + D5 + D6 + D7
B = D2 + D3 + D6 + D7
C = D1 + D3 + D5 + D7

1
PROCEDURE:
1. Construct the circuit as per the diagram
2. Switch on the power supply.
3. Apply the necessary input and observe the outputs to verify the truth table.

RESULTS:

Thus an 8 x 3 encoder is constructed and verified.

1
EXPERIMENT:
DESIGN AND IMPLEMENTATION OF DECODER
DATE:

AIM:
To design, construct the decoder circuits and implement the function F (A,B,C) = ∑(1,2,4,7) using the
decoder ICs and also driver along with seven segment LED display unit and verify the results.

REQUIREMENTS:

S. No. Components / Equipments Specification Quantity

1. Decoder IC 7447 1

2. Seven Segment Display Common Anode 1

3. Resistors 330Ω 7
4. IC Trainer Kit --- 1
5. Connecting Wires --- Required numbers

THEORY:
The process of taking some type of code and determining what it represents in terms of a recognizable
number or character is called decoding. A decoder is a combinational logic circuit that performs the
decoding function, andproduce an output that indicates the (meaning) of the input code. The decoder is an
important part of the system which selects the cells to be read from and write into. This particular circuit
is called a decoder matrix, or simplya decoder, and has a characteristic that for each of the possible 2 n
binary input number which can be taken by the n input cells, the matrix will have a unique one of its 2 n
output lines selected.

n×2n
n Decoder 2n
Input Output

1
2 X 4
DECODER
:
W0
2×4
X1 W1
Decoder
X2____________________________________________________________ W2

W3

TRUTH TABLE:

INPUTS OUTPUTS
X2 X1 W0 W1 W2 W3
0 0 1 0 0 0
0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 0 0 1

LOGIC CIRCUIT DIAGRAM:

1
7408 3 W0

2
1 2
X2 7404 4 7408 6
W1
5
3
7404 4 9
X1 7408 8
W2
10
12
7408 11
W3
13
3 X 8 DECODER:

Implementation using decoder. F (A,B,C) = ∑(1,2,4,7)

Inputs Output
A B C F
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 1
Solution:

PROCEDURE:
1. Connect the circuit as per circuit diagram.
2. Apply the inputs to the IC7447(A,B,C&D).
3. Observe the output and verify the result.

RESULT:
Thus the decoder, function implementation using decoder and the results were verified.
EXPERIMENT: DESIGN AND IMPLEMENTATION OF MULTIPLEXER AND
DATE: DEMULTIPLEXER
AIM:
To design and implement multiplexer and demultiplexer using logic gates and implement the
Boolean function using multiplexer ICs.
Boolean function:

F(A,B,C,D) = Σ (0,1,3,4,8,9,15).
REQUIREMENTS :
S.No. Name of the apparatus Specification Quantity

1 Digital Trainer kit - 1

2 OR gate IC7432 1

3 AND gate IC7411 1

4 NOT gate IC7404 1

5 Multiplexer ICs 74150, 74151 / 74154 1

6 Connecting wires - -

THEORY:
Multiplexer:
It has a group of data inputs and a group of control inputs. The control inputs are used to select one of
the data inputs and connected to the output terminal. It selects one information out of many
information lines and directed to a single output line.
Demultiplexer:
Demultiplexers perform the opposite function of multiplexers. They transfer a small number of
information units (usually one unit) over a larger number of channels under the control of selection
signals. Fig shows a 1-line to 2-line Demultiplexer circuit. Construct this circuit; connect an LED to
each of the outputs D0 and D1. Set the select signal S to logic 1 or logic 0, and toggle the input I
between logic 1 and logic 0. Which output followed the input when S = 1 and S = 0.
4:1 MULTIPLEXER:

BLOCK DIAGRAM

Circuit Diagram:

Truth Table:

S1 S0 Y

0 0 I0

0 1 I1

1 0 I2

1 1 I3
 1:4 DEMULTIPLEXER:
BLOCK DIAGRAM

Circuit Diagram:

Truth Table:

Selection Lines
S1 S0 OUTPUT V0

0 0 D0=Di

0 1 D1= Di

1 0 D2= Di

1 1 D3= Di
PIN DIAGRAM FOR IC 74150:

PIN DIAGRAM FOR IC 74151:

TRUTH TABLE:

LOGIC DIAGRAM:
PIN DIAGRAM FOR IC 74154:

FUNCTION IMPLEMENTATION :
Implement the following function: F(A,B,C,D) = Σ

(0,1,3,4,8,9,15). Design :
D0 D1 D2 D3 D4 D5 D6 D7
A’ 0 1 2 3 4 5 6 7
A 8 9 10 11 12 13 14 15

1 1 0 A’ A’ 0 0 A
 Truth table of the function:

Table 3:

A B C D F(A,B,C,D)
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1

PROCEDURE:
1. Connections are given as per in the circuit diagram.
2. Inputs are given through the logic switches.
3. Outputs are noted and verified with truth table

RESULT:
Thus the truth table of multiplexer and demultiplexer was studied and verified using logic
gates also the given Boolean function were implemented successfully.
EXPERIMENT:
DESIGN AND IMPLEMENTATION OF SYNCHRONOUS COUNTER
DATE:

AIM:
To construct and verify the synchronous up/down counters.

REQUIREMENTS:

S. No.Components / Equipments Specification Quantity

1. Digital IC trainer kit ---- 1

2. JK Flip-Flop, AND Gate IC 7473,7408 2,1

3. Connecting wires ---- Sufficient Nos

THEORY:
Synchronous Counter
Clock input is applied simultaneously to all flip-flops. The output of the first FLIP-FLOP is
connected to the input of second FLIP-FLOP and so on.

Design of synchronous counter

Step 1: Find the number of flip-flops required. For an n-bit counter, n- flip-flops is required.
Step 2: Write the count sequence in tabular form.
Step 3: Determine the flip-flop inputs, which must be present for the desired next State from the
present state using excitation table of flip-flops.
Step 4: Prepare K-map for each flip-flop input in terms of flip-flop output as input Variables. Simplify
the K-map and obtain the minimized expressions.
Step 5: Connect the circuit using the flip-flops.
CIRCUIT DIAGRAM:
Design of 3-bit synchronous up:

Design of 3-bit synchronous down counter:

Pin Diagram
Truth Table:
3 Bit Synchronous UP 3 Bit Synchronous DOWN
Counter Counter

Clock Q2 Q1 Q0 Clock Q2 Q1 Q0

0 0 0 0 0 1 1 1

1 0 0 1 1 1 1 0

2 0 1 0 2 1 0 1

3 0 1 1 3 1 0 0

4 1 0 0 4 0 1 1

5 1 0 1 5 0 1 0

6 1 1 0 6 0 0 1

7 1 1 1 7 0 0 0

PROCEDURE:
1. The connections are made as per the circuit diagram.
2. Switch on the power supply.
3. The input is given at the appropriate terminal and corresponding output is observed
and truth table is verified.

RESULT:
Thus the counters were constructed and their truth tables verified.
EXPERIMENT: IMPLEMENTATION OF SISO, SIPO, PISO AND PIPO SHIFT
DATE: REGISTERS

AIM:
To implement the 4 bit shift register using flip flops and to study the operations in the
following modes.
(i) Serial in serial out
(ii) Serial in parallel out
(iii) Parallel in parallel out
(iv) Parallel in serial out
REQUIREMENTS:

S.No. Name of the apparatus Range Quantity

1 Digital Trainer kit 1
2 D Flip Flop IC 7474 2
3 Connecting wires some

THEORY:
SHIFT REGISTER:
A register is a device capable of storing a bit. The data can be serial or parallel. The register can
convert a data from serial to parallel and vice versa shifting then digits to left and right is the
important aspect for arithmetic operations,
A register capable of shifting its binary information either to the right or to the left is called a
shift register. An N bit shift register consists of N flip-flops and the gates that control the shift
operation. A shift register can be used in four different configurations depending upon the way in
which the data are entered into and taken out of it. These four configurations are:
a. Serial-input, Serial-output
. b. Parallel-input, Serial-output
c. Serial-input, parallel-output
d. Parallel-Input, parallel-output
The serial input is a single line going to the input of the leftmost flip-flop of the register. The serial
output is a single line from the output of the rightmost flip-flop of the register, so that the bits stored
in the register can come out through this line one at a time. The parallel output consists of N lines, one
for each of the flip-flops in the register, so the information stored in the register can be inspected
through these lines all at once.
PIN DIAGRAM:

Logic Diagram for Serial in Serial out:

Logic Diagram for Serial in Parallel Out:

Logic Diagram for Parallel In Parallel Out

Logic Diagram for Parallel in Serial out

TRUTH TABLE FOR PISO SHIFT REGISTER:

CLK Q3 Q2 Q1 Q0 O/P
0 1 0 0 1 1
1 0 0 0 0 0
2 0 0 0 0 0
3 0 0 0 0 1

PROCEDURE:
1. The flip-flop is connected using connecting wires as shown in the circuit.
2. The flip flop are then reset to zero internally with the help of reset to set inputs.
3. The bits are shifted in by giving suitable clock input.
4. Thus the truth table is then verified.

RESULT:
Thus the operation of 4 bit shift register for SISO, SIPO, and PIPO was studied and verified.
EXPERIMENT:
IMPLEMENTATION OF MOD-10 RIPPLE COUNTER
DATE:
AIM:
To construct and verify Mod-10 Ripple Counters.
APPARATUS REQUIRED:
S.No. Name of the apparatus SPECIFICATION Quantity

1 Digital Trainer kit 1

2 JK Flip Flop IC 7473 2

3 NAND Gate IC7400 1

4 Connecting wires some

THEORY:
Counters are a group of flip flops connected together to perform counting operation. According
to the way the flip flops are clocked, there are two types of flip flops,
a. Asynchronous Counter
b. Synchronous Counter
In asynchronous counter, the flip flop is clocked by the external clock pulse. Then each
successive flip flop are clock by Q or Q’ output of the previous flip flop. In 4 bit ripple counter, the
total number of states is 16 (24) and this varies from 00002 to 11112 . If the counters are designed with
number of sequence which is less than 2, then those counters are said to be Mod-N counters where N
denotes number of sequence. Thus in Mod-10 counter, total number of states is 10 and number of flip
flops are 4. Similarly in Mod-12 counter, total number of states is 12 and number of flip flops are 4.
CIRCUIT DIAGRAM OF MOD-10 RIPPLE COUNTERS

PROCEDURE:
1. Verify the flip flop.
2. Make the connections as per the circuit diagram.
3. Switch on VCC and apply various combinations of input according to truth table.
4. By applying the clock pulse, all the input combinations are given and the outputs
are verified with the truth table.
RESULT:Thus the Mod 10 ripple counter was designed and constructed successfully.
EXPERIMENT:
STUDY OF UNIVERSAL SHIFT REGISTER
DATE:
AIM:
To study and verify the load, shift and rotate operation of a 4-bit shift register.
EQUIPMENT/APPARATUS USED:
S. No. Name of the equipment Range/Rating Quantity
1. Digital IC Trainer .... 1
2. IC 74195 ... 1
3. Connecting Wires ...

THEORY:

A register is a group of binary storage cells capable of holding binary information. A group of flip
flops constitutes a register, since each flip-flop can work as a binary cell. An n-bit register, has n flip-
flops and is capable of holding n-bits of information. In addition to flip-flops a register can have a
combinational part that performs data-processing tasks.

Shift Register: A register capable of shifting its binary contents either to the left or to the right iscalled a
shift register. The shift register permits the stored data to move from a particular locationto some other
location within the register. Registers can be designed using discrete flip-flops (S- R, J-K, and D-type).
The data in a shift register can be shifted in two possible ways: (a) serial shifting and (b) parallel shifting.
The serial shifting method shifts one bit at a time for each clock pulse in a serial manner, beginning with
either LSB or MSB. On the other hand, in parallel shiftingoperation, all the data (input or output) gets
shifted simultaneously during a single clock pulse. Hence, we may say that parallel shifting operation is
much faster than serial shifting operation.

8-bit Universal Shift Register: IC 74195 is a 4-bit TTL MSI having both serial/parallel input
and serial/parallel output capability. The pinout diagram of IC 74195 is shown in Figure 1.
When the SH / LD input is LOW, the data on the parallel inputs, i.e., A, B, C, and D are entered
synchronously on the positive transition of the clock. When SH / LD is HIGH, the stored data willshift
right (QA to QD) synchronously with the clock. J and K are the serial inputs to the first stageof the
register (QA); QD can be used for getting a serial output data. The active low clear is asynchronous.
Example:
Right Shift Operation: :Input data: 1011
Clock QA QB QC QD
0 1 0 1 1
1 0 1 0 1
2 0 0 1 0
3 0 0 0 1
4 0 0 0 0
1 0 0 1 1 0 0 1

0 1 0 0 1 1 0 0
PROCEDURE:
1. Load data using parallel loading
2. Use clock 1(9)
3. Mode Control 6 OFF (0) connect logic input switch
4. Serial input 1 OFF (0) connect logic input switch
5. Press the clock button
 Example:
Rotate Right Operation: Input data: 1011

Clock QA QB QC QD
0 1 0 1 1
1 1 1 0 1
2 1 1 1 0
3 0 1 1 1
4 1 0 1 1

1 0 1 1 0 0 0 1

PROCEDURE:

1. Load data using parallel loading

2. Use clock 1(9)
3. Mode Control 6 OFF (0) connect logic input switch
4. Serial input 1 connects to the QD logic output switch
5. Press the clock button

RESULT:
Thus the 4-bit Universal Shift Register was studied successfully.
 EXPT NO:
Simulator based study of Computer Architecture
DATE:

AIM:

To study Simulator based on Computer Architecture.

DESCRIPTION:

A computer architecture simulator is a program that simulates the execution of computer architecture.

Computer architecture simulators are used for the following purposes:

 Lowering cost by evaluating hardware designs without building physical hardware systems.
 Enabling access to unobtainable hardware.
 Increasing the precision and volume of computer performance data.
 Introducing abilities that are not normally possible on real hardware such as running code backwards when
an error is detected or running in faster-than-real time.
 In architecture, virtual or graphical simulation models can help in arriving at conceptual designs, taking into
account wide ranges of criteria, such as layout, positioning, landscaping and lighting.
 Also, realistic rendering can be used to help make depictions lifelike, adding to their value for clients.

RESULT:
Thus Simulator based on Computer Architecture model were studied.
 EXPT NO:
Design of Hazard Free Circuits.
DATE:

AIM:

To Eliminate the 0-hazards by adding 3 additional loops Z = (A+C)(A'+D')(B'+C'+D)(C+D')(A+B'+D)(A'+B'+C')

DESCRIPTION:

K-MAP

CIRCUIT DIAGRAM

TIMING DIAGRAM

RESULT:
Thus the 0-hazards were eliminated by adding additional loops.
 EXPT NO:
Simulator based study of Control Unit Design.
DATE:

AIM:

To study Simulator based on Control Unit Design.

DESCRIPTION:

DESIGN OF CONTROL UNIT

The Control Unit is classified into two major categories:
 Hardwired Control
 Microprogrammed Control
HARDWIRED CONTROL
The Hardwired Control organization involves the control logic to be implemented with gates, flip-flops, decoders, and
other digital circuits.
The following image shows the block diagram of a Hardwired Control organization.
 A Hard-wired Control consists of two decoders, a sequence counter, and a number of logic gates.
 An instruction fetched from the memory unit is placed in the instruction register.
 The component of an instruction register includes; I bit, the operation code, and bits 0.
 The operation code in bits 12 through 14 are coded with a 3 x 8 decoder.
 The outputs of the decoder are designated by the symbols D0 through D7.
 The operation code at bit 15 is transferred to a flip-flop designated by the symbol I.
 The operation codes from Bits 0 through 1are applied to the control logic gates.
 The Sequence counter can count in binary from 0 through 15.

MICRO-PROGRAMMED CONTROL
The Microprogrammed Control organization is implemented by using the programming approach.
In Microprogrammed Control, the micro-operations are performed by executing a program consisting of micro-
instructions.
 The following image shows the block diagram of a Microprogrammed Control organization.
 The Control memory address register specifies the address of the micro-instruction.
 The Control memory is assumed to be a ROM, within which all control information is permanently stored.
 The control register holds the microinstruction fetched from the memory.
 The micro-instruction contains a control word that specifies one or more micro-operations for the data processor.
 While the micro-operations are being executed, the next address is computed in the next address generator
circuit and then transferred into the control address register to read the next microinstruction.
 The next address generator is often referred to as a micro-program sequencer, as it determines the
address sequence that is read from control memory.

RESULT:
Thus Simulator based on Control Unit Design were studied.
HARDWIRED CONTROL

MICRO-PROGRAMMED CONTROL