Flag register

Flag register is a 16-bit register containing nine 1-bit flags:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OF DF IF TF SF ZF AF PF CF
Six status or condition flags (OF, SF, ZF, AF, PF, CF)
Three control flags (TF, DF, IF)
• Overflow Flag (OF) – It is set if an overflow occurs, i.e., a result is out of range.
• Sign Flag (SF) – It is set if the most significant bit of the result is set.
• Zero Flag (ZF) – It is set if the result is zero.
• Auxiliary carry Flag (AF) – It is set if there is a carry out of bit 3 during addition or borrow by
bit 3 during subtraction. This flag is used exclusively for BCD arithmetic.
• Parity Flag (PF) – It is set to 1 if the low-order 8-bits of the result contain an even number of 1s.
• Carry Flag (CF) – It is set if carry from or borrow to the most significant bit during last result
calculation.
• Trap Flag (TF) – if set, a trap is executed after each instruction.
• Direction Flag (DF) – Used by string manipulation instructions. If set then string
manipulation instructions will auto- decrement index registers. If cleared then the index
registers will be auto-incremented.
• Interrupt-enable Flag (IF) - Setting this bit enables maskable interrupts.

1
 1. The 8086 Addressing Modes
AUQ: What are the addressing modes in 8086? Explain with example.(Dec-2006,07,08,10,11,
May2006,07,08,09,11,15, May 2016, Dec 2016)
Addressing modes in 8086:
The 8086 memory addresses are calculated by adding the segment register contents to an offset
address. The offset address calculation depends on the addressing mode being used. The total number of
address lines in the 8086 is 20 whereas the segment registers are 16 bits. The actual address in memory
(effective address) is calculated as per the following steps.
• The segment register contents are multiplied by 1OH, thus, shifting the contents left by 4 bits.
This results in the starting address of the segment in memory.
• The offset address is calculated. The offset address is basically the offset of the actual memory
location from the starting location of the segment. The calculation of this offset value depends
on the addressing mode being used.
• The offset address is added to the starting address of the segment to get the effective address, i.e.
the actual memory address.

2
 Effective Address – 16 bits

+ 4 bits

Segment Address – 16 bits

Physical Address – 20 bits

Suppose a segment register contents are xyzwH, and the offset value calculated is abcdH, then:
• Starting address of the segment
• Offset address
• Effective address
The addressing modes specify the location of the operand and also how its location may be
determined. The following addressing modes are supported in the 8086.

 Register Addressing Mode

 Immediate Addressing Mode
 Direct Memory Addressing Mode
 Register Indirect Addressing Mode
 Base plus Index Register Addressing Mode
 Register Relative Addressing Mode
 Base plus Index Register Relative Addressing Mode
 String Addressing Mode
Register Addressing Mode
When both destination and source operands reside in registers, the addressing mode is known as
register addressing mode. Following are the examples:
 MOVAX,BX
Move the contents of BX register to AX register. The contents of BX register remain unchanged.
 AND AL, BL
AND the contents of AL register with the contents of BL register and place the resultant contents
in AL register.
Immediate Addressing Mode
When one of the operands is part of the instruction, the addressing mode is known as immediate
addressing mode. Examples are given below

3
 MOV CX, 2346H
Copy into CX the 16-bit data 2346H.
 SUB AL, 24H
Subtract 24H from the contents of AL register and put the result in AL register.
Direct Memory Addressing Mode
In this mode, the 16-bit offset address is part of the instruction as displacement field. It is stored as 16-bit
unsigned or 8-bit sign-extended number.
 MOV (4625H), Dl
Copy the contents of DL register into memory locations calculated from Data Segment register and offset
4625H.
 OR AL, (3030H)
OR the contents of AL register with the contents of memory location calculated from DS register and
offset 3030H.
Register Indirect Addressing Mode
In this addressing mode, the offset address is specified through pointer register or index register.
For index register, the SI (Source Index) register or DI (Destination Index) register may be used,
whereas for pointer register, BX (Base Register) register or BP (Base Pointer) register may be used.
Following are some examples of the application of the register indirect addressing mode.
 MOV AL, (BP)
Copy into AL register the contents of memory location, whose address is calculated using offset as
contents of BP register and the contents of DS register.
Base plus Index Register Addressing Mode
In this mode, both base register (BP or BX) and index register (SI or DI) are used to indirectly
address the memory location. An example is given below.
 MOV (BX + DI), AL
Copy the contents of AL register into memory location whose address is calculated using the contents of
DS (Data Segment), BX (Base Register) and DI (Destination Index) registers.
Register Relative Addressing Mode
This mode is similar to base plus index addressing mode. In this mode, the offset is calculated using
either a base register (BP, BX) or an index register (SI, DI) and the displacement specified as an 8 -bit or
a 16-bit number, as part of the instruction.

4
 MOV AX, (DI + 06)
Copy to AL the contents of memory location whose address is calculated using DS (Data Segment), DI
(Destination Index) register with displacement of 06, and copy to AH the contents of the next higher
memory location.
Base plus Index Register Relative Addressing Mode
This addressing mode is basically the combination of base plus index register addressing mode and
register relative addressing mode. To find the address of the operand in memory, a base register (BP or
BX), an index register (DI or SI) and the displacement which is specified in instruction is used along
with the data segment register. For example:
 MOV (BX + DI + 2), CL
Copy the contents of the CL register to the memory location whose address is calculated using DS (Data
Segment), BX (Base Register) and DI (Destination Index) registers and 02 as displacement.
String Addressing Mode
In this addressing mode, the string instruction uses index registers implicitly to access memory.
Example: MOVSB
Copy the byte from the source string location determined by DS and SI to the destination string
location determined by ES and DI.
 The addressing modes for branch related instructions are
 Intrasegment direct (within the same segment)
 Intrasegment Indirect
 Intersegment Direct (Control transfer to different segment)
 Intersegment Indirect

Intrasegment direct (within the same segment)

Displacement

Effective Address
IP

If the displacement is 8 bit long, it is called short jump SJMP

If the displacement is 16 bit long, it is called Long jump
LJMP. For example CALL NEAR
A NEAR JMP is a jump where destination location is in the same code segment. In this case only IP

5
 is changed.
Intrasegment Indirect
The content of register or memory is accessed using any of the above data related addressing
mode except immediate mode.

Intersegment Direct (control transfer is in different segment)

The purpose of the addressing mode is to provide a means of branching from one code
segment to another .Replaces the content of IP with the part of the instruction and the contents of the CS
with another part of instruction.
Example: FAR CALL
A FAR JMP is a jump where destination location is from a different segment. In this case
both IP and CS are changed as specified in the destination.

Intersegment Indirect
The content of memory block containing 4 bytes.ie IP (LSB),IP(MSB),CS (LSB),and CS(MSB)
sequentially .The starting address of the memory block may be referred using any of the addressing
mode except immediate mode.

1
 UNIT-III
8086 SYSTEM BUS STRUCTURE
8086 signals – Basic configurations – System bus timing –System design using 8086 – IO
programming – Introduction to Multiprogramming – System Bus Structure - Multiprocessor
configurations – Coprocessor, Closely coupled and loosely Coupled configurations – Introduction to
advanced processors.

 The 8086 Microprocessor is a 16-bit CPU.

 Available clock rates: 5, 8 and 10MHz
 Packages: 40 pin CERDIP or plastic package
 Operates in single processor or multiprocessor configurations
 Modes of operation: Minimum mode (single processor mode) and Maximum mode
(multiprocessor mode) configuration.

SIGNAL DESCRIPTION OF 8086

AUQ: Explain the signal used in 8086 processor. (Dec 2003,06,07,09,10,13, May 2006,07,08,09,11)
The 8086 signals can be categorized in three groups.
 Signals having common function in minimum and maximum mode.
 Signals having special functions in minimum mode
 Signals having special functions in maximum mode
PIN DIAGRAM

2
Signals having common function in minimum and maximum mode

AD15 – AD0
 These are time multiplexed address and data lines. They act as address lines during first part of
machine cycle and data lines in later part.
A19 / S6 – A16 / S3
 These are time multiplexed address and status lines. They act as address lines during first part of
machine cycle and status lines in later part.
 These are most significant address lines for memory operations. During I/O operations these lines are
low.
 The status signals S4 and S3 indicate which segment registers is being used for memory access.
 The status of interrupt enable flag bit will be displayed on S5.
 The status line S6 is always low.
S4 S3 Indications

0 0 ES

0 1 SS

1 0 CS

1 1 DS

3
 - Bus high enable/ status
 Low signal on indicates access to higher order memory banks, otherwise access is to only lower
order memory banks.
 and A0 decide the memory bank and type of access.

 S7 has no function.
A0 Indications

0 0 Both higher and lower order banks for word read/ write

0 1 Higher order bank for byte read/ write

1 0 Lower order bank for byte read/ write

1 1 None

 Read control signal

 is low when 8086 is receiving the data from memory or I/O.
READY
 Wait state request signal.
 A HIGH on READY input causes the 8086 to extend the machine cycle by inserting wait states.

 This input is examined by WAIT instruction.

 If the input goes low, execution will continue, else, the processor remains in idle state.
INTR
 This is level triggered input.
 INTR is sampled during the last clock cycle of each instruction to determine the availability of
request.
 These interrupts can be masked internally by resetting the interrupt enable flag.
NMI
 NMI (Non-Maskable interrupt) is positive edge triggered non-maskable interrupt request.
CLK
 CLK is clock signal from external crystal oscillator.
 8086 requires clock signal with 33% duty cycle.

4
RESET
 System reset signal must be high for atleast 4 clock periods to cause reset.
 Reset operation takes about 10 clock periods.
VCC
 +5V supply with ±5% tolerance.
GND
 Ground for internal circuits.

 High on this pin selects minimum mode and low signal selects maximum mode.
Signals having special functions in minimum mode

ALE
 Address latch enable.
 High on this pin indicates valid address on address/data bus.

 Write control signal.

 is low when 8086 sends the data to memory or I/O.

 = High, indicates memory access.

5
 = low, indicates I/O access.

 is the acknowledgement for the interrupt request on INTR pin.

 It is pulsed low in two consecutive bus cycles.
 First pulse indicates interrupt acknowledgement.
 During second pulse, external logic puts the interrupt type on data bus.

 Data transmit/receive.
 This signal, when high indicates data is being transmitted by 8086.
 The low signal indicates that 8086 is receiving the data.

 Data bus enable.

 This signal, when low indicates that the 8086 processors address/data bus is used as data bus.
 It is used to enable data buffers.
HOLD
 HOLD signal when high indicates another master has requested for direct memory access.
 When HOLD becomes low, it indicates that direct memory access is no more required.
HLDA
 The microprocessor sends high signal on HLDA to indicate acknowledgement of DMA request. It
then tristates the buses and control.
 When HOLD becomes low, the microprocessor makes HLDA low and regains the control of buses.
Signals having special functions in maximum mode

6
 This signal indicates that an instruction with lock prefix is being executed and the bus is not to be
used by any other processor.

 In maximum mode DMA request is received and acknowledged using these

signals. has highest priority compared to

 These are the status lines which indicate the type of operation being carried out by the processor.
Control functions

0 0 0 Interrupt acknowledge

0 0 1 I/O read

0 1 0 I/O write

0 1 1 Halt

1 0 0 Opcode fetch

1 0 1 Memory read

1 1 0 Memory write

1 1 1 No operation

 These two signals are decoded to provide instruction queue status.

Indications

0 0 Queue is in idle state

0 1 First byte of opcode has entered queue

1 0 Queue empty

1 1 Subsequent byte of opcode has entered queue

7
Basic configurations :

1. Minimum Mode configuration:

AUQ: Explain with neat diagram minimum mode configuration of 8086 system. (Dec 2006,08,
May 2006,07)
 A processor is in minimum mode when its MN / /MX pin is strapped to +5V. In a minimum mode 8086
system, the microprocessor 8086 is operated in minimum mode by strapping its MN/MX pin to logic 1.
 In this mode, all the control signals are given out by the microprocessor chip itself.
 There is a single microprocessor in the minimum mode system.
 The remaining components in the system are latches, transreceivers, clock generator, memory and I/O
devices. Some type of chip selection logic may be required for selecting memory or I/O devices,
depending upon the address map of the system.
 Latches are generally buffered output D-type flip-flops like 74LS373 or 8282.
 They are used for separating the valid address from the multiplexed address/data signals and are
controlled by the ALE signal generated by 8086.
 Transreceivers are the bidirectional buffers and sometimes they are called as data
amplifiers. They are required to separate the valid data from the time multiplexed
address/data signals.
 They are controlled by two signals namely, DEN and DT/R.
 The DEN signal indicates the direction of data, i.e. from or to the processor. The system contains memory
for the monitor and users program storage.
 The clock generator generates the clock from the crystal oscillator and then shapes it and divides to make
it more precise so that it can be used as an accurate timing reference for the system.
 The clock generator also synchronizes some external signal with the system clock. The general system
organisation is as shown in below fig.

8
9
 2. Maximum Mode configuration:
AUQ: Explain with neat diagram maximum mode configuration of 8086 system. (Dec 2007)

A processor is in maximum mode when its MN / /MX pin is grounded. The maximum mode
definitions of pins 24 through 31 are given in table and a typical maximum mode configuration is shown
in Fig.

The circuitry is for converting the status bits /S0, /S1 and /S2 into the I/O and memory transfer
signals needed to direct data transfers and for controlling the 8282 latches and 8286 transceivers.

It is normally implemented with an Intel 8288 bus controller. Also included in the system is an
interrupt priority management device: however, its presence is optional.

 In the maximum mode, there may be more than one microprocessor in the system configuration.
The components in the system are same as in the minimum mode system.
 The basic function of the bus controller chip IC8288, is to derive control signals like RD and WR (
for memory and I/O devices), DEN, DT/R, ALE etc. using the information by the processor on the
status lines.
 The bus controller chip has input lines S2, S1, S0 and CLK. These inputs to 8288 are driven by
CPU. The process to be activated for this combination is listed below.
 It derives the outputs ALE, DEN, DT/R, MRDC, MWTC,AMWC, IORC, IOWC and AIOWC. The
AEN, IOB and CEN pins are specially useful for multiprocessor systems.
 AEN and IOB are generally grounded. CEN pin is usually tied to +5V. The significance of the
MCE/PDEN output depends upon the status of the IOB pin.
 If IOB is grounded, it acts as master cascade enable to control cascade 8259A, else it acts as peripheral
data enable used in the multiple bus configurations.

The HOLD and HLDA pins become the /RQ / /GT0 and /RQ / /GT1 pins. Both bus requests and bus
grants can be given through each of these pins. They are exactly the same except that if requests are seen
on both pins at the same time, then one on /RQ / /GT0 is given higher priority. A request consists of a
negative puls arriving before the start of the current bus cycle. The grant is negative puls that is issued at
the beginning of the current bus cycle provided that:

1. The previous bus transfer was not the low byte of a word to or from an odd address if the CPU is
an 8086. For 8088, regardless of the address alignment the grant signal will not be sent until
second byte of a word reference is accessed.
2. The first pulse of an interrupt acknowledgement did not occure during the previous bus cycle.
3. An instruction with a LOCK prefix is not being executed.
4. If condition 1 or 2 is not met, then the grant will not be given until the next bus cycle and if
condition 3 is not met, the grant will wait until the locked instruction is completed. In response to
the grant the three-state pins are put in their high-impedance state and the next bus cycle will be
given to the requesting master.

10
Read Write Timing Diagram

AUQ: Draw and explain the timing diagram of different cycle in 8086 processor. (Dec 2007,
May 2009,13, Dec 2016, May 2017)

The typical sequence of bus cycles is shown below;

11
Bus timing for Minimum Mode:

 The opcode fetch and read cycles are similar. Hence the timing diagram can be categorized in two parts, the
first is the timing diagram for read cycle and the second is the timing diagram for write cycle.
 The read cycle begins in T1 with the assertion of address latch enable (ALE) signal and also M / IO signal.
During the negative going edge of this signal, the valid address is latched on the local bus.
 The BHE and A0 signals address low, high or both bytes. From T1 to T4 , the M/IO signal indicates a
memory or I/O operation.• At T2, the address is removed from the local bus and is sent to the output. The
bus is then tristated. The read (RD) control signal is also activated in T2.
 The read (RD) signal causes the address device to enable its data bus drivers. After RD goes low, the valid
data is available on the data bus.
 The addressed device will drive the READY line high. When the processor returns the read signal to high
level,the addressed device will again tristate its bus drivers.

Figure:Readcycle timing diagarm of minimum mode8086

12
 Figure: Write cycle timing diagarm of minimum mode8086

 A write cycle also begins with the assertion of ALE and the emission of the address. The M/IO signal is again
asserted to indicate a memory or I/O operation. In T2, after sending the address in T1, the processor sends the
data to be written to the addressed location.
 The data remains on the bus until middle of T4 state. The WR becomes active at the beginning of T2 (unlike RD
is somewhat delayed in T2 to provide time for floating).
 The BHE and A0 signals are used to select the proper byte or bytes of memory or I/O word to be read or write.
 The M/IO, RD and WR signals indicate the type of data transfer as specified in table below.

13
 Bus Timing for Maximum Mode:

 The maximum mode system timing diagrams are divided in two portions as read (input) and write (output)
timing diagrams.
 The address/data and address/status timings are similar to the minimum mode.
 ALE is asserted in T1, just like minimum mode. The only difference lies in the status signal used and the
available control and advanced command signals.
 Here the only difference between in timing diagram between minimum mode and maximum mode is the
status signals used and the available control and advanced command signals.
 R0, S1, S2 are set at the beginning of bus cycle.8288 bus controller will output a pulse as on the ALE and
apply a required signal to its DT / R pin during T1.
 In T2, 8288 will set DEN=1 thus enabling transceivers, and for an input it will activate MRDC or IORC.
These signals are activated until T4. For an output, the AMWC or AIOWC is activated from T2 to T4 and
MWTC or IOWC is activated from T3 to T4.
 The status bit S0 to S2 remains active until T3 and become passive during T3 and T4.
 If reader input is not activated before T3, wait state will be inserted between T3 and T4.

Figure:Memory read timing diagram in maximum mode

14
 Figure: Memory write timing diagram in maximum mode

IO programming
With example explain the input output program concepts in 8086.
On the 8086, all programmed communications with the I/O ports is done by the IN
and OUT instructions defined in Fig. 6-2.
 IN and OUT instructions
Name Mnemonic and Format Description
Input
Long form, byte IN AL, PORT (AL) <- (PORT)
Long form, word IN AX, PORT (AX) <- (PORT+1: PORT)
Short form, byte IN AL, DX (AL) <- ((DX))
Short form, word IN AX, DX (AX) <- ((DX) + 1: (DX))
Output
Long form, byte OUT PORT, AL (PORT) <- (AL)
Long form, word OUT PORT, AX (PORT+1: PORT) <- (AX)
Short form, byte OUT DX, AL ((DX)) <- (AL)
Short form, word OUT DX, AX ((DX)+1: (DX)) <- (AX)
Note: PORT is a constant ranging from 0 to 255
Flags: No flags are affected
Addressing modes: Operands are limited as indicated above.

If the second operand is DX, then there is only one byte in the instruction and the contents of DX
are used as the port address.
Unlike memory addressing, the contents of DX are not modified by any segment register. This
allows variable access to I/O ports in the range 0 to 64K. The machine language code for the IN
instruction is:

15
 Although AL or AX is implied as the first operand in an IN instruction, either AL or AX must be
specified so that the assembler can determine the W-bit.
Similar comments apply to the OUT instruction except that for it the port address is the
destination and is therefore indicated by the first operand, and the second operand is either AL or AX. Its
machine code is:

Note that if the long form of the IN or OUT instruction is used the port address must be in the
range 0000 to 00FF, but for the short form it can be any address in the range 0000 to FFFF (i.e. any
address in the I/O address space). Neither IN nor OUT affects the flags.
The IN instruction may be used to input data from a data buffer register or the status from
a status register. The instructions
IN AX, 28H
MOV DATA_WORD, AX
would move the word in the ports whose address are 0028 and 0029 to the memory location
DATA_WORD.

PROGRAMMED I/O

Programmed I/O consists of continually examining the status of an interface and performing an
I/O operation with the interface when its status indicates that it has data to be input or its data-out buffer
register is ready to receive data from the CPU.

16
 As a more complete example, suppose a line of characters is to be input from a terminal to an 82-
byte array beginning at BUFFER until a carriage return is encountered or more then 80 characters are
input. If a carriage return is not found in the first 81 characters then the message "BUFFER
OVERFLOW" is to be output to the terminal; otherwise, a line feed is to be automatically appended to
the carriage return.

Because the ASCII code is a 7-bit code, the eighth bit, bit 7, is often used as parity bit during the
transmission from the terminal. Let us assume that bit 7 is set according to even parity and if an odd
parity byte is detected, a branch is to be made to ERROR. If there is no parity error, bit 7 is to be cleared
before the byte is transferred to the memory buffer.

INTERRUPT I/O

Even though programmed I/O is conceptually simple, it can waste a considerable amount of time
while waiting for ready bits to become active. In the above example, if the person typing on the terminal

17
could type 10 characters per second and only 10 µs is required for the computer to input each character,
then approximately

of the time is not being utilized.

Before an 8086 interrupt sequence can begin, the currently executing instruction must be completed
unless the current instruction is a HLT or WAIT instruction.

For a prefixed instruction, because the prefix is considered as part of the instruction, the interrupt
request is not recognized between the prefix and the instruction.

In the case of the REP instruction, the interrupt request is recognized after the primitive operation
following the REP is completed, and the return address is the location of the REP prefix.

For MOV and POP instructions in which the destination is a segment register, an interrupt request is
not recognized until after the instruction following the MOV or POP instruction is executed.

For the 8086, once the interrupt request has been recognized, the interrupt sequence consists of:

1. Establishing a type N.
2. Pushing the current contents of the PSW, CS and IP onto the stack (in that order).
3. Clearing the IF and TF flags.
4. Putting the contents of the memory location 4*N into the IP and the contents of 4*N+2 into the
CS.

Thus, an interrupt causes the normal program sequence to be suspended and a branch to be made to
the location indicated by the double word beginning at four times the type (i.e. the interrupt pointer).
Control can be returned to the point at which the interrupt occurred by placing an IRET instruction at the
end of the interrupt routine.

It was mentioned that there are two classes of interrupts, internal and external interrupts, with external
interrupts being caused by a signal being sent to the CPU through one of its pins, which for the 8086 is
either the NMI pin or the INTR pin.

An interrupt initiated by a signal on the NMI pin is called a nonmaskable interrupt and will cause a
type 2 interrupt regardless of the setting of the IF flag. Nonmaskable interrupt signals are normally
caused by circuits for detecting catastrophic events.

An interrupt on the INTR pin is masked by the IF flag so that this flag is 0 the interrupt is not
recognized until IF returns to 1.

When IF=1 and a maskable external interrupt occures, the CPU will return an acknowledgment signal
to the device interface through its /INTA pin and initiate the interrupt sequence.

The acknowledgment signal will cause the interface that sent the interrupt signal to send to the CPU
(over the data bus) the byte which specifies the type and hence the address of the interrupt pointer. The
pointer, in turn, supplies the beginning address of the interrupt routine.

18
 There are several ways of combining with interrupt I/O, some involving only software, some only
hardware, and some a combination of the two. Let us consider the following means of giving priority to
an interrupt system:

1. Polling
2. Daisy chaining
3. Interrupt priority management hardware

By putting a program sequence (similar to the one in Fig.6-7) at the beginning of the interrupt
routine, the priority of the interfaces could be established by the order in which they are polled by the
sequence.

Daisy chaining is a simple hardware means of attaining a priority scheme. It consists of associating a
logic circuit with each interface and passing the interrupt acknowledge signal through these circuits as
shown in Fig.(a). The details of daisy chain logic are shown in Fig.6-14(b). The priority of an interface is
determined by its position on the daisy chain. The closer it is to the CPU the higher its priority.

19
20
BLOCK TRANSFERS AND DMA

The activity involved in transferring a byte or word over the system bus is called a bus cycle. The
execution of an instruction may require more than one bus cycle. For example the instruction:

MOV AL, TOTAL

would use a bus cycle to bring in the contents of TOTAL in addition to the cycle needed to fetch the
instruction.

During any given bus cycle one of the system components connected to the system bus is given
control of the bus. This component is said to be the master during that cycle and the component it is
communicating with is said to be the slave.

The 8086 receives bus requests through its HOLD pin and issues grants from its hold
acknowledge (HLDA) pin. A request is made when a potential master sends a 1 to the HOLD pin.
Normally, after the current bus cycle is complete the 8086 will respond by putting a 1 on the HLDA pin.

During a block input byte transfer the following sequence occurs as the datum is sent from the
interface to the memory:

1. The interface sends the controller a request for DMA service

2. The controller gains control of the bus
3. The contents of the address register are put on the address bus
4. The controller sends the interface a DMA acknowledgment which tells the interface to put data on
the data bus (For an output it signals the interface to latch the next data placed on the bus)
5. The data byte is transferred to the memory location indicated by the address bus
6. The controller relinquishes the bus
7. The address register is incremented by 1
8. The byte count register is decremented by 1
9. If the byte count register is nonzero return to step 1; otherwise stop

The controller/interface design shows bidirectional address lines connected to the controller and only
unidirectional address lines going to the interface.

Multiprocessor Systems
Explain the different configurations of multiprocessor systems. (May 2008)
Multiprocessor Systems refer to the use of multiple processors that execute instructions
simultaneously and communicate using mailboxes and semaphores Maximum mode of 8086 is designed
to implement 3 basic multiprocessor configurations:
1. Coprocessor (8087)
2. Closely coupled (dedicated I/O processor: 8089)
3. Loosely coupled (Multi bus)
Coprocessors and closely coupled configurations are similar - both the CPU and the external
processor share:
 Memory
 I/O system
 Bus & bus control logic
 Clock generator

21
 Multiprocessor configuration
Discuss about the multiprocessor system of 8086.
Explain multiprocessor system. (June 2016, Dec 2016)
Introduction:
Multiprocessor Systems refer to the use of multiple processors that execute instructions simultaneously and
communicate using mailboxes and semaphores.

Maximum mode of 8086 is designed to implement 3 basic multiprocessor configurations:

1. Coprocessor (8087)
2. Closely coupled (8089)
3. Loosely coupled (Multibus)
Need for Multiprocessor system
1. Due to limited data width and lack of floating point arithmetic instructions, 8086 requires many
instructions for computing even single floating point operations. For this Numeric data processor
8087 is used.
2. Some processor like DMA processor can take care of low level operations , while the 8086 CPU
execute high level operations.
Advantages of Multiprocessor
 Easy to add more processor for expansion as per requirement
 When failure occurs, it is easier to replace the faulty processor
 Avoiding the expense of unneeded capabilities of a centralized system by combining several low
cost processor.

6. Explain how co processor works and interacts with 8086 . (June 2016)
Coprocessor configuration
Coprocessors and closely coupled configurations are similar in that both the CPU and the external processor
share:
 Memory
 I/O system
 Bus & bus control logic
 Clock generator
WAIT instruction allows the processor to synchronize itself with external hardware, eg., waiting
for 8087 math co-processor. When the CPU executes WAIT waiting state.
TEST input is asserted (low), the waiting state is completed and execution will resume. ESC
instruction: ESC opcode, operand, opcode: immediate value recognizable to a coprocessor as an
instruction opcode

Coprocessor cannot take control of the bus, it does everything through the CPU.
 8089 shares CPU and clock and bus control logic
 It communication with host CPU is by the way of shared memory

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  The host sets up a message (command) in memory
 The independent processor interrupts host on completion.
Co processor adds instruction to the instruction set. An instruction to be executed by the co- processor
is indicated by an escape (ESC) prefix or instruction.

Figure: Flow diagram of coprocessor

The steps to be followed during the program execution of co processor are

1. The 8086 fetches the instruction
2. The co processor monitors the instruction sequence and captures its own instructions.
3. The ESC is decoded by the CPU and coprocessor simultaneously.
4. The CPU computes the 20 bit address of memory operand and does a dummy read. The co
processor captures the address of the data and obtains control of the bus to load or store as
needed.
5. The co processor sends BUSY (high) to the TEST pin
6. The CPU goes to the next instruction and if this is an 8086 instruction, the CPU and coprocessor
execute in parallel.

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 7. If another coprocessor instruction occurs, the 8086 must wait until BUSY goes low.ie TEST pin
become active. To implement this, a WAIT instruction is put in front of most 8087 instructions by
the assembler.
8. The WAIT instruction does the operations ie wait until the TEST pin is active.
9. The co processor also makes use of Queue status.

*********************************************************************
7. Explain the closely coupled configuration of 8086 with example
. Closely Coupled Configuration:

The main difference between co processor and closely coupled configuration is no special instruction
such as WAIT and ESC is used. The communication between 8086 and independent processor is done through
memory space.
NOTE: Closely Coupled processor may take control of the bus independently. Two 8086’s cannot be
closely coupled.

Figure: closely coupled configuration

The 8086 sets up a message in memory and wakes up independent processor by sending
command to one of its ports. The independent processor then accesses the memory to execute the task in
parallel with the 8086.When task is completed the external processor informs the 8086 about the completion of
task by using either a status bit or an interrupt request.

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 Figure:Interaction between 8086 and 8089

*************************************************************************
8. Write brief note on 8086 loosely coupled system configuration. (April 2006, May 2017)
Loosely Coupled Configuration:

 In loosely coupled configuration a number of modules of 8086 can be interfaced through a common system
bus to work as a multiprocessor system.
 Each module in the loosely coupled configuration is an independent microprocessor based system with its
own clock source, and its own memory and 10 devices interfaced through a local bus.
 Each module can also be a closely coupled configuration of a processor or coprocessor. The block
diagram of a loosely coupled configuration of 8086 is shown in figure

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Fig loosely coupled configuration

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 Advantages:
1. Better system throughput by having more than one processor.
2. The system can be expanded in modular form. Each processor is an independent unit and normally
on a separate PC board. One can be added or removed without affecting the others in the system.
3. A failure in one module normally does not affect the breakdown of the entire system and faulty
module can be easily detected and replaced.
4. Each processor may have its own local bus to access dedicated memory or I/O devices so that a greater
degree of parallel processing can be achieved
Disadvantages
1. Bus Arbitration (contention): Make sure that only 1 processor can access the bus at any given time
2. It must synchronize local and system clocks for synchronous transfer
3. It requires control chips to tie into the system bus.

*************************************************************************
9. Explain the basic bus access control and arbitration schemes used in multiprocessor systems.
(dec 2008)
Bus allocation schemes:
 It needs some kind of priority allocation.
 It output a Bus Request (BRQ) to request the bus and BRQ line goes to some controller.
 The CPU input a Bus Grant (BGR) to gain access to bus
 The Bus access logic output a Bus Busy >BBSY= signal to hold the bus.
 To allocate the bus various methods are available.They are
 Daisy Chaining
 Polling
 Independent
Priority Daisy Chaining:
Need a bus controller to monitor bus busy and bus request signals
 It does not require any priority resolving network, rather the priorities of all the devices are
essentially assumed to be in sequence.
 All the masters use a single bus request line for requesting the bus access.
 The controller sends a bus grant signal, in response to the request, if the busy signal is inactive
when the bus is free.
 The bus grant pulse goes to each of the masters in the sequence till it reaches a requesting master.
 The master then receives the grant signal, activates the busy line and gains the control of the bus.
 The priority is decided by the position of the requesting master in the sequence.

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Polling:
 In polling schemes, a set of address lines is driven by the controller to address each of the masters in
sequence.
 When a bus request is received from a device by the controller, it generates the address on the address
lines.
 If the generated address matches with that of the requesting masters, the controller activates the BUSY
line.

Independent Priority
 In independent priority scheme each master has a pair of Bus request and Bus grant line and each pair
has a priority assigned to it.
 The built in priority decoder within the controller selects the highest priority request a asserts the
corresponding bus grant signal.
 Synchronization of the clocks must be performed once a Master is recognized.
 Master will receive a common clock from one side and pass it to the controller which will derive a
clock for transfer.

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 Due to separate pairs of bus request and bus grant signals, arbitration is fast.

Introduction to Advanced processors: 80286 Microprocessor

Salient Features of 80286
 The 80286 is the first member of the family of advanced microprocessors with memory management
and protection abilities. The 80286 CPU, with its 24-bit address bus is able to address 16 Mbytes of
physical memory. Various versions of 80286 are available that runs on 12.5 MHz, 10 MHz and 8 MHz
clock frequencies. 80286 is upwardly compatible with 8086 in terms of instruction set.
 80286 has two operating modes namely real address mode and virtual address mode. In real address
mode, the 80286 can address upto 1Mb of physical memory address like 8086. In virtual address mode, it
can address up to 16 Mb of physical memory address space and 1 GB of virtual memory address space.
 The instruction set of 80286 includes the instructions of 8086 and 80186. 80286 has some extra
instructions to support operating system and memory management. In real address mode, the 80286 is
object code compatible with 8086. In protected virtual address mode, it is source code compatible with
8086. The performance of 80286 is five times faster than the standard 8086.
Need for Memory Management
The part of main memory in which the operating system and other system programs are stored is
not accessible to the users. It is required to ensure the smooth execution of the running process and also
to ensure their protection. The memory management which is an important task of the operating system is
supported by a hardware unit called memory management unit.
Swapping in of the Program
Fetching of the application program from the secondary memory and placing it in the physical
memory for execution by the CPU.
Swapping out of the executable Program
Saving a portion of the program or important results required for further execution back to the
secondary memory to make the program memory free for further execution of another required portion of
the program.
Concept of Virtual Memory
Large application programs requiring memory much more than the physically available 16Mbytes
of memory, may be executed by diving it into smaller segments. Thus for the user, there exists a very
large logical memory space which is not actually available. Thus there exists a virtual memory which

29
does not exist physically in a system. This complete process of virtual memory management is taken care
of by the 80286 CPU and the supporting operating system.
Internal Architecture of 80286
Register Organization of 80286
The 80286 CPU contains almost the same set of registers, as in 8086, namely
1. Eight 16-bit general purpose registers
2. Four 16-bit segment registers
3. Status and control registers
4.Instruction Pointer

D2, D4, D6, D7 and D11 are called as status flag bits. The bits D 8 (TF) and D9 (IF) are used for controlling
machine operation and thus they are called control flags. The additional fields available in 80286 flag
registers are:
1. IOPL - I/O Privilege Field (bits D12 and D13)
2. NT - Nested Task flag (bit D14)
3. PE - Protection Enable (bit D16)
4. MP - Monitor Processor Extension (bit D17)
5. EM - Processor Extension Emulator (bit D18)
6. TS – Task Switch (bit D19)
Protection Enable flag places the 80286 in protected mode, if set. This can only be cleared by
resetting the CPU. If the Monitor Processor Extension flag is set, allows WAIT instruction to generate a
processor extension not present exception.
Processor Extension Emulator flag if set, causes a processor extension absent exception and
permits the emulation of processor extension by the CPU.
Task Switch flag if set, indicates the next instruction using extension will generate exception 7,
permitting the CPU to test whether the current processor extension is for the current task.
Machine Status Word (MSW)
The machine status word consists of four flags – PE, MO, EM and TS of the four lower order bits
D19 to D16 of the upper word of the flag register. The LMSW and SMSW instructions are available in
the instruction set of 80286 to write and read the MSW in real address mode.
Internal Block Diagram of 80286
The CPU contain four functional blocks
1. Address Unit (AU), 2. Bus Init (BU)
3. Instruction Unit (IU), 4. Execution Unit (EU)
The address unit is responsible for calculating the physical address of instructions and data that
the CPU wants to access. Also the address lines derived by this unit may be used to address different
peripherals. The physical address computed by the address unit is handed over to the bus unit (BU) of the
CPU. Major function of the bus unit is to fetch instruction bytes from the memory. Instructions are
fetched in advance and stored in a queue to enable faster execution of the instructions.
The bus unit also contains a bus control module that controls the prefetcher module. These
prefetched instructions are arranged in a 6-byte instructions queue. The 6-byte prefetch queue forwards
the instructions arranged in it to the instruction unit (IU).

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 The instruction unit accepts instructions from the prefetch queue and an instruction decoder
decodes them one by one. The decoded instructions are latched onto a decoded instruction queue. The
output of the decoding circuit drives a control circuit in the execution unit, which is responsible for
executing the instructions received from decoded instruction queue.
The decoded instruction queue sends the data part of the instruction over the data bus. The EU
contains the register bank used for storing the data as scratch pad, or used as special purpose registers.
The ALU, the heart of the EU, carries out all the arithmetic and logical operations and sends the results
over the data bus or back to the register bank.

Interrupts of 80286
The Interrupts of 80286 may be divided into three categories,
1. External or hardware interrupts
2. INT instruction or software interrupts
3. Interrupts generated internally by exceptions
While executing an instruction, the CPU may sometimes be confronted with a special situation
because of which further execution is not permitted. While trying to execute a divide by zero instruction,
the CPU detects a major error and stops further execution.
In this case, we say that an exception has been generated. In other words, an instruction exception
is an unusual situation encountered during execution of an instruction that stops further execution. The
return address from an exception, in most of the cases, points to the instruction that caused the exception.
As in the case of 8086, the interrupt vector table of 80286 requires 1Kbytes of space for storing 256,
four-byte pointers to point to the corresponding 256 interrupt service routines (lSR).
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 Each pointer contains a 16-bit offset followed by a 16-bit segment selector to point to a particular
ISR. The calculation of vector pointer address in the interrupt vector table from the (8-bit) INT type is
exactly similar to 8086. Like 8086, the 80286 supports the software interrupts of type 0 (INT 00) to type
FFH (INT FFH).
Maskable Interrupt INTR: This is a maskable interrupt input pin of which the INT type is to be
provided by an external circuit like an interrupt controller. The other functional details of this interrupt
pin are exactly similar to the INTR input of 8086.
Non-Maskable Interrupt NMI: It has higher priority than the INTR interrupt. Whenever this interrupt is
received, a vector value of 02 is supplied internally to calculate the pointer to the interrupt vector table.
Once the CPU responds to a NMI request, it does not serve any other interrupt request (including NMI).
Further it does not serve the processor extension (coprocessor) segment overrun interrupt, till either it
executes IRET or it is reset. To start with, this clears the IF flag which is set again with the execution of
IRET, i.e. return from interrupt.
Single Step Interrupt
As in 8086, this is an internal interrupt that comes into action, if trap flag (TF) of 80286 is set.
The CPU stops the execution after each instruction cycle so that the register contents (including flag
register), the program status word and memory, etc. may be examined at the end of each instruction
execution. This interrupt is useful for troubleshooting the software. An interrupt vector type 01 is
reserved for this interrupt.
Interrupt Priorities:
If more than one interrupt signals occur simultaneously, they are processed according to their
priorities as shown below:

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Signal Description of 80286
CLK: This is the system clock input pin. The clock frequency applied at this pin is divided by two
internally and is used for deriving fundamental timings for basic operations of the circuit. The clock is
generated using 8284 clock generator.
D15-D0: These are sixteen bidirectional data bus lines. A23-A0: These are the physical address output lines
used to address memory or I/O devices. The address lines A23 - A16 are zero during I/O transfers
BHE: This output signal, as in 8086, indicates that there is a transfer on the higher byte of the data bus
(D15 – D8) .
S1 , S0: These are the active-low status output signals which indicate initiation of a bus cycle and with
M/IO and COD/INTA, they define the type of the bus cycle.
M/ IO: This output line differentiates memory operations from I/O operations. If this signal is it “0”
indicates that an I/O cycle or INTA cycle is in process and if it is “1” it indicates that a memory or a
HALT cycle is in progress.
COD/ INTA: This output signal, in combination with M/ IO signal and S1 , S0 distinguishes different
memory, I/O and INTA cycles.
LOCK: This active-low output pin is used to prevent the other masters from gaining the control of the
bus for the current and the following bus cycles. This pin is activated by a "LOCK" instruction prefix, or
automatically by hardware during XCHG, interrupt acknowledge or descriptor table access
READY This active-low input pin is used to insert wait states in a bus cycle, for interfacing low speed
peripherals. This signal is neglected during HLDA cycle.
HOLD and HLDA This pair of pins is used by external bus masters to request for the control of the
system bus (HOLD) and to check whether the main processor has granted the control (HLDA) or not, in
the same way as it was in 8086.
INTR: Through this active high input, an external device requests 80286 to suspend the current
instruction execution and serve the interrupt request. Its function is exactly similar to that of INTR pin of
8086.
NMI: The Non-Maskable Interrupt request is an active-high, edge-triggered input that is equivalent to an
INTR signal of type 2. No acknowledge cycles are needed to be carried out.
PEREG and PEACK (Processor Extension Request and Acknowledgement)

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 Processor extension refers to coprocessor (80287 in case of 80286 CPU). This pair of pins
extends the memory management and protection capabilities of 80286 to the processor extension 80287.
The PEREQ input requests the 80286 to perform a data operand transfer for a processor extension. The
PEACK active-low output indicates to the processor extension that the requested operand is being
transferred.
BUSY and ERROR: Processor extension BUSY and ERROR active-low input signals indicate the
operating conditions of a processor extension to 80286. The BUSY goes low, indicating 80286 to
suspend the execution and wait until the BUSY become inactive.
In this duration, the processor extension is busy with its allotted job. Once the job is completed
the processor extension drives the BUSY input high indicating 80286 to continue with the program
execution. An active ERROR signal causes the 80286 to perform the processor extension interrupt while
executing the WAIT and ESC instructions. The active ERROR signal indicates to 80286 that the
processor extension has committed a mistake and hence it is reactivating the processor extension
interrupt.
CAP: A 0.047 μf, 12V capacitor must be connected between this input pin and ground to filter the output
of the internal substrate bias generator. For correct operation of 80286 the capacitor must be charged to
its operating voltage. Till this capacitor charges to its full capacity, the 80286 may be kept stuck to reset
to avoid any spurious activity.
Vss: This pin is a system ground pin of 80286.
Vcc: This pin is used to apply +5V power supply voltage to the internal circuit of 80286. RESET The
active-high RESET input clears the internal logic of 80286, and reinitializes it.
RESET The active-high reset input pulse width should be at least 16 clock cycles. The 80286 requires at
least 38 clock cycles after the trailing edge of the RESET input signal, before it makes the first opcode
fetch cycle.
Real Address Mode
• Act as a fast 8086
• Instruction set is upwardly compatible
• It address only 1 M byte of physical memory using A0-A19.
• In real addressing mode of operation of 80286, it just acts as a fast 8086. The instruction set is upward
compatible with that of 8086.
The 80286 addresses only 1Mbytes of physical memory using A 0- A19. The lines A20-A23 are not
used by the internal circuit of 80286 in this mode. In real address mode, while addressing the physical
memory, the 80286 uses BHE along with A 0- A19. The 20-bit physical address is again formed in the
same way as that in 8086.
The contents of segment registers are used as segment base addresses. The other registers,
depending upon the addressing mode, contain the offset addresses. Because of extra pipelining and other
circuit level improvements, in real address mode also, the 80286 operates at a much faster rate than 8086,
although functionally they work in an identical fashion. As in 8086, the physical memory is organized in
terms of segments of 64Kbyte maximum size.
An exception is generated, if the segment size limit is exceeded by the instruction or the data. The
overlapping of physical memory segments is allowed to minimize the memory requirements for a task.
The 80286 reserves two fixed areas of physical memory for system initialization and interrupt vector
table. In the real mode the first 1Kbyte of memory starting from address 0000H to 003FFH is reserved
for interrupt vector table. Also the addresses from FFFF0H to FFFFFH are reserved for system
initialization.
The program execution starts from FFFFH after reset and initialization. The interrupt vector table
of 80286 is organized in the same way as that of 8086. Some of the interrupt types are reserved for
exceptions, single-stepping and processor extension segment overrun, etc

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 When the 80286 is reset, it always starts the execution in real address mode. In real address mode,
it performs the following functions: it initializes the IP and other registers of 80286, it prepares for
entering the protected virtual address mode.

Protected Virtual Address Mode (PVAM)

80286 is the first processor to support the concepts of virtual memory and memory management.
The virtual memory does not exist physically it still appears to be available within the system. The
concept of VM is implemented using Physical memory that the CPU can directly access and secondary
memory that is used as a storage for data and program, which are stored in secondary memory initially.
The Segment of the program or data required for actual execution at that instant is fetched from
the secondary memory into physical memory. After the execution of this fetched segment, the next
segment required for further execution is again fetched from the secondary memory, while the results of
the executed segment are stored back into the secondary memory for further references. This continues
till the complete program is executed.
During the execution the partial results of the previously executed portions are again fetched into
the physical memory, if required for further execution. The procedure of fetching the chosen program
segments or data from the secondary storage into physical memory is called swapping. The procedure of
storing back the partial results or data back on the secondary storage is called unswapping. The virtual
memory is allotted per task.
The 80286 is able to address 1 G byte (230 bytes) of virtual memory per task. The complete virtual
memory is mapped on to the 16Mbyte physical memory. If a program larger than 16Mbyte is stored on
the hard disk and is to be executed, if it is fetched in terms of data or program segments of less than
16Mbyte in size into the program memory by swapping sequentially as per sequence of execution.
Whenever the portion of a program is required for execution by the CPU, it is fetched from the
secondary memory and placed in the physical memory is called swapping in of the program. A portion of
the program or important partial results required for further execution, may be saved back on secondary
storage to make the PM free for further execution of another required portion of the program is called
swapping out of the executable program.

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