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IJARSE, Vol. No.2, Issue No.4, April, 2013 ISSN-2319-8354(E)
ABSTRACT
Adders are one of the widely used digital components in digital integrated circuit design. Carry select adder
(CSLA) is known to be the fastest adder among the conventional adder structures. Due to the rapidly growing
mobile industry not only the faster arithmetic unit but also less area and low power arithmetic units are needed.
Carry-select method has deemed to be a good compromise between cost and performance in carry propagation
adder design. However, conventional carry-select adder (CSLA) is still area-consuming due to the dual ripple
carry adder structure. The modified CSLA architecture has developed using Binary to Excess-1 converter
(BEC). This paper proposes an efficient method by modifying the gates in the BEC design. This work uses a
simple and efficient gate-level modification to significantly reduce the area and power of the CSLA. Based on
this modification 8-bit and 16-bit CSLA architecture have been developed and compared with the regular CSLA
architecture. This work evaluates the performance of the proposed designs in terms of area and power. The
results analysis shows that the proposed CSLA structure is better than the conventional CSLA. This work proves
that carry select adder using binary to excess 1 converter is efficient for VLSI implementation.
I INTRODUCTION
Adders are commonly found in the critical path of many building blocks of microprocessors and digital signal
processing chips. Adders are essential not only for addition, but also for subtraction, multiplication, and
division. Addition is one of the fundamental arithmetic operations. A fast and accurate operation of a digital
system is greatly influenced by the performance of the resident adders. The most important for measuring the
quality of adder designs in the past were propagation delay, and area. The three most widely accepted metrics
for measuring the Performance of a circuit are power, delay and area. Minimizing Area and delay has always
been considered important, but Reducing power consumption has been gaining prominence Recently with the
increasing level of device integration and the Growth in complexity of micro-electronic circuits, reduction of
Power dissipation has come to fore as a primary design goal. While power efficiency has always been desirable
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IJARSE, Vol. No.2, Issue No.4, April, 2013 ISSN-2319-8354(E)
in electronic Circuits, only recently has it become a limiting factor for a broad Range of applications, thereby
requiring consideration early on in the design process.
Carry Select Adder is one of the fastest adders used in many data-processing processors to perform fast
arithmetic functions. It alleviates the problem of carry propagation delay by independently generating multiple
carries and then selects a carry to generate the sum (3).The carry-select adder (CSLA) provides a compromise
between small area but longer delay ripple carry adder (RCA) and larger area with shorter delay carry look-
ahead adder (6). CSLA uses multiple pairs of ripple carry adder (RCA) to generate partial sum and carry by
considering carry input Cin=0 and Cin=1, then the final sum and carry are selected by multiplexers (MUX) (6).
The modified CSLA using BEC has reduced area and power consumption with slight increase in delay(2, 4, 5).
BEC design consists of AND, XOR and NOT gates as its structure. In this structure the XOR gate will be
replaced by MUX with NOT gate. The proposed CSLA design reduces the area and power by replacing the
gates in BEC design..
This paper is organized as follows; section II explains the conventional carry select adder. The modified and
proposed CSLA are presented in Section III and section IV respectively. Section V deals with the result
obtained. Section VI concludes the paper.
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IJARSE, Vol. No.2, Issue No.4, April, 2013 ISSN-2319-8354(E)
block receives the two sets of input and selects the final sum based on the select input from the previous stage.
One input of the 8:4 multiplexer gets as its input B3, B2, B1, and B0 and another input of the multiplexer is the
BEC output. Use of BEC with multiplexer thus achieves fast incrementing action with reduced gate count. Thus,
the modified CSLA is better than the conventional CSLA circuit in terms of area and power.
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IJARSE, Vol. No.2, Issue No.4, April, 2013 ISSN-2319-8354(E)
8-bit 48 11
16-bit 50 13
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IJARSE, Vol. No.2, Issue No.4, April, 2013 ISSN-2319-8354(E)
60
50%
50 48%
40
30 area
power
20
13%
11%
10
0
8-bit 16-bit
VI. CONCLUSION
The adders are designed using VHDL (Very High Speed Integration Hardware Description Language), Xilinx
Project Navigator 8.1i is used as a synthesis tool and ModelSim ISE III 6.2C for simulation. Thus the result
analysis shows that the proposed CSLA is better compared to the conventional CSLA.
REFERENCES
[1] AkhileshTyagi, (1993) “A Reduced-Area Scheme for Carry-Select Adders”, IEEE Transactions on
Computers, Vol.42, No.10, pp.1163-1170.
[2] B .Ramkumar,.and Harish M Kittur, (2012) “Low Power and Area Efficient Carry Select Adder”, IEEE
Transactions on Very Large Scale Integration (VLSI) Systems, vol. 20, no. 2 pp.371-375.
[3] B. Ramkumar, Kittur, H.M. and Kannan, P. M. (2010) “ASIC Implementation of Modified Faster Carry Save
Adder”, Eur. J. Sci. Res., Vol.42, No.1, pp.53–58.
[4] O. J. Bedrij, (1962) “Carry-Select Adder’, IRE Trans. Electron. Computers”. pp. 340-344.
[5] Padma Devi, AshimaGirdher and Balwinder Singh (2010) “Improved Carry Select Adder with Reduced Area
and Low Power Consumption”, International Journal of Computer Applications, Vol.3, No.4, pp. 14-18.
[6]T.Y. Ceiang, and Hsiao, M. J. (1998) “Carry Select Adder Using Single Ripple Carry Adder”, Electron. Lett.,
Vol.34, No.22, pp.2101–2103.
[7] Y. Kim, and Kim, L.S. (2001) “64-Bit Carry-Select Adder with Reduced Area”, Electron. Lett., Vosl.37,
No.10, pp.614–615.
[8]J.M.Rabaey, (2001) “Digital Integrated Circuits-A Design Perspective” Upper Saddle River,NJ:Prentice-
Hall.
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