Automotive Electronics

D_CAN IP Module

General description
process (BOSCH D_CAN IP) The D_CAN is a CAN IP module that can be realized as a
stand-alone device, as part of an ASIC or as a FPGA.
begin
if (CAN IP Module in VHDL) The D_CAN performs communication according to the CAN
then protocol version 2.0 part A and B. The bit rate can be
programmed to values up to 1 MBit/s depending on the

-- D_CAN used technology.

The dual clock design provides highest performance in CPU

endif; access and highest accuracy for the CAN bus sampling.
end process;
For communication on a CAN network, individual Message
Objects are configured. The Message Objects and Identifier
Masks are stored in the Message RAM.
Customer benefits:
 High performance CAN IP module All functions concerning the handling of messages, like
 Dual Clock approach for highest design flexibility acceptance filtering, transfer of messages between
 100% successfully conformance tested CAN_Core and Message RAM, handling of transmission
 Supports enhanced debug modes requests as well as generation of module interrupt are
 Power down mode for lowest power consumption implemented in the Message Handler.

The register set of the D_CAN can be accessed directly by

Features an external CPU via the module interface. These registers
 Supports CAN protocol version 2.0 part A, B are used to control/configure the CAN_Core and the
 Bit rates up to 1 MBit/s Message Handler and to access the Message RAM.
 Dual clock source, enabling FM-PLL designs
 16, 32, 64 or 128 Message Objects (configurable) The D_CAN module is delivered with the Avalon bus
 Each Message Object has its own Identifier Mask interface from Altera. It can easily be replaced by a user-
 Programmable FIFO mode defined module interface.
 Programmable loop-back mode for self-test
 Parity check for Message RAM (optional)
 Maskable interrupt, 2 interrupt lines
 DMA support, automatic Message Object increment
 Power-down support
 Automotive Electronics | D_CAN IP Module

Block Diagram Generic Interface

Enables connection to a wide range of customer CPUs.
Registers
IF CON REG 1
Approximate size of D_CAN IP module for ASIC design
GENERIC INTERFACE

D_CAN 18,200 gates

Address

D_CAN_SYNCH
Message RAM (32 buffers) 4,352 bits + 160 bit parity

CAN_CORE
CAN_TX
Data
Message
Handler CAN_RX
Control Approximate size of D_CAN IP module for Altera FPGAs
IF CON REG 2

Min. 16 Message Objects 2210 ALUTs + 4 M4Ks RAM

Max. 128 Message Objects 4160 ALUTs + 4 M4Ks RAM

RAM Control Unit Approximate size of D_CAN IP module for Lattice FPGAs
bus_clk CAN_clk Min. 16 Message Objects 4420 LUTs + 270 LUT4s RAM
Max. 128 Message Objects 9400 LUTs + 8 EBRs RAM
RAM
16,32,64,128 Message Buffer
* (136 Bit + 5 Bit Parity) Deliverables for ASIC design
 Well documented VHDL source code
Block functions and size  VHDL source code of Altera Avalon interface
 Complete test bench including the Bosch VHDL
CAN_Core Reference CAN model
The CAN_Core performs communication according to the  D_CAN User’s Manual (programmer's view)
CAN protocol version 2.0 A, B and ISO 11898-1.  D_CAN Module Integration Guide (designer's view)
 D_CAN Conformance Test Report
Message RAM
Message Objects and Identifier Masks for acceptance Deliverables for FPGA design
filtering of received messages are stored in the Message  Altera encrypted VHDL source code or Lattice
RAM.  synthesized core netlist
 Source code of Avalon interface for Altera or
Registers  Wishbone interface for Lattice
All registers used to control and to configure the module.  D_CAN User’s Manual (programmer's view)
 D_CAN FPGA Integration Guide (designer's view)
Message Handler  Programming examples for fast start up
State Machine that controls the data transfer between the  D_CAN Conformance Test Report
Rx/Tx Shift Register of the CAN_Core and the Message RAM
as well as the generation of interrupts as programmed in Supported FPGA families
the Control and Configuration Registers.  Altera Cyclone and Stratix series
 Lattice ECP and XP series
Interface Control Register 1 and 2
The interface control registers are used for the data
transfer between the external bus and the Message RAM.

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