8086/8088 Microprocessor:

Internal Architecture

Course Teacher:
Md. Obaidur Rahman, Ph.D.
Professor
Department of Computer Science and Engineering (CSE)
Dhaka University of Engineering & Technology (DUET), Gazipur.
Course ID: CSE - 4503
Course Title: Microprocessors and Assembly Language
Department of Computer Science and Engineering (CSE)
Islamic University of Technology (IUT), Gazipur.
Lecture References:
 Book:
 Microprocessors and Interfacing: Programming and Hardware,
Chapter # 2, Author: Douglas V. Hall

 Lecture Materials:
 IBM PC Organization, CAP/IT221

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Internal Structure of a Microprocessor

Address bus
ALU Register
Section
Data bus

Control and timing

section Control bus

Block Diagram of a Microprocessor

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8086/8088 Microprocessor
 Intel 8086
 The microprocessor 8086 can be considered to be the basic
processor for the Intel X86 family from 1978.
 It has a 20-bit address bus along with 16-bit data bus.
 With the knowledge of 8086 16-bit processor, one can study
the further versions of this processor 80286, 80406 and
Pentium.
 Intel 8088
 The Intel 8088 have 20-bit address bus with 8-bit data bus
(allowing the use of cheaper and fewer supporting logic chips).
 8086/8088 have the same instruction set, it forms the basic set
of instructions for other Intel families.

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16-Bit 8088/8086 Intel Processor Architecture

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16-Bit 8086 Intel Processor (Pin Diagram) MAXIMUM
MODE
MINIMUM
MODE

GND 1 40 Vcc
AD14 AD15
AD13 A16,S3
AD12 A17,S4
AD11 A18,S5
AD10 A19,S6
AD9 /BHE,S7
AD8 MN,/MX
AD7 /RD
AD6 /RQ,/GT0 HOLD
AD5
8086 /RQ,/GT1 HLDA
AD4 /LOCK /WR
AD3 /S2 IO/M
AD2 /S1 DT/R
AD1 /S0 /DEN
AD0 QS0 ALE
NMI QS1 /INTA
INTR /TEST
CLK READY
GND 20 21 RESET

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Organization of the 8088/8086
 2 main components:
1. Execution Unit (EU)
2. Bus Interface Unit (BIU)

 EU: ALU + Registers (AX, BX, CX, DX, SI, DI, BP, and SP) +
FLAGS register.
 ALU: performs arithmetic & logic operations.
 Registers: store data
 FLAGS Register: Individual bits reflect the result of a computation.

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Organization of the 8088/8086
 BIU: facilitates communication between the EU & the
memory or I/O circuits.
 Responsible for transmitting addresses, data, and control
signals on the buses.
 Registers (CS, DS, ES, SS, and IP) hold addresses of
memory locations.
 IP (instruction pointer) contain the address of the next
instruction to be executed by the EU.

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8086 Registers and Memory
Number of Registers: 14, each of that16-bit registers
Memory Size: 1M Bytes

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8086 Register Categories
 Data registers (4):
General data registers
hold data for an
operation (AX, BX,
CX, DX).
 Address registers
(9): (Segment, Pointer
and Index registers)
hold the address of an
instruction or data.
 Status register (1):
FLAG register keeps
the current states of
the processor.
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General Data Registers
 These are 16-bit registers and can also be used as two 8 bit
registers: low and high bytes can be accessed separately
 AX (Accumulator)
 Most efficient register for arithmetic, logic operations and data transfer:
the use of AX generates the shortest machine code.
 In multiplication and division operations, one of the numbers involved
must be in AL or AX
 BX (Base)
 The base address register (offset)
 CX (Counter)
 Counter for looping operations: loop counter, and in the shift and rotate
bits
 DX (Data)
 Used in multiply and divide, also used in I/O operations

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Memory Segment and Offset Concept
 The 8086 processor assign a 20-bit physical
address to its memory locations.
220 → 1 Mbyte
20 bits → 5 hex digits
First addresses: 00000, 00001,…,0000A,…FFFFF.
But Registers are 16-bits and can address only 216 =
64 KBytes.

 Partition the memory into segments

 One way four (4) 64 Kbytes segments might be positioned
within the 1 Mbyte address space of an 8086 processor.

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Memory Segment and Offset Concept
 Memory segment is a block of 216 (64) KBytes
consecutive memory bytes.

 Each segment is identified by a 16-bit number called

segment number, starting with 0000 up to FFFFh.
Segment registers hold segment number.

 Within a segment, a memory location is specified by

giving an offset (16-bit) = It is the number of bytes
from the beginning of the segment (0→ FFFFh).

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Memory Segment and Offset Concept
F0000 FFFF0 To FFFFF
E0000 is reserved for
D0000
ROM (16 bytes)
C0000
B0000
A0000
90000 8000:FFFF
80000 One Segment
8000:0000
70000
60000
50000 segment offset
40000
30000 00000 to 3FFFF
20000 is reserved in
10000 RAM to load
00000 system function/OS
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Memory Segment and Offset Concept
 A memory location may be specified by a segment
number and offset ( logical address ).
Example :
A4FB : 4872
h
Segment Offset

 Offset: is the distance from the beginning to a

particular location in the segment.

 Segment Number: defines the starting of the

segment within the memory space.
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Memory Segment and Offset Concept
F0000
E0000 8000:FFFF
D0000
C0000
B0000
A0000
90000
80000 one segment
70000
60000
8000:0250
50000
0250
40000
30000 8000:0000
20000
10000
seg ofs
00000

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Memory Segment and Offset Concept
 Segmented Memory Address:
 Start location of the segment must be 20 bits  the absolute
address is obtained by appending a hexadecimal zero to the
segment number, i.e. , multiplying by 16(10h).
 Adds 4 Nibble bits at the lower portion of each 16-bit address.
 So, the Physical Memory Address is equal to:
Physical Address = Segment number X 10h + Offset

 Physical Address for A4FB : 4872

A4FB0 h
+ 4872 h
A9822 h (20 Bits)
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Physical Location of Segments
 Segment 0
 starts at address 0000:0000  00000 h

 ends at address 0000:FFFF  0FFFF h

 Segment 1
 starts at address 0001:0000  00010 h
 ends at address 0001:FFFF  1000F h

 Overlap occurs between the Segment 0 and 1 having varying

size.
 Advantage: Utilization of memory would be higher.

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Physical Location of Segments
Segment Physical Address (hex)
…
10021
10020
End of Segment 2 1001F
1001E
…
10010
End of Segment 1 1000F
1000E
…
10000
End of Segment 0 0FFFF
0FFFE
…
00021
Start of Segment 2 00020
0001F
…
00011
Start of Segment 1 00010
0000F
…
00003
00002
00001
Start of Segment 0 00000

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Segment Registers
 Four Segment Registers in the BIU are used to hold the
upper 16-bits of the starting addresses of four memory
segments, namely
 Code segment CS: holds segment address of the code
segment.
 Data Segment DS: holds segment address of the data
segment.
 Extra Segment ES: extra segment : holds alternate
segment address of the data segment.
 Stack Segment SS: holds segment address of the stack
segment and used when sub-program executes.
 Codes , data , and stack are loaded into different memory
segments (registers).

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Memory Segment and Segment Registers

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Instruction Pointer (IP) and Code Segment
Register
 IP (Instruction pointer):
 Points to the next instruction.
 Offset address relative to CS
 Code segment CS: holds segment address of the code
segment.

 Suppose, CS = B3FFh and IP = 12ABh

 Physical Address of the next instruction:

B3FF0 h
+ 12AB h
B529B h (20 Bits)

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Stack Pointer and Index Registers
 Used for offset of data, often used as pointers. Unlike segment
registers, they can be used in arithmetic and other operations.
 SP (Stack Pointer):
 Used with SS for accessing the stack segment.
 Holds Offset address relative to SS
 Always points to word (byte at even address)
 An empty stack will had SP = FFFEh

 BP (Base Pointer):
 Used with SS to access data on the stack. However, unlike SP, BP
can be used to access data in other segments.
 Primarily used to access parameters passed via the stack
 Holds Offset address relative to SS

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Stack Pointer and Stack Segment Register
 Suppose, SS = 5D27h and SP = FFFEh

 Physical Address of the Top of Stack (ToS) information/data:

5D270 h
+ FFFE h
6D26E h (20 Bits)

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Data Pointer and Index Registers
 SI (Source Index):
 Source of string operations. Used with DS (or ES).
 Can be used for pointer addressing of data with effective
address (EA)
 Used as source in some string processing instructions
 Offset address relative to DS
 DI (Destination Index):
 Destination of string operation. Used with ES (or DS).
 Can be used for pointer addressing of data
 Used as destination in some string processing instructions
 Offset address relative to ES

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Source Index and Data Segment Register
 Suppose, DS = E000h and SI (EA) = 437Ah

 Physical Address of the data:

E0000 h
+ 437A h
E437A h (20 Bits)

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Flag Register
 Flags Register: A 16-Bits register specify status of CPU and
information about the results of the arithmetic operations.
 Flags Register determines the current state of the processor.
 It is modified automatically by CPU after mathematical
operations, this allows to determine the type of the result, and
to determine conditions to transfer control to other parts of
the program.
 Generally you cannot access these registers directly.

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Flag Register
 Carry Flag (CF) - this flag is set to ’1’ when there is
an unsigned overflow. For example when you add
bytes 255 + 1 (result is not in range 0...255). When there
is no overflow this flag is reset to 0.
 Parity Flag (PF) - this flag is set to ’1’ when there is
even number of one bits in result, and reset to ’0’ when
there is odd number of one bits.
 Auxiliary Flag (AF) - set to ’1’ when there is
an unsigned overflow for low nibble (4 bits).
 Zero Flag (ZF) - set to ’1’ when result is zero. For non-
zero result this flag is reset to ’0’.

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Flag Register
 Sign Flag (SF) - set to ’1’ when result is negative. When
result is positive it is reset to ‘0’. (This flag takes the value
of the most significant bit).
 Trap Flag (TF) - Used for on-chip single-step debugging.
 Interrupt enable Flag (IF) - when this flag is set
to ’1’ CPU reacts to interrupts from external devices.
 Direction Flag (DF) - this flag is used by some
instructions to process data chains, when this flag is set
to ’0’ - the processing is done forward, when this flag is
set to ‘1’ the processing is done backward.
 Overflow Flag (OF) - set to ’1’ when there is a signed
overflow. For example, when you add bytes 100 + 50.

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Flag Register (Example)

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Thank You !!

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