D

Pentium® II Processor
Developer’s Manual

243502-001
October 1997

1997

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 Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or
otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions
of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating
to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability,
or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical,
life saving, or life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice.

Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined."
Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising
from future changes to them.
The Pentium® II processor may contain design defects or errors known as errata which may cause the product to deviate
from published specifications. Current characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product
order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be
obtained from:

Intel Corporation
P.O. Box 5937
Denver, CO 80217-9808

or call 1-800-548-4725
or visit Intel’s website at http://www.intel.com
*Third-party brands and names are the property of their respective owners.
COPYRIGHT © INTEL CORPORATION, 1995, 1996, 1997

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TABLE OF CONTENTS

CHAPTER 1
COMPONENT INTRODUCTION
1.1. SYSTEM OVERVIEW.............................................................................................. 1-1
1.2. TERMINOLOGY...................................................................................................... 1-2
1.2.1. S.E.C. Cartridge Terminology .............................................................................. 1-3
1.3. REFERENCES ........................................................................................................ 1-3

CHAPTER 2
MICRO-ARCHITECTURE OVERVIEW
2.1. FULL CORE UTILIZATION...................................................................................... 2-2
2.2. THE PENTIUM® II PROCESSOR PIPELINE ........................................................... 2-3
2.2.1. The Fetch/Decode Unit ........................................................................................ 2-4
2.2.2. The Dispatch/Execute Unit................................................................................... 2-5
2.2.3. The Retire Unit .................................................................................................... 2-6
2.2.4. The Bus Interface Unit ......................................................................................... 2-7
2.3. MMX™ TECHNOLOGY AND THE PENTIUM® II PROCESSOR.............................. 2-9
2.3.1. MMX™ Technology in the Pentium® II Processor Pipeline ................................... 2-9
2.3.2. Caches...............................................................................................................2-13
2.4. WRITE BUFFERS ..................................................................................................2-14
2.5. ADDITIONAL INFORMATION ................................................................................2-14
2.6. ARCHITECTURE SUMMARY .................................................................................2-14

CHAPTER 3
SYSTEM BUS OVERVIEW
3.1. SIGNALING ON THE PENTIUM® II PROCESSOR SYSTEM BUS .......................... 3-1
3.2. SIGNAL OVERVIEW ............................................................................................... 3-2
3.2.1. Execution Control Signals .................................................................................... 3-2
3.2.2. Arbitration Signals................................................................................................ 3-3
3.2.3. Request Signals .................................................................................................. 3-5
3.2.4. Snoop Signals ..................................................................................................... 3-5
3.2.5. Response Signals................................................................................................ 3-6
3.2.6. Data Response Signals........................................................................................ 3-7
3.2.7. Error Signals........................................................................................................ 3-7
3.2.8. Compatibility Signals............................................................................................ 3-9
3.2.9. Diagnostic Signals ..............................................................................................3-10

CHAPTER 4
DATA INTEGRITY
4.1. ERROR CLASSIFICATION...................................................................................... 4-1
4.2. PENTIUM® II PROCESSOR SYSTEM BUS DATA INTEGRITY ARCHITECTURE ... 4-2
4.2.1. Bus Signals Protected Directly ............................................................................. 4-2
4.2.2. Bus Signals Protected Indirectly........................................................................... 4-3

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4.2.3.
E
Unprotected Bus Signals...................................................................................... 4-3
4.2.4. Hard-Error Response........................................................................................... 4-4
4.2.5. Pentium® II Processor System Bus Error Code Algorithms .................................. 4-4
4.2.5.1. PARITY ALGORITHM...................................................................................... 4-4
4.2.5.2. PENTIUM® II SYSTEM BUS ECC ALGORITHM.............................................. 4-4

CHAPTER 5
CONFIGURATION
5.1. DESCRIPTION........................................................................................................ 5-1
5.1.1. Output Tristate .................................................................................................... 5-2
5.1.2. Built-in Self Test .................................................................................................. 5-2
5.1.3. Data Bus Error Checking Policy ........................................................................... 5-3
5.1.4. Response Signal Parity Error Checking Policy...................................................... 5-3
5.1.5. AERR# Driving Policy .......................................................................................... 5-3
5.1.6. AERR# Observation Policy .................................................................................. 5-3
5.1.7. BERR# Driving Policy for Initiator Bus Errors........................................................ 5-3
5.1.8. BERR# Driving Policy for Target Bus Errors......................................................... 5-3
5.1.9. Bus Error Driving Policy for Initiator Internal Errors............................................... 5-4
5.1.10. BINIT# Driving Policy ........................................................................................... 5-4
5.1.11. BINIT# Observation Policy ................................................................................... 5-4
5.1.12. In-Order Queue Pipelining ................................................................................... 5-4
5.1.13. Power-On Reset Vector....................................................................................... 5-4
5.1.14. FRC Mode Enable ............................................................................................... 5-4
5.1.15. APIC Mode.......................................................................................................... 5-5
5.1.16. APIC Cluster ID ................................................................................................... 5-5
5.1.17. Symmetric Agent Arbitration ID ............................................................................ 5-5
5.1.18. Low Power Standby Enable ................................................................................. 5-6
5.2. CLOCK FREQUENCIES AND RATIOS.................................................................... 5-6
5.3. SOFTWARE-PROGRAMMABLE OPTIONS............................................................. 5-7
5.4. INITIALIZATION PROCESS .................................................................................... 5-9

CHAPTER 6
TEST ACCESS PORT (TAP)
6.1. INTERFACE ............................................................................................................ 6-1
6.2. ACCESSING THE TAP LOGIC................................................................................ 6-2
6.2.1. Accessing the Instruction Register ....................................................................... 6-4
6.2.2. Accessing the Data Registers .............................................................................. 6-6
6.3. INSTRUCTION SET ................................................................................................ 6-7
6.4. DATA REGISTER SUMMARY ................................................................................. 6-8
6.4.1. Bypass Register .................................................................................................. 6-8
6.4.2. Device ID Register............................................................................................... 6-8
6.4.3. BIST Result Boundary Scan Register................................................................... 6-9
6.4.4. Boundary Scan Register ...................................................................................... 6-9
6.5. RESET BEHAVIOR ................................................................................................. 6-9

CHAPTER 7
ELECTRICAL SPECIFICATIONS
7.1. THE PENTIUM® II PROCESSOR SYSTEM BUS AND VREF .................................. 7-1
7.2. CLOCK CONTROL AND LOW POWER STATES .................................................... 7-2

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7.2.1.
CONTENTS

Normal State — State 1....................................................................................... 7-3

7.2.2. Auto HALT Power Down State — State 2............................................................. 7-3
7.2.3. Stop-Grant State — State 3 ................................................................................. 7-3
7.2.4. HALT/Grant Snoop State — State 4..................................................................... 7-4
7.2.5. Sleep State — State 5 ......................................................................................... 7-4
7.2.6. Deep Sleep State — 6 ......................................................................................... 7-5
7.2.7. Clock Control and Low Power Modes................................................................... 7-5
7.3. POWER AND GROUND PINS................................................................................. 7-5
7.4. DECOUPLING GUIDELINES................................................................................... 7-6
7.4.1. Pentium® II Processor VccCORE Decoupling ...................................................... 7-6
7.4.2. System Bus GTL+ Decoupling ............................................................................. 7-6
7.5. SYSTEM BUS CLOCK AND PROCESSOR CLOCKING .......................................... 7-7
7.5.1. Mixing Processors of Different Frequencies ......................................................... 7-9
7.6. VOLTAGE IDENTIFICATION................................................................................... 7-9
7.7. PENTIUM® II PROCESSOR SYSTEM BUS UNUSED PINS ...................................7-11
7.8. PENTIUM® II PROCESSOR SYSTEM BUS SIGNAL GROUPS..............................7-12
7.8.1. Asynchronous vs. Synchronous for System Bus Signals .....................................7-12
7.9. TEST ACCESS PORT (TAP) CONNECTION..........................................................7-14
7.10. MAXIMUM RATINGS .............................................................................................7-14
7.11. PROCESSOR SYSTEM BUS DC SPECIFICATIONS..............................................7-14
7.12. PENTIUM® II PROCESSOR SYSTEM BUS AC SPECIFICATIONS ........................7-19

CHAPTER 8
GTL+ INTERFACE SPECIFICATIONS
8.1. SYSTEM SPECIFICATION...................................................................................... 8-1
8.1.1. System Bus Specifications................................................................................... 8-2
8.1.2. System AC Parameters: Signal Quality ................................................................ 8-3
8.1.2.1. RINGBACK TOLERANCE ................................................................................ 8-5
8.1.3. AC Parameters: Flight Time................................................................................. 8-7
8.2. GENERAL GTL+ I/O BUFFER SPECIFICATION ....................................................8-13
8.2.1. I/O Buffer DC Specification .................................................................................8-13
8.2.2. I/O Buffer AC Specifications................................................................................8-14
8.2.3. Determining Clock-to-Out, Setup and Hold..........................................................8-14
8.2.3.1. CLOCK-TO-OUTPUT TIME, TCO ...................................................................8-14
8.2.3.2. MINIMUM SETUP AND HOLD TIMES ............................................................8-16
8.2.3.3. RECEIVER RINGBACK TOLERANCE ............................................................8-19
8.2.4. System-Based Calculation of Required Input and Output Timings .......................8-19
8.2.4.1. CALCULATING TARGET TFLIGHT_MAX .......................................................8-19
8.2.4.2. CALCULATING TARGET THOLD ...................................................................8-20
8.3. PACKAGE SPECIFICATION ..................................................................................8-20

CHAPTER 9
SIGNAL QUALITY SPECIFICATIONS
9.1. SYSTEM BUS CLOCK (BCLK) SIGNAL QUALITY SPECIFICATIONS ..................... 9-1
9.2. GTL+ SIGNAL QUALITY SPECIFICATIONS............................................................ 9-3
9.3. NON-GTL+ SIGNAL QUALITY SPECIFICATIONS................................................... 9-3
9.3.1. Overshoot/Undershoot Guidelines ....................................................................... 9-3
9.3.2. Ringback Specification......................................................................................... 9-4
9.3.3. Settling Limit Guideline ........................................................................................ 9-5

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CHAPTER 10
THERMAL SPECIFICATIONS AND DESIGN CONSIDERATIONS
10.1. THERMAL SPECIFICATIONS ................................................................................10-1
10.2. PENTIUM® II PROCESSOR THERMAL ANALYSIS ...............................................10-2
10.2.1. Thermal Solution Performance............................................................................10-2
10.2.2. Measurements for Thermal Specifications...........................................................10-3
10.2.2.1. THERMAL PLATE TEMPERATURE MEASUREMENT ....................................10-3
10.2.2.2. COVER TEMPERATURE MEASUREMENT ....................................................10-5
10.3. THERMAL SOLUTION ATTACH METHODS ..........................................................10-6
10.3.1. Heatsink Clip Attach ...........................................................................................10-7
10.3.2. Rivscrew* Attach ................................................................................................10-9

CHAPTER 11
S.E.C. CARTRIDGE MECHANICAL SPECIFICATIONS
11.1. S.E.C. CARTRIDGE MATERIALS INFORMATION .................................................11-1
11.2. PROCESSOR EDGE FINGER SIGNAL LISTING..................................................11-13

CHAPTER 12
BOXED PROCESSOR SPECIFICATIONS
12.1. INTRODUCTION....................................................................................................12-1
12.2. MECHANICAL SPECIFICATIONS ..........................................................................12-2
12.2.1. Boxed Processor Fan/Heatsink Dimensions ........................................................12-2
12.2.2. Boxed Processor Fan/Heatsink Weight ...............................................................12-4
12.2.3. Boxed Processor Retention Mechanism and Fan/Heatsink Support.....................12-4
12.3. BOXED PROCESSOR REQUIREMENTS...............................................................12-8
12.3.1. Fan/Heatsink Power Supply ................................................................................12-8
12.4. THERMAL SPECIFICATIONS ..............................................................................12-10
12.4.1. Boxed Processor Cooling Requirements ...........................................................12-10

CHAPTER 13
INTEGRATION TOOLS
13.1. IN-TARGET PROBE (ITP) FOR THE PENTIUM® II PROCESSOR .........................13-1
13.1.1. Primary Function ................................................................................................13-1
13.1.2. Debug Port Connector Description ......................................................................13-2
13.1.3. Debug Port Signal Descriptions...........................................................................13-2
13.1.4. Debug Port Signal Notes.....................................................................................13-3
13.1.4.1. SIGNAL NOTE 1: DBRESET#.........................................................................13-3
13.1.4.2. SIGNAL NOTE 5: TDO AND TDI.....................................................................13-3
13.1.4.3. SIGNAL NOTE 7: TCK....................................................................................13-7
13.1.5. Debug Port Layout..............................................................................................13-8
13.1.5.1. SIGNAL QUALITY NOTES............................................................................13-10
13.1.5.2. DEBUG PORT CONNECTOR .......................................................................13-10
13.1.6. Using Boundary Scan to Communicate to the Processor...................................13-11
13.2. INTEGRATION TOOL CONSIDERATIONS ..........................................................13-11
13.2.1. Integration Tool Mechanical Keepouts...............................................................13-11
13.2.2. Pentium® II Processor LAI System Design Considerations ...............................13-11

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CHAPTER 14
ADVANCED FEATURES
14.1. ADDITIONAL INFORMATION ................................................................................14-1

APPENDIX A
SIGNALS REFERENCE

Figures
Figure Title Page
1-1. Second Level Cache Implementations ................................................................. 1-2
2-1. Three Engines Communicating Using an Instruction Pool..................................... 2-1
2-2. A Typical Pseudo Code Fragment........................................................................ 2-2
2-3. The Three Core Engines Interface with Memory via Unified Caches ..................... 2-3
2-4. Inside the Fetch/Decode Unit ............................................................................... 2-4
2-5. Inside the Dispatch/Execute Unit.......................................................................... 2-5
2-6. Inside the Retire Unit ........................................................................................... 2-7
2-7. Inside the Bus Interface Unit ................................................................................ 2-8
2-8. Out of Order Core and Retirement Pipeline.........................................................2-10
2-9. Out-of-Order Core and Retirement Pipeline ........................................................2-12
3-1. Latched Bus Protocol........................................................................................... 3-1
5-1. Hardware Configuration Signal Sampling ............................................................. 5-1
6-1. Simplified Block Diagram of Processor TAP Logic ................................................ 6-2
6-2. TAP Controller Finite State Machine .................................................................... 6-3
6-3. Processor TAP Instruction Register ..................................................................... 6-5
6-4. Operation of the Processor TAP Instruction Register............................................ 6-5
6-5. TAP Instruction Register Access .......................................................................... 6-6
7-1. GTL+ Bus Topology............................................................................................. 7-1
7-2. Stop Clock State Machine.................................................................................... 7-2
7-3. Timing Diagram of Clock Ratio Signals................................................................. 7-7
7-4. Example Schematic for Clock Ratio Pin Sharing................................................... 7-8
7-5. BCLK to Core Logic Offset..................................................................................7-25
7-6. BCLK, PICCLK, TCK Generic Clock Waveform...................................................7-25
7-7. System Bus Valid Delay Timings.........................................................................7-26
7-8. System Bus Setup and Hold Timings ..................................................................7-26
7-9. FRC Mode BCLK to PICCLK Timing ...................................................................7-27
7-10. System Bus Reset and Configuration Timings.....................................................7-27
7-11. Power-On Reset and Configuration Timings........................................................7-28
7-12. Test Timings (TAP Connection) ..........................................................................7-29
7-13. Test Reset Timings.............................................................................................7-29
8-1. Example Terminated Bus with GTL+ Transceivers ............................................... 8-2
8-2. Receiver Waveform Showing Signal Quality Parameters...................................... 8-3
8-3. Low to High GTL+ Receiver Ringback Tolerance ................................................. 8-5
8-4. Standard Input Hi-to-Lo Waveform for Characterizing Receiver
Ringback Tolerance ............................................................................................. 8-6
8-5. Measuring Nominal Flight Time............................................................................ 8-8
8-6. Flight Time of a Rising Edge Slower than 0.3V/ns ................................................ 8-9
8-7. Extrapolated Flight Time of a Non-Monotonic Rising Edge ..................................8-10
8-8. Extrapolated Flight Time of a Non-Monotonic Falling Edge ..................................8-11
8-9. Test Load for Measuring Output AC Timings.......................................................8-15
8-10. Clock to Output Data Timing (TCO) ....................................................................8-15

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8-11. Standard Input Lo-to-Hi Waveform for Characterizing Receiver Setup Time ........8-17
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8-12. Standard Input Hi-to-Lo Waveform for Characterizing Receiver Setup Time ........8-18
9-1. BCLK, TCK PICCLK Generic Clock Waveform at the Processor Edge Fingers ..... 9-2
9-2. Non-GTL+ Overshoot/Undershoot and Ringback Tolerance ................................. 9-4
10-1. Processor S.E.C. Cartridge Thermal Plate ..........................................................10-1
10-2. Processor Thermal Plate Temperature Measurement Location ...........................10-4
10-3. Technique for Measuring TPLATE with 0° Angle Attachment...............................10-4
10-4. Technique for Measuring TPLATE with 90° Angle Attachment.............................10-5
10-5. Guideline Locations for Cover Temperature (TCOVER) Thermocouple
Placement ..........................................................................................................10-6
10-6. Heatsink Attachment Mechanism Design Space..................................................10-7
10-7. Processor with an Example Low Profile Heatsink Attached using Spring Clips .....10-8
10-8. Processor with an Example Full Height Heatsink Attached using Spring Clips......10-8
10-9. Heatsink Recommendations and Guidelines for Use with Rivscrews* ..................10-9
10-10. Heatsink, Rivscrew* and Thermal Plate Recommendations and Guidelines .........10-9
10-11. General Rivscrew* Heatsink Mechanical Recommendations .............................10-10
11-1. S.E.C. Cartridge—Thermal Plate and Cover Side Views......................................11-3
11-2. S.E.C. Cartridge Top and Side Views..................................................................11-4
11-3. S.E.C. Cartridge Bottom Side View .....................................................................11-5
11-4. S.E.C. Cartridge Thermal Plate Side Dimensions ................................................11-6
11-5. S.E.C. Cartridge Thermal Plate Flatness Dimensions..........................................11-6
11-6. S.E.C. Cartridge Thermal Plate Attachment Detail Dimensions............................11-7
11-7. S.E.C. Cartridge Latch Arm, Thermal Plate Lug and Cover Lug Dimensions........11-8
11-8. S.E.C. Cartridge Latch Arm, Cover and Thermal Plate Detail Dimensions ...........11-9
11-9. S.E.C. Cartridge Substrate Dimensions (Skirt not shown for clarity) ..................11-10
11-10. S.E.C. Cartridge Substrate Dimensions, Cover Side View .................................11-10
11-11. S.E.C. Cartridge Substrate—Detail A ................................................................11-11
11-12. S.E.C. Cartridge Mark Locations (Processor Markings) .....................................11-12
12-1. Conceptual Boxed Pentium® II Processor in Retention Mechanism.....................12-2
12-2. Side View Space Requirements for the Boxed Processor (Fan/heatsink
supports not shown) ...........................................................................................12-3
12-3. Front View Space Requirements for the Boxed Processor...................................12-3
12-4. Top View Space Requirements for the Boxed Processor.....................................12-4
12-5. Heatsink Support Hole Locations and Sizes ........................................................12-6
12-6. Side View Space Requirements for Boxed Processor Fan/Heatsink Supports......12-7
12-7. Top View Space Requirements for Boxed Processor Fan/Heatsink Supports.......12-8
12-8. Boxed Processor Fan/Heatsink Power Cable Connector Description ...................12-9
12-9. Recommended Motherboard Power Header Placement Relative to Fan Power
Connector and Slot 1 ........................................................................................12-10
13-1. Hardware Components of the ITP .......................................................................13-2
13-2. GTL+ Signal Termination ....................................................................................13-3
13-3. TCK/TMS with Series and Parallel Termination, Single Processor Configuration..13-6
13-4. TCK/TMS with Daisy Chain Configuration, 2-Way MP Configuration....................13-7
13-5. TCK with Daisy Chain Configuration....................................................................13-8
13-6. Generic DP System Layout for Debug Port Connection.......................................13-9
13-7. Debug Port Connector on Thermal Plate Side of Circuit Board ..........................13-10
13-8. Hole Positioning for Connector on Thermal Plate Side of Circuit Board..............13-10
13-9. Processor System where Boundary Scan is Not Used.......................................13-11
13-10. LAI Probe Input Circuit......................................................................................13-12
13-11. Pentium® II Processor Integration Tool Mechanical Keep Out Volume—
Thermal Plate Side View...................................................................................13-13
13-12. Pentium® II Processor Integration Tool Mechanical Keep Out Volume—
Cover Side View ...............................................................................................13-14

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13-13. Pentium® II Processor Integration Tool Mechanical Keep Out Volume—
CONTENTS

Side View .........................................................................................................13-15

A-1. PWRGOOD Relationship at Power-On............................................................... A-11

Tables
Table Title Page
2-1. Pentium® II Processor Execution Unit Pipelines..................................................2-13
3-1. Execution Control Signals .................................................................................... 3-2
3-2. Arbitration Signals................................................................................................ 3-4
3-3. Request Signals .................................................................................................. 3-5
3-4. Snoop Signals ..................................................................................................... 3-5
3-5. Response Signals................................................................................................ 3-6
3-6. Data Phase Signals ............................................................................................. 3-7
3-7. Error Signals........................................................................................................ 3-7
3-8. PC Compatibility Signals...................................................................................... 3-9
3-9. Diagnostic Support Signals .................................................................................3-10
4-1. Direct Bus Signal Protection................................................................................. 4-2
5-1. APIC Cluster ID Configuration for the Pentium® II Processor Family 1 ................. 5-5
5-2. Pentium® II Processor Bus BREQ[1:0]# Interconnect (Two Agents)..................... 5-5
5-3. Arbitration ID Configuration with Processors Supporting BR[1:0]# 1 ..................... 5-6
5-4. Pentium® II Processor Family Power-On Configuration Register.......................... 5-7
5-5. Pentium® II Processor Family Power-On Configuration Register APIC
Cluster ID Bit Field............................................................................................... 5-8
5-6. Pentium® II Processor Family Power-On Configuration Register Arbitration
ID Configuration................................................................................................... 5-8
5-7. Pentium® II Processor Family Power-On Configuration Register Bus Frequency
to Core Frequency Ratio Bit Field ........................................................................ 5-8
6-1. 1149.1 Instructions in the Processor TAP............................................................. 6-7
6-2. TAP Data Registers ............................................................................................. 6-8
6-3. Device ID Register............................................................................................... 6-9
6-4. TAP Reset Actions............................................................................................... 6-9
7-1. Core Frequency to System Bus Multiplier Configuration ....................................... 7-7
7-2. Voltage Identification Definition (1, 2, 3) ..............................................................7-10
7-3. Recommended Pull-Up Resistor Values (Approximate) for CMOS
Signals ...............................................................................................................7-11
7-4. Pentium® II Processor/Slot 1 System Bus Signal Groups....................................7-13
7-5. Pentium® II Processor Absolute Maximum Ratings.............................................7-15
7-6. Pentium® II Processor/Slot 1 Connector Voltage/Current Specifications..............7-16
7-7. GTL+ Signal Groups DC Specifications...............................................................7-18
7-8. Non-GTL+ Signal Groups DC Specifications .......................................................7-18
7-9. System Bus AC Specifications (Clock) (1, 2) .......................................................7-20
7-10. Valid Pentium® II Processor System Bus, Core Frequency and Cache Bus
Frequencies (1, 2) ..............................................................................................7-21
7-11. Pentium® II Processor System Bus AC Specifications (GTL+ Signal Group) .......7-21
7-12. Pentium® II Processor System Bus AC Specifications (CMOS Signal Group)......7-22
7-13. System Bus AC Specifications (Reset Conditions)...............................................7-22
7-14. System Bus AC Specifications (APIC Clock and APIC I/O) (1, 2).........................7-23
7-15. System Bus AC Specifications (TAP Connection) (1) ..........................................7-24
8-1. Pentium® II Processor GTL+ Bus Specifications (1)............................................. 8-3
8-2. Specifications for Signal Quality ........................................................................... 8-4
8-3. I/O Buffer DC Parameters...................................................................................8-13

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8-4.
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I/O Buffer AC Parameters...................................................................................8-14
9-1. BCLK Signal Quality Specifications ...................................................................... 9-1
9-2. GTL+ Signal Groups Ringback Tolerance ............................................................ 9-3
9-3. Signal Ringback Specifications for Non-GTL+ Signals .......................................... 9-5
10-1. Pentium® II Processor Thermal Design Specifications (1) ...................................10-2
10-2. Example Thermal Solution Performance for 266 MHz Pentium® II
Processor at Thermal Plate Power of 37.0 Watts ................................................10-3
11-1. S.E.C. Cartridge Materials ..................................................................................11-2
11-2. Description Table for Processor Markings .........................................................11-12
11-3. Signal Listing in Order by Pin Number...............................................................11-13
11-4. Signal Listing in Order by Signal Name .............................................................11-18
12-1. Boxed Processor Fan/Heatsink Spatial Dimensions.............................................12-4
12-2. Boxed Processor Fan/Heatsink Support Dimensions ...........................................12-5
12-3. Fan/Heatsink Power and Signal Specifications ....................................................12-9
13-1. Debug Port Pinout Description and Requirements 1 ............................................13-4
A-1. BR0#(I/O), BR1#, BR2#, BR3# Signals Rotating Interconnect .............................. A-4
A-2. BR[3:0]# Signal Agent IDs ................................................................................... A-4
A-3. Burst Order Used for Pentium® II Processor Bus Line Transfers.......................... A-5
A-4. Slot 1 Occupation Truth Table............................................................................ A-13
A-5. Output Signals (1).............................................................................................. A-16
A-6. Input Signals (1) ................................................................................................ A-17
A-7. Input/Output Signals (Single Driver) ................................................................... A-18
A-8. Input/Output Signals (Multiple Drivers) ............................................................... A-18

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