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Mt6328 Pmic Data Sheet v1

The MT6328 PMIC datasheet provides detailed specifications for a power management integrated circuit designed for 2G/3G/4G smartphones, featuring 5 buck converters and 28 LDOs. It includes information on electrical characteristics, functional descriptions, and applications, along with pin assignments and ordering information. The document is proprietary to MediaTek Inc. and is subject to change without notice.

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100% found this document useful (1 vote)

74 views304 pages

Mt6328 Pmic Data Sheet v1

Uploaded by

moviluna6

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Available Formats

Download as PDF, TXT or read online on Scribd

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MT6328 PMIC Datasheet

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Version: 1.0
Release date: 2015-03-16
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Specifications are subject to change without notice.

© 2015 MediaTek Inc.

This document contains information that is proprietary to MediaTek Inc.
Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited.
MT6328
PMIC Datasheet
Confidential A

Document Revision History

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Revision Date Author Description
0.1 2014-12-01 Luke Tsai Initial draft
1.0 2015-03-13 Luke Tsai First release

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Table of Contents

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Document Revision History ............................................................................................. 2
Table of Contents .............................................................................................................. 3
1 Overview .................................................................................................................. 6
1.1 Features ..................................................................................................................................... 6

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1.2 Applications ............................................................................................................................... 6
1.3 General Descriptions................................................................................................................. 6
1.4 Ordering Information ................................................................................................................ 7

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1.5 Top Marking Definition ............................................................................................................. 7
1.6 Pin Assignments and Descriptions .......................................................................................... 8
2 Electrical Characteristics ....................................................................................... 13
2.1 Absolute Maximum Ratings over Operating Free-Air Temperature Range ......................... 13

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2.2 Thermal Characteristic ............................................................................................................ 13
2.3 Pin Voltage Range .................................................................................................................... 13
2.4 Recommended Operating Range ............................................................................................ 17
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2.5 Electrical Characteristics ......................................................................................................... 17
2.6 Regulator Output ..................................................................................................................... 18
2.7 Driver ....................................................................................................................................... 25
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2.8 Class AB/D Audio Amplifier ................................................................................................... 25

2.9 Audio CODEC .......................................................................................................................... 29
2.10 Battery Charger ........................................................................................................................35
2.11 BC1.x .........................................................................................................................................35
2.12 Down Load Without Battery ....................................................................................................35
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2.13 AUXADC .................................................................................................................................. 36

2.14 Fuel Gauge ............................................................................................................................... 36
3 Functional Descriptions ......................................................................................... 37
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3.1 General Descriptions................................................................................................................37

3.2 PMIC Functional Blocks ..........................................................................................................37
3.2.1 Power-On/Off Sequence .......................................................................................... 38
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3.2.2 Buck Converter and Application Reference ............................................................ 40

3.2.3 Low Dropout Regulator (LDOs) and Application Reference .................................. 41
3.2.4 Drivers ....................................................................................................................... 43
3.2.5 Vibrator Driver.......................................................................................................... 44
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3.2.6 Audio CODEC and Accessory Detection .................................................................. 45

3.2.7 Class-AB/D Audio Amplifier .................................................................................... 46
3.2.8 Battery Charger (Charger Controller).......................................................................47
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3.2.9 AUXADC .................................................................................................................... 51

3.2.10 Fuel Gauge ................................................................................................................. 51
3.2.11 Real-time Clock ......................................................................................................... 52
3.2.12 Interrupt and Watchdog ........................................................................................... 54
3.2.13 SPI Interface ............................................................................................................. 59
3.2.14 GPIO ........................................................................................................................... 61
3.3 Register Table and Descriptions ............................................................................................ 63

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4 Application Notes ................................................................................................. 301

4.1 Hardware External Shutdown ...............................................................................................301
4.2 Configuration for Unused Buck Converter .......................................................................... 302

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5 MT6328 Packaging ............................................................................................... 303
5.1 Package Dimensions ............................................................................................................. 303
Appendix ...................................................................................................................... 304

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Lists of Tables

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Table 1-1. MT6328 pin descriptions ............................................................................................................ 8
Table 2-1. Absolute maximum ratings ........................................................................................................ 13
Table 2-2. Pin voltage range........................................................................................................................ 13

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Table 2-3. Operation condition ................................................................................................................... 17
Table 2-4. General electrical specifications ............................................................................................... 18
Table 2-5. Buck specifications..................................................................................................................... 18
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Table 2-6. LDO specifications ..................................................................................................................... 21
Table 2-7. Driver specifications ................................................................................................................. 25
Table 2-8. Class AB/D audio amplifier specifications .............................................................................. 25
Table 2-9. Audio downlink specifications ................................................................................................. 29
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Table 2-10. Audio uplink specifications ..................................................................................................... 31

Table 2-11. MICBIAS specifications ........................................................................................................... 34
Table 2-12. ACCDET specifications ........................................................................................................... 34
Table 2-13. Charger specifications ............................................................................................................. 35
Table 2-14. BC1.x specifications ................................................................................................................. 35
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Table 2-15. Download without battery specifications............................................................................... 35

Table 2-16. AUXADC specifications .......................................................................................................... 36
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Table 2-17. Fuel gauge specifications ........................................................................................................ 36

Table 3-1. Buck converter brief specifications .......................................................................................... 40
Table 3-2. LDO types and brief specifications ........................................................................................... 41
Table 3-3. Application and input range of ADC channels ......................................................................... 51
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Table 3-4. Functional specifications of XOSC32 ...................................................................................... 54

Table 3-5. Recommended parameters of 32kHz crystal .......................................................................... 54
Table 3-6. MT6328 interrupts ................................................................................................................... 56
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Table 3-7. MT6328 GPIO list ...................................................................................................................... 61

Table 3-8. MT6328 GPIO electrical characteristics ................................................................................. 62

Lists of Figures
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Figure 1-1. MT6328 VFBGA 205 (6.6x6.6mm) pin assignment ................................................................ 8

Figure 2-1. THD+N v.s. output power (Class AB/D, VBAT=4.2/3.8/3.4V, gain=12dB) ........................ 28
Figure 2-2. PSRR with 217Hz TDMA noise (Class AB/D, VBAT=3.8V, gain=12dB) ............................. 28
Figure 2-3. Audio path THD+N v.s. frequency .......................................................................................... 31
Figure 2-4. Audio path Xtalk v.s. frequency @POUT=10mW ..................................................................... 31
Figure 2-5. Frequency response (16kHz) .................................................................................................. 33

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Figure 2-6. Frequency response (48kHz) ................................................................................................. 33

Figure 3-1. MT6328 block diagram ............................................................................................................37
Figure 3-2. Power-on/off control sequence with XTAL by pressing PWRKEY ...................................... 38

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Figure 3-3. Power-on/off control sequence with XTAL by charger plug in ............................................ 39
Figure 3-4. Configuration for indicator LED drivers ................................................................................ 44
Figure 3-5. Audio CODEC block diagram ................................................................................................. 46
Figure 3-6. Block diagram of class-AB/D...................................................................................................47

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Figure 3-7. Block diagram of battery charger ........................................................................................... 48
Figure 3-8. Flow chart of charging states .................................................................................................. 49
Figure 3-9. Fuel gauge block diagram and external connection .............................................................. 52

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Figure 3-10. RTC configuration methods for XTAL ................................................................................. 53
Figure 3-11. RTC configuration methods for w/o XTAL mode ................................................................ 53
Figure 4-1. Hardware external shut-down function ................................................................................301
Figure 4-2. Configuration for unused DC/DC ........................................................................................ 302

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Figure 5-1. Package dimension ................................................................................................................ 303
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1 Overview

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phones, containing 5 buck converters and 28
1.1 Features LDOs optimized for specific 2G/3G/4G smart
phone subsystems.

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 Handles all 2G/3G/4G smart phone
baseband power management LED drivers support up to 2 channels of LEDs
 Input range: 2.5 ~ 4.5V with independent control. Flexible control

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 5 buck converters and 28 LDOs includes register mode, PWM mode and breath
optimized for specific 2G/3G/4G smart mode.
phone subsystems
 Full-set high-quality audio feature: Sophisticated controls are available for power-


Supports uplink/downlink audio CODEC.
32K RTC oscillator for system timing, 1.8
and 2.8V clock buffer output
ID up, battery charging and the RTC alarm.
MT6328 is optimized for maximum battery life,
allowing the RTC circuit to stay alive without a
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 Flexibility for various configurations of battery for several hours.
indicator LED current source: 2 ISINK
 SPI interface MT6328 adopts SPI interface and 2 SRCLKEN
 Li-ion battery charging function control pins to control buck converters, LDOs,
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 USB Battery Charging Specification ver and various drivers; it provides enhanced
1.1/1.2 (BC1.x) Compliance safety control and protocol for handshaking
 Over-current and thermal overload with BB.
protection
 Programmable under voltage lockout MT6328 is available in a 205-pin VFBGA
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protection package. The operating temperature ranges

 Watchdog reset from -25 to +65°C.
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 Flexibility hardware PMIC reset function

 Power-on reset and start-up timer
 Precision voltage, temperature, and
current measurement fuel gauge
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 205-pin VFBGA package

1.2 Applications
MT6328 is ideal for power management of 2G,
3G and 4G smart phones and other portable
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systems.

1.3 General Descriptions

MT6328 is a power management system chip
optimized for 2G/3G/4G handsets and smart

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1.4 Ordering Information

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Order # Marking Temp. range Package
MT6328V/A -25 ~ +65°
C VFBGA 205L

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1.5 Top Marking Definition
MT6328V/A

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YYWW: Date code

$: Random code
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1.6 Pin Assignments and Descriptions

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Figure 1-1. MT6328 VFBGA 205 (6.6x6.6mm) pin assignment

Table 1-1. MT6328 pin descriptions

Ball Symbol I/O Description

A1,B1 AVDD45_VSYS22 PWR Power supply of VSYS22
A2,B2 VSYS22 O SW node of VSYS22
A3,B3 AVSS45_VSYS22 GND VSYS22 ground
C3 VSYS22_FB I BUCK VSYS22 feedback pin
B4,C5,C4 AVDD45_VCORE1 PWR Power supply of VCORE1

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Ball Symbol I/O Description

A5,A6,B5 VCORE1 O SW node of VCORE1
B6,C6,D6 AVSS45_VCORE1 GND VCORE1 ground

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C1 AVSS45_VCORE1_FB I Remote sense on ground of VCORE1
C2 VCORE1_FB I BUCK VCORE1 feedback pin
B10,B11,C10,D10 AVDD45_VPROC PWR Power supply of VPROC
A7,B7,B8,C7,D7 VPROC O SW node of VPROC

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A9,B9,C8,C9,D9 AVSS45_VPROC GND VPROC ground
B15 AVSS45_VPROC_FB I Remote sense on ground of VPROC
C16 VPROC_FB I BUCK VPROC feedback pin

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B13,C13,D13 AVDD45_VLTE PWR Power supply of VLTE
A12,B12,C12 VLTE O SW node of VLTE
C11,D11,D12 AVSS45_VLTE GND VLTE ground
E13 AVSS45_VLTE_FB I Remote sense on ground of VLTE
C14
A16
A15
VLTE_FB
AVDD45_VPA
VPA
I

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PWR
O
BUCK VLTE feedback pin
Power supply of VPA
SW node of VPA
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A14 AVSS45_VPA GND VPA ground
B14 VPA_FB I BUCK VPA feedback pin
C15 AVDD45_SMPS PWR Power supply of buck controller
B16 AVSS45_SMPS GND Ground of buck controller
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D5,E5,E6,E7,E8,E9,
E10,E11,E12,F11,F12,
G6,G7,G8,G9,G10,G
11,G12,H6,H7,H8,H AVSS45_LDO GND LDO ground
9,H10,H11,H12,J6,J
7,J8,J9,J10,J11,K7,K
8,K9,K10,K11,L7,L8,
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L9,L10,L11,L12
T13 AVDD45_LDO1 PWR Power supply input of LDO group1
T8 AVDD45_LDO2 PWR Power supply input of LDO group2
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K1 AVDD45_LDO3 PWR Power supply input of LDO group3

T11 AVDD45_LDO4 PWR Power supply input of LDO group4
M2 AVDD45_LDO5 PWR Power supply input of LDO group5
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H3 AVDD22_LDO1 PWR Power supply input of SYS LDO group1

J2 AVDD22_LDO1 PWR Power supply input of SYS LDO group1
E1 AVDD22_LDO2 PWR Power supply input of SYS LDO group2
F1 AVDD22_LDO3 PWR Power supply input of SYS LDO group3
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G1 AVDD22_LDO4 PWR Power supply input of SYS LDO group4

P9 VTCXO_0 O VTCXO_0 output voltage
T16 VTCXO_1 O VTCXO_1 output voltage
F10 VRF18_0 O VRF18_0 output voltage
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F9 VRF18_1 O VRF18_1 output voltage

J1 VM O VDRAM output voltage
E4 VSRAM O VSRAM output voltage
H2 VCAMD O VCAMD output voltage
T14 VCAMA O VCAMA output voltage
E3 VCAMIO O VCAMIO output voltage

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Ball Symbol I/O Description

H5 VCAMAF O VCAMAF output voltage
F2 VIO18 O VIO18 output voltage

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K2 VIO28 O VIO28 output voltage
K4 VMC O VMC output voltage
R9 VMCH O VMCH output voltage
R10 VEMC_3V3 O VEMC_3V3 output voltage

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T15 VEFUSE O VEFUSE output voltage
P11 VUSB33 O VUSB33 output voltage
R11 VSIM1 O VSIM1 output voltage

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N11 VSIM2 O VSIM2 output voltage
F3 VCN18 O VCN18 output voltage
R13 VCN28 O VCN28 output voltage
R12 VCN33 O VCN33 output voltage
R14
R15
H4
J4
VAUD28
VAUX18
VGP1
VIBR
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O
O
O
VAUD28 output voltage
VAUX18 output voltage
VGP1 output voltage
VIBR output voltage
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E2 PWRKEY I PWRKEY button
D2 EXT_PMIC_EN O Ext PMIC enable pin
D3 RESETB O System reset release signal
M7 WDTRSTB_IN I Watchdog reset from AP
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PMU test mode signal (tied to GND in normal

D4 PMU_TESTMODE I
operation)
L4 VREF O Band gap reference voltage
L3 AVSS45_VREF GND Ground for band gap
N5 SPI_MISO IO SPI control interface
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L6 SPI_MOSI IO SPI control interface

K6 SPI_CLK I SPI control interface
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M6 SPI_CSN IO SPI control interface

N2 UVLO_VTH I UVLO threshold control pin
N6 HOMEKEY I HOMEKEY button
P4 FSOURCE PWR EFUSE power source
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P8 SRCLKEN_IN0 I Source clock enable pin 0

R5 SRCLKEN_IN1 I Source clock enable pin 1
M12 AVDD18_AUXADC PWR 1.8V power supply of AUXADC
M14 ACCDET I Accessory detection input
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P14 AUXADC_VIN I AUXADC input

N13 AVSS18_AUXADC GND AUXADC ground
Negative terminal for battery's charging current
N3 BATSNS I
sensing resistor
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Positive terminal for battery's charging current

N4 ISENSE I
sensing resistor
VSYS supply input for internal block and UVLO
M4 VSYSSNS PWR
detection
N1 CHG_DP I USB D+ for BC1.x standard
M1 CHG_DM I USB D- for BC1.x standard
D15 CS_P I Fuel gauge ADC input pin

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Ball Symbol I/O Description

E15 CS_N I Fuel gauge ADC input pin
J5 FCHR_ENB I Force charging disable pin

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P13 TREF O TREF output voltage
Fractional charger input voltage for charger
R1 VCDT I
detection
R2 VDRV O Charger current drive output

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Battery NTC pin for battery and its temperature
P2 BATON I
sensing
P3 CHRLDO O CHRLDO output voltage
RTC LDO output. Supply of RTC macro where

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R8 AVDD28_RTC O
backup battery can be added.
R7 AVSS28_RTC GND RTC ground
32K crystal connection port while using crystal
T6 XIN IO
to generate 32kHz clock

T1
R3
XOUT

XOSC_EN
ENBB
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IO

O
O
32K crystal connection port while using crystal
to generate 32kHz clock
XOSC_EN control of RF chip
ENBB control of RF chip
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M9 RTC32K_2V8 O VRTC domain 32kHz clock output
P5 RTC32K_1V8_0 O VIO18 domain 32kHz clock output
R4 RTC32K_1V8_1 O VIO18 domain 32kHz clock output
R16 ISINK0 IO ISINK channel 0
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P15 ISINK1 IO ISINK channel 1

N14 AVSS45_ISINK GND ISINK ground
T2 DVDD18_IO PWR Digital IO power
T3 DVDD18_DIG O VDIG18 output voltage
T5 DVSS18_IO GND Digital IO ground
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F15 AU_FLYN O Flying capacitor bottom

G15 AU_FLYP O Flying capacitor top
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H14 AU_REFN GND Audio reference ground

F13 AVSS18N_AUD PWR Audio -1.8V supply
G13 AVDD18_AUD PWR 1.8V power supply of Audio
G14 AVSS18_AUD GND Audio DL ground
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F16 SPK_P O Positive output of internal speaker amp

E16 SPK_N O Negative output of internal speaker amp
N15 AU_MICBIAS1 O Microphone Bias 1
N16 AU_MICBIAS0 O Microphone Bias 0
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D14 AVDD45_SPK PWR Power supply of SPK

E14 AVSS45_SPK GND GND of internal speaker amp
M15 AU_VIN0_N I Microphone channel 0 negative input
M16 AU_VIN0_P I Microphone channel 0 positive input
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L13 AU_VIN1_N I Microphone channel 1 negative input

K13 AU_VIN1_P I Microphone channel 1 positive input
L14 AU_VIN2_N I Microphone channel 2 negative input
K14 AU_VIN2_P I Microphone channel 2 positive input
H15 AU_HPL O Earphone left channel output
H16 AU_HPR O Earphone right channel output

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Ball Symbol I/O Description

J12 CLK26M I 26MHz clock input
J14 AU_HSN O Handset negative output

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K15 AU_HSP O Handset positive output
M10 AUD_DAT_MISO IO Audio control interface
N8 AUD_DAT_MOSI IO Audio control interface
K12 AVSS28_AUD GND Audio UL ground

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K16 AVDD28_AUD PWR 2.8V supply of Audio UL
M8 AUD_CLK I Audio control interface

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2 Electrical Characteristics

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2.1 Absolute Maximum Ratings over Operating Free-Air Temperature
Range

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Stresses beyond those listed in Table 2-1. Absolute maximum ratingsmay cause permanent damage to
the device. These numbers are stress ratings only, and functional operation of the device at these or

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any other conditions beyond those indicated in the operational sections of specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect the device reliability.

Table 2-1. Absolute maximum ratings

Parameter
Free-air temperature range
Conditions ID Min.
-40
Typical Max.
85
Unit
°
C
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Storage temperature range -65 150 °
C
Battery Pin input voltage range 4.5 V
ESD robustness HBM 2,000 V
Charger input withstand 30 V
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2.2 Thermal Characteristic

Parameter Conditions Min. Typical Max. Unit
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Thermal resistance from junction

In free air 36.92[1] °
C/W
to ambient
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Note: The device is mounted on a 4-metal-layer PCB and modeled per JEDEC51-9 condition.
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2.3 Pin Voltage Range

The table below lists operation rang voltages for all MT6328 I/O pins.
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Table 2-2. Pin voltage range

Ball Symbol Voltage range Unit

A1,B1 AVDD45_VSYS22 0 ~ 4.5 v

A2,B2 VSYS22 0 ~ 4.5 v
A3,B3 AVSS45_VSYS22 0 v
C3 VSYS22_FB 0 v
B4,C5,C4 AVDD45_VCORE1 0 ~ 4.5 v
A5,A6,B5 VCORE1 0 ~ 4.5 v

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Ball Symbol Voltage range Unit

B6,C6,D6 AVSS45_VCORE1 0 v
C1 AVSS45_VCORE1_FB 0 v

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C2 VCORE1_FB 0 ~ 4.5 v
A11,B10,B11,C10,D10 AVDD45_VPROC 0 ~ 4.5 v
A7,B7,B8,C7,D7 VPROC 0 ~ 4.5 v
A9,B9,C8,C9,D9 AVSS45_VPROC 0 v

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B15 AVSS45_VPROC_FB 0 v

C16 VPROC_FB 0 ~ 4.5 v

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B13,C13,D13 AVDD45_VLTE 0 ~ 4.5 v

A12,B12,C12 VLTE 0 ~ 4.5 v

C11,D11,D12 AVSS45_VLTE 0 v

E13 AVSS45_VLTE_FB 0 v

C14
A16
VLTE_FB
AVDD45_VPA
ID 0 ~ 4.5
0 ~ 4.5
v
v
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A15 VPA 0 ~ 4.5 v

A14 AVSS45_VPA 0 v

B14 VPA_FB 0 ~ 4.5 v

C15 AVDD45_SMPS 0 ~ 4.5 v

B16 AVSS45_SMPS 0 v
D5,E5,E6,E7,E8,E9, v
E10,E11,E12,F11,F12,
G6,G7,G8,G9,G10,G11,G12,H6,H7,
AVSS45_LDO 0
H8,H9,H10,H11,H12,J6,J7,J8,J9,J
10,J11,K7,K8,K9,K10,K11,L7,L8,L9
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,L10,L11,L12
T13 AVDD45_LDO1 0 ~ 4.5 v
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T8 AVDD45_LDO2 0 ~ 4.5 v

K1 AVDD45_LDO3 0 ~ 4.5 v

T11 AVDD45_LDO4 0 ~ 4.5 v

M2 AVDD45_LDO5 0 ~ 4.5 v

H3 AVDD22_LDO1 0 ~ 2.42 v

J2 AVDD22_LDO1 0 ~ 2.42 v
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E1 AVDD22_LDO2 0 ~ 2.42 v

F1 AVDD22_LDO3 0 ~ 2.42 v

G1 AVDD22_LDO4 0 ~ 2.42 v
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P9 VTCXO_0 0 ~ 4.5 v
T16 VTCXO_1 0 ~ 4.5 v
F10 VRF18_0 0 ~ 4.5 v

F9 VRF18_1 0 ~ 4.5 v

J1 VM 0 ~ 4.5 v

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Ball Symbol Voltage range Unit

E4 VSRAM 0 ~ 1.98 v

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H2 VCAMD 0 ~ 1.98 v
T14 VCAMA 0 ~ 4.5 v
E3 VCAMIO 0 ~ 4.5 v
H5 VCAMAF 0 ~ 4.5 v

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F2 VIO18 0 ~ 4.5 v
K2 VIO28 0 ~ 4.5 v

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K4 VMC 0 ~ 4.5 v
R9 VMCH 0 ~ 4.5 v
R10 VEMC_3V3 0 ~ 4.5 v
T15 VEFUSE 0 ~ 4.5 v
P11
R11
VUSB33
VSIM1
ID 0 ~ 4.5
0 ~ 4.5
v
v
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N11 VSIM2 0 ~ 4.5 v
F3 VCN18 0 ~ 4.5 v
R13 VCN28 0 ~ 4.5 v
R12 VCN33 0 ~ 4.5 v
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R14 VAUD28 0 ~ 4.5 v

R15 VAUX18 0 ~ 4.5 v
H4 VGP1 0 ~ 4.5 v
J4 VIBR 0 ~ 3.3 v
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E2 PWRKEY 0 ~ 4.5 v
D2 EXT_PMIC_EN 0 ~ 4.5 v
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D3 RESETB 0 ~ 1.98 v
M7 WDTRSTB_IN 0 ~ 1.98 v
D4 PMU_TESTMODE 0 ~ 4.5 v
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L4 VREF 0 ~ 1.32 v
L3 AVSS45_VREF 0 v
N5 SPI_MISO 0 ~ 1.98 v
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L6 SPI_MOSI 0 ~ 1.98 v
K6 SPI_CLK 0 ~ 1.98 v
M6 SPI_CSN 0 ~ 1.98 v
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N2 UVLO_VTH 0 ~ 3.3 v
N6 HOMEKEY 0 ~ 1.98 v
P4 FSOURCE 0 ~ 1.98 v
P8 SRCLKEN_IN0 0 ~ 1.98 v
R5 SRCLKEN_IN1 0 ~ 1.98 v

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Ball Symbol Voltage range Unit

M12 AVDD18_AUXADC 0 ~ 1.98 v

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M14 ACCDET 0 ~ 3.08 v
P14 AUXADC_VIN 0 ~ 1.98 v

N13 AVSS18_AUXADC 0 v
N3 BATSNS 0 ~ 4.5 v

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N4 ISENSE 0 ~ 4.5 v
M4 VSYSSNS 0 ~ 4.5 v

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N1 CHG_DP 0 ~ 4.5 v
M1 CHG_DM 0 ~ 4.5 v
D15 CS_P 0 ~ 0.1 v
E15 CS_N 0 ~ 0.1 v
J5
P13
FCHR_ENB
TREF
ID 0 ~ 4.5
0 ~ 1.98
v
v
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R1 VCDT 0 ~ 1.8 v
R2 VDRV 0 ~ 4.5 v
P2 BATON 0 ~ 4.5 v
P3 CHRLDO 0 ~ 3.08 v
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R8 AVDD28_RTC 0~3.08 v
R7 AVSS28_RTC 0 v
T6 XIN 0 ~ 3.08 v
R6 XOUT 0 ~ 3.08 v
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T1 XOSC_EN 0 ~ 3.08 v
R3 ENBB 0 ~ 1.98 v
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M9 RTC32K_2V8 0 ~ 3.08 v
P5 RTC32K_1V8_0 0 ~ 1.98 v
R4 RTC32K_1V8_1 0 ~ 1.98 v
IA

R16 ISINK0 0 ~ 4.5 v

P15 ISINK1 0 ~ 4.5 v
N14 AVSS45_ISINK 0 v
ED

T2 DVDD18_IO 0 ~ 1.98 v
T3 DVDD18_DIG 0 ~ 1.98 v
T5 DVSS18_IO 0 v
M

F15 AU_FLYN -1.98 ~ 0 v

G15 AU_FLYP 0 ~ 1.8 v
H14 AU_REFN 0 v
F13 AVSS18N_AUD -1.98 ~ 0 v
G13 AVDD18_AUD 0 ~ 1.98 v

MediaTek Confidential © 2015 MediaTek Inc. Page 16 of 304

Ball Symbol Voltage range Unit

G14 AVSS18_AUD 0 v

AL
F16 SPK_P 0 ~ 4.5 v
E16 SPK_N 0 ~ 4.5 v
N15 AU_MICBIAS1 0~3.08 v

N16 AU_MICBIAS0 0~3.08 v

TI
D14 AVDD45_SPK 0 ~ 4.5 v

E14 AVSS45_SPK 0 v

EN
M15 AU_VIN0_N 0~3.08 v

M16 AU_VIN0_P 0~3.08 v

L13 AU_VIN1_N 0~3.08 v

K13 AU_VIN1_P 0~3.08 v

L14
K14
AU_VIN2_N
AU_VIN2_P
ID 0~3.08
0~3.08
v
v
v
NF
H15 AU_HPL -1.98 ~ 1.98
H16 AU_HPR -1.98 ~ 1.98 v

J12 CLK26M 0 ~ 1.98 v

J14 AU_HSN -1.98 ~ 1.98 v

K15 AU_HSP -1.98 ~ 1.98 v

M10 AUD_DAT_MISO 0 ~ 1.98 v

N8 AUD_DAT_MOSI 0 ~ 1.98 v

K12 AVSS28_AUD 0 v
K

K16 AVDD28_AUD 0 ~ 3.08 v

M8 AUD_CLK 0 ~ 1.98 v
TE

2.4 Recommended Operating Range

Table 2-3. Operation condition

Parameter Conditions Min. Typical Max. Unit

Operating temperature range -25 85 °

2.5 Electrical Characteristics

VBAT = 2.5 ~ 4.5V, minimum loads applied on all outputs, unless otherwise noted.
Typical values are at TA = 25°
C.

MediaTek Confidential © 2015 MediaTek Inc. Page 17 of 304

Table 2-4. General electrical specifications

Parameter Conditions Min. Typical Max. Unit

AL
Operation Ground Current
Standby Low-power mode 250 300 μA
Power down leakage current with 32K VBAT=4.5V,
55 100 uA
XTAL Temp=-40°C~85°C

TI
Power down leakage current without VBAT=4.5V,
70 115 uA
32K XTAL Temp=-40°C ~85°C
Under Voltage (UV)

EN
Programmable,
Under voltage falling threshold 1 2.5 2.6 2.9 V
50mV steps.
Threshold voltage accuracy -50 +50 mV
UV_SEL[4:0] =
Under voltage rising threshold 2.95 3.0 3.05 V
xxxxx (w/o charger)
Under voltage rising threshold w/o
power path
Under voltage rising threshold with
UV_SEL[4:0] =
xxxxx (w/i charger)
UV_SEL[4:0] =
ID 2.75

2.95
2.8

3.0
2.85

3.05
V

V
NF
power path xxxxx (w/i charger)
Reset Generator
Output high VIO-0.4 V
Output low 0.2 V
CO

Output current (Ioh) Vo > VIO-0.4V 1 mA

Delay Time from VMC turn on to
32 40 48 ms
RESETB release
Interrupt
Output high VIO-0.4 V
K

Output low 0.2 V

PWRKEY
TE

High voltage 0.7*VBAT V

Low voltage 0.3*VBAT V
De-bounce time 26 32 38 ms
Control Input Voltage
IA

Control input high

0.7*VIO V
(HOMEKEY, SPI, SRCLKEN related)
Control input low
0.3*VIO V
ED

(HOMEKEY, SPI, SRCLKEN related)

Thermal Shut-down
PMIC shut-down threshold 150 degree
Shut-down release threshold 110 degree
M

2.6 Regulator Output

Table 2-5. Buck specifications

Parameter Conditions Min. Typical Max. Unit

MediaTek Confidential © 2015 MediaTek Inc. Page 18 of 304

Parameter Conditions Min. Typical Max. Unit

Buck – VPROC
Turn-on overshoot No load 10 %

AL
Short current Imax*1.2 Imax*2.5
Vbat=3.8V
Temperature coefficient -100 +100 ppm/C
I_Load=0.5*Imax
Vbat=3.8V, Vout=0.85V,

TI
L_DCR=35mohm 83 %
I_Load=100mA
Vbat=3.8V, Vout=1.05V,
L_DCR=35mohm 83 %

EN
I_Load=500mA
Efficiency Vbat=3.8V, Vout=1.15V,
L_DCR=35mohm 83 %
I_Load=2.5A
Vbat=3.8V, Vout=1.15V,
L_DCR=35mohm I_Load=4A
Vbat=3.8V, Vout=1.15V,
L_DCR=35mohm I_Load=5A
ID 80

77
%

%
NF
Soft start No load 1 ms
Vbat=3.8V,
Output Ripple Voltage (PWM) I_Load=0.5*Imax 20 mVpp
20MHz measurement BW
Vbat=3.8V
CO

Load transient(PWM) IOUT = 1.5A to 4A -3.5 +3.5 %

(slew rate=2.5A/us)
DC Accuracy
VBAT=2.8V to 4.5V
(Included Line/Load regulation -1 +1 %
I_Load=10mA to Imax
@PWM)
DC Accuracy
K

VBAT=2.8V to 4.5V
(Included Line/Load regulation -2 +3 %
I_Load=0~10mA
@PFM)
TE

Buck – VCORE1
Turn-on overshoot No load 10 %
Short current Imax*1.2 Imax*2.5
Vbat=3.8V
Temperature coefficient -100 +100 ppm/C
I_Load=0.5*Imax
IA

Vbat=3.8V, Vout=1.05V,
L_DCR=40mohm 83 %
I_Load=100mA
ED

Vbat=3.8V, Vout=1.15V,
L_DCR=40mohm 85 %
I_Load=800mA
Efficiency
Vbat=3.8V, Vout=1.25V,
L_DCR=40mohm 70 %
M

I_Load=2.6A
Vbat=3.8V, Vout=1.25V
L_DCR=40mohm 60 %
I_Load=3.2A
Soft start No load 1 ms
Vbat=3.8V,
Output Ripple Voltage (PWM) 20 mVpp
I_Load=0.5*Imax

MediaTek Confidential © 2015 MediaTek Inc. Page 19 of 304

Parameter Conditions Min. Typical Max. Unit

20MHz measurement BW
Vbat=3.8V

AL
Load transient(PWM) IOUT = 1.0A to 2.0A -3.5 +3.5 %
(slew rate=1A/us)
DC Accuracy
VBAT=2.8V to 4.5V
(Included Line/Load regulation -1 +1 %
I_Load=10mA to Imax
@PWM)

TI
DC Accuracy
VBAT=2.8V to 4.5V
(Included Line/Load regulation -2 +3 %
I_Load=0~10mA
@PFM)

EN
Buck – VLTE
Turn-on overshoot No load 10 %
Short current Imax*1.2 Imax*2.5
Vbat=3.8V
Temperature coefficient -100 +100 ppm/C
I_Load=0.5*Imax
Vbat=3.8V, Vout=0.85V,
L_DCR=40mohm
I_Load=100mA
ID 83 %
NF
Vbat=3.8V, Vout=1.05V,
L_DCR=40mohm 85 %
I_Load=800mA
Efficiency
Vbat=3.8V, Vout=1.05V
L_DCR=40mohm 75 %
CO

I_Load=2.2A
Vbat=3.8V, Vout=1.05V
L_DCR=40mohm 70 %
I_Load=2.6A
Soft start No load 1 ms
Vbat=3.8V,
K

Output Ripple Voltage (PWM) I_Load=0.5*Imax 20 mVpp

20MHz measurement BW
TE

Vbat=3.8V
Load transient(PWM) IOUT = 1.0A to 2.5A -3.5 +3.5 %
(slew rate=1.5A/us)
DC Accuracy
VBAT=2.8V to 4.5V
(Included Line/Load regulation -1 +1 %
I_Load=10mA to Imax
IA

@PWM)
DC Accuracy
VBAT=2.8V to 4.5V
(Included Line/Load regulation -2 +3 %
I_Load=0~10mA
@PFM)
ED

Buck – VSYS22
Turn-on overshoot No load 10 %
Short current Imax*1.2 Imax*3
Vbat=3.8V
Temperature coefficient -100 +100 ppm/C
M

I_Load=0.5*Imax
Vbat=3.8V, L_DCR=40mohm
87 %
I_Load=50mA
Vbat=3.8V,
Efficiency
L_DCR=40mohm 88 %
I_Load=500mA
Vbat=3.8V, 87 %

MediaTek Confidential © 2015 MediaTek Inc. Page 20 of 304

Parameter Conditions Min. Typical Max. Unit

L_DCR=40mohm
I_Load=1000mA

AL
Soft start No load 1 ms
Vbat=3.8V,
Output Ripple Voltage (PWM) I_Load=0.5*Imax 20 mVpp
20MHz measurement BW
Vbat=3.8V

TI
Load transient(PWM) IOUT = 1.0A to 2.0A -3.5 +3.5 %
(slew rate=1000mA/us)
DC Accuracy
VBAT=2.8V to 4.5V

EN
(Included Line/Load regulation -3 +3 %
I_Load=10mA to Imax
@PWM)
DC Accuracy
VBAT=2.8V to 4.5V
(Included Line/Load regulation -3 +3 %
I_Load=1~500mA
@PFM)
Buck – VPA
Turn-on overshoot
Short current
No load
ID 10
Imax*5
%
NF
Vbat=3.8V
Temperature Coefficient I_Load=0.5*Imax -100 +100 ppm/C
Vo=1.8V
Vbat=3.8V,
L_DCR=110 mohm
CO

82 %
I_Load=80mA
Vo=1.2V
Vbat=3.8V,
L_DCR=110 mohm
Efficiency 88 %
I_Load=180mA
Vo=2.4V
K

Vbat=3.8V,
L_DCR=110mohm
95 %
I_Load=280mA
TE

Vo=3.4V
Soft start No load 200 us
Vbat=3.8V
Vo=1.8V
Output Ripple Voltage (PWM) 30 mVpp
IA

I_Load=0.5*Imax
20MHz measurement BW
DC Accuracy VBAT=2.8V to 4.5V
(Included Line/Load regulation Vo=1.7V -5 +5 %
ED

@PWM) I_Load=10mA~360mA
No load quiescent current VBAT=3.8V
(PFM) Vo=0.5V 150 uA
I_Load=0A
M

Table 2-6. LDO specifications

Parameter Type Conditions Min. Typ. Max. Unit

LDO output voltage ≦

All test condition VBAT range 2.5 V
2.1V

MediaTek Confidential © 2015 MediaTek Inc. Page 21 of 304

Parameter Type Conditions Min. Typ. Max. Unit

Output
LDO output voltage ＞

AL
Voltage 4.5 V
2.1V +0.35V

Droup out voltage All LDOs 350 mV

VTCXO_0,

TI
-100 +100 mV
VTCXO_1

VRF18_0 ,
-75 +75 mV
VRF18_1

EN
VCAMA -3 +3 %

VSRAM, 1. Iout= 0~Imax

VM, 2. VBAT range
VSIM1, 3. Capacitor range=

Line/
Load regulation
VSIM2,
VAUX18,
VAUD28,
Min~max
ID
4. TA= -25°C ~+65°C
-1 +1 %
NF
VCAMD

ALDO and DLDO -5 +5 %

VRTC 2 V
CO

DVDD18_DIG -10 10 %

1. Iout= 0~0.05*Imax
ALDO and DLDO 2. VBAT range
low 3. Capacitor range= -5 +5 %
power mode Min~max
4. TA= -25°C ~+65°C
K

Temperature
ALDO and DLDO TA= -25°C~+65°C -100 +100 ppm/C
coefficient
TE

1. Iout= 0.1mA~50mA
(slew rate= 50mA/us)
VMCH, 2. VBAT range
-5 +5 %
VEMC33 3. Capacitor range=
IA

Min~max
4. TA= -25°C ~+65°C

1. Iout= 1mA~Imax
ED

(slew rate= 15mA/us)

Load 2. VBAT range
VCAMA -3 +3 %
transient 3. Capacitor range=
response Min~max
4. TA= -25°C ~+65°C
M

1. Iout=
100mA~200mA (slew
rate= 100mA/us)
VRF18_0, 2. VBAT range -5 +5 %
VRF18_1 3. Capacitor range=
Min~max
4. TA= -25°C ~+65°C

MediaTek Confidential © 2015 MediaTek Inc. Page 22 of 304

Parameter Type Conditions Min. Typ. Max. Unit

1. Iout= 1mA~350mA

AL
(slew rate= 70mA/us)
2. VBAT range
VCN33 -6 +6 %
3. Capacitor range=
Min~max
4. TA= -25°C ~+65°C

TI
1. Iout= 1mA~150mA
(slew rate=
150mA/us)

EN
VSRAM 2. VBAT range -4 +4 %
3. Capacitor range=
Min~max
4. TA= -25°C~+65°C

VM
1. Iout=
0.01mA~600mA
(slew rate=
600mA/us)
2. VBAT range
ID -4 +4 %
NF
3. Capacitor range=
Min~max
4. TA= -25°C~+65°C

1. Iout=
CO

0.01mA~150mA
(slew rate= 50mA/us)
VGP1 2. VBAT range -4 +4 %
3. Capacitor range=
Min~max
4. TA= -25°C~+65°C
K

1. Iout= 1mA~Imax
(slew rate= 15mA/us)
TE

2. VBAT range
ALDO and DLDO -5 +5 %
3. Capacitor range=
Min~max
4. TA= -25°C~+65°C
IA

1. Iout= 0mA
2. VBAT range
Turn-on rise time ALDO and DLDO 3. Capacitor range= 300 us
min
ED

4. TA= +25°C

1. Iout= 0mA
2. VBAT range
Turn-on overshoot ALDO and DLDO 3. Capacitor range= +10 %
M

min
4. TA= +25°C

1. Freq= 10Hz to 80kHz

Output noise ALDO 2. Iout= 0.01*Imax/ 90 uVrms
0.5*Imax

MediaTek Confidential © 2015 MediaTek Inc. Page 23 of 304

Parameter Type Conditions Min. Typ. Max. Unit

3. VBAT range

AL
4. Capacitor range=
DLDO min 500 uVrms
5. TA= +25°C

1. Freq= 217Hz to 3kHz

2. Iout= 0.01*Imax/

TI
0.5*Imax
ALDO 3. VBAT range 65 dB
4. Capacitor range=
min

EN
5. TA= +25°C
PSRR
1. Freq= 217Hz
2. Iout= 0.01*Imax/
0.5*Imax
DLDO 3. VBAT range
ID
4. Capacitor range=
min
5. TA= +25°C
40 dB
NF
Imax* Imax*
Short current ALDO and DLDO VBAT range
1.2 5

VCAMA 300 uA
CO

VMCH/VEMC33/
100 uA
VRF18_0/VRF18_1
Normal mode 1. Iout= 0mA
quiescent current VSRAM/VCN33/VM 2. VBAT range 200 uA
3. Capacitor range=
DIG18 5 uA
min
K

Other LDO 4. TA= +25°C 55 uA

Low power mode VMCH 15 uA

quiescent current ALDO and DLDO 10 uA

IA
ED
M

MediaTek Confidential © 2015 MediaTek Inc. Page 24 of 304

2.7 Driver
Table 2-7. Driver specifications

AL
Parameter Conditions Min. Typ. Max. Unit
ISINK
ISINK_SEL = 000 3.6 4 4.4 mA

TI
ISINK_SEL = 001 7.2 8 8.8 mA
ISINK_SEL = 010 10.8 12 13.2 mA
ISINK LED sink current
ISINK_SEL = 011 14.4 16 17.6 mA
mA

EN
ISINK_SEL = 100 18 20 22
ISINK_SEL = 101 21.6 24 26.4 mA
4 ~ 24mA
ISINK dropout voltage 150 250 mV
VISINK drop
ISINK rise/fall time VISINK > 0.3V 3.33 uS
VIBR
VIBR_SEL = 000
VIBR_SEL = 001
ID 1.1
1.2
1.2
1.3
1.3
1.4
V
V
NF
VIBR_SEL = 010 1.4 1.5 1.6 V
VIBR_SEL = 011 1.7 1.8 1.9 V
Output voltage
VIBR_SEL = 100 2.35 2.5 2.65 V
VIBR_SEL = 101 2.65 2.8 2.95 V
CO

VIBR_SEL = 110 2.85 3.0 3.15 V

VIBR_SEL = 111 3.1 3.3 3.5 V
Output current 100 mA
K

2.8 Class AB/D Audio Amplifier

Table 2-8. Class AB/D audio amplifier specifications
TE

Parameter Conditions Min. Typ. Max. Unit

Class AB Audio Amplifier
8Ω load, VBAT = 4.2V
890 mW
IA

THD + N = 1%
8Ω load, VBAT = 3.8V
700 mW
THD + N = 1%
8Ω load, VBAT = 3.4V
ED

500 mW
THD + N = 1%
RMS power
8Ω load, VBAT = 4.2V
1100 mW
THD + N = 10%
8Ω load, VBAT = 3.8V
850 mW
M

THD + N = 10%
8Ω load, VBAT = 3.4V
600 mW
THD + N = 10%
1kHz, Po = 0.5Wrms,
0.01 0.03 %
VBAT = 4.2V
THD+N
1kHz, Po = 0.4Wrms,
0.01 0.03 %
VBAT = 3.8V

MediaTek Confidential © 2015 MediaTek Inc. Page 25 of 304

Parameter Conditions Min. Typ. Max. Unit

1kHz, Po = 0.3Wrms,
0.01 0.03 %
VBAT = 3.4V

AL
217Hz, Vin = 200mVpk-pk
Input AC to ground, 80 dB
VBAT = 4.2V
217Hz, Vin = 200mVpk-pk

TI
Input AC to ground, 80 dB
VBAT = 3.8V
217Hz, Vin = 200mVpk-pk
Input AC to ground, 80 dB

EN
VBAT = 3.4V
PSRR
1kHz, Vin = 200mVpk-pk
Input AC to ground, 80 dB
VBAT = 3.8V
4kHz, Vin = 200mVpk-pk
Input AC to ground,
VBAT = 3.8V
20kHz, Vin = 200mVpk-pk
ID 80 dB
NF
Input AC to ground, 80 dB
VBAT = 3.8V
VBAT = 4.2V, 12dB gain
30 μV
8Ω, A-weighted
VBAT = 3.4V, 12dB gain
CO

30 uV
8Ω, A-weighted
VBAT = 4.2V, 0dB gain
10 μV
8Ω, A-weighted
Noise level
VBAT = 3.4V, 0dB gain
10 uV
8Ω, A-weighted
K

VBAT = 4.2V, -6dB gain

6 μV
8Ω, A-weighted
VBAT = 3.4V, -6dB gain
TE

6 uV
8Ω, A-weighted
Gain adjustment 6 15 dB
Gain adjustment steps 1 dB
No load, VBAT=4.2V 5 mA
IA

Quiescent current No load, VBAT=3.8V 5 mA

No load, VBAT=3.4V 5 mA
VBAT = 4.2V, 12dB gain 5 mV
ED

VBAT = 3.8V, 12dB gain 5 mV

VBAT = 3.4V, 12dB gain 5 mV
VBAT = 4.2V, 0dB gain 1 mV
DC offset VBAT = 3.8V, 0dB gain 1 mV
M

VBAT = 3.4V, 0dB gain 1 mV

VBAT = 4.2V, -6dB gain 1 5 mV
VBAT = 3.8V, -6dB gain 1 5 mV
VBAT = 3.4V, -6dB gain 1 5 mV
Class D Audio Amplifier
8Ω load, VBAT = 4.2V
RMS power 900 mW
THD + N = 1%

MediaTek Confidential © 2015 MediaTek Inc. Page 26 of 304

Parameter Conditions Min. Typ. Max. Unit

8Ω load, VBAT = 3.8V
700 mW
THD + N = 1%

AL
8Ω load, VBAT = 3.4V
500 mW
THD + N = 1%
8Ω load, VBAT = 4.2V
1100 mW
THD + N = 10%

TI
8Ω load, VBAT = 3.8V
850 mW
THD + N = 10%
8Ω load, VBAT = 3.4V
600 mW
THD + N = 10%

EN
1kHz, Po = 0.5Wrms,
0.02 0.16 %
VBAT = 4.2V
1kHz, Po = 0.4Wrms,
THD+N 0.02 0.16 %
VBAT = 3.8V
1kHz, Po = 0.3Wrms,
VBAT = 3.4V
217Hz, Vin = 200mVpk-pk
Input AC to ground,
ID 0.02

80
0.16 %

dB
NF
VBAT = 4.2V
217Hz, Vin = 200mVpk-pk
Input AC to ground, 80 dB
VBAT = 3.8V
CO

217Hz, Vin = 200mVpk-pk

Input AC to ground, 80 dB
VBAT = 3.4V
PSRR
1kHz, Vin = 200mVpk-pk
Input AC to ground, 80 dB
VBAT = 3.8V
K

4kHz, Vin = 200mVpk-pk

Input AC to ground, 80 dB
VBAT = 3.8V
TE

20kHz, Vin = 200mVpk-pk

Input AC to ground, 80 dB
VBAT = 3.8V
VBAT = 4.2V, 12dB gain
60 μV
IA

8Ω, A-weighted
VBAT = 3.4V, 12dB gain
60 uV
8Ω, A-weighted
Noise level
VBAT = 4.2V, 0dB gain
ED

25 μV
8Ω, A-weighted
VBAT = 3.4V, 0dB gain
25 uV
8Ω, A-weighted
VBAT = 4.2V
85 %
M

0.8W, 8Ω with 68uH, 1kHz

VBAT = 4.2V
85 %
0.5W, 8Ω with 68uH, 1kHz
Efficiency
VBAT = 3.8V
85 %
0.5W, 8Ω with 68uH, 1kHz
VBAT = 3.4V
85 %
0.5W, 8Ω with 68uH, 1kHz

MediaTek Confidential © 2015 MediaTek Inc. Page 27 of 304

Parameter Conditions Min. Typ. Max. Unit

Gain adjustment 6 15 dB
Gain adjustment steps 1 dB

AL
No load, VBAT=4.2V 5 mA
Quiescent current No load, VBAT=3.8V 5 mA
No load, VBAT=3.4V 5 mA
VBAT = 4.2V, 12dB gain 5 mV

TI
VBAT = 3.8V, 12dB gain 5 mV
VBAT = 3.4V, 12dB gain 5 mV
DC offset
VBAT = 4.2V, 0dB gain 1 mV

EN
VBAT = 3.8V, 0dB gain 1 mV
VBAT = 3.4V, 0dB gain 1 mV
Audio Precision A-A FFT SPECTRUM ANALYSIS 11/03/14 17:21:13 Audio Precision A-A FFT SPECTRUM ANALYSIS 11/03/14 17:24:20

20 20

ID
10 10
5 5

2 2
1
1
0.5
% % 0.5
0.2
NF
0.2
0.1
0.1
0.05
0.05
0.02
0.02
0.01
0.006 0.01
100m 200m 300m 400m 500m 600m 700m 800m 1 2 100m 200m 300m 400m 500m 600m 700m 800m 1 2
W W

Sweep Trace Color Line Style Thick Data Axis Comment Sweep Trace Color Line Style Thick Data Axis Comment
CO

1 1 Blue Solid 2 Anlr.THD+N Ratio Left Vin=4.2V 1 1 Blue Solid 2 Anlr.THD+N Ratio Left Vin=4.2V
2 1 Blue Solid 2 Anlr.THD+N Ratio Left Vin=4V 2 1 Blue Solid 2 Anlr.THD+N Ratio Left Vin=4V
3 1 Cyan Solid 2 Anlr.THD+N Ratio Left Vin=3.8V 3 1 Cyan Solid 2 Anlr.THD+N Ratio Left Vin=3.8V
4 1 Green Solid 2 Anlr.THD+N Ratio Left Vin=3.6V 4 1 Green Solid 2 Anlr.THD+N Ratio Left Vin=3.6V
5 1 Yellow Solid 2 Anlr.THD+N Ratio Left Vin=3.4V 5 1 Yellow Solid 2 Anlr.THD+N Ratio Left Vin=3.4V

Requires DSP. Analog Analyzer input is A-D converted and analyzed with the FFT Digital analyzer. Signal source may be Generator or external. Click Requires DSP. Analog Analyzer input is A-D converted and analyzed with the FFT Digital analyzer. Signal source may be Generator or external. Click
"Sweep Spectrum/Waveform" swap button to switch between frequency and time displays . "Sweep Spectrum/Waveform" swap button to switch between frequency and time displays .
I2S_SPK_THDvsOutputPower.at27 I2S_SPK_THDvsOutputPower.at27

Figure 2-1. THD+N v.s. output power (Class AB/D, VBAT=4.2/3.8/3.4V, gain=12dB)
K

Audio Precision A-A FFT SPECTRUM ANALYSIS 11/03/14 20:41:47 Audio Precision A-A FFT SPECTRUM ANALYSIS 11/03/14 20:43:11

+10 +10 +10 +10

+1.333 +1.333 +1.333 +1.333
TE

-7.333 -7.333 -7.333 -7.333

-16 -16 -16 -16
-24.667 -24.667 -24.667 -24.667
-33.333 -33.333 -33.333 -33.333
-42 -42 -42 -42
d -50.667 -50.667 d d -50.667 -50.667 d
B B B B
V -59.333 -59.333 V V -59.333 -59.333 V
-68 -68 -68 -68
-76.667 -76.667 -76.667 -76.667
IA

-85.333 -85.333 -85.333 -85.333

-94 -94 -94 -94
-102.667 -102.667 -102.667 -102.667
-111.333 -111.333 -111.333 -111.333
-120 -120 -120 -120
20 50 100 200 500 1k 2k 5k 10k 20k 20 50 100 200 500 1k 2k 5k 10k 20k
Hz Hz
ED

Sweep Trace Color Line Style Thick Data Axis Comment Sweep Trace Color Line Style Thick Data Axis Comment

1 1 Cyan Solid 2 Fft.Ch.1 Ampl Left 1 1 Cyan Solid 2 Fft.Ch.1 Ampl Left
1 2 Blue Solid 1 Fft.Ch.2 Ampl Right 1 2 Blue Solid 1 Fft.Ch.2 Ampl Right

Requires DSP. Analog Analyzer input is A-D converted and analyzed with the FFT Digital analyzer. Signal source may be Generator or external. Requires DSP. Analog Analyzer input is A-D converted and analyzed with the FFT Digital analyzer. Signal source may be Generator or external.
Click "Sweep Spectrum/Waveform" swap button to switch between frequency and time displays . Click "Sweep Spectrum/Waveform" swap button to switch between frequency and time displays .
I2S_1KHzFFT.at27 I2S_1KHzFFT.at27

Figure 2-2. PSRR with 217Hz TDMA noise (Class AB/D, VBAT=3.8V, gain=12dB)
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MediaTek Confidential © 2015 MediaTek Inc. Page 28 of 304

2.9 Audio CODEC

Table 2-9. Audio downlink specifications

AL
Symbol Parameter Min. Typ. Max. Unit
DAC to Audio Buffer Output (single-ended output, AU_HPL/R; RLOAD = 32)
Temp = 25deg, 1kHz sinusoid signal, FS,DL = 48kHz, Gain = +0dB, 24bit audio data (default)

TI
POUT Maximum output power @<0.1% THD 25 mW
SNR (1) Signal to noise ratio (A-weighted) 100 dB(A)
Total Harmonic distortion (THD)

EN
@POUT = 2mW -86
THD dB
@POUT = 10mW -88
@POUT = 22.5mW -86
THD plus noise (THD+N)

THD+N
@POUT = 2mW
@POUT = 10mW
@POUT = 22.5mW ID -84
-86
-84
dB

μVrms
NF
NFOUT Output noise floor (A-weighted) 4
(A)
RLOAD Output resistor load (headphone) 16 32 Ω
CLOAD Output capacitor load 250 pF
APGRDL Analog programmable gain range -10 8 dB
CO

APGSDL Analog programmable gain step 1 dB

XTLR L/R channel crosstalk @1kHz -90 dB
Power supply rejection ratio
PSRR 90 dB
(From AVDD18_AUD to AU_HPL/R)
DAC to Audio Buffer Output (single-ended output, AU_HPL/R; RLOAD = 16)
K

Temp = 25deg, 1kHz sinusoid signal, FS,DL = 48kHz, Gain = +0dB, 24bit audio data (default)
TE

POUT Maximum output power @<0.1% THD 35 mW

SNR (1) Signal to noise ratio (A-weighted) 100 dB(A)

Total Harmonic distortion (THD)
@POUT = 2mW -84
IA

THD dB
@POUT = 10mW -88
@POUT = 22.5mW -88
THD plus noise (THD+N)
ED

@POUT = 2mW -81

THD+N dB
@POUT = 10mW -86
@POUT = 22.5mW -86
μVrms
NFOUT Output noise floor (A-weighted) 4
(A)
M

Note 1: Ratio of output level with 1kHz full-scale sine wave input, to the output level with the inputs short circuited, measured
A-weighted over a 20Hz to 20kHz bandwidth using an audio analyzer

Note 2: The output voltage range of both audio and voice buffer outputs are within [AVSS18N_AUD, AVDD18_AUD]

MediaTek Confidential © 2015 MediaTek Inc. Page 29 of 304

Symbol Parameter Min. Typ. Max. Unit

DAC to Voice Buffer Output (differential outputs, AU_HSP/N; RLOAD = 32)
Temp = 25deg, 1kHz sinusoid signal, FS,DL = 48kHz, Gain = +0dB, 24bit audio data (default)

AL
POUT Maximum output power @<1% THD 100 mW
SNR (1) Signal to noise ratio (A-weighted) -104 dB(A)
Total Harmonic distortion (THD)

TI
THD @POUT = 10mW -87 dB
@POUT = 50mW -88
THD plus noise (THD+N)
THD+N @POUT = 10mW -85 dB

EN
@POUT = 50mW -86
μVrms
NFOUT Output noise floor (A-weighted) 5
(A)
RLOAD Output resistor load (headphone) 16 32 Ω
CLOAD
APGRDL
APGSDL
Output capacitor load
Analog programmable gain range
Analog programmable gain step
ID -10
1
250
8
pF
dB
dB
NF
Power supply rejection ratio
PSRR 90 dB
(From AVDD18_AUD to AU_HSP/N)
DAC to Voice Buffer Output (differential outputs, AU_HSP/N; RLOAD =16)
Temp = 25deg, 1kHz sinusoid signal, FS,DL = 48kHz, Gain = +0dB, 24bit audio data (default)
CO

POUT Maximum output power @<1% THD 130 mW

SNR (1) Signal to noise ratio (A-weighted) -104 dB(A)

Total harmonic distortion (THD)
THD @POUT = 20mW -87 dB
K

@POUT = 100mW -88

THD Plus noise (THD+N)
TE

THD+N @POUT = 20mW -85 dB

@POUT = 100mW -86
μVrms
NFOUT Output noise floor (A-weighted) 5
(A)
IA

Note 1: Ratio of output level with 1kHz full-scale sine wave input, to the output level with the inputs short circuited, measured
A-weighted over a 20Hz to 20kHz bandwidth using an audio analyzer

Note 2: The output voltage range of both audio and voice buffer outputs are within [AVSS18N_AUD, AVDD18_AUD]
ED
M

MediaTek Confidential © 2015 MediaTek Inc. Page 30 of 304

AL
TI
EN
(a) POUT=10mW (b) POUT=22.5mW
Figure 2-3. Audio path THD+N v.s. frequency

ID
NF
CO
K

(a) XtalkRtoL (b) XtalkLtoR

Figure 2-4. Audio path Xtalk v.s. frequency @POUT=10mW

Table 2-10. Audio uplink specifications

Symbol Parameter Min. Typ. Max. Unit

Analogue Input Paths to ADC (differential) DCC mode
ED

Temp = 25deg, 1kHz sinusoid signal, FS,UL = 48kHz, PGAUL gain = 0dB, 16bit audio data (A-weighted)
SNR*1 Signal to noise ratio 98 dB
NIN Input-referred noise 16 μVrms
Total Harmonic Distortion (THD) @0dBV input
THD -89 dB
M

(-3dBFS)
THD plus noise (THD+N) @0dBV input (-3dBFS) -86 dB
THD+N
THD plus noise (THD+N) @-60dBV input (-63dBFS) -36 dB
Analogue Input Paths to ADC (differential) DCC mode
Temp = 25deg, 1kHz sinusoid signal, FS,UL = 48kHz, PGAUL gain = 18dB, 16bit audio data (A-weighted)
SNR*1 Signal to noise ratio 89 dB

MediaTek Confidential © 2015 MediaTek Inc. Page 31 of 304

Symbol Parameter Min. Typ. Max. Unit

NIN Input-referred noise 6.3 μVrms

AL
Total Harmonic Distortion (THD) @-18dBV input
THD -89 dB
(-3dBFS)
THD plus noise (THD+N) @-18dBV input (-3dBFS) -84 dB
THD+N
THD plus noise (THD+N) @-78dBV input (-63dBFS) -26 dB

TI
Symbol Parameter Min. Typ. Max. Unit
Analogue Input Paths to ADC (differential) ACC mode

EN
Temp = 25deg, 1kHz sinusoid signal, FS,UL = 48kHz, PGAUL gain = 0dB, 16bit audio data (A-weighted)
SNR*1 Signal to noise ratio 99 dB
NIN Input-referred noise 14 μVrms
Total Harmonic Distortion (THD) @0dBV input
THD -87 dB

THD+N
(-3dBFS)
THD plus noise (THD+N) @0dBV input (-3dBFS)
THD plus noise (THD+N) @-60dBV input (-63dBFS)
ID -85
-37
dB
dB
NF
Analogue Input Paths to ADC (differential) ACC mode
Temp = 25deg, 1kHz sinusoid signal, FS,UL = 48kHz, PGAUL gain = 18dB, 16bit audio data (A-weighted)
SNR*1 Signal to noise ratio 92 dB
NIN Input-referred noise 4.2 μVrms
CO

Total Harmonic Distortion (THD) @-18dBV input

THD -87 dB
(-3dBFS)
THD plus noise (THD+N) @-18dBV input (-3dBFS) -84 dB
THD+N
THD plus noise (THD+N) @-78dBV input (-63dBFS) -29 dB
K

Note 1: Ratio of output level with 1kHz full-scale sine wave input, to the output level with the inputs short circuited, measured
w/i A-weighted over a 20Hz to 20kHz bandwidth using an audio analyzer

Note 2: The input voltage range of AU_VIN0, AU_VIN1, and AU_VIN2 are within [AVDD28_AUD, AVSS28_AUD], and
TE

suggesting maximum input swing Vpp ≤ 1Vrms (0 dBV) @ PGAUL gain = 0dB

General
Symbol Parameter Min. Typ. Max. Unit
IA

APGRUL Uplink Analog Programmable Gain Range 0 24 dB

APGSUL Uplink Analog Programmable Gain Step 6 dB
Common-mode Rejection Ratio @-18dBV, 1kHz sinusoid
CMRR 40 76 dB
ED

signal to both pins of an input configured differentially

ULL-to-ULR Channel Separation @ one input terminated
XTInternal with -18dBV, 1KHz sinusoid signal. Measure digital output 60 100 dB
of terminated channel
DL-to-UL Channel Separation @ 0dBV, 1kHz Rx path with
M

XTDL2UL 60 101 dB
RLOAD = 32
217Hz @ 200 mVpp square wave imposed on power.
-70 dB
Measure digital output
PSRR 1kHz @ 200 mVpp square wave imposed on power.
-70 dB
Measure digital output
10kHz @ 200 mVpp square wave imposed on power. -70 dB

MediaTek Confidential © 2015 MediaTek Inc. Page 32 of 304

General
Symbol Parameter Min. Typ. Max. Unit
Measure digital output

AL
Audio Uplink Sampling Rate
FS,UL 8 48 KHz
8, 16, 32, and 48KHz

Audio Precision 10/29/14 21:12:34

TI
+0 +0
T T
-5 -5

-10 -10

EN
-15 -15

-20 -20
d d
B -25 -25 B
F F
S S

ID
-30 -30

-35 -35

-40 -40

-45 -45
NF
-50 -50
2k 4k 6k 8k 10k 12k 14k 16k 18k 20k
Hz

Sweep Trace Color Line Style Thick Data Axis Comment

1 1 Cyan Solid 2 DSP Anlr.Level A Left

1 2 Blue Solid 1 DSP Anlr.Level B Right

07_I2S_out_sweep_BW.at27

Figure 2-5. Frequency response (16kHz)

Audio Precision A-A FFT SPECTRUM ANALYSIS 10/29/14 20:26:32
K

+0 +0

-5 -5

-10 -10
TE

-15 -15

-20 -20
d d
B -25 -25 B
V V
-30 -30
IA

-35 -35

-40 -40

-45 -45
ED

-50 -50
20 50 100 200 500 1k 2k 5k 10k 20k 30k
Hz

Sweep Trace Color Line Style Thick Data Axis Comment

1 1 Cyan Solid 2 DSP Anlr.Level A Left

1 2 Blue Solid 1 DSP Anlr.Level B Right
M

Requires DSP. Analog Analyzer input is A-D converted and analyzed with the FFT Digital analyzer. Signal source may be Generator or external.
Click "Sweep Spectrum/Waveform" swap button to switch between frequency and time displays .
07_I2S_out_sweep_BW.at27

Figure 2-6. Frequency response (48kHz)

MediaTek Confidential © 2015 MediaTek Inc. Page 33 of 304

Digital MIC
Symbol Parameter Min. Typ. Max. Unit

AL
DCLK DMIC clock frequency 3.25/1.62 MHz
DTY DMIC clock duty cycle 40 60 %
DCRT DMIC clock rise time (MaxCL = 65p) 10 ns
DCFT DMIC clock fall time (MaxCL = 65p) 10 ns

TI
Table 2-11. MICBIAS specifications

EN
Microphone Bias (MICBIAS)
Temp = 25deg, 1μF capacitor on MICBIAS
Symbol Parameter Min. Typ. Max. Unit
VOUT Microphone Bias Voltage 1.7 2.5 V

VOUT Step

IOUT
Bias Voltage Output Step Size
1.7~2.1
2.3~2.5
Maximum Output Current (Two MICBIAS loads total)
ID 0.1

3
V

mA
NF
Output Integrated Noise (20~20KHz A-weighted) with
NOUT 3.9 μVrms
1μF cap.
217Hz @ 200 mVpp square wave imposed on VBAT.
-100 dB
Measure MICBIAS output
CO

1kHz @ 200 mVpp square wave imposed on VBAT.

PSRR -100 dB
Measure MICBIAS output
10kHz @ 200 mVpp square wave imposed on VBAT.
-95 dB
Measure MICBIAS output
CLOAD,MIC Output Capacitor Load on MICBIAS 0.1 22 μF
K

Table 2-12. ACCDET specifications

Accessory Detection (ACCDET)

Symbol Parameter Min. Typ. Max. Unit
*1: Load impedance detection range (ACCDET) by 1& 1.5kΩ (1%) MICBIAS resistors
*2: Note the characteristics assume no other component is connected to ACCDET
-
IA

*3: Note the key detection voltage will be normalized automatic. For different MICBIAS setting ,
the same key (resistance is the same)is pressed , read voltage (key pressed) value will be similar
- 4 pole Microphone Detection 2K 14K Ohm
ED

- Microphone impedance detection after 4-pole microphone plugged-in

- MICD_LVL[0]: Down key 400 620 Ohm
- MICD_LVL[1]: Up key 150 320 Ohm
MICD_LVL[2]: Hook key 0 100 Ohm
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MediaTek Confidential © 2015 MediaTek Inc. Page 34 of 304

2.10 Battery Charger

Table 2-13. Charger specifications

AL
Parameter Conditions Min. Typ. Max. Unit
CHRIN(or called VBUS in ref.
4.3 5 10.5 V
schematic) operating voltage
OTG B-Valid detection 0.8 2.4 4 V

TI
VCDT_VTHL[3:0] = 0000 ~
VCDT detection threshold 4.3 10.5 V
1111
CHRIN switch threshold

EN
7 V
HV adaptive current @ (300mA => 70mA)
pre_charge CHRIN switch threshold
6 V
(70mA => 300mA)
Programmable: 3.3~3.45,
VBAT CC voltage accuracy

VBAT CV voltage accuracy

VBAT OV voltage accuracy
50mV steps
Programmable: 3.5~4.4 V
Programmable: 3.9~4.5 V
ID -50

-30
-30
+50

+30
+30
mV

mV
mV
NF
Programmable:500 ~2000
mA -10 +10 %
CC mode charging current (Rsense=56mohm)
accuracy
Programmable:300 ~500 mA
-15 +15 %
(Rsense=56mohm)
CO

2.11 BC1.x
Table 2-14. BC1.x specifications
K

Parameter Conditions Min. Typ. Max. Unit

Standard down-stream port 35 70 94 mA
TE

BC11 charging port detection Standard charging down-

35 70 94 mA
(Pre-CC current) stream port
DP, DM short 210 300 390 mA
DP, DM floating 210 300 390 mA
IA

IPU_DP, IPU_DM 7 9.6 13 uA

IPD_DP, IPD_DM 50 96 150 uA
VSRC on DP, DM 500 630 700 mV
ED

BC11 characteristics Current pulse value under

70 mA
2.2V
Current pulse period under
550 ms
2.2V
OSC1M, timer 5 min
M

2.12 Down Load Without Battery

Table 2-15. Download without battery specifications

MediaTek Confidential © 2015 MediaTek Inc. Page 35 of 304

Parameter Conditions Min. Typ. Max. Unit

Duration 32.0 s
USBDL
Current 450 mA

AL
2.13 AUXADC

TI
Table 2-16. AUXADC specifications

Parameter Conditions Min. Typ. Max. Unit

EN
Supply voltage - 1.8 - V
Channel 0,1,7 - - 15 Bits
Resolution
Others - - 12 Bits
Analog-input bandwidth 0.5K Hz
Sample rate 1K Hz
Offset error
Gain error
INL
Relative to full-scale
Relative to full-scale
15-bit output
ID -1
-1
-
-
2
+1
+1
%
%
LSB
NF
DNL 15-bit output 2 LSB

2.14 Fuel Gauge

Table 2-17. Fuel gauge specifications

Parameter Conditions Min. Typ. Max. Unit

Output resolution 16 Bit
K

FG current characteristics Conversion time 1/16 s

Over-sampling ratio 2^11 2^18
Input voltage range -60 60 mV
TE

Supply 2.8 V
ADC characteristics Current 40 uA
Gain error -2 2 %
Accuracy 0.03 %
IA
ED
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MediaTek Confidential © 2015 MediaTek Inc. Page 36 of 304

3 Functional Descriptions

AL
3.1 General Descriptions
MT6328 is a fully integrated PMIC target for smart phone power provider. Figure 3-1 is the block

TI
diagram of MT6328 PMIC.

EN
MT6328
DCDC: VPA 3G/LTE PA
(Main PMIC)
RTC Macro RF Regulators MT6169
VRF18_0: LDO (2G/3G/4G)
VRF18_1: LDO
VTCXO_0: LDO MT6158

ID
VTCXO_1: LDO (for dual talk)
Main Chip WRAPPER/SPI MD LDOs:
VSIMx2 SIM
Indicator
Core DC/DC
Current Sink *2 VPROC/VCORE1/
NF
VLTE
Base Band
Connectivity Processor/GPU
LDOs BB LDOs
MT6625 VSRAM/VM/
VCN18/VCN28/
VCN33 VIO18
/AVDD28_AUD/
VRTC/VIO28/
CO

Backup Battery
Vibrator Driver VIO18
M (ERM)
VM Memory

Class-AB/D Audio Peripheral LDOs

USB
Audio Amplifier 1 Codec VUSB33
VCAMA/VCAMD/
VCAM_AF/VCAM Camera Sensor
_IO (AF)
AUXADC VAUXA18
VMC/VMCH/
VEMC33 Memory Card
K

Fuel Gauge
eMMC

Pulse Charger Reserve LDOs CPT/

Control BUS VGP1/VeFuse E-fuse
TE

Figure 3-1. MT6328 block diagram

3.2 PMIC Functional Blocks

MT6328 manages the power supply of baseband processor, SIM cards, camera, vibrator, etc. MT6328
includes the following analog functions for use on smart phone platforms.
M

 LDO and BUCK: Provides regulated lower output voltage level from Li-Ion battery
 Current sink (ISINK) driver: Sink current for indicator
 Vibrator driver: Provides regulated power for vibrator.
 AUXADC: 15 bits of analog to digital converter for thermal/accessory detection monitor and
measurement
 Controller: Generates power-on/off sequence, system reset and exceptional handling function

MediaTek Confidential © 2015 MediaTek Inc. Page 37 of 304

 Charger controller: Controls/Protects battery charging procedure

 Full-set high-quality audio feature: Supports uplink/downlink audio CODEC
 Fuel gauge: Supports accurate battery capacity monitor

AL
More detailed descriptions of each sub-block are explained in the following sections.

TI
3.2.1 Power-On/Off Sequence
PMIC handles the power-on and power-off of the handset. If the battery voltage is neither in the

EN
UVLO state (VBAT ≥ UVLO_VTHH) nor in the thermal condition, there are 3 methods to power on
the handset system.

1) Pulling PWRKEY low (User presses PWRKEY.)

2) Setting BBWAKEUP to high
3) Valid charger plug-in ID
NF
VBAT

DDLO

UVLO
CO

PWRKEY
De-bounce
time = 32ms
BBWAKEUP

4ms
VRTC

VAUXA18 2ms
4ms
K

VCORE
2ms

VLTE 10ms
2ms

VSYS22 2ms
TE

2ms

VIO18/VEMC_3V3 2ms
2ms

VIO28
2ms

VEFUSE
2ms

EXT_PMIC_EN
2ms
IA

VPROC
2ms

VSRAM
2ms

VM
2ms

VAUD28 2ms
ED

VUSB33 2ms

VTCXO_0
2ms
2ms
VMC/VMCH

XOSC_EN
M

ENBB
40ms
RESETB

VTCXO on/off controlled by DDLO

32K removal application~ VTCXO turn on after VRTC
VTCXO on/off controlled by Power on/off signal
W/I 32K OSC application~ VTCXO turn on after VMC/VMCH
*DDLO and UVLO are internal signal

Figure 3-2. Power-on/off control sequence with XTAL by pressing PWRKEY

MediaTek Confidential © 2015 MediaTek Inc. Page 38 of 304

VBAT

AL
DDLO

UVLO

Charger in
De-bounce time

TI
= (131+67)ms

BBWAKEUP

4ms
VRTC

VAUXA18 2ms
4ms

EN
VCORE
2ms

VLTE 10ms
2ms

VSYS22 2ms
2ms

VIO18/VEMC_3V3 2ms
2ms

ID
VIO28
2ms

VEFUSE
2ms

EXT_PMIC_EN
2ms

VPROC
2ms
NF
VSRAM
2ms

VM
2ms

VAUD28 2ms

VUSB33 2ms
CO

VTCXO_0
2ms
2ms
VMC/VMCH

XOSC_EN

ENBB
40ms
RESETB

VTCXO on/off controlled by DDLO

32K removal application~ VTCXO turn on after VRTC
K

VTCXO on/off controlled by Power on/off signal

W/I 32K OSC application~ VTCXO turn on after VMC/VMCH
*DDLO and UVLO are internal signal
TE

Figure 3-3. Power-on/off control sequence with XTAL by charger plug in

1. Pushing PWRKEY (pulling the PWRKEY pin to low level)

Pulling PWRKEY low is a typical method to turn on the handset. The system reset ends at the
IA

moment when all default-on regulators are sequentially turned on. After that, the baseband will
send the BBWAKEUP signal back to PMIC for acknowledgement. To successfully power on the
handset, PWRKEY should be kept low until PMIC receives BBWAKEUP from the baseband.
ED

2. RTC module generates BBWAKEUP to wake up the system.

If the RTC module is scheduled to wake up the handset at some time, the BBWAKEUP signal will
be directly sent to PMIC. In this case, BBWAKEUP becomes high at specific moment and allows
M

PMIC power-on. This is called the RTC alarm.

3. Valid charger plug-in (CHRIN voltage within valid range)

The charger plug-in will also turn on the handset if the charger is valid. When PMU_CHGIN input
voltage> CHGIN_VTHH and VSYS>UVLO, the handset will also be powered on.

MediaTek Confidential © 2015 MediaTek Inc. Page 39 of 304

Under-voltage lockout (UVLO)

The UVLO state in PMIC prevents start-up if the initial voltage of the main battery is below
UVLO_VTH. The judgment is done by VSYSNS (with charger plugged in) and VBATSNS+VSYSNS

AL
(without charger plugged in). It ensures that the handset is powered on with the battery in good
condition. The UVLO function is performed by a hysteretic comparator which ensures smooth power-
on sequence. In addition, when the battery voltage is getting lower, it will enter the UVLO state and
PMIC will be turned off by itself, except for VRTC LDO, to prevent further discharging. Once PMIC

TI
enters the UVLO state, it will draw low quiescent current. RTC LDO will still be working until DDLO
disables it.

EN
Deep discharge lockout (DDLO)
PMIC will enter the deep discharge lockout (DDLO) state when the battery voltage drops below
DDLO_VTHL. In this state, VRTC LDO will be shut down. Otherwise, it will draw very low quiescent
current to prevent further discharging or even damage to the cells.

Reset ID
PMIC contains a reset control circuit which takes effect at both power-up and power-down. The
NF
RESETB pin is held low in the beginning of power-up and returns to high after the pre-determined
delay time. The delay time is controlled by a large counter, which uses the clock from the internal ring-
oscillator. At power-off, the RESETB pin will return to low immediately without any delay.
CO

Over-temperature protection
If the die temperature of PMIC exceeds 150°C, PMIC will automatically disable all regulators except
for VRTC. Once the over-temperature state is resolved, a new power-on sequence will be required to
enable the regulators.
K

3.2.2 Buck Converter and Application Reference

There are 5 buck converters in MT6328 to efficiently generate regulated power for graphic processor,
digital core and circuits. The block diagram is shown in Figure 3-1. The buck converters operate with 3
or 2MHz fixed frequency pulse width modulation (PWM) mode at moderate to heavy load currents. At
IA

light load currents, the converter automatically enters Pulse Frequency Modulation (PFM) mode to
save power and improve light load efficiency. It also has a force-PWM mode option to allow the
converter to remain in the PWM mode regardless of the load current, so that the noise spectrum of the
ED

converter can be minimized for certain highly-noise-sensitive handset applications. The buck
converters also have an internal Over-Current Protection (OCP) circuit to limit the maximum high-
side power FET current in over-load conditions. It has an internal soft start circuit to control the
ramp-up rate of the output voltage during start-up.
M

Table 3-1. Buck converter brief specifications

Default
Vout Voltage Default
BUCK name Voltage Imax (mA) Application
(Volt) step (mV) on (Y/N)
(V)

MediaTek Confidential © 2015 MediaTek Inc. Page 40 of 304

Default
Vout Voltage Default
BUCK name Voltage Imax (mA) Application
(Volt) step (mV) on (Y/N)
(V)

AL
VPROC 1.15 0.6~1.31 6.25 5000 Y CPU
Digital core
VCORE1 1.15 0.6~1.31 6.25 3500 Y always on domain
(CORE_AO)

TI
Digital core power
VLTE 1.05 0.6~1.31 6.25 2800 Y down domain
(CORE_PDN)
VSYS22 2.0 2.0/2.2 NA 1900 Y SYS LDOs power

EN
VPA 0.0 0.5~3.4 50 600 N 3G/LTE PA

3.2.3 Low Dropout Regulator (LDOs) and Application Reference

ID
Table 3-2. LDO types and brief specifications
NF
Input Default Imax Default
Type LDO name power Vout (Volt) Application
Voltage (mA) on (Y/N)
domain
CO

AVDD45_L 26MHz reference

ALDO VTCXO_0 2.8 2.8 40 Y
DO2 clock

AVDD45_L 26MHz reference

ALDO VTCXO_1 2.8 2.8 40 N
DO1 clock

AVDD45_L
K

ALDO VAUD28 2.8 2.8 40 Y Audio

DO1

AVDD45_L
TE

ALDO VAUXA18 1.8 1.8 40 Y AUXADC

DO1

AVDD45_L
ALDO VCAMA 2.8 1.5/1.8/2.5/2.8 200 N Camera module
DO1
IA

AVDD45_L
ALDO VCN28 2.8 2.8 40 N Connectivity 2.8V
DO1

AVDD22_L
ALDO VRF18_0 1.825 1.825 350 N RF power
ED

DO3

AVDD22_L
ALDO VRF18_1 1.825 1.825 300 N RF power
DO4

VBAT_
M

ALDO TREF 1.8 1.8 1 N Battery interface

LDOS1

AVDD45_L 1.7/1.8/1.86/
DLDO VSIM1 1.8 50 N 1st SIM card
DO4 2.76/3.0/3.1

AVDD45_L 1.7/1.8/1.86/
DLDO VSIM2 1.8 50 N 2nd SIM card
DO4 2.76/3.0/3.1

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Input Default Imax Default

Type LDO name power Vout (Volt) Application
Voltage (mA) on (Y/N)
domain

AL
1.2/1.3/1.5/1.8/
AVDD45_L
DLDO VCAM_AF 2.8 2.5/ 200 N Camera module
DO5
2.8/3.0/3.3

TI
1.2/1.3/1.5/1.8/
AVDD45_L
DLDO VGP1 2.8 2.5/ 200 N Cap touch
DO3
2.8/3.0/3.3

EN
AVDD45_L SD 2.0/3.0 memory
DLDO VMC 2.9 1.8/2.9/3.0/3.3 200 Y
DO5 card

AVDD45_L SD 3.0 memory

DLDO VMCH 2.9 2.9/3.0/3.3 800 Y
DO2 card

DLDO VEMC_3V3
AVDD45_L
DO4

AVDD45_L
2.9
ID
2.9/3.0/3.3 400 Y eMMC 3.3V
NF
DLDO VIO28 2.8 2.8 200 Y 2V8 IO
DO3

AVDD45_L
DLDO VCN33 3.3 3.3/3.4/3.5/3.6 350 N Connectivity 3.3V
DO1
CO

AVDD45_L
DLDO VUSB33 3.3 3.3 20 Y USB 3.3V
DO4

AVDD45_L 1.8/1.9/ Main chip Efuse

DLDO VEFUSE 1.8 200 Y
DO4 2.0/2.1/2.2 power
K

AVDD22_L
DLDO VIO18 1.8 1.8 600 Y 1.8V IO
DO2
TE

AVDD22_L By HW
DLDO VM 1.24/1.39/1.54 1000 Y DRAM
DO1 Trapping

AVDD22_L
DLDO VCAM_IO 1.8 1.2/1.3/1.5/1.8 200 N Camera module
DO2
IA

AVDD22_L
DLDO VCN18 1.8 1.8 150 N Connectivity 1.8V
DO2

AVDD22_L 0.9/1.0/1.1/1.22/
ED

DLDO VCAMD 1.3 500 N Camera module

DO1 1.3/1.5

AVDD22_L
DLDO VSRAM 1.2 0.6~1.31 400 Y CPU SRAM
DO2
M

AVDD45_L
VRTC VRTC 2.8 2.8 2 Y Real-time clock
DO2

DVDD1 AVDD45_L
DVDD18_DIG 1.8 1.8 20 Y Internal digital
8_DIG DO2

VIBR VIBR AVDD45_L 2.8 1.2/1.3/1.5/1.8/2 100 N Vibrator

MediaTek Confidential © 2015 MediaTek Inc. Page 42 of 304

Input Default Imax Default

Type LDO name power Vout (Volt) Application
Voltage (mA) on (Y/N)
domain

AL
DO5 .5/2.8/3.0/3.3

TI
3.2.4 Drivers
MT6328 supports 2 indicator LED drivers at most. The following figure depicts the major application
for indicator LEDs drivers, and how to configure breath mode.

EN
ID
NF
CO
K
TE
IA
ED
M

MediaTek Confidential © 2015 MediaTek Inc. Page 43 of 304

VBAT

AL
TI
EN
ISINK0

ISINK1

Mode setting:
Register/PWM/Breath
ID
NF
CO
K
TE
IA
ED

Figure 3-4. Configuration for indicator LED drivers

3.2.5 Vibrator Driver

The VIBR driver power allows up to 100mA current for is for ERM (Eccentric Rotating Mass) or coin
type vibrator with programmable output voltage.

MediaTek Confidential © 2015 MediaTek Inc. Page 44 of 304

3.2.6 Audio CODEC and Accessory Detection

3.2.6.1 Block Descriptions

AL
The block diagram of audio codec is illustrated below. The audio uplink path is composed of PGA and
audio ADC. There are three input pairs of the uplink path to support dual-MIC, earphone-MIC, and
digital MIC. The uplink front-end to PGA can be configured as ACC or DCC type. The audio downlink

TI
is composed of stereo audio DACs, stereo headphone drivers and a mono voice driver. High-fidelity
audio is reproduced on headphones and clear mobile speech on earpiece is driven by voice drivers.
The internal high output power loud-speaker amplifier is also embedded. The necessary MIC bias

EN
voltages and multi-key accessory detection are also provided by this completed audio codec.

DCC_Control

DMIC_CLK

DMIC_DATAL ID
3.25M/1.625M/812.5K Hz
3.25M Hz
NF
DMIC_DATAR
Digital MIC
MICBIAS0
ACC/DCC
AIN0_P
AIN0_N Main_MIC
ADC0_L PreampL ACCDET
MICBIAS1
CO

AIN1_P
AIN1_N Headset_MIC

ACCDET
ADC_R PreampR AIN2_P
Ref_MIC
AIN2_N

0 dB ~24 dB (6 dB/step)
K

CLK_Gen CLKSQ CLK26M

(a) Audio/speech uplink and accessory detection

IA
ED
M

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IV Mux L-Ch IV Converter

iDACLP IVLP

AL
to SPK-L
iDACLN
IVLN

TI
HS Mux HS Driver AUDHSPWRUP

AUDZCDENABLE HSP
AUDZCDMUXSEL iDACLP
VCM0 AUDHSSCDISABLE
HPLP/HPLN (HPRP/HPRN) AUDHSBSCCURRENT
iDACLN
HSN
ZCD HSP/HSN

EN
(Ana. Part) Line-R/Line-L
AUDHSMUXINPUTSEL -10dB to +8dB AUDHSGAIN
IVLP/IVLN (IVRP/IVRN)
in 1dB steps
VCM0

HPL Mux HPL Driver AUDHPLPWRUP

iDACLP /
IVLP
HPLP
DAC_13M_CK
Audio VCM0 AUDHPLSCDISABLE
iDACLN / AUDHPLBSCCURRENT
LCH-DAC

ID
IVLN
HPLN

AUDHPLMUXINPUTSEL -10dB to +8dB AUDHPLGAIN

VREFP Low Noise AUDDACLPWRUP in 1dB steps
AUDHPSTARTUP
Digital Block VREFN Iref. Gen. AUDDACRPWRUP
HPR Mux HPR Driver AUDHPRPWRUP

iDACRP HPRP
NF
DAC_13M_CK
Audio VCM0 AUDHPRSCDISABLE
RCH-DAC iDACRN AUDHPRBSCCURRENT
HPRN

FIFO_13M_CK
AUDHPRMUXINPUTSEL -10dB to +8dB AUDHPRGAIN
AUDCLK26M_EN
AUDINTERPRSTB
in 1dB steps
AUDIO_FIFO_ENABLE
AUDREFN
CO

(b) Audio/speech downlink

Figure 3-5. Audio CODEC block diagram

3.2.7 Class-AB/D Audio Amplifier

MT6328 has one built-in channel high efficiency class AB/D audio power amplifier capable of
delivering 0.7 watt of power on an 8 ohm BTL load from a 3.7V battery supply. Over-current
protection is integrated. MT6328 also has built-in receiver mode for 2-in-1 loudspeaker which
IA

supports multi-purpose loudspeaker without any extra BOM cost. The output power can reach 97mW
onto 8 ohm speaker load. The block diagram is shown below.
ED
M

MediaTek Confidential © 2015 MediaTek Inc. Page 46 of 304

Speaker Amplifier

AL
Voice input
SPK _P

Input MUX
-
Class AB/D
SPK _N

TI
Audio input +

EN
Figure 3-6. Block diagram of class-AB/D

3.2.8 Battery Charger (Charger Controller)

ID
The charger controller senses the charger input voltage from either a standard AC-DC adaptor or an
NF
USB charger. When the charger input voltage is within a pre-determined range, the charging process
will be activated. This detector resists higher input voltages than other parts of PMIC.
CO

3.2.8.1 Block Descriptions

The block diagram of battery charger is illustrated below.
K
TE
IA
ED
M

MediaTek Confidential © 2015 MediaTek Inc. Page 47 of 304

Charger block diagram

Off Chip ON Chip

CHRIN

AL
CHRIN
CHRLDO 2.8V
VBAT

CHRLDO28 DRV
VBAT_DDLO_DET

TI
CSDAC_EN 8V LDMOS

VBAT_DDLO_VTH<1:0>

CSDAC_DAT<7:0>
VBAT_UVLO_DET

VREF VBAT_UVLO_VTH<1:0>
VBAT
Voltage VBAT_CC_DET ISENSE

EN
divider VBAT_CC_VTH[1:0]

CS_DET Current in2

in1
Sensing vr set Rsense
VBAT_CV_DET EN

CS_EN VREF
VBAT_CV_VTH[1:0]
CS_VTH[3:0]
gain BATSNS
VBAT
VBAT_OV_DET CHR_LDO_DET (VBAT)
VBAT_OV_VTH[1:0]

TREF

BATON
COMP BATON_UNDET
And

ID
Charger Core

Digital Controller

Interface To BB
NF
RNTC
OTG/BATON VREF GEN

COMP OTG_BVALID_DET
BC1.1
Controller

CHRIN
VCDT UpTo 10.5V
OTG_BVAILD_EN

VCDT
CO

COMP VCDT_DET
VCDT VREF GEN MUX
CCHRLDO_DET_CMP
VCDT_VTH[3:0]
VTH CGRLDOGOOD
CHR_LDO_DET COMP
VBGR

Figure 3-7. Block diagram of battery charger

K
TE

3.2.8.1.1 Charger Detection

Whenever an invalid charging source is detected (> 7.0V, software default setting), the charger
detector will stop the charging process immediately to avoid burning out the chip or even the phone.
IA

Furthermore, if the charger-in level is not high enough (< 4.3V), the charger will also be disabled to
avoid improper charging behavior.
ED

3.2.8.1.2 Charging Control

When the charger is active, the charger controller will manage the charging phase according to the
battery status. During the charging period, the battery voltage is constantly monitored. The battery
M

charger supports pre-charge mode (VBAT < 3.0V, PMIC power-off state), CC mode (Constant Current
mode or fast charging mode at the range of 3.0V < VBAT < 4.2V, CV default voltage) and CV mode
(Constant Voltage mode) to optimize the charging procedure for Li-ion battery. See the figure below
for the charging states diagram.

MediaTek Confidential © 2015 MediaTek Inc. Page 48 of 304

NON-CHARGING

AL
Dead Battery YES
VBAT < 2.2V
5min timeout

TI
CHRIN > 4.3V
CHRIN DET

EN
YES

YES
VBAT > 3.0V

Charger OFF
YES
VBAT < 3.0V
35min timeout
ID CC MODE
NF
NO

NO
PreCC VBAT > 4.2V
CO

CV MODE

YES

FULL
K

NO
VBAT= 4.2V
TE

YES

Reduce ICHG
IA

NO
ICHG =0V
ED

YES

Charger OFF
M

NO
VBAT < 4.3V

YES

Figure 3-8. Flow chart of charging states

MediaTek Confidential © 2015 MediaTek Inc. Page 49 of 304

Pre-charge mode
When the battery voltage is in the UVLO state, the charger will operate in the pre-charge mode. There
are two steps in this mode. While the battery voltage is deeply discharged below 2.2V, IUNIT trickle

AL
charging current is applied to the battery.

The IUNIT trickle charging current is about 550ms pulse 70mA current when VBAT is under 2.2V.

TI
When the battery voltage exceeds 2.2V, i.e. the PRECC1 stage, the closed-loop pre-charge will be
enabled. The voltage drop across the external RSENSE is kept around 16.8mV (AC charger) or 3.92mV
(USB host). The closed-loop pre-charge current can be calculated:

EN
VSENSE 16.8mV
IPRECC1, ACadapter  
Rsense Rsense
V
IPRECC1, USBHOST  SENSE 
3.92mV
Rsense Rsense

Constant current mode

ID
NF
As the battery is charged up and over 3.0V, it can switch to the CC mode. (CHR_EN should be high)
In the CC mode, several charging currents can be set by programming registers or the external
RSENSE resistor. The charging current can be determined by CS_VTH/RSENSE, where CS_VTH is
CO

programmed by registers. For example, if RSENSE is selected as 0.056ohm, the CC mode charging
current can be set from 70 to 2,000mA. It can accommodate the battery charger to various charger
inputs with different current capabilities.

Constant-voltage mode and over-voltage protection (OV)

When the battery voltage reaches about 4.2V, a constant voltage is used for charging. This is called the
full-voltage charging mode or constant-voltage charging mode in correspondence to a linear charger.
When the battery voltage actually reaches 4.2V, the charging current gradually decreased step-by-step,
TE

and the end-of-charging process starts. It may prolong the charging and detecting period for acquiring
optimized full charging volume. The charging process is completed once the current reaches
termination current automatically and this mechanism is optimized for different battery packs.
IA

Whenever the battery voltage exceeds 4.3V (programmed by SW), a hardware OV protection will be
activated and turns off the charger immediately.
ED

3.2.8.1.3 BC1.x Dead-Battery Support

MT6328 also supports dead-battery condition BC1.x. These specifications protect dead-battery
charging by timer and trickle current. Once the battery voltage is below 2.2V, a period (TUNIT) of
M

trickle current (IUNIT) will be applied to the battery.

If the battery voltage is still below 2.2V after the trickle current is applied, the charger will be disabled.
On the other hand, once the battery voltage rises to above 2.2V, the charger will enter the PRECC1
stage, and the charging current will be 70mA or 300mA depending on the type of the charging port.

MediaTek Confidential © 2015 MediaTek Inc. Page 50 of 304

When the battery is below 3.0V, the charger will charge the battery by the PRECC1 current.
A dedicated 5 min. (T1) timer will be timed out and disable the charger if the battery voltage is always
below 2.4V under charging. Another 35 min. (T2) timer will also be timed out and disable the charger

AL
if the battery voltage is always kept between 2.7V and 3.0V under charging.

The trickle current (IUNIT) and two dedicated timers protect the charging action if the battery is dead.

TI
3.2.8.1.4 Auto Power-On Mode (USB down load without battery)

EN
MT6328 features a default auto power-on mode (or USB DL without battery) no matter with or
without battery. Users can disable auto power-on by adding external pull-high resistor on the
FCHR_ENB pin. They can still initiate USB DL (auto power-on) by pressing DL_KEY or under valid
BAT_ON information (decided by customers’ PCB options). Nonetheless, DL_KEY supports key

ID
function in normal mode. The valid BAT_ON information can be detected through battery’s NTC
when it is connected to pin BAT_ON of MT6328.
NF
3.2.9 AUXADC

3.2.9.1 Block Descriptions

The auxiliary ADC includes the following functional blocks:

1. Analog multiplexer: Selects signal from one of the input channels. Real-world messages to be
monitored, e.g. temperature, should be transferred to the voltage domain.
2. 15-bit A/D converter: Converts the multiplexed input signal to 15-bit digital data.
K

Table 3-3. Application and input range of ADC channels

Channel Application Input range [V]

0 BATSNS 2.5 ~ 4.5
1 ISENSE 2.5 ~ 4.5
2 VCDT 0 ~ 1.5
IA

3 BATON 0.1 ~ 1.7

5 ACCDET 0 ~ 1.8
7 AUXADC_VIN 0 ~ 1.8
ED

others Internal use N/A

3.2.10 Fuel Gauge

The fuel gauging system includes a dedicated ADC for Li-Ion battery current measurement and
utilizes the measurement ADC (AUXADC) for battery voltage and temperature measurement. The
battery state-of-charge (SOC) estimation is performed by the software using the three measuring
methods and the accumulated current measurement. The application diagram of the fuel gauging
system is shown in the figure below, where an external resistor is used to convert the current drawn

MediaTek Confidential © 2015 MediaTek Inc. Page 51 of 304

from the battery into a voltage which is then measured by FG ADC. The value of the external resistor
must be chosen so that the maximum current during charging or discharging will not cause ADC to
exceed its input voltage range.

AL
The principle of operation of the fuel gauge relies on a combination of Coulomb counting and light
load battery voltage measurement. Coulomb counting provides an estimate of the charge that has been
withdrawn or delivered to the battery, while battery voltage measurement proves a good estimate of

TI
the battery SOC under low-load conditions. The battery voltage measurement compensates for error
accumulation during the current integration inherent in Coulomb counting. The hardware also
includes necessary modes to allow for simultaneous current and voltage measurement which can be

EN
utilized to estimate the battery impedance.

VBAT

ID
VSENSE

R 2R

TREF
NF
AUXADC
Battery Pack
Digital System and I2C
Control Serial Port

TEMP

FG
FGADC
Digital
K

Bandgap
Ref
CLK 32KHz
TE

NTC
IA

CURRENT
ED

Figure 3-9. Fuel gauge block diagram and external connection

3.2.11 Real-time Clock

The Real Time Clock (RTC) module provides time and data information. The clock is based on a
32.768kHz oscillator with an independent power supply. When the mobile handset is powered off, a
dedicated regulator supplies the RTC block. If the main battery is not present, a backup supply such as
a small mercury cell battery or a large capacitor will be used. In addition to providing timing data, an
alarm interrupt is generated and can be used to power up the baseband core via the BBWAKEUP pin.

MediaTek Confidential © 2015 MediaTek Inc. Page 52 of 304

Regulator interrupts corresponding to seconds, minutes, hours and days can be generated whenever
the time counter value reaches a maximum value (e.g. 59 for seconds and minutes, 23 for hours, etc.).
The year span is supported up to 2,127. The maximum day-of-month values, which depend on the leap

AL
year condition, are stored in the RTC block.

In MT6328, RTC module also supports function without 32kHz crystal. It can be configured by
hardware option. The two configurations are shown below. While crystal is absent, RTC module has

TI
an embedded 32kHz oscillator to assist life time extension after master 32kHz clock is off.

EN
(a) XTAL Mode

RTC

XIN
ID XOUT
NF

CL CL
CO

Figure 3-10. RTC configuration methods for XTAL

(b) w/o XTAL Mode

RTC
IA

XIN XOUT
ED

Other Clock
Source
M

Figure 3-11. RTC configuration methods for w/o XTAL mode

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3.2.11.1 32kHz Crystal Oscillator (XOSC32)

The low-power 32kHz crystal oscillator XOSC32 is designed to work with an external piezoelectric

AL
32.768kHz crystal and a load composed of two functional capacitors. The key performance is shown in
the table below.

Table 3-4. Functional specifications of XOSC32

TI
Symbol Parameter Min. Typical Max. Unit
VRTC RTC module power 1.1 2.8 3.0 V

EN
Tosc Start-up time 1 sec
Dcyc Duty cycle 20 80 %
I Current consumption 5 μA
T Operating temperature -20 80 °C

ID
The minimum VRTC value means if the crystal oscillator starts up successfully, then the minimum
VRTC for the clock to still be alive is 1.1V.
NF
Since the crystal parameters determine the oscillation allowance, below are a few recommendations
for the crystal parameters to be used well with XOSC32 in MT6328.
CO

Table 3-5. Recommended parameters of 32kHz crystal

Symbol Parameter Min. Typical Max. Unit

F Frequency range 32768 Hz
GL Drive level 0.5 uW
∆f/f Frequency tolerance +/- 20 ppm
K

ESR Series resistance 50 70 KΩ

C0 Static capacitance 0.9 2 pF
TE

CL1 Load capacitance 6 12.5 pF

Under such CL range and crystal, the –R is greater than 3 times. If CL is selected larger, the frequency
accuracy will be decreased, and the –R will degrade too.
IA

3.2.12 Interrupt and Watchdog

3.2.12.1 Interrupt
Here are interrupt lists of PMIC to inform BB IC:
M

1. Key pressed and released interrupt

 PWRKEY: Interrupt is issued when PWRKEY is pressed (and released, set by the register).
After receiving the interrupt, the software will read the PWRKEY_DEB status to see if it is
pressed or released.

MediaTek Confidential © 2015 MediaTek Inc. Page 54 of 304

 HOMEKEY: Interrupt is issued when HOMEKEY is pressed (and released, set by the register).
After receiving the interrupt, the software will read the HOMEKEY_DEB status to see if it is
pressed or released.

AL
2. Thermal interrupt
PMIC issues THR_H interrupt for the software high power latch if PMIC die temperature is over
thermal regulation high threshold (e.g. 125° c) and issues THR_L for software latch release if
PMIC die temperature goes from thermal regulation high threshold (e.g. 125° c) back to under

TI
thermal regulation low threshold (e.g. 110° c). The thermal regulation high/low threshold is
adjustable.
3. Charger related interrupt

EN
4. Battery voltage/current H/L interrupt
There are two groups of VBAT detection interrupts.
1) VBAT detected by AUXADC
If VBAT is higher than the threshold specified by a register setting, the HIGHBATTERY

setting, the LOWBATTERY interrupt will be issued.

2) VBAT detected by fuel gauge
ID
interrupt will be issued. If VBAT is lower than the threshold specified by another register
NF
If VBAT is higher than the threshold specified by a register setting, the VBAT_H interrupt will
be issued. If VBAT is lower than the threshold specified by another register setting, the
VBAT_L interrupt will be issued.
5. Fuel-Gauge
CO

6. Speaker OC interrupt
PMIC supports speaker OC interrupt generation which uses PWM detection method.
7. Buck OC interrupt
There are 9 bucks and each has its individual interrupt which uses PWM detection method.
K

8. LDO OC interrupt
PMIC supports LDO OC interrupt generation. It will be issued if any one of the LDOs has OC
condition.
TE

9. RTC interrupt
10. AUDIO interrupt
Audio interrupt can inform AP playback of the audio status.
IA

11. ACCDET interrupt

This is for headphone detection.
ED
M

MediaTek Confidential © 2015 MediaTek Inc. Page 55 of 304

This document contains information that is proprietary to MediaTek Inc.
Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited.
E
MT6328

ID
PMIC Datasheet
Confidential A

NF
Table 3-6. MT6328 interrupts

Status

CO
Module Interrupt ENABLE STATUS Default
ENABLE STATUS Level/Edge De-bounce time Clear
name Name ADR ADR EN
Condition

edge(rising & Write 1

STRUP PWRKEY RG_INT_EN_PWRKEY 0x029C bit0 RG_INT_STATUS_PWRKEY 0x02B4 bit0 1 50ms (in STRUP)
falling) Clear
edge(rising & Write 1
STRUP HOMEKEY RG_INT_EN_HOMEKEY 0x029C bit1 RG_INT_STATUS_HOMEKEY 0x02B4 bit1 0 50ms (in STRUP)
K falling) Clear
Write 1
STRUP PWRKEY_R RG_INT_EN_PWRKEY_R 0x029C bit2 RG_INT_STATUS_PWRKEY_R 0x02B4 bit2 edge(rising) 1 50ms (in STRUP)
Clear
TE
Write 1
STRUP HOMEKEY_R RG_INT_EN_HOMEKEY_R 0x029C bit3 RG_INT_STATUS_HOMEKEY_R 0x02B4 bit3 edge(rising) 0 50ms (in STRUP)
Clear
Write 1
AUXADC THR_H RG_INT_EN_THR_H 0x029C bit4 RG_INT_STATUS_THR_H 0x02B4 bit4 edge(rising) 0 50ms (in STRUP)
Clear
Write 1
IA

AUXADC THR_L RG_INT_EN_THR_L 0x029C bit5 RG_INT_STATUS_THR_L 0x02B4 bit5 edge(rising) 0 50ms (in STRUP)
Clear
Write 1
AUXADC BAT_H RG_INT_EN_BAT_H 0x029C bit6 RG_INT_STATUS_BAT_H 0x02B4 bit6 level (high active) 0 V (in AUXADC)
Clear
Write 1
ED

AUXADC BAT_L RG_INT_EN_BAT_L 0x029C bit7 RG_INT_STATUS_BAT_L 0x02B4 bit7 level (high active) 0 V (in AUXADC)
Clear
Write 1
RTC RTC RG_INT_EN_RTC 0x029C bit9 RG_INT_STATUS_RTC 0x02B4 bit9 level (low active) 0 No
Clear
0x02B4 Write 1
Audio AUDIO RG_INT_EN_AUDIO 0x029C bit10 RG_INT_STATUS_AUDIO level (high active) 0 No
bit10 Clear
M

Write 1
Accdet ACCDET RG_INT_EN_ACCDET 0x029C bit12 RG_INT_STATUS_ACCDET 0x02B4 bit12 level (high active) 0 No
Clear
RG_INT_EN_ACCDET_EIN RG_INT_STATUS_ACCDET_EIN Write 1
Accdet ACCDET_EINT 0x029C bit13 0x02B4 bit13 level (high active) 0 No
T T Clear
ACCDET_NEG RG_INT_EN_ACCDET_NEG RG_INT_STATUS_ACCDET_NEG 0x02B4 Write 1
Accdet 0x029C bit14 level (high active) 0 No
V V V bit14 Clear
Write 1
STRUP NI_LBAT_INT RG_INT_EN_NI_LBAT_INT 0x029C bit15 RG_INT_STATUS_NI_LBAT_INT 0x02B4 bit15 edge(rising) 0 150us (in STRUP)
Clear
Regulator VPROC_OC RG_INT_EN_VPROC_OC 0x02A2 bit0 RG_INT_STATUS_VPROC_OC 0x02B6 bit0 level (high active) 0 PMW deb (in Write 1

MediaTek Confidential © 2015 MediaTek Inc. Page 56 of 304

This document contains information that is proprietary to MediaTek Inc.
Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited.
E
MT6328

ID
PMIC Datasheet
Confidential A

NF
Status
Module Interrupt ENABLE STATUS Default
ENABLE STATUS Level/Edge De-bounce time Clear
name Name ADR ADR EN
Condition

CO
STRUP) Clear

PMW deb (in Write 1

Regulator VSYS_OC RG_INT_EN_VSYS_OC 0x02A2 bit1 RG_INT_STATUS_VSYS_OC 0x02B6 bit1 level (high active) 0
STRUP) Clear
PMW deb (in Write 1
Regulator VLTE_OC RG_INT_EN_VLTE_OC 0x02A2bit2 RG_INT_STATUS_VLTE_OC 0x02B6 bit2 level (high active) 0
STRUP) Clear
K PMW deb (in Write 1
Regulator VCORE_OC RG_INT_EN_VCORE_OC 0x02A2 bit5 RG_INT_STATUS_VCORE_OC 0x02B6 bit5 level (high active) 0
STRUP) Clear
PMW deb (in Write 1
Regulator VPA_OC RG_INT_EN_VPA_OC 0x02A2 bit8 RG_INT_STATUS_VPA_OC 0x02B6 bit8 level (high active) 0
TE
STRUP) Clear
100/200/400/80 Write 1
LDO LDO_OC RG_INT_EN_LDO_OC 0x02A2 bit9 RG_INT_STATUS_LDO_OC 0x02B6 bit9 level (high active) 1
0us (in INTCTRL) Clear
0x02B6 Write 1
AUXADC BAT2_H RG_INT_EN_BAT2_H 0x02A2 bit10 RG_INT_STATUS_BAT2_H level (high active) 0 V (in AUXADC)
bit10 Clear
IA

Write 1
AUXADC BAT2_L RG_INT_EN_BAT2_L 0x02A2 bit11 RG_INT_STATUS_BAT2_L 0x02B6 bit11 level (high active) 0 V (in AUXADC)
Clear
0x02B6 Write 1
AUXADC VISMPS0_H RG_INT_EN_VISMPS0_H 0x02A2 bit12 RG_INT_STATUS_VISMPS0_H level (high active) 0 V (in AUXADC)
bit12 Clear
ED

Write 1
AUXADC VISMPS0_L RG_INT_EN_VISMPS0_L 0x02A2 bit13 RG_INT_STATUS_VISMPS0_L 0x02B6 bit13 level (high active) 0 V (in AUXADC)
Clear
0x02B6 Write 1
AUXADC AUXADC_IMP RG_INT_EN_AUXADC_IMP 0x02A2 bit14 RG_INT_STATUS_AUXADC_IMP level (high active) 0 V (in AUXADC)
bit14 Clear
M

Write 1
Speaker SPKL_D RG_INT_EN_SPKL_D 0x02A8 bit0 RG_INT_STATUS_SPKL_D 0X02B8 bit0 level (high active) 0 V (in SPK)
Clear
Write 1
Speaker SPKL_AB RG_INT_EN_SPKL_AB 0x02A8 bit1 RG_INT_STATUS_SPKL_AB 0X02B8 bit1 level (high active) 0 V (in SPK)
Clear
4us (in Write 1
Charger OV RG_INT_EN_OV 0x02A8 bit2 RG_INT_STATUS_OV 0X02B8 bit2 edge(rising) 1
PCHR_DIG) Clear
0/100/200/400u Write 1
Charger BVALID_DET RG_INT_EN_BVALID_DET 0x02A8 bit3 RG_INT_STATUS_BVALID_DET 0X02B8 bit3 level (high active) 1
s (in INTCTRL) Clear
RGS_BATON_ RG_INT_EN_RGS_BATON_ RG_INT_STATUS_RGS_BATON_ Write 1
Charger 0x02A8 bit4 0X02B8 bit4 level (high active) 1 N
HV HV HV Clear

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MT6328

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NF
Status
Module Interrupt ENABLE STATUS Default
ENABLE STATUS Level/Edge De-bounce time Clear
name Name ADR ADR EN
Condition

CO
VBATON_UND RG_INT_EN_VBATON_UN RG_INT_STATUS_VBATON_UN 0/100/200/400u Write 1
Charger 0x02A8 bit5 0X02B8 bit5 level (high active) 1
ET DET DET s (in INTCTRL) Clear
Write 1
Charger WATCHDOG RG_INT_EN_WATCHDOG 0x02A8 bit6 RG_INT_STATUS_WATCHDOG 0X02B8 bit6 level (high active) 1 N
Clear

K
TE
IA
ED
M

MediaTek Confidential © 2015 MediaTek Inc. Page 58 of 304

3.2.12.2 Watchdog Reset

AL
WDTRSTB_IN is the watchdog reset from AP. PMIC resets all modules to initial state when receiving
watchdog reset from AP.

3.2.13 SPI Interface

TI
PMIC uses a 4-wire interface consisting of a clock, a chip select and two data signals (MOSI and MISO)
to connect to BB. This serial-parallel interface allows BB to write commands to and read status from
PMIC.

EN
On the other hand, the IO pin (MISO) can be used as data pin or interrupt pin depending on what the
system scenario is. It is used as data pin when system is in normal mode but as INT pin when system
is in suspend mode.

3.2.13.1 Data Format

ID
NF
The pre-defined SPI format consists of two modes: Single I/O mode and dual I/O mode. Single I/O
always uses MOSI as output and input. Dual I/O uses both MOSI and MISO to be output and input to
achieve better channel usage. The format conveys information of R/W direction, 15-bit address (bit 15
CO

to bit 1) and 16-bit data, and both addresses and data are MSB first. The operation waveform of SPI is
illustrated as below. The SPI slave in PMIC latch data sent from the master at rising edge of clock, and
output data at falling edge of clock. The parameter tSLCH, tDMMY and tCHSH are fully configurable
through command registers (in BB instead of PMIC) as illustrated in the figures below.
K

SPI format:
Master output Slave latch
tSLCH
@falling edge @rising edge
TE

CS
CS
CK
Dual I/O CK
Write
SIO0 1
5
R 1
W 4
1
3
1
2
1
1
1
0
9 8 7 6 5 4 3 2 1
1
5
1
4
1
3
1
2
1
1
1
0
9 8 7 6 5 4 3 2 1 0
SIO0 1
5
1
3
1
1
9 7 5 3 1
1
5
1
3
1
1
9 7 5 3 1

SIO1 SIO1 R 1
W 2
1
0
8 6 4 2 0
1
4
1
2
1
0
8 6 4 2 0
IA

ADR, M->S DATA, M->S

ADR, M->S DATA, M->S
Master output Master latch
tSLCH
@falling edge @rising edge

CS
CS
CK
ED

Dual I/O CK
Read
SIO0 1
5
R 1
W 4
1
3
1
2
1
1
1
0
9 8 7 6 5 4 3 2 1
1
5
1
4
1
3
1
2
1
1
1
0
9 8 7 6 5 4 3 2 1 0
SIO0 1
5
1
3
1
1
9 7 5 3 1
1
5
1
3
1
1
9 7 5 3 1

SIO1 SIO1 R 1
W 2
1
0
8 6 4 2 0
1
4
1
2
1
0
8 6 4 2 0

ADR, M->S Dummy DATA, S->M

ADR, M->S Dummy DATA, S->M
M

MediaTek Confidential © 2015 MediaTek Inc. Page 59 of 304

SPI parameter configuration:

1+EXT_CK (1 or 2)
1.5+CSLEXT_END
1.5+CSLEXT_START

AL
1+RDDMY 1+CSHEXT
CS
CK

TI
ADR, M->S Dummy DATA, S->M

EN
ID
NF
CO
K
TE
IA
ED
M

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E
MT6328

ID
PMIC Datasheet
Confidential A

NF
3.2.14 GPIO

CO
3.2.14.1 GPIO List
Table 3-7. MT6328 GPIO list

Pin Name Aux Func.0 Aux Func.1 Aux Func.2 Aux Func.5 Aux Func.6 Aux Func.7 PU/PD
PAD_HOMEKEY GPIO0 I1:HOMEKEY O:INT_0 I0:TEST_CK0 PU/PD
PAD_SRCLKEN_IN0
KGPIO1 I1:SRCLKEN_IN0 I0:TEST_IN0 O:TEST_OUT0 PU/PD
PAD_SRCLKEN_IN1 GPIO2 I1:SRCLKEN_IN1 I0:TEST_IN1 O:TEST_OUT1 PU/PD
TE
PAD_RTC32K_1V8_0 GPIO3 O:RTC_32K1V8_0 I0:TEST_IN2 O:TEST_OUT2 PU/PD
PAD_RTC32K_1V8_1 GPIO4 O:RTC_32K1V8_1 O:INT_1 I0:TEST_CK2 I0:TEST_IN3 O:TEST_OUT3 PU/PD
PAD_SPI_CLK GPIO5 I0:SPI_CLK PU/PD
IA

PAD_SPI_CSN GPIO6 I1:SPI_CSN PU/PD

PAD_SPI_MOSI GPIO7 B0:SPI_MOSI PU/PD
PAD_SPI_MISO GPIO8 B0:SPI_MISO PU/PD
ED

PAD_AUD_CLK GPIO9 I0:AUD_CLK I0:TEST_CK1 PU/PD

PAD_AUD_DAT_MOSI GPIO10 I0:AUD_DAT_MOSI I0:TEST_IN4 O:TEST_OUT4 PU/PD
PAD_AUD_DAT_MISO GPIO11 O:AUD_DAT_MISO I0:TEST_IN5 O:TEST_OUT5 PU/PD
M

PAD_ENBB GPIO12 O:ENBB I0:TEST_IN6 O:TEST_OUT6 PU/PD

PAD_XOSC_EN GPIO13 O:XOSC_EN PU/PD

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E
MT6328

ID
PMIC Datasheet
Confidential A

NF
3.2.14.2 GPIO Specification
Table 3-8. MT6328 GPIO electrical characteristics

CO
Parameters Descriptions Min. Typ. Max. Unit
Inputs
VIH Input logic low voltage 0.65*VDDQ VDDQ+0.3 V
VIL Input logic high voltage -0.3 0.35*VDDQ V
Rpu Input pull-up resistance 40 75 190 KΩ
Rpd
Outputs
K
Input pull-down resistance 40 75 190 KΩ

VOH (DC) DC Output logic low voltage 0.75*VDDQ V

TE
VOL (DC) DC Output logic high voltage 0.25*VDDQ V
Leakage
IIN Input leakage current (any input 0V<VIN<VDDIO) -5 5 mA
IA

IOZ Tri-state output leakage current -5 5 mA

IIN Input leakage current (VIN=3.3V/0V) for floating nwell IO -10 10 mA
IOZ Tri-state output leakage current for floating nwell IO -10 10 mA
ED
M

MediaTek Confidential © 2015 MediaTek Inc. Page 62 of 304

3.3 Register Table and Descriptions

Module name: PMIC_REG Base address: (+0h)

AL
Address Name Width Register Function
0000 STRUP_CON0 16 STRUP Control Register 0
0002 STRUP_CON2 16 STRUP Control Register 2

TI
0004 STRUP_CON3 16 STRUP Control Register 3
0008 STRUP_CON5 16 STRUP Control Register 5
0010 STRUP_CON9 16 STRUP Control Register 9

EN
0012 STRUP_CON10 16 STRUP control register 10
0014 STRUP_CON11 16 STRUP Control Register 11
0018 STRUP_CON13 16 STRUP Control Register 13
001A STRUP_CON14 16 STRUP Control Register 14
001C
001E

0040
STRUP_CON15
STRUP_CON16
STRUP_ANA_C
ON0
16
16

16
ID
STRUP Control Register 15
STRUP Control Register 16

STRUP ANA Control Register 0

NF
0206 TEST_OUT 16 TEST_OUT
0220 TOPSTATUS 16 TOP Status
0222 TDSEL_CON 16 TDSEL_CON
0224 RDSEL_CON 16 RDSEL_CON
CO

0226 SMT_CON0 16 SMT_CON0

0228 SMT_CON1 16 SMT_CON1
022A SMT_CON2 16 SMT_CON2
022C DRV_CON0 16 DRV_CON0
022E DRV_CON1 16 DRV_CON1
K

0230 DRV_CON2 16 DRV_CON2

0232 DRV_CON3 16 DRV_CON3
TE

0234 TOP_STATUS 16 TOP_STATUS

RGS_ANA_MO
023A N 16 RGS_ANA_MON

023C TOP_CKPDN_C 16 TOP_CKPDN Control Register 0

ON0
IA

TOP_CKPDN_C
023E ON0_SET 16 TOP_CKPDN_CON0 Register SET

0240 TOP_CKPDN_C 16 TOP_CKPDN_CON0 Register CLR

ON0_CLR
ED

TOP_CKPDN_C
0242 ON1 16 TOP_CKPDN Control Register 1

TOP_CKPDN_C
0244 ON1_SET 16 TOP_CKPDN_CON1 Register SET

TOP_CKPDN_C
M

0246 ON1_CLR 16 TOP_CKPDN_CON1 Register CLR

TOP_CKPDN_C
0248 ON2 16 TOP_CKPDN Control Register 2

024A TOP_CKPDN_C 16 TOP_CKPDN_CON2 Register SET

ON2_SET
TOP_CKPDN_C
024C ON2_CLR 16 TOP_CKPDN_CON2 Register CLR

MediaTek Confidential © 2015 MediaTek Inc. Page 63 of 304

Address Name Width Register Function

TOP_CKPDN_C
024E ON3 16 TOP_CKPDN control register 3

AL
0250 TOP_CKPDN_C 16 TOP_CKPDN_CON3 Register SET
ON3_SET
TOP_CKPDN_C
0252 ON3_CLR 16 TOP_CKPDN_CON3 Register CLR

TOP_CKPDN_C

TI
0254 ON4 16 TOP_CKPDN control register 4

TOP_CKPDN_C
0256 ON4_SET 16 TOP_CKPDN_CON4 Register SET

TOP_CKPDN_C

EN
0258 16 TOP_CKPDN_CON4 Register CLR
ON4_CLR

025A TOP_CKSEL_C 16 TOP_CKSEL Control Register 0

ON0
TOP_CKSEL_C
025C ON0_SET 16 TOP_CKSEL_CON0 Register SET

025E

0260
TOP_CKSEL_C
ON0_CLR
TOP_CKSEL_C
ON1
16

16
ID
TOP_CKSEL_CON0 Register CLR

TOP_CKSEL control register 1

NF
0262 TOP_CKSEL_C 16 TOP_CKSEL_CON1 Register SET
ON1_SET
TOP_CKSEL_C
0264 ON1_CLR 16 TOP_CKSEL_CON1 Register CLR
CO

TOP_CKSEL_C
0266 ON2 16 TOP_CKSEL Control Register 2

0268 TOP_CKSEL_C 16 TOP_CKSEL_CON2 Register SET

ON2_SET
TOP_CKSEL_C
026A ON2_CLR 16 TOP_CKSEL_CON2 Register CLR
K

026C TOP_CKDIVSE 16 TOP_CKDIVSEL Control Register 0

L_CON0
TOP_CKDIVSE
026E 16 TOP_CKDIVSEL_CON0 Register SET
TE

L_CON0_SET

0270 TOP_CKDIVSE 16 TOP_CKDIVSEL_CON0 Register CLR

L_CON0_CLR

0272 TOP_CKDIVSE 16 TOP_CKDIVSEL Control Register 1

L_CON1
IA

TOP_CKDIVSE
0274 L_CON1_SET 16 TOP_CKDIVSEL_CON1 Register SET

0276 TOP_CKDIVSE 16 TOP_CKDIVSEL_CON1 Register CLR

L_CON1_CLR
ED

TOP_CKHWEN
0278 _CON0 16 TOP_CKHWEN control register 0

027A TOP_CKHWEN 16 TOP_CKHWEN_CON0 Register SET

_CON0_SET
TOP_CKHWEN
M

027C _CON0_CLR 16 TOP_CKHWEN_CON0 Register CLR

TOP_CKHWEN
027E _CON1 16 TOP_CKHWEN control register 1

0280 TOP_CKHWEN 16 TOP_CKHWEN_CON1 Register SET

_CON1_SET
TOP_CKHWEN
0282 _CON1_CLR 16 TOP_CKHWEN_CON1 Register CLR

MediaTek Confidential © 2015 MediaTek Inc. Page 64 of 304

Address Name Width Register Function

028A TOP_CLKSQ 16 TOP_CLKSQ Register
TOP_CLKSQ_S

AL
028C ET 16 TOP_CLKSQ Register SET

TOP_CLKSQ_C
028E LR 16 TOP_CLKSQ Register CLR

0290 TOP_CLKSQ_R 16 TOP_CLKSQ_RTC Register

TI
TOP_CLKSQ_R
0292 TC_SET 16 TOP_CLKSQ_RTC Register SET

0294 TOP_CLKSQ_R 16 TOP_CLKSQ_RTC Register CLR

TC_CLR

EN
0296 TOP_CLK_TRI 16 TOP_CLK_TRIM Register
M
BUCK_ALL_CO
0418 N18 16 Buck All Control Register 18

041A

0420
BUCK_ALL_CO
N19
BUCK_ALL_CO
N22
16

16
ID
Buck All Control Register 19

Buck All Control Register 22

NF
042E SMPS_TOP_AN 16 SMPS_TOP Control Register 0
A_CON0
SMPS_TOP_AN
0430 A_CON1 16 SMPS_TOP control register 1

SMPS_TOP_AN
CO

0432 A_CON2 16 SMPS_TOP control register 2

0434 SMPS_TOP_AN 16 SMPS_TOP control register 3

A_CON3
SMPS_TOP_AN
0436 A_CON4 16 SMPS_TOP control register 4

0438 SMPS_TOP_AN 16 SMPS_TOP control register 5

A_CON5
SMPS_TOP_AN
043A A_CON6 16 SMPS_TOP Control Register 6
TE

043C SMPS_TOP_AN 16 SMPS_TOP Control Register 7

A_CON7

0440 VCORE_ANA_C 16 VCORE_ANA Control Register 0

ON0
VCORE_ANA_C
IA

0442 ON1 16 VCORE_ANA Control Register 1

0444 VCORE_ANA_C 16 VCORE_ANA Control Register 2

ON2
ED

VCORE_ANA_C
0446 ON3 16 VCORE_ANA Control Register 3

0448 VCORE_ANA_C 16 VCORE_ANA Control Register 4

ON4
VSYS22_ANA_
044A CON0 16 VSYS22_ANA Control Register 0
M

VSYS22_ANA_
044C CON1 16 VSYS22_ANA Control Register 1

044E VSYS22_ANA_ 16 VSYS22_ANA Control Register 2

CON2
VSYS22_ANA_
0450 CON3 16 VSYS22_ANA Control Register 3

0452 VSYS22_ANA_ 16 VSYS22_ANA Control Register 4

MediaTek Confidential © 2015 MediaTek Inc. Page 65 of 304

Address Name Width Register Function

CON4
VPROC_ANA_C

AL
0454 16 VPROC_ANA Control Register 0
ON0

0456 VPROC_ANA_C 16 VPROC_ANA Control Register 1

ON1
VPROC_ANA_C
0458 ON2 16 VPROC_ANA Control Register 2

TI
045A VPROC_ANA_C 16 VPROC_ANA Control Register 3
ON3
VPROC_ANA_C
045C ON4 16 VPROC_ANA Control Register 4

EN
045E OSC32_ANA_C 16 OSC32 Control Register 0
ON0
OSC32_ANA_C
0460 ON1 16 OSC32 Control Register 1

0462

0464
VPA_ANA_CO
N0
VPA_ANA_CO
N1
16

16
ID
VPA_ANA Control Register 0

VPA_ANA Control Register 1

NF
VPA_ANA_CO
0466 N2 16 VPA_ANA Control Register 2

0468 VPA_ANA_CO 16 VPA_ANA Control Register 3

N3
VLTE_ANA_CO
046A 16 VLTE_ANA Control Register 0
CO

046C VLTE_ANA_CO 16 VLTE_ANA Control Register 1

046E VLTE_ANA_CO 16 VLTE_ANA Control Register 2

N2
VLTE_ANA_CO
0470 16 VLTE_ANA Control Register 3
K

0472 VLTE_ANA_CO 16 VLTE_ANA Control Register 4

N4
TE

048A VPROC_CON11 16 VPROC Control Register 11

04B2 VSRAM_CON11 16 VSRAM Control Register 11
04DA VLTE_CON11 16 VLTE Control Register 11
VCORE1_CON1
0616 16 VCORE1 Control Register 11
IA

1
063E VSYS22_CON11 16 VSYS22 Control Register 11
0666 VPA_CON11 16 VPA Control Register 11
0800 ZCD_CON0 16 ZCD Control Register 0
ED

0802 ZCD_CON1 16 ZCD Control Register 1

0804 ZCD_CON2 16 ZCD Control Register 2
0806 ZCD_CON3 16 ZCD Control Register 3
0808 ZCD_CON4 16 ZCD Control Register 4
M

080A ZCD_CON5 16 ZCD Control Register 5

080C ISINK0_CON0 16 ISINK0 Control Register 0
080E ISINK0_CON1 16 ISINK0 Control Register 1
0810 ISINK0_CON2 16 ISINK0 Control Register 2
0812 ISINK0_CON3 16 ISINK0 Control Register 3
0814 ISINK1_CON0 16 ISINK1 Control Register 0

MediaTek Confidential © 2015 MediaTek Inc. Page 66 of 304

Address Name Width Register Function

0816 ISINK1_CON1 16 ISINK1 Control Register 1
0818 ISINK1_CON2 16 ISINK1 Control Register 2

AL
081A ISINK1_CON3 16 ISINK1 Control Register 3
081C ISINK2_CON1 16 ISINK2 Control Register 1
081E ISINK3_CON1 16 ISINK3 Control Register 1
ISINK_PHASE

TI
0824 16 ISINK PHASE DELAY
_DLY
0826 ISINK_SFSTR 16 ISINK Soft Start
ISINK_EN_CT
0828 16 ISINK Enable Control

EN
RL

082A ISINK_MODE_ 16 ISINK Mode Control

CTRL
VTCXO_0_CON
0A00 0 16 VTCXO_0 Control Register 0

0A02

0A04
0A06
VTCXO_1_CON
0
VAUD28_CON0
VAUX18_CON0
16

16
16
ID
VTCOX_1 Control Register 0

VAUD28 Control Register 0

VAUX18 Control Register 0
NF
0A08 VRF18_0_CON 16 VRF18_0 Control Register 0
0
VRF18_0_CON
0A0A 1 16 VRF18_0 Control Register 1
CO

0A0C VCAMA_CON0 16 VCAMA Control Register 0

0A0E VCN28_CON0 16 VCN28 Control Register 0
0A10 VCN33_CON0 16 VCN33 Control Register 0
0A12 VCN33_CON1 16 VCN33 Control Register 1
0A14 VCN33_CON2 16 VCN33 Control Register 2
VRF18_1_CON
K

0A16 0 16 VRF18_1 Control Register 0

0A18 VRF18_1_CON1 16 VRF18_1 Control Register 1

0A1A VUSB33_CON0 16 USB33 Control Register 0

0A1C VMCH_CON0 16 VMCH Control Register 0
0A1E VMCH_CON1 16 VMCH Control Register 1
0A20 VMC_CON0 16 VMC Control Register 0
IA

0A22 VMC_CON1 16 VMC control register 1

0A24 VEMC_3V3_CO 16 VEMC_3V3 Control Register 0

N0
VEMC_3V3_CO
ED

0A26 N1 16 VEMC_3V3 Control Register 1

0A28 VIO28_CON0 16 VIO28 Control Register 0

0A2A VCAMAF_CON 16 VCAMAF Control Register 0

0
M

0A2C VGP1_CON0 16 VGP1 Control Register 0

0A2E VGP1_CON1 16 VGP1 Control Register 1
0A30 VEFUSE_CON0 16 VEFUSE Control Register 0
0A32 VSIM1_CON0 16 VSIM1 Control Register 0
0A34 VSIM2_CON0 16 VSIM2 Control Register 0
0A36 VIO18_CON0 16 VIO18 Control Register 0

MediaTek Confidential © 2015 MediaTek Inc. Page 67 of 304

Address Name Width Register Function

0A38 VIBR_CON0 16 VIBR Control Register 0
0A3A VCN18_CON0 16 VCN18 Control Register 0

AL
0A3C VCAM_CON0 16 VCMAD Control Register 0

0A3E VCAMIO_CON 16 VCAMIO Control Register 0

0
LDO_VSRAM_
0A40 16 LDO_VSRAM Control Register 0

TI
CON0

0A42 LDO_VSRAM_ 16 LDO_VSRAM Control Register 1

CON1
0A44 VTREF_CON0 16 VTREF Control Register 0

EN
0A46 VM_CON0 16 VM Control Register 0
0A48 VM_CON1 16 VM Control Register 1
0A4A VRTC_CON0 16 VRTC Control Register 0

0A4E ALDO_ANA_C 16 ADLDO Control Register 0

0A50
ON0
ADLDO_ANA_
CON1
ADLDO_ANA_
16 ID
ADLDO Control Register 1
NF
0A52 CON2 16 ADLDO Control Register 2

0A54 ADLDO_ANA_ 16 ADLDO Control Register 3

CON3
ADLDO_ANA_
0A56 CON4 16 ADLDO Control Register 4
CO

0A58 ADLDO_ANA_ 16 ADLDO Control Register 5

CON5
ADLDO_ANA_
0A5A CON6 16 ADLDO Control Register 6

0A5C ADLDO_ANA_ 16 ADLDO Control Register 7

CON7
K

0A5E ADLDO_ANA_ 16 ADLDO Control Register 8

CON8
ADLDO_ANA_
TE

0A60 CON9 16 ADLDO Control Register 9

0A62 ADLDO_ANA_ 16 ADLDO Control Register 10

CON10
ADLDO_ANA_
0A64 16 ADLDO Control Register 11
IA

CON11

0A66 ADLDO_ANA_ 16 ADLDO Control Register 12

CON12
ADLDO_ANA_
0A68 16 ADLDO Control Register 13
ED

CON13
DLDO_ANA_C
0A6A ON0 16 DLDO Control Register 0

0A6C DLDO_ANA_C 16 DLDO Control Register 1

ON1
M

DLDO_ANA_C
0A6E ON2 16 DLDO Control Register 2

0A70 DLDO_ANA_C 16 DLDO Control Register 3

ON3
DLDO_ANA_C
0A72 ON4 16 DLDO Control Register 4

0A74 DLDO_ANA_C 16 DLDO Control Register 5

ON5

MediaTek Confidential © 2015 MediaTek Inc. Page 68 of 304

Address Name Width Register Function

SLDO_ANA_CO
0A76 N0 16 SLDO Control Register 0

AL
0A78 SLDO_ANA_CO 16 SLDO Control Register 1
N1
SLDO_ANA_CO
0A7A N2 16 SLDO Control Register 2

SLDO_ANA_CO

TI
0A7C N3 16 SLDO Control Register 3

SLDO_ANA_CO
0A7E N4 16 SLDO Control Register 4

SLDO_ANA_CO

EN
0A80 16 SLDO Control Register 5
N5

0A82 SLDO_ANA_CO 16 SLDO Control Register 6

N6
SLDO_ANA_CO
0A84 N7 16 SLDO Control Register 7

0A86

0A88
SLDO_ANA_CO
N8
SLDO_ANA_CO
N9
16

16
ID
SLDO Control Register 8

SLDO Control Register 9

NF
0A8A SLDO_ANA_CO 16 SLDO Control Register10
N10
0A90 SPK_CON0 16 Speaker Control Register 0
0A92 SPK_CON1 16 Speaker Control Register 1
CO

0A94 SPK_CON2 16 Speaker Control Register 2

0A9C SPK_CON6 16 Speaker Control Register 6
0A9E SPK_CON7 16 Speaker Control Register 7
0AA0 SPK_CON8 16 Speaker Control Register 8
0AA2 SPK_CON9 16 Speaker Control Register 9
K

0AA4 SPK_CON10 16 Speaker Control Register 10

0AA6 SPK_CON11 16 Speaker Control Register 11
TE

0AA8 SPK_CON12 16 Speaker Control Register 12

0AAA SPK_CON13 16 Speaker Control Register 13
0AAC SPK_CON14 16 Speaker Control Register 14
0AAE SPK_CON15 16 Speaker Control Register 15
IA

0AB0 SPK_CON16 16 Speaker Control Register 16

0AB2 SPK_ANA_CO 16 SPK Control Register 0

N0
SPK_ANA_CO
ED

0AB4 N1 16 SPK Control Register 1

0AB6 SPK_ANA_CO 16 SPK Control Register 3

N3
0C00 OTP_CON0 16 OTP Control Register 0
M

0C02 OTP_CON1 16 OTP Control Register 1

0C04 OTP_CON2 16 OTP Control Register 2
0C06 OTP_CON3 16 OTP Control Register 3
0C08 OTP_CON4 16 OTP Control Register 4
0C0A OTP_CON5 16 OTP Control Register 5
0C0C OTP_CON6 16 OTP Control Register 6

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Address Name Width Register Function

0C0E OTP_CON7 16 OTP Control Register 7
0C10 OTP_CON8 16 OTP Control Register 8

AL
0C12 OTP_CON9 16 OTP Control Register 9
0C14 OTP_CON10 16 OTP Control Register 10
0C16 OTP_CON11 16 OTP Control Register 11
0C18 OTP_CON12 16 OTP Control Register 12

TI
0C1A OTP_CON13 16 OTP Control Register 13
0C1C OTP_CON14 16 OTP Control Register 14
OTP_DOUT_0_

EN
0C1E 15 16 OTP dout 0 15

OTP_DOUT_16
0C20 _31 16 OTP dout 16 31

0C22 OTP_DOUT_32 16 OTP dout 32 47

_47

0C24

0C26
OTP_DOUT_48
_63
OTP_DOUT_64
_79
16

16
ID
OTP dout 48 63

OTP dout 64 79
NF
0C28 OTP_DOUT_80 16 OTP dout 80 95
_95
OTP_DOUT_96
0C2A _111 16 OTP dout 96 111
CO

0C2C OTP_DOUT_11 16 OTP dout 112 127

2_127
OTP_DOUT_12
0C2E 8_143 16 OTP dout 128 143

0C30 OTP_DOUT_14 16 OTP dout 144 159

4_159
OTP_DOUT_16
K

0C32 0_175 16 OTP dout 160 175

OTP_DOUT_17
0C34 6_191 16 OTP dout 176 191
TE

0C36 OTP_DOUT_19 16 OTP dout 192 207

2_207
OTP_DOUT_20
0C38 8_223 16 OTP dout 208 223
IA

0C3A OTP_DOUT_22 16 OTP dout 224 239

4_239
OTP_DOUT_24
0C3C 0_255 16 OTP dout 240 255
ED

OTP_DOUT_25
0C3E 6_271 16 OTP dout 256 271

0C40 OTP_DOUT_27 16 OTP dout 272 287

2_287
OTP_DOUT_28
M

0C42 8_303 16 OTP dout 288 303

0C44 OTP_DOUT_30 16 OTP dout 304 319

4_319
OTP_DOUT_32
0C46 0_335 16 OTP dout 320 335

0C48 OTP_DOUT_33 16 OTP dout 336 351

6_351

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Address Name Width Register Function

OTP_DOUT_35
0C4A 2_367 16 OTP dout 352 367

AL
0C4C OTP_DOUT_36 16 OTP dout 368 383
8_383
OTP_DOUT_38
0C4E 4_399 16 OTP dout 384 399

OTP_DOUT_40

TI
0C50 0_415 16 OTP dout 400 415

OTP_DOUT_41
0C52 6_431 16 OTP dout 416 431

OTP_DOUT_43

EN
0C54 16 OTP dout 432 447
2_447

0C56 OTP_DOUT_44 16 OTP dout 448 463

8_463
OTP_DOUT_46
0C58 4_479 16 OTP dout 464 479

0C5A

0C5C
OTP_DOUT_48
0_495
OTP_DOUT_49
6_511
16

16
ID
OTP dout 480 495

OTP dout 496 511

NF
0C5E OTP_VAL_0_1 16 OTP val 0 15
5
OTP_VAL_16_3
0C60 1 16 OTP val 16 31
CO

OTP_VAL_32_
0C62 47 16 OTP val 32 47

0C64 OTP_VAL_48_ 16 OTP val 48 63

63
OTP_VAL_64_
0C66 79 16 OTP val 64 79
K

0C68 OTP_VAL_80_ 16 OTP val 80 95

95
OTP_VAL_96_
0C6A 16 OTP val 96 111
TE

111

0C6C OTP_VAL_112_ 16 OTP val 112 127

127

0C6E OTP_VAL_128 16 OTP val 128 143

_143
IA

OTP_VAL_144
0C70 _159 16 OTP val 144 159

0C72 OTP_VAL_160 16 OTP val 160 175

_175
ED

OTP_VAL_176_
0C74 191 16 OTP val 176 191

0C76 OTP_VAL_192_ 16 OTP val 192 207

207
OTP_VAL_208
M

0C78 _223 16 OTP val 208 223

OTP_VAL_224
0C7A _239 16 OTP val 224 239

0C7C OTP_VAL_240 16 OTP val 240 255

_255
OTP_VAL_256
0C7E _271 16 OTP val 256 271

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Address Name Width Register Function

OTP_VAL_272
0C80 _287 16 OTP val 272 287

AL
0C82 OTP_VAL_288 16 OTP val 288 303
_303
OTP_VAL_304
0C84 _319 16 OTP val 304 319

OTP_VAL_320

TI
0C86 _335 16 OTP val 320 335

OTP_VAL_336
0C88 _351 16 OTP val 336 351

OTP_VAL_352

EN
0C8A 16 OTP val 352 367
_367

0C8C OTP_VAL_368 16 OTP val 368 383

_383
OTP_VAL_384
0C8E _399 16 OTP val 384 399

0C90

0C92
OTP_VAL_400
_415
OTP_VAL_416
_431
16

16
ID
OTP val 400 415

OTP val 416 431

NF
0C94 OTP_VAL_432 16 OTP val 432 447
_447
OTP_VAL_448
0C96 _463 16 OTP val 448 463
CO

OTP_VAL_464
0C98 _479 16 OTP val 464 479

0C9A OTP_VAL_480 16 OTP val 480 495

_495
OTP_VAL_496
0C9C _511 16 OTP val 496 511
K

0CA6 FGADC_CON1 16 FGADC Control Register 1

0CA8 FGADC_CON2 16 FGADC Control Register 2
0CAA FGADC_CON3 16 FGADC Control Register 3
TE

0CAC FGADC_CON4 16 FGADC Control Register 4

0CB2 FGADC_CON7 16 FGADC Control Register 7
0CB8 FGADC_CON10 16 FGADC Control Register 10
IA

AUDDEC_ANA
0CDC _CON0 16 AUDDEC Control Register 0

0CDE AUDDEC_ANA 16 AUDDEC Control Register 1

_CON1
ED

AUDDEC_ANA
0CE0 _CON2 16 AUDDEC Control Register 2

AUDDEC_ANA
0CE2 _CON3 16 AUDDEC Control Register 3

0CE4 AUDDEC_ANA 16 AUDDEC Control Register 4

_CON4
M

AUDDEC_ANA
0CE6 _CON5 16 AUDDEC Control Register 5

0CE8 AUDDEC_ANA 16 AUDDEC Control Register 6

_CON6
AUDDEC_ANA
0CEA _CON7 16 AUDDEC Control Register 7

0CEC AUDDEC_ANA 16 AUDDEC Control Register 8

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Address Name Width Register Function

_CON8
AUDENC_ANA

AL
0CEE 16 AUDENC Control Register 0
_CON0

0CF0 AUDENC_ANA 16 AUDENC Control Register 1

_CON1
AUDENC_ANA
0CF2 _CON2 16 AUDENC Control Register 2

TI
0CF4 AUDENC_ANA 16 AUDENC Control Register 3
_CON3
AUDENC_ANA
0CF6 _CON4 16 AUDENC Control Register 4

EN
0CF8 AUDENC_ANA 16 AUDENC Control Register 5
_CON5
AUDENC_ANA
0CFA _CON6 16 AUDENC Control Register 6

0CFC

0CFE
AUDENC_ANA
_CON7
AUDENC_ANA
_CON8
16

16
ID
AUDENC Control Register 7

AUDENC Control Register 8

NF
AUDENC_ANA
0D00 _CON9 16 AUDENC Control Register 9

0D02 AUDENC_ANA 16 AUDENC Control Register 10

_CON10
AUDNCP_CLK
0D04 16 AUDNCP_CLKDIV Control Register 0
CO

DIV_CON0

0D06 AUDNCP_CLK 16 AUDNCP_CLKDIV Control Register 1

DIV_CON1

0D08 AUDNCP_CLK 16 AUDNCP_CLKDIV Control Register 2

DIV_CON2
AUDNCP_CLK
0D0A 16 AUDNCP_CLKDIV Control Register 3
K

DIV_CON3

0D0C AUDNCP_CLK 16 AUDNCP_CLKDIV Control Register 4

DIV_CON4
TE

AUXADC_ADC
0E00 0 16 AUXADC ADC Register 0

0E02 AUXADC_ADC1 16 AUXADC ADC Register 1

AUXADC_ADC
0E04 2 16 AUXADC ADC Register 2
IA

AUXADC_ADC
0E06 3 16 AUXADC ADC Register 3

0E08 AUXADC_ADC 16 AUXADC ADC Register 4

4
ED

AUXADC_ADC
0E0A 5 16 AUXADC ADC Register 5

0E0C AUXADC_ADC 16 AUXADC ADC Register 6

6
M

0E0E AUXADC_ADC7 16 AUXADC ADC Register 7

0E10 AUXADC_ADC 16 AUXADC ADC Register 8

0E12 AUXADC_ADC 16 AUXADC ADC Register 9

9
AUXADC_ADC1
0E14 0 16 AUXADC ADC Register 10

MediaTek Confidential © 2015 MediaTek Inc. Page 73 of 304

Address Name Width Register Function

AUXADC_ADC1
0E16 1 16 AUXADC ADC Register 11

AL
0E18 AUXADC_ADC1 16 AUXADC ADC Register 12
2
AUXADC_ADC1
0E1A 3 16 AUXADC ADC Register 13

AUXADC_ADC1

TI
0E1C 4 16 AUXADC ADC Register 14

AUXADC_ADC1
0E1E 5 16 AUXADC ADC Register 15

AUXADC_ADC1

EN
0E20 16 AUXADC ADC Register 16
6

0E22 AUXADC_ADC1 16 AUXADC ADC Register 17

7
AUXADC_ADC1
0E24 8 16 AUXADC ADC Register 18

0E26

0E28
AUXADC_ADC1
9
AUXADC_ADC
20
16

16
ID
AUXADC ADC Register 19

AUXADC ADC Register 20

NF
0E2A AUXADC_ADC 16 AUXADC ADC Register 21
21
AUXADC_ADC
0E2C 22 16 AUXADC ADC Register 22
CO

AUXADC_ADC
0E2E 23 16 AUXADC ADC Register 23

0E30 AUXADC_ADC 16 AUXADC ADC Register 24

24
AUXADC_ADC
0E32 25 16 AUXADC ADC Register 25
K

0E34 AUXADC_ADC 16 AUXADC ADC Register 26

26
AUXADC_ADC
0E36 16 AUXADC ADC Register 27
TE

0E38 AUXADC_ADC 16 AUXADC ADC Register 28

0E3A AUXADC_ADC 16 AUXADC ADC Register 29

29
IA

AUXADC_ADC
0E3C 30 16 AUXADC ADC Register 30

0E3E AUXADC_ADC 16 AUXADC ADC Register 31

31
ED

AUXADC_ADC
0E40 32 16 AUXADC ADC Register 32

0E42 AUXADC_ADC 16 AUXADC ADC Register 33

33
AUXADC_BUF
M

0E44 0 16 AUXADC_BUF0

0E46 AUXADC_BUF1 16 AUXADC_BUF1

0E48 AUXADC_BUF 16 AUXADC_BUF2

2
AUXADC_BUF
0E4A 3 16 AUXADC_BUF3

0E4C AUXADC_BUF 16 AUXADC_BUF4

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Address Name Width Register Function

4
0E4E AUXADC_BUF5 16 AUXADC_BUF5

AL
0E50 AUXADC_BUF 16 AUXADC_BUF6
6
0E52 AUXADC_BUF7 16 AUXADC_BUF7

0E54 AUXADC_BUF 16 AUXADC_BUF8

TI
AUXADC_BUF
0E56 9 16 AUXADC_BUF9

0E58 AUXADC_BUF1 16 AUXADC_BUF10

EN
0
AUXADC_BUF1
0E5A 1 16 AUXADC_BUF11

AUXADC_BUF1
0E5C 2 16 AUXADC_BUF12

0E5E

0E60
AUXADC_BUF1
3
AUXADC_BUF1
4
16

16
ID
AUXADC_BUF13

AUXADC_BUF14
NF
0E62 AUXADC_BUF1 16 AUXADC_BUF15
5
AUXADC_BUF1
0E64 6 16 AUXADC_BUF16

AUXADC_BUF1
CO

0E66 16 AUXADC_BUF17
7

0E68 AUXADC_BUF1 16 AUXADC_BUF18

8
AUXADC_BUF1
0E6A 9 16 AUXADC_BUF19

AUXADC_BUF
K

0E6C 20 16 AUXADC_BUF20

AUXADC_BUF
0E6E 21 16 AUXADC_BUF21
TE

0E70 AUXADC_BUF 16 AUXADC_BUF22

22
AUXADC_BUF
0E72 23 16 AUXADC_BUF23
IA

AUXADC_BUF
0E74 24 16 AUXADC_BUF24

0E76 AUXADC_BUF 16 AUXADC_BUF25

25
ED

AUXADC_BUF
0E78 26 16 AUXADC_BUF26

0E7A AUXADC_BUF 16 AUXADC_BUF27

27
AUXADC_BUF
0E7C 16 AUXADC_BUF28
M

0E7E AUXADC_BUF 16 AUXADC_BUF29

0E80 AUXADC_BUF 16 AUXADC_BUF30

30
AUXADC_BUF
0E82 31 16 AUXADC_BUF31

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Address Name Width Register Function

0E84 AUXADC_STA0 16 AUXADC_STA0
0E86 AUXADC_STA1 16 AUXADC_STA1

AL
AUXADC_VISM
0EF4 PS0_5 16 AUXADC_VISMPS0_5

0F02 AUXADC_LBA 16 AUXADC_LBAT2_5

T2_5

TI
0F14 ACCDET_CON0 16 ACCDET Control Register 0
0F16 ACCDET_CON1 16 ACCDET Control Register 1
0F18 ACCDET_CON2 16 ACCDET control register 2

EN
0F1A ACCDET_CON3 16 ACCDET Control Register 3
0F1C ACCDET_CON4 16 ACCDET Control Register 4
0F1E ACCDET_CON5 16 ACCDET Control Register 5
0F20 ACCDET_CON6 16 ACCDET Control Register 6
0F22 ACCDET_CON7 16 ACCDET Control Register 7
0F24
0F26
ACCDET_CON8
ACCDET_CON9
ACCDET_CON1
16
16 ID
ACCDET Control Register 8
ACCDET Control Register 9
NF
0F28 0 16 ACCDET Control Register 10

0F2C ACCDET_CON1 16 ACCDET Control Register 12

2
ACCDET_CON1
0F30 4 16 ACCDET Control Register 14
CO

0F32 ACCDET_CON1 16 ACCDET Control Register 15

0F34 ACCDET_CON1 16 ACCDET Control Register 16

6
ACCDET_CON1
0F3A 9 16 ACCDET Control Register 19
K

0F48 CHR_CON0 16 Charger Control Register 0

0F4A CHR_CON1 16 Charger Control Register 1
TE

0F4C CHR_CON2 16 Charger Control Register 2

0F4E CHR_CON3 16 Charger Control Register 3
0F50 CHR_CON4 16 Charger Control Register 4
0F54 CHR_CON6 16 Charger Control Register 6
IA

0F56 CHR_CON7 16 Charger Control Register 7

0F5A CHR_CON9 16 Charger Control Register 9
0F5C CHR_CON10 16 Charger Control Register 10
ED

0F60 CHR_CON12 16 Charger Control Register 12

0F62 CHR_CON13 16 Charger Control Register 13
0F64 CHR_CON14 16 Charger Control Register 14
0F66 CHR_CON15 16 Charger Control Register 15
M

0F68 CHR_CON16 16 Charger Control Register 16

0F6A CHR_CON17 16 Charger Control Register 17
0F6C CHR_CON18 16 Charger Control Register 18
0F6E CHR_CON19 16 Charger Control Register 19
0F70 CHR_CON20 16 Charger Control Register 20
0F72 CHR_CON21 16 Charger Control Register 21

MediaTek Confidential © 2015 MediaTek Inc. Page 76 of 304

Address Name Width Register Function

0F74 CHR_CON22 16 Charger Control Register 22
0F76 CHR_CON23 16 Charger Control Register 23

AL
0F78 CHR_CON24 16 Charger Control Register 24
0F7A CHR_CON25 16 Charger Control Register 25
0F7C CHR_CON26 16 Charger Control Register 26
0F7E CHR_CON27 16 Charger Control Register 27

TI
0F80 CHR_CON28 16 Charger Control Register 28
0F82 CHR_CON29 16 Charger Control Register 29
0F84 CHR_CON30 16 Charger Control Register 30

EN
0F86 CHR_CON31 16 Charger Control Register 31
0F88 CHR_CON32 16 Charger Control Register 32
0F8A CHR_CON33 16 Charger Control Register 33
0F8C CHR_CON34 16 Charger Control Register 34
0F8E
0F90
0F92
CHR_CON35
CHR_CON36
CHR_CON37
16
16
16
ID
Charger Control Register 35
Charger Control Register 36
Charger Control Register 37
NF
0F94 CHR_CON38 16 Charger Control Register 38
0F96 CHR_CON39 16 Charger Control Register 39
0F98 CHR_CON40 16 Charger Control Register 40
0F9A CHR_CON41 16 Charger Control Register 41
CO

0F9C CHR_CON42 16 Charger Control Register 42

0F9E BATON_CON0 16 BATON Control Register 0
0FA0 CHR_CON43 16 Charger Control Register 43
K

STRUP_CON
0000 STRUP Control Register 0 0040
0
TE

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
THR
THR
_H
_DE
Name WPD
T_DI
N_E
S
IA

N
Type RW RW
Reset 0 0
ED

Bit(s) Name Description

5 THR_HWPDN_EN Enables thermal auto power-down
Powers down some PMU modules
0: Disable
1: Enable
M

0 THR_DET_DIS Disables thermal detection function and thermal shut-down

0: Normal mode
1: Disable thermal detection

MediaTek Confidential © 2015 MediaTek Inc. Page 77 of 304

STRUP_CON
0002 STRUP Control Register 2 0000
2

AL
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RG_STRUP_IREF_TRIM
Type RW
Reset 0 0 0 0 0

TI
Bit(s) Name Description
4:0 RG_STRUP_IREF_ Reference current trimming bits
TRIM Trimming current range: 0.5uA~1.4375uA (step=31.25nA), typ=1uA
00000: 1uA

EN
00001~01111: +31.25nA/step
10000: 0.5uA
10001~11111: -31.25nA/step

0004
STRUP_CON
3
STRUP Control Register 3 ID 4001
NF
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RG_
RG_
FCH
FCH
R_K
Name RG_VREF_BG R_P
EYD
U_E
ET_
CO

N
EN
Type RW RW RW
Reset 1 0 0 0 0

Bit(s) Name Description

RG_VREF_BG Reference current fine tuning to compensate bandgap (BG) voltage
K

variation
000: VBG=1.16V
TE

001: VBG=1.17V
14:12 010: VBG=1.18V
011: VBG=1.19V
100: VBG=1.20V (default)
101: VBG=1.21V
110: VBG=1.22V
IA

111: VBG=1.23V
RG_FCHR_PU_EN Enables FCHR internal resistor pull-up
2 0: Disable pull up R
1: Enable pull up R
ED

RG_FCHR_KEYDE FCHR mode state hold without key press detection feature
1 T_EN 0: Disable
1: Enable
M

STRUP_CON
0008 STRUP Control Register 5 0000
5
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PMU_THR_STA
Name TUS
Type RO

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Reset 0 0 0

Bit(s) Name Description

AL
10:8 PMU_THR_STATU Thermal detection status
S

TI
STRUP_CON
0010 STRUP Control Register 9 0000
9
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

EN
JUS
T_P
QI_
WR
Name OSC
KEY
_EN
_RS
T
Type
Reset
RO
0
RO
0
ID
NF
Bit(s) Name Description
15 QI_OSC_EN Enables internal oscillator
0: Disable
1: Enable
CO

14 JUST_PWRKEY_RS Long pressed reset indicator

STRUP_CON
0012 STRUP control register 10 0000
K

10
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STR STR
TE

UP_ UP_
EXT EXT
Name _PM _PM
IC_S IC_E
EL N
Type RW RW
IA

Reset 0 0

Bit(s) Name Description

1 STRUP_EXT_PMIC Selects QI_EXT_PMIC_EN control

_SEL 0: HW mode
1: SW mode
0 STRUP_EXT_PMIC Enables QI_EXT_PMIC_EN software mode
_EN
M

STRUP_CON
0014 STRUP Control Register 11 0020
11
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name STR STR STR STR

MediaTek Confidential © 2015 MediaTek Inc. Page 79 of 304

UP_ UP_ UP_ UP_

AUX AUX AUX AUX
ADC ADC ADC ADC
_RS _ST _RS _ST

AL
TB_ ART TB_ ART
SEL _SE SW _SW
L
Type RW RW RW RW
Reset 0 0 1 0

TI
Bit(s) Name Description
7 STRUP_AUXADC_ Selects STRUP_AUXADC_RSTB
RSTB_SEL 0: HW mode

EN
1: SW mode
6 STRUP_AUXADC_S Selects STRUP_AUXADC_START
TART_SEL 0: HW mode
1: SW mode
5

4
STRUP_AUXADC_
RSTB_SW
STRUP_AUXADC_S
TART_SW
STRUP_AUXADC_RSTB SW path

STRUP_AUXADC_START SW path ID
NF

STRUP_CON
0018 STRUP Control Register 13 17C0
13
CO

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RG_UVLO_VTHL_RSV0
Type RW
Reset 0 0 0 1 0
K

Bit(s) Name Description

15:11 RG_UVLO_VTHL_ Selects UVLO low threshold
RSV0 00000: 2.5V
TE

00001: 2.55V
00010: 2.6V (default)
00011: 2.65V
00100: 2.7V
00101: 2.75V
IA

00110: 2.8V
00111: 2.85V
01000: 2.9V
ED

STRUP_CON
001A STRUP Control Register 14 0000
14
M

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RG_ RG_ RG_ RG_ RG_
Name BGR BGR RG_BGR_RSV2
BGR
RG_BGR_RSV4
BGR BGR
_RS _RS _RS _RS _RS
V0 V1 V3 V5 V6
Type RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0

MediaTek Confidential © 2015 MediaTek Inc. Page 80 of 304

Bit(s) Name Description

15 RG_BGR_RSV0

AL
14 RG_BGR_RSV1
13:11 RG_BGR_RSV2
10 RG_BGR_RSV3
9:5 RG_BGR_RSV4

TI
1 RG_BGR_RSV5
0 RG_BGR_RSV6

EN
STRUP_CON
001C STRUP Control Register 15 0000
15
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
Type
Reset ID 0 0 0
RG_STRUP_RSV

0
RW
0 0 0 0
NF
Bit(s) Name Description
7:0 RG_STRUP_RSV
CO

STRUP_CON
001E STRUP Control Register 16 0800
16
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RG_
TES
RG_ RG_ RG_ RG_
K

TMO
Name STRUP_DIG0_RSV1 EN_ EN_ EN_ EN_
DE_
E4 E8 SR SMT
SWE
N
TE

Type RW RW RW RW RW RW
Reset 0 0 0 0 1 0 0 0 0

Bit(s) Name Description

15:12 STRUP_DIG0_RSV
1
11 RG_TESTMODE_S
WEN
ED

3 RG_EN_E4
2 RG_EN_E8
1 RG_EN_SR
0 RG_EN_SMT
M

STRUP_ANA
0040 STRUP ANA Control Register 0 0000
_CON0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RG_

MediaTek Confidential © 2015 MediaTek Inc. Page 81 of 304

RST
_DR
VSE
L

AL
Type RW
Reset 0

Bit(s) Name Description

TI
RG_RST_DRVSEL Reset pin output driving capability Selection
12 0: 7.5mA (default)
1: 15mA

EN
0206 TEST_OUT TEST_OUT 0000
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
Type
Reset ID 0 0 0
TEST_OUT

0
RO
0 0 0 0
NF
Bit(s) Name Description
7:0 TEST_OUT Monitor
CO

0220 TOPSTATUS TOP Status 0000

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HO PWR
MEK KEY
Name EY_ _DE
DEB B
K

Type RO RO
Reset 0 0
TE

Bit(s) Name Description

2 HOMEKEY_DEB
1 PWRKEY_DEB
IA

0222 TDSEL_CON TDSEL_CON 0000

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RG_
RG_ RG_ RG_
E32C
AUD SPI_ PMU
Name AL_
_TD TDS _TD
TDS
SEL EL SEL
EL
M

Type RW RW RW RW
Reset 0 0 0 0

Bit(s) Name Description

3 RG_E32CAL_TDSE TDSEL
L

MediaTek Confidential © 2015 MediaTek Inc. Page 82 of 304

Bit(s) Name Description

2 RG_AUD_TDSEL TDSEL

AL
1 RG_SPI_TDSEL TDSEL
0 RG_PMU_TDSEL TDSEL

TI
0224 RDSEL_CON RDSEL_CON 0000
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RG_
RG_ RG_ RG_
E32C

EN
AUD SPI_ PMU
Name AL_
_RD RDS _RD
RDS
SEL EL SEL
EL
Type RW RW RW RW
Reset 0 0 0 0

Bit(s)
3
Name
RG_E32CAL_RDSE
L
Description
RDSEL
ID
NF
2 RG_AUD_RDSEL RDSEL
1 RG_SPI_RDSEL RDSEL
0 RG_PMU_RDSEL RDSEL
CO

0226 SMT_CON0 SMT_CON0 003C

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RG_ RG_ RG_ RG_ RG_
RG_
K

SMT SMT SMT SMT SMT

SMT
_RT _RT _SR _SR _WD
Name C_32 C_32 CLK CLK
_HO
TRS
MEK
K1V K1V EN_I EN_ TB_I
TE

EY
8_1 8_0 N1 IN0 N
Type RW RW RW RW RW RW
Reset 1 1 1 1 0 0

Bit(s) Name Description

5 RG_SMT_RTC_32K SMT
1V8_1 0: Disable
1: Enable
ED

4 RG_SMT_RTC_32K SMT
1V8_0 0: Disable
1: Enable
3 RG_SMT_SRCLKE SMT
N_IN1 0: Disable
M

1: Enable
2 RG_SMT_SRCLKE SMT
N_IN0 0: Disable
1: Enable
1 RG_SMT_HOMEK SMT
EY 0: Disable
1: Enable

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Bit(s) Name Description

0 RG_SMT_WDTRST SMT
B_IN 0: Disable

AL
1: Enable

TI
0228 SMT_CON1 SMT_CON1 0000
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RG_ RG_ RG_ RG_
SMT SMT SMT SMT

EN
Name _SPI _SPI _SPI _SPI
_MI _MO _CS _CL
SO SI N K
Type RW RW RW RW
Reset 0 0 0 0

Bit(s)
3
Name
RG_SMT_SPI_MIS
O
Description
SMT
0: Disable
ID
NF
1: Enable
2 RG_SMT_SPI_MOS SMT
I 0: Disable
1: Enable
CO

1 RG_SMT_SPI_CSN SMT
0: Disable
1: Enable
0 RG_SMT_SPI_CLK SMT
0: Disable
1: Enable
K
TE

022A SMT_CON2 SMT_CON2 0000

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RG_ RG_
RG_ SMT SMT RG_
RG_
SMT _AU _AU SMT
IA

SMT
Name _XO D_D D_D _AU
_EN
SC_ AT_ AT_ D_C
BB
EN MIS MOS LK
O I
Type RW RW RW RW RW
ED

Reset 0 0 0 0 0

Bit(s) Name Description

5 RG_SMT_XOSC_E SMT
M

N 0: Disable
1: Enable
4 RG_SMT_ENBB SMT
0: Disable
1: Enable
2 RG_SMT_AUD_DA SMT
T_MISO 0: Disable

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Bit(s) Name Description

1: Enable
1 RG_SMT_AUD_DA SMT

AL
T_MOSI 0: Disable
1: Enable
0 RG_SMT_AUD_CL SMT
K 0: Disable

TI
1: Enable

EN
022C DRV_CON0 DRV_CON0 CCCC
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RG_OCTL_RTC_32K1V RG_OCTL_RTC_32K1V RG_OCTL_SRCLKEN_I RG_OCTL_SRCLKEN_I
Name 8_1 8_0 N1 N0
Type RW RW RW RW
Reset

Bit(s)
1

Name
1 0 0 1 1

Description
0 0

ID 1 1 0 0 1 1 0 0
NF
15:12 RG_OCTL_RTC_32 OC CTL
K1V8_1
11:8 RG_OCTL_RTC_32 OC CTL
K1V8_0
7:4 RG_OCTL_SRCLKE OC CTL
CO

N_IN1
3:0 RG_OCTL_SRCLKE OC CTL
N_IN0
K

022E DRV_CON1 DRV_CON1 CCCC

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TE

Name RG_OCTL_SPI_MISO RG_OCTL_SPI_MOSI RG_OCTL_SPI_CSN RG_OCTL_SPI_CLK

Type RW RW RW RW
Reset 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0

Bit(s) Name Description

15:12 RG_OCTL_SPI_MI OC CTL

SO
11:8 RG_OCTL_SPI_MO OC CTL
ED

SI
7:4 RG_OCTL_SPI_CS OC CTL
N
3:0 RG_OCTL_SPI_CL OC CTL
K
M

0230 DRV_CON2 DRV_CON2 0CCC

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RG_OCTL_AUD_DAT RG_OCTL_AUD_DAT
Name RG_OCTL_AUD_CLK
_MISO _MOSI

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Type RW RW RW
Reset 1 1 0 0 1 1 0 0 1 1 0 0

AL
Bit(s) Name Description
11:8 RG_OCTL_AUD_C OC CTL
LK
7:4 RG_OCTL_AUD_D OC CTL

TI
AT_MISO
3:0 RG_OCTL_AUD_D OC CTL
AT_MOSI

EN
0232 DRV_CON3 DRV_CON3 0CCC
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
Type
Reset
RG_OCTL_XOSC_EN

1 1
RW
0 0
ID 1
RG_OCTL_ENBB

1
RW
0 0
RG_OCTL_HOMEKEY

1 1
RW
0 0
NF
Bit(s) Name Description
11:8 RG_OCTL_XOSC_E OC CTL
N
7:4 RG_OCTL_ENBB OC CTL
CO

3:0 RG_OCTL_HOMEK OC CTL

TOP_STATU
0234 TOP_STATUS 0000
K

S
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name TOP_STATUS
TE

Type RW
Reset 0 0 0 0

Bit(s) Name Description

3:0 TOP_STATUS
ED

RGS_ANA_
023A RGS_ANA_MON 0000
MON
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RGS RGS RGS RGS
M

_VS _VC _VL _VP

YS22 ORE TE_ ROC
_EN 1_E ENP _EN
Name
PW NPW WM PW
M_S M_S _ST M_S
TAT TAT ATU TAT
US US S US
Type RO RO RO RO
Reset 0 0 0 0

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Bit(s) Name Description

AL
3 RGS_VSYS22_ENP ENPWM status
WM_STATUS H: PWM mode
L: PFM mode
2 RGS_VCORE1_ENP
WM_STATUS

TI
1 RGS_VLTE_ENPW
M_STATUS
0 RGS_VPROC_ENP ENPWM status
WM_STATUS H: PWM mode

EN
L: PFM mode

023C

Bit 15
RG_
TOP_CKPDN
_CON0
14
RG_
13 12
TOP_CKPDN Control Register 0

RG_
11 10
RG_
9
RG_
ID
RG_
8
RG_
7
RG_
6
RG_
5 4
RG_
RG_
3 2
RG_
1
RG_
DEFC

0
RG_
NF
RG_ RG_ AUX AUX AUX AUX DRV DRV DRV DRV G_S G_S
ZCD AUD DRV G_D
AUD AUD ADC ADC ADC ADC _ISI _ISI _ISI _ISI MPS MPS
13M NCP _32 RV_
Name _CK
_CK IF_C
_CK
_26 _RN _SM _1M NK3 NK2 NK1 NK0
K_C 2M_
_AU _PD
_PD K_P M_C G_C PS_ _CK _CK _CK _CK _CK D_C _CK
_PD _PD K_P CK_
N DN K_P K_P CK_ _PD _PD _PD _PD _PD K_P _PD
N N DN PDN
DN DN PDN N N N N N DN N
CO

Type RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Reset 1 1 0 1 1 1 1 0 1 1 1 1 1 1 0 0

Bit(s) Name Description

15 RG_ZCD13M_CK_P Powers down ZCD13M_CK
DN 0: Power on
K

1: Power down
14 RG_AUD_CK_PDN Powers down AUD_CK
TE

0: Power on
1: Power down
13 RG_AUDIF_CK_PD Powers down AUDIF_CK
N 0: Power on
1: Power down
IA

12 RG_AUDNCP_CK_ Powers down AUDNCP_CK

PDN 0: Power on
1: Power down
ED

11 RG_AUXADC_26M Powers down AUXADC_26M_CK

_CK_PDN 0: Power on
1: Power down
10 RG_AUXADC_RNG Powers down AUXADC_RNG_CK
_CK_PDN 0: Power on
M

1: Power down
9 RG_AUXADC_SMP Powers down AUXADC_SMPS_CK
S_CK_PDN 0: Power on
1: Power down
8 RG_AUXADC_1M_ Powers down AUXADC_1M_CK
CK_PDN 0: Power on
1: Power down

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Bit(s) Name Description

7 RG_DRV_ISINK3_ Powers down DRV_ISINK3_CK
CK_PDN 0: Power on

AL
1: Power down
6 RG_DRV_ISINK2_ Powers down DRV_ISINK2_CK
CK_PDN 0: Power on
1: Power down

TI
5 RG_DRV_ISINK1_ Powers down DRV_ISINK1_CK
CK_PDN 0: Power on
1: Power down
4 RG_DRV_ISINK0_ Powers down DRV_ISINK0_CK

EN
CK_PDN 0: Power on
1: Power down
3 RG_DRV_32K_CK_ Powers down DRV_32K_CK
PDN 0: Power on
1: Power down
2 RG_G_DRV_2M_C
K_PDN
Powers down G_DRV_2M_CK
0: Power on
1: Power down
ID
NF
1 RG_G_SMPS_AUD Powers down G_SMPS_AUD_CK
_CK_PDN 0: Power on
1: Power down
0 RG_G_SMPS_PD_ Powers down G_SMPS_PD_CK
CK_PDN 0: Power on
CO

1: Power down

TOP_CKPDN
023E TOP_CKPDN_CON0 Register SET 0000
_CON0_SET
K

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name TOP_CKPDN_CON0_SET
TE

Type W1
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit(s) Name Description

15:0 TOP_CKPDN_CON Sets up TOP_CKPDN_CON0

0_SET 1'b0: Does not set
1'b1: Set
ED

TOP_CKPDN
0240 TOP_CKPDN_CON0 Register CLR 0000
_CON0_CLR
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M

Name TOP_CKPDN_CON0_CLR
Type W1
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit(s) Name Description

15:0 TOP_CKPDN_CON Clears TOP_CKPDN_CON0
0_CLR 1'b0: Does not clear

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Bit(s) Name Description

1'b1: Clear

AL
TOP_CKPDN
0242 TOP_CKPDN Control Register 1 04A0
_CON1

TI
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RG_
RG_ RG_ RG_
RG_ RG_ RG_ RTC RG_ RG_ RG_
PW RG_ RTC RTC RG_
AUX BUC STB _2SE RTC RTC RTC
MOC FQM 32K 32K RTC
ADC K_1 _1M C_O DET _75K _32

EN
Name _6M
_CK M_C _CK
TR_
FF_
_1V8 _1V8
_CK _CK
_MC
K_C
_CK CK_ _1_ _0_ LK_
_PD K_P _PD DET _PD _PD K_P
_PD PDN O_P O_P PDN
N DN N _PD N N DN
N DN DN
N
Type RW RW RW RW RW RW RW RW RW RW RW RW
Reset 0 1 0 0 1 0 1 0 0 0 0 0

Bit(s)
11
Name
RG_PWMOC_6M_
Description
Powers down PWMOC_6M_CK
ID
NF
CK_PDN 0: Power on
1: Power down
10 RG_AUXADC_CK_ Powers down AUXADC_CK
PDN 0: Power on
CO

1: Power down
9 RG_BUCK_1M_CK Powers down BUCK_1M_CK
_PDN 0: Power on
1: Power down
8 RG_STB_1M_CK_P Powers down STB_1M_CK
DN 0: Power on
K

1: Power down
7 RG_FQMTR_CK_P Powers down FQMTR_CK
DN 0: Power on
TE

1: Power down
6 RG_RTC_2SEC_OF Powers down RTC_2SEC_OFF_DET
F_DET_PDN 0: Power on
1: Power down
IA

5 RG_RTC32K_1V8_1 Powers down RTC32K_1V8_1_O

_O_PDN 0: Power on
1: Power down
4 RG_RTC32K_1V8_ Powers down RTC32K_1V8_0_O
ED

0_O_PDN 0: Power on
1: Power down
3 RG_RTCDET_CK_P Powers down RTCDET_CK
DN 0: Power on
1: Power down
M

2 RG_RTC_75K_CK_ Powers down RTC_75K_CK

PDN 0: Power on
1: Power down
1 RG_RTC_MCLK_P Powers down RTC_MCLK
DN 0: Power on
1: Power down

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Bit(s) Name Description

0 RG_RTC_32K_CK_ Powers down RTC_32K_CK
PDN 0: Power on

AL
1: Power down

TI
TOP_CKPDN
0244 TOP_CKPDN_CON1 Register SET 0000
_CON1_SET
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name TOP_CKPDN_CON1_SET

EN
Type W1
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit(s) Name Description

15:0 TOP_CKPDN_CON1
_SET
Sets up TOP_CKPDN_CON1
1'b0: Does not set
1'b1: Set ID
NF
TOP_CKPDN
0246 TOP_CKPDN_CON1 Register CLR 0000
_CON1_CLR
CO

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name TOP_CKPDN_CON1_CLR
Type W1
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit(s) Name Description

15:0 TOP_CKPDN_CON1 Clears TOP_CKPDN_CON1

_CLR 1'b0: Does not clear
1'b1: Clear
TE

TOP_CKPDN
0248 TOP_CKPDN Control Register 2 167F
IA

_CON2
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RG_
RG_ RG_ RG_ RG_
STR RG_ RG_ RG_ RG_ RG_
RTC RG_ FQM RG_ RG_ RG_ FGA FGA RG_
ED

UP_ TRI RTC ACC PCH SPK

_EO INT TR_ BIF_ BIF_ BIF_ DC_ DC_ SPK
Name LBA M_7
SC32
_26
RP_ 32K
DET R_3
X1_ X4_ X72_ DIG ANA
_PW
_CK
T_S 5K_ M_C _CK 2K_ M_C
_CK CK_ _CK CK_ CK_ CK_ _CK _CK _PD
EL_ CK_ K_P _PD CK_ K_P
_PD PDN _PD PDN PDN PDN _PD _PD N
CK_ PDN DN N PDN DN
N N N N
PDN
M

Type RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Reset 0 0 0 1 0 1 1 0 1 1 1 1 1 1 1

Bit(s) Name Description

15 RG_STRUP_LBAT_ Powers down STRUP_LBAT_SEL_CK
SEL_CK_PDN 0: Power on
1: Power down

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Bit(s) Name Description

RG_TRIM_75K_CK Powers down TRIM_75K_CK
14 _PDN 0: Power on

AL
1: Power down
RG_RTC_EOSC32_ Powers down RTC_EOSC32_CK
13 CK_PDN 0: Power on
1: Power down

TI
RG_RTC_26M_CK Powers down RTC_26M_CK
12 _PDN 0: Power on
1: Power down
RG_INTRP_CK_PD Powers down INTRP_CK

EN
11 N 0: Power on
1: Power down
RG_FQMTR_32K_ Powers down FQMTR_32K_CK
10 CK_PDN 0: Power on
1: Power down

9
RG_ACCDET_CK_P
DN
Powers down ACCDET_CK
0: Power on
1: Power down
ID
NF
RG_PCHR_32K_CK Powers down PCHR_32K_CK
7 _PDN 0: Power on
1: Power down
RG_BIF_X1_CK_P Powers down BIF_X1_CK
6 DN 0: Power on
CO

1: Power down
RG_BIF_X4_CK_P Powers down BIF_X4_CK
5 DN 0: Power on
1: Power down
RG_BIF_X72_CK_ Powers down BIF_X72_CK
4 PDN 0: Power on
K

1: Power down
RG_FGADC_DIG_C Powers down FGADC_DIG_CK
TE

3 K_PDN 0: Power on
1: Power down
RG_FGADC_ANA_ Powers down FGADC_ANA_CK
2 CK_PDN 0: Power on
1: Power down
IA

RG_SPK_PWM_CK Powers down SPK_PWM_CK

1 _PDN 0: Power on
1: Power down
ED

RG_SPK_CK_PDN Powers down SPK_CK

0 0: Power on
1: Power down
M

TOP_CKPDN
024A TOP_CKPDN_CON2 Register SET 0000
_CON2_SET
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name TOP_CKPDN_CON2_SET
Type W1
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

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Bit(s) Name Description

15:0 TOP_CKPDN_CON Sets up TOP_CKPDN_CON2
2_SET 1'b0: Does not set

AL
1'b1: Set

TI
TOP_CKPDN
024C TOP_CKPDN_CON2 Register CLR 0000
_CON2_CLR
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name TOP_CKPDN_CON2_CLR

EN
Type W1
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit(s) Name Description

15:0 TOP_CKPDN_CON
2_CLR
Clears TOP_CKPDN_CON2
1'b0:
1'b1: Clear
Does
ID not clear
NF
TOP_CKPDN
024E TOP_CKPDN control register 3 05E0
_CON3
CO

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RG_
RG_ RG_
EOS RG_ RG_ RG_ RG_ RG_ RG_
PCH RG_ STR
C_C BUC BUC FGA BGR RG_ SMP STR
R_T EFU UP_
ALI_ K_A K_3 DC_ _TE SPI_ S_C UP_
Name TES NA_ 2K_
EST
FT_ ST_ CK_ K_D
SE_ 32K
75K_
_CK CK_ _CK
T_C CK_ CK_ CK_ CK_ PDN IV_P CK_
_PD PDN _PD
K_P PDN PDN PDN PDN DN PDN
K

N N
DN
Type RW RW RW RW RW RW RW RW RW RW RW
Reset 1 0 1 1 1 1 0 0 0 0 0
TE

Bit(s) Name Description

10 RG_EOSC_CALI_T Powers down EOSC_CALI_TEST_CK
EST_CK_PDN 0: Power on
IA

1: Power down
9 RG_BUCK_ANA_C Powers down BUCK_ANA_CK
K_PDN 0: Power on
1: Power down
ED

8 RG_BUCK_32K_CK Powers down BUCK_32K_CK

_PDN 0: Power on
1: Power down
7 RG_PCHR_TEST_C Powers down PCHR_TEST_CK
M

K_PDN 0: Power on
1: Power down
6 RG_FGADC_FT_CK Powers down FGADC_FT_CK
_PDN 0: Power on
1: Power down
5 RG_BGR_TEST_CK Powers down BGR_TEST_CK
_PDN 0: Power on

MediaTek Confidential © 2015 MediaTek Inc. Page 92 of 304

Bit(s) Name Description

1: Power down
4 RG_SPI_CK_PDN Powers down SPI_CK

AL
0: Power on
1: Power down
3 RG_SMPS_CK_DIV Powers down SMPS_CK_DIV
_PDN 0: Power on

TI
1: Power down
2 RG_EFUSE_CK_PD Powers down EFUSE_CK
N 0: Power on
1: Power down

EN
1 RG_STRUP_32K_C Powers down STRUP_32K_CK
K_PDN 0: Power on
1: Power down
0 RG_STRUP_75K_C Powers down STRUP_75K_CK
K_PDN 0: Power on
1: Power down
ID
NF
TOP_CKPDN
0250 TOP_CKPDN_CON3 Register SET 0000
_CON3_SET
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name TOP_CKPDN_CON3_SET
CO

Type W1
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit(s) Name Description

15:0 TOP_CKPDN_CON Sets up TOP_CKPDN_CON3
K

3_SET 1'b0: Does not set

1'b1: Set
TE

TOP_CKPDN
0252 TOP_CKPDN_CON3 Register CLR 0000
_CON3_CLR
IA

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name TOP_CKPDN_CON3_CLR
Type W1
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ED

Bit(s) Name Description

15:0 TOP_CKPDN_CON Clears TOP_CKPDN_CON3
3_CLR 1'b0: Does not clear
1'b1: Clear
M

TOP_CKPDN
0254 TOP_CKPDN control register 4 0000
_CON4
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RG_ RG_ RG_ RG_ RG_ RG_ RG_

MediaTek Confidential © 2015 MediaTek Inc. Page 93 of 304

BUC BUC BUC BUC BUC BUC BUC

K_V K_V K_V K_V K_V K_V K_18
PRO COR SYS2 LTE PA_1 SRA M_C
C_18 E1_1 2_18 _18 8M_ M_1 K_P

AL
M_C 8M_ M_C M_C CK_ 8M_ DN
K_P CK_ K_P K_P PDN CK_
DN PDN DN DN PDN
Type RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0

TI
Bit(s) Name Description
6 RG_BUCK_VPROC Powers down BUCK_VPROC_18M_CK
_18M_CK_PDN 0: Power on

EN
1: Power down
5 RG_BUCK_VCORE1 Powers down BUCK_VCORE1_18M_CK
_18M_CK_PDN 0: Power on
1: Power down
4

3
RG_BUCK_VSYS22
_18M_CK_PDN

RG_BUCK_VLTE_1
0: Power on
1: Power down
Powers down BUCK_VLTE_18M_CK
ID
Powers down BUCK_VSYS22_18M_CK
NF
8M_CK_PDN 0: Power on
1: Power down
2 RG_BUCK_VPA_18 Powers down BUCK_VPA_18M_CK
M_CK_PDN 0: Power on
1: Power down
CO

1 RG_BUCK_VSRAM Powers down BUCK_VSRAM_18M_CK

_18M_CK_PDN 0: Power on
1: Power down
0 RG_BUCK_18M_C Powers down BUCK_18M_CK
K_PDN 0: Power on
K

1: Power down
TE

TOP_CKPDN
0256 TOP_CKPDN_CON4 Register SET 0000
_CON4_SET
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IA

Name TOP_CKPDN_CON4_SET
Type W1
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ED

Bit(s) Name Description

15:0 TOP_CKPDN_CON Sets up TOP_CKPDN_CON4
4_SET 1'b0: Does not set
1'b1: Set
M

TOP_CKPDN
0258 TOP_CKPDN_CON4 Register CLR 0000
_CON4_CLR
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name TOP_CKPDN_CON4_CLR
Type W1

MediaTek Confidential © 2015 MediaTek Inc. Page 94 of 304

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit(s) Name Description

AL
15:0 TOP_CKPDN_CON Clears TOP_CKPDN_CON4
4_CLR 1'b0: Does not clear
1'b1: Clear

TI
TOP_CKSEL
025A TOP_CKSEL Control Register 0 0000
_CON0

EN
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RG_ RG_ RG_ RG_
RG_ RG_
RG_ DRV DRV DRV DRV RG_
AUX AUD
RG_SRCLK RG_OSC_S 75K_ _ISI _ISI _ISI _ISI AUD
ADC RG_FQMTR_CK_ IF_C
Name EN_SRC_S EL_HW_S _CK
32K
CKSEL
NK3 NK2 NK1 NK0 _CK
K_C

Type
Reset 0
EL

RW
0
RC_SEL

0
RW
0
_CK
SEL
RW
0
_SE
L

RW
0 0
ID
RW
0 0
_CK
_CK
SEL
RW
0
_CK
_CK
SEL
RW
0
_CK _CK _CK
_CK _CK SEL
SEL SEL
RW
0
RW
0
RW
0
KSE
L
RW
0
NF
Bit(s) Name Description
15:14 RG_SRCLKEN_SRC Selects srclken source
_SEL 2'b00: From srclken0
CO

2'b01: From srclken1

2'b10: From srclken0 and srclken1
2'b11: Reserved
13:12 RG_OSC_SEL_HW Selects OSC_SEL source under hardware control
_SRC_SEL 2'b00: From buck controller
2'b01: From srclken
K

2'b10: Reserved
2'b11: Reserved
10 RG_AUXADC_CK_ Selects AUXADC_CK clock
TE

CKSEL 1'b0: R_SMPS_CK/n

1'b1: R_AUD26_CK/n
9 RG_75K_32K_SEL Selects RTC_32K1V8_CK clock
1'b0: R_PMU75K_CK/2
IA

1'b1: R_RTC32K_CK
8:6 RG_FQMTR_CK_C Selects FQMTR_CK clock
KSEL 3'b000: R_AUD_26M_CK
3'b001: R_XOSC32_CK_DETECTION
ED

3'b010: R_EOSC32_CK
3'b011: R_RTC32K_CK
3'b100: R_SMPS_CK
3'b101: R_RTC_TICK_SEC
3'b11x: R_PMU75K_CK
5 Selects DRV_ISINK3_CK clock
M

RG_DRV_ISINK3_
CK_CKSEL 1'b0: R_RTC32K_CK
1'b1: G_DRV_2M_CK
4 RG_DRV_ISINK2_ Selects DRV_ISINK2_CK clock
CK_CKSEL 1'b0: R_RTC32K_CK
1'b1: G_DRV_2M_CK
3 RG_DRV_ISINK1_ Selects DRV_ISINK1_CK clock
CK_CKSEL 1'b0: R_RTC32K_CK

MediaTek Confidential © 2015 MediaTek Inc. Page 95 of 304

Bit(s) Name Description

1'b1: G_DRV_2M_CK
2 RG_DRV_ISINK0_ Selects DRV_ISINK0_CK clock

AL
CK_CKSEL 1'b0: R_RTC32K_CK
1'b1: G_DRV_2M_CK
1 RG_AUD_CK_CKS Selects AUD_CK clock
EL 1'b0: R_AUD_26M_CK

TI
1'b1: R_PAD_AUDIF_CK
0 RG_AUDIF_CK_CK Selects AUDIF_CK clock
SEL 1'b0: R_PAD_AUDIF_CK
1'b1: R_AUD_26M_CK

EN
TOP_CKSEL
025C TOP_CKSEL_CON0 Register SET 0000
_CON0_SET
Bit
Name
Type
Reset
15

0
14

0
13

0
12

0
11

0
10

0
9
ID 8
TOP_CKSEL_CON_SET

0 0
W1
0 0
7 6 5

0
4

0
3

0
2

0
1

0
0

0
NF
Bit(s) Name Description
15:0 TOP_CKSEL_CON_ Sets up TOP_CKSEL_CON0
SET
CO

1'b0: Does not set

1'b1: Set

TOP_CKSEL
025E TOP_CKSEL_CON0 Register CLR 0000
K

_CON0_CLR
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name TOP_CKSEL_CON_CLR
TE

Type W1
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit(s) Name Description

15:0 TOP_CKSEL_CON_ Clears TOP_CKSEL_CON0

CLR 1'b0: Does not clear
1'b1: Clear
ED

TOP_CKSEL
0260 TOP_CKSEL control register 1 0000
_CON1
M

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RG_ RG_ RG_
FGA PCH BGR
DC_ R_T _TE RG_STRUP
Name ANA EST ST_ _75K_CK_
_CK _CK CK_ CKSEL
_CK _CK CKS
SEL SEL EL
Type RW RW RW RW

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Reset 0 0 0 0 0

Bit(s) Name Description

AL
4 RG_FGADC_ANA_ Selects FGADC_ANA_CK clock
CK_CKSEL 1'b0: R_RTC32K_CK
1'b1: FGADC_FT_CK_DIV8
3 RG_PCHR_TEST_C Selects PCHR_TEST_CK clock

TI
K_CKSEL 1'b0: R_AUD_26M_CK
1'b1: R_SMPS_CK
2 RG_BGR_TEST_CK Selects BGR_TEST_CK clock
_CKSEL 1'b0: R_AUD_26M_CK

EN
1'b1: R_SMPS_CK
1:0 RG_STRUP_75K_C Selects STRUP_75K_CK clock
K_CKSEL 2'b00: R_PMU75K_CK
2'b01: R_AUD_26M_CK
2'b1x: R_SMPS_CK

ID
NF
TOP_CKSEL
0262 TOP_CKSEL_CON1 Register SET 0000
_CON1_SET
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Nam
TOP_CKSEL_CON1_SET
e
CO

Type W1
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit(s) Name Description

15:0 TOP_CKSEL_CON1 Sets up TOP_CKSEL_CON1
_SET
K

1'b0: Does not set

1'b1: Set
TE

TOP_CKSEL
0264 TOP_CKSEL_CON1 Register CLR 0000
_CON1_CLR
IA

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name TOP_CKSEL_CON1_CLR
Type W1
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ED

Bit(s) Name Description

15:0 TOP_CKSEL_CON1 Clears TOP_CKSEL_CON1
_CLR 1'b0: Does not clear
1'b1: Clear
M

TOP_CKSEL
0266 TOP_CKSEL Control Register 2 0000
_CON2
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name TOP RG_ RG_ RG_ RG_ RG_ RG_

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_CK VCO BUC SRC VCO BUC SRC

SEL RE2 K_O VOL RE2 K_O VOL
_CO _OS SC_ TEN _OS SC_ TEN
N2_ C_S SEL _MO C_S SEL _SW

AL
RSV EL_ _MO DE EL_ _SW
MOD DE SW
E
Type RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0

TI
Bit(s) Name Description
9 TOP_CKSEL_CON2
_RSV

EN
7 RG_VCORE2_OSC_ VCORE2_OSC_SEL mode
SEL_MODE 1'b0: HW mode
1'b1: SW mode
6 RG_BUCK_OSC_SE BUCK_OSC_SEL mode

4
L_MODE

RG_SRCVOLTEN_
MODE
1'b0: HW mode
1'b1: SW mode
SRCVOLTEN mode
1'b0: HW mode
ID
NF
1'b1: SW mode
3 RG_VCORE2_OSC_ VCORE2_OSC_SEL SW mode value
SEL_SW
2 RG_BUCK_OSC_SE BUCK_OSC_SEL SW mode value
L_SW
CO

0 RG_SRCVOLTEN_S SRCVOLTEN SW mode value

W
K

TOP_CKSEL
0268 TOP_CKSEL_CON2 Register SET 0000
_CON2_SET
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TE

Name TOP_CKSEL_CON2_SET
Type W1
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IA

Bit(s) Name Description

15:0 TOP_CKSEL_CON2 Sets up TOP_CKSEL_CON2
_SET 1'b0: Does not set
1'b1: Set
ED

TOP_CKSEL
026A TOP_CKSEL_CON2 Register CLR 0000
_CON2_CLR
M

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name TOP_CKSEL_CON2_CLR
Type W1
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit(s) Name Description

MediaTek Confidential © 2015 MediaTek Inc. Page 98 of 304

Bit(s) Name Description

15:0 TOP_CKSEL_CON2 Clears TOP_CKSEL_CON2
_CLR 1'b0: Does not clear

AL
1'b1: Clear

TI
TOP_CKDIV
026C TOP_CKDIVSEL Control Register 0 0001
SEL_CON0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RG_STRUP

EN
RG_SPK_P RG_REG_
RG_SPK_C RG_BIF_X4_CK_ _LBAT_SE
Name WM_CK_D K_DIVSEL CK_DIVSE
DIVSEL L_CK_DIV
IVSEL L
SEL
Type RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 1

Bit(s)
15:14
Name
RG_SPK_PWM_CK
_DIVSEL
Description
Selects SPK_PWM_CK divider
2'b00: DIV1
ID
NF
2'b01: DIV16
2'b10: DIV32
2'b11: DIV64
13:12 RG_SPK_CK_DIVS Selects SPK_CK divider
EL
CO

2'b00: DIV1
2'b01: DIV2
2'b10: DIV4
2'b11: DIV8
9:8 RG_REG_CK_DIVS Selects REG_CK divider
EL 2'b00: DIV1
2'b01: DIV2
K

2'b10: DIV4
2'b11: DIV8
6:4 RG_BIF_X4_CK_D Selects BIF_X4_CK divider
TE

IVSEL 3'b000: DIV1

3'b001: DIV2
3'b010: DIV4
3'b011: DIV8
3'b1xx: DIV16
IA

1:0 RG_STRUP_LBAT_ Selects STRUP_LBAT_SEL_CK divider

SEL_CK_DIVSEL 2'b00: DIV18
2'b01: DIV9
2'b10: DIV4
ED

2'b11: DIV2
M

TOP_CKDIV
026E SEL_CON0_ TOP_CKDIVSEL_CON0 Register SET 0000
SET
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name TOP_CKDIVSEL_CON0_SET
Type W1
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

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Bit(s) Name Description

15:0 TOP_CKDIVSEL_C Sets up TOP_CKDIVSEL_CON0
ON0_SET 1'b0: Does not set

AL
1'b1: Set

TI
TOP_CKDIV
0270 SEL_CON0_ TOP_CKDIVSEL_CON0 Register CLR 0000
CLR
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

EN
Name TOP_CKDIVSEL_CON0_CLR
Type W1
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit(s)
15:0
Name
TOP_CKDIVSEL_C
ON0_CLR
Description
Clears TOP_CKDIVSEL_CON0
1'b0: Does not clear
1'b1: Clear
ID
NF

TOP_CKDIV
0272 TOP_CKDIVSEL Control Register 1 0015
SEL_CON1
CO

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RG_
BUC
RG_AUXA
K_18 RG_AUXA
DC_SMPS_
Name M_C DC_26M_C
CK_DIVSE
K_D K_DIVSEL
L
K

IVSE
L
Type RW RW RW
Reset 1 0 1 0 1
TE

Bit(s) Name Description

4 RG_BUCK_18M_C Selects BUCK_18M_CK divider
K_DIVSEL 1'b0: DIV1
IA

1'b1: DIV2
3:2 RG_AUXADC_26M Selects AUXADC_26M_CK divider
_CK_DIVSEL 2'b00: DIV26
ED

2'b01: DIV13
2'b1x: DIV8
1:0 RG_AUXADC_SMP Selets AUXADC_SMPS_CK divider
S_CK_DIVSEL 2'b00: DIV18
2'b01: DIV9
M

2'b10: DIV6
2'b11: DIV4

MediaTek Confidential © 2015 MediaTek Inc. Page 100 of 304

TOP_CKDIV
0274 SEL_CON1_ TOP_CKDIVSEL_CON1 Register SET 0000
SET

AL
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name TOP_CKDIVSEL_CON1_SET
Type W1
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TI
Bit(s) Name Description
15:0 TOP_CKDIVSEL_C Sets up TOP_CKDIVSEL_CON1
ON1_SET

EN
1'b0: Does not set
1'b1: Set

0276

Bit 15
TOP_CKDIV
SEL_CON1_
CLR
14 13 12 11 10 9
ID
TOP_CKDIVSEL_CON1 Register CLR

8 7 6 5 4 3 2 1
0000

0
NF
Name TOP_CKDIVSEL_CON1_CLR
Type W1
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CO

Bit(s) Name Description

15:0 TOP_CKDIVSEL_C Clears TOP_CKDIVSEL_CON1
ON1_CLR 1'b0: Does not clear
1'b1: Clear
K

TOP_CKHW
0278 TOP_CKHWEN control register 0 30FF
EN_CON0
TE

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RG_ RG_ RG_
RG_ RG_ RG_ RG_ RG_
AUX RG_ AUX RG_ G_S
AUX RTC BUC G_D G_S
ADC EFU ADC AUX MPS
ADC _26 K_1 RV_ MPS
_26 SE_ _SM ADC _AU
IA

_CK M_C M_C 2M_ _PD

Name M_C CK_ PS_ _CK D_C
_CK K_P K_P CK_ _CK
K_P PDN CK_ _PD K_P
SEL DN_ DN_ PDN _PD
DN_ _H PDN N_H DN_
_H HW HW _H N_H
HW WEN _H WEN HW
WEN EN EN WEN WEN
EN WEN EN
ED

Type RW RW RW RW RW RW RW RW RW RW
Reset 0 0 1 1 1 1 1 1 1 1

Bit(s) Name Description

11 RG_AUXADC_CK_ AUXADC_CK clock selection control

CKSEL_HWEN 0: SW mode
1: HW mode
10 RG_AUXADC_26M AUXADC_26m_CK clock selection control
_CK_PDN_HWEN 0: SW mode
1: HW mode
7 RG_RTC_26M_CK RTC_26M_CK power down control

MediaTek Confidential © 2015 MediaTek Inc. Page 101 of 304

Bit(s) Name Description

_PDN_HWEN 0: SW mode
1: HW mode

AL
6 RG_EFUSE_CK_PD EFUSE_CK power down control
N_HWEN 0: SW mode
1: HW mode
5 RG_BUCK_1M_CK BUCK_1M_CK power down control
_PDN_HWEN

TI
0: SW mode
1: HW mode
4 RG_AUXADC_SMP AUXADC_SMPS_CK power down control
S_CK_PDN_HWEN 0: SW mode

EN
1: HW mode
3 RG_AUXADC_CK_ AUXADC_CK power down control
PDN_HWEN 0: SW mode
1: HW mode
2 RG_G_DRV_2M_C G_DRV_2M_CK power down control

1
K_PDN_HWEN

RG_G_SMPS_AUD
_CK_PDN_HWEN
0: SW mode
1: HW mode ID
G_SMPS_AUD_CK power down control
NF
0: SW mode
1: HW mode
0 RG_G_SMPS_PD_ G_SMPS_PD_CK power down control
CK_PDN_HWEN 0: SW mode
1: HW mode
CO

TOP_CKHW
027A EN_CON0_S TOP_CKHWEN_CON0 Register SET 0000
ET
K

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name TOP_CKHWEN_CON0_SET
Type
TE

W1
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit(s) Name Description

15:0 TOP_CKHWEN_CO Sets up TOP_CKHWEN_CON0

N0_SET 1'b0: Does not set
1'b1: Set
ED

TOP_CKHW
027C EN_CON0_C TOP_CKHWEN_CON0 Register CLR 0000
LR
M

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name TOP_CKHWEN_CON0_CLR
Type W1
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit(s) Name Description

15:0 TOP_CKHWEN_CO Clears TOP_CKHWEN_CON0

MediaTek Confidential © 2015 MediaTek Inc. Page 102 of 304

Bit(s) Name Description

N0_CLR 1'b0: Does not clear
1'b1: Clear

AL
TOP_CKHW
027E TOP_CKHWEN control register 1 303F
EN_CON1

TI
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RG_ RG_ RG_ RG_ RG_
RG_
BUC BUC BUC BUC BUC
BUC

EN
K_V K_V K_V K_V K_V
K_V
PRO COR SYS2 LTE SRA
PA_1
C_18 E1_1 2_18 _18 M_1
Name M_C 8M_ M_C M_C
8M_
8M_
CK_
K_P CK_ K_P K_P CK_
PDN
DN_ PDN DN_ DN_ PDN
_H
HW _H HW HW _H

Type
Reset ID EN
RW
1
WEN
RW
1
EN
RW
1
EN
RW
1
WEN
RW
1
WEN
RW
1
NF
Bit(s) Name Description
5 RG_BUCK_VPROC BUCK_VPROC_18M_CK power down control
_18M_CK_PDN_H 0: SW mode
WEN 1: HW mode
CO

4 RG_BUCK_VCORE1 BUCK_VCORE1_18M_CK power down control

_18M_CK_PDN_H 0: SW mode
WEN 1: HW mode
3 RG_BUCK_VSYS22 BUCK_VSYS22_18M_CK power down control
_18M_CK_PDN_H 0: SW mode
WEN 1: HW mode
K

2 RG_BUCK_VLTE_1 BUCK_VLTE_18M_CK power down control

8M_CK_PDN_HW 0: SW mode
EN
TE

1: HW mode
1 RG_BUCK_VPA_18 BUCK_VPA_18M_CK power down control
M_CK_PDN_HWE 0: SW mode
N 1: HW mode
0 RG_BUCK_VSRAM BUCK_VSRAM_18M_CK power down control
IA

_18M_CK_PDN_H 0: SW mode
WEN 1: HW mode
ED

TOP_CKHW
0280 EN_CON1_S TOP_CKHWEN_CON1 Register SET 0000
ET
M

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name TOP_CKHWEN_CON1_SET
Type W1
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit(s) Name Description

15:0 TOP_CKHWEN_CO Sets up TOP_CKHWEN_CON1

MediaTek Confidential © 2015 MediaTek Inc. Page 103 of 304

Bit(s) Name Description

N1_SET 1'b0: Does not set
1'b1: Set

AL
TOP_CKHW
0282 EN_CON1_C TOP_CKHWEN_CON1 Register CLR 0000

TI
LR
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name TOP_CKHWEN_CON1_CLR

EN
Type W1
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit(s) Name Description

15:0
TOP_CKHWEN_CO
N1_CLR
Clears TOP_CKHWEN_CON1
1'b0: Does not clear
1'b1: Clear ID
NF
028A TOP_CLKSQ TOP_CLKSQ Register 0000
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RG_ RG_
CO

RG_
DA_ CLK CLK RG_ RG_
CLK RG_ RG_
CLK SQ_ SQ_ CLK CLK
SQ_ CLK CLK
SQ_ EN_ EN_ SQ_ SQ_
Name EN_ SQ_ SQ_
EN_ AUX AUX EN_ EN_
AUX EN_ EN_
VA2 _MD _AP AUX AUX
_GP FQR AUD
8 _MO _MO _MD _AP
S
DE DE
K

Type RO RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
TE

Bit(s) Name Description

15 DA_CLKSQ_EN_V Status of CLKSQ
A28 0: Disable
1: Enable
IA

9 RG_CLKSQ_EN_A Selects CLKSQ_EN_AUX_MD mode

UX_MD_MODE 0: SW mode
1: HW mode: SRCLKEN_IN0
8 RG_CLKSQ_EN_A Selects CLKSQ_EN_AUX_AP mode
ED

UX_AP_MODE 0: SW mode
1: HW mode: SRCLKEN_IN0
4 RG_CLKSQ_EN_A Enables CLKSQ for GPS
UX_GPS 0: Disable clock
M

1: Enable clock
3 RG_CLKSQ_EN_A Enables CLKSQ for MD (SW mode)
UX_MD 0: Disable clock
1: Enable clock
2 RG_CLKSQ_EN_A Enables CLKSQ for AP (SW mode)
UX_AP 0: Disable clock
1: Enable clock

MediaTek Confidential © 2015 MediaTek Inc. Page 104 of 304

Bit(s) Name Description

1 RG_CLKSQ_EN_F Enables CLKSQ for FQMTR
QR 0: Disable clock

AL
1: Enable clock
0 RG_CLKSQ_EN_A Enables CLKSQ for AUDIO
UD 0: Disable clock
1: Enable clock

TI
TOP_CLKSQ

EN
028C TOP_CLKSQ Register SET 0000
_SET
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name TOP_CLKSQ_SET
Type W1
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit(s)
15:0
Name
TOP_CLKSQ_SET
Description
Sets up TOP_CLKSQ
ID
NF
1'b0: Does not set
1'b1: Set
CO

TOP_CLKSQ
028E TOP_CLKSQ Register CLR 0000
_CLR
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name TOP_CLKSQ_CLR
Type W1
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
K

Bit(s) Name Description

15:0 TOP_CLKSQ_CLR Clears TOP_CLKSQ

1'b0: Does not clear
1'b1: Clear
IA

TOP_CLKSQ
0290 TOP_CLKSQ_RTC Register 0002
_RTC
ED

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RG_
CLK
DA_
SQ_ RG_
CLK
RTC CLK
SQ_
M

Name EN_
_EN SQ_
_H RTC
VDI
W_ _EN
G18
MOD
E
Type RO RW RW
Reset 0 1 0

MediaTek Confidential © 2015 MediaTek Inc. Page 105 of 304

Bit(s) Name Description

15 DA_CLKSQ_EN_V Status of CLKSQ_RTC
DIG18 0: Disable

AL
1: Enable
1 RG_CLKSQ_RTC_E CLKSQ_RTC HW mode
N_HW_MODE If enable, CLKSQ_RTC will be from HW control; if disable, CLKSQ_RTC will
be from RG_CLKSQ_RTC_EN.
0: SW mode

TI
1: HW mode
0 RG_CLKSQ_RTC_E Enables CLKSQ_RTC
N 0: Disable clock

EN
1: Enable clock

TOP_CLKSQ
0292

Bit
Name
Type
15
_RTC_SET
14 13 12
TOP_CLKSQ_RTC Register SET

11 10 9 ID 8
TOP_CLKSQ_RTC_SET
W1
7 6 5 4 3 2 1
0000

0
NF
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit(s) Name Description

15:0 TOP_CLKSQ_RTC_ Sets up TOP_CLKSQ_RTC
CO

SET 1'b0: Does not set

1'b1: Set

TOP_CLKSQ
K

0294 TOP_CLKSQ_RTC Register CLR 0000

_RTC_CLR
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TE

Name TOP_CLKSQ_RTC_CLR
Type W1
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit(s) Name Description

15:0 TOP_CLKSQ_RTC_ Clears TOP_CLKSQ_RTC

CLR 1'b0: Does not clear
1'b1: Clear
ED

TOP_CLK_T
0296 TOP_CLK_TRIM Register 0C6C
RIM
M

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RG_OSC_75K_TRIM
Type RO
Reset 0 1 1 0 0

Bit(s) Name Description

MediaTek Confidential © 2015 MediaTek Inc. Page 106 of 304

Bit(s) Name Description

12:8 RG_OSC_75K_TRI 75kHz OSC trimming bit
M

AL
BUCK_ALL_
0418 Buck All Control Register 18 0000

TI
CON18
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VSY VCO VLT VPR
VPA
S22_ RE1 E_O OC_
_OC

EN
OC_ _OC C_F OC_
Name _FL
FLA _FL LAG FLA
AG_
G_C AG_ _CL G_C
CLR
LR CLR R LR
Type RW RW RW RW RW
Reset 0 0 0 0 0

Bit(s)
4
Name
VPA_OC_FLAG_CL
Description
0: Keep OC status
ID
NF
R 1: Clear OC status
3 VSYS22_OC_FLAG 0: Keep OC status
_CLR 1: Clear OC status
2 VCORE1_OC_FLAG 0: Keep OC status
CO

_CLR 1: Clear OC status

1 VLTE_OC_FLAG_C 0: Keep OC status
LR 1: Clear OC status
0 VPROC_OC_FLAG_ 0: Keep OC status
CLR 1: Clear OC status
K
TE

BUCK_ALL_
041A Buck All Control Register 19 0000
CON19
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VCO
VPA VSY VLT VPR
RE1
_OC S22_ E_O OC_
IA

_OC
_FL OC_ C_F OC_
_FL
Name AG_ FLA LAG FLA
AG_
CLR G_C _CL G_C
CLR
_SE LR_ R_S LR_
_SE
L SEL EL SEL
ED

L
Type RW RW RW RW RW
Reset 0 0 0 0 0

Bit(s) Name Description

4 VPA_OC_FLAG_CL 0: HW clear OC status

R_SEL 1: SW clear OC status
3 VSYS22_OC_FLAG 0: HW clear OC status
_CLR_SEL 1: SW clear OC status
2 VCORE1_OC_FLAG 0: HW clear OC status
_CLR_SEL 1: SW clear OC status

MediaTek Confidential © 2015 MediaTek Inc. Page 107 of 304

Bit(s) Name Description

1 VLTE_OC_FLAG_C 0: HW clear OC status
LR_SEL 1: SW clear OC status

AL
0 VPROC_OC_FLAG_ 0: HW clear OC status
CLR_SEL 1: SW clear OC status

TI
BUCK_ALL_
0420 Buck All Control Register 22 0000
CON22

EN
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VSY VCO VPR
VPA VLT
S22_ RE1 OC_
_EN E_E
EN_ _EN EN_
_OC N_O
Name OC_ _OC OC_
_SD C_S
SDN _SD SDN
N_S DN_

Type
Reset
ID EL
RW
0
_SE
L
RW
0
N_S
EL
RW
0
SEL
RW
0
_SE
L
RW
0
NF
Bit(s) Name Description
4 VPA_EN_OC_SDN 0: Enable OC shut-down
_SEL 1: Disable OC shut-down
CO

3 VSYS22_EN_OC_S 0: Enable OC shut-down

DN_SEL 1: Disable OC shut-down
2 VCORE1_EN_OC_S 0: Enable OC shut-down
DN_SEL 1: Disable OC shut-down
1 VLTE_EN_OC_SD 0: Enable OC shut-down
N_SEL 1: Disable OC shut-down
K

0 VPROC_EN_OC_S 0: Enable OC shut-down

DN_SEL 1: Disable OC shut-down
TE

SMPS_TOP_
042E SMPS_TOP Control Register 0 0000
ANA_CON0
IA

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RG_VPROC_TRIMH RG_SMPS_TESTMODE_B
Type RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ED

Bit(s) Name Description

13:9 RG_VPROC_TRIM Fine-tunes R2R DAC reference
H 11111: Vo offset=+6.25mV
M

11110: Vo offset=+12.5mV
11101: Vo offset=+18.75mV
11100: Vo offset=+25mV
11011: Vo offset=+31.25mV
11010: Vo offset=+37.5mV
11001: Vo offset=+43.75mV
11000: Vo offset=+50mV
10111: Vo offset=+56.25mV

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Bit(s) Name Description

10110: Vo offset=+62.5mV
10101: Vo offset=+68.75mV

AL
10100: Vo offset=+75mV
10011: Vo offset=+81.25mV
10010: Vo offset=+87.5mV
10001: Vo offset=+93.75mV
00000: Vo offset=0mV (default)
00001: Vo offset=-6.25mV

TI
00010: Vo offset=-12.5mV
00011: Vo offset=-18.75mV
00100: Vo offset=-25mV
00101: Vo offset=-31.25mV

EN
00110: Vo offset=-37.5mV
00111: Vo offset=-43.75mV
01000: Vo offset=-50mV
01001: Vo offset=-56.25mV
01010: Vo offset=-62.5mV
01011: Vo offset=-68.75mV
01100: Vo offset=-75mV
01101: Vo offset=-81.25mV
01110: Vo offset=-87.5mV
01111: Vo offset=-93.75mV
ID
NF
10000: Vo offset=-100mV
8:0 RG_SMPS_TESTM Test mode enable bit
ODE_B Default 0: Disable testmode
(Default) NORMAL: 8'b00000000
[0]:
CO

0: VBUF GOOD
1: VBUF not good
[3:1]: N/A
[4] CSM measure from LDO bist
0: No value
1: CSM from LDO bist
[7:5]: CSM measurement selection
K

000: N/A
001: N/A
010: VCORE1
TE

011: VLTE
100: N/A
101: VPROC
110: VSYS22
111: N/A
IA

[8]: Pass CSM signal to KP_LED or AUXADC

0: Disable
1: Enable
ED

SMPS_TOP_
0430 SMPS_TOP control register 1 0000
ANA_CON1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M

Name RG_VCORE1_TRIML RG_VCORE1_TRIMH RG_VPROC_TRIML

Type RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit(s) Name Description

14:10 RG_VCORE1_TRIM Fine-tunes R2R DAC reference
L 11111: Vo offset=+6.25mV

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Bit(s) Name Description

11110: Vo offset=+12.5mV
11101: Vo offset=+18.75mV

AL
11100: Vo offset=+25mV
11011: Vo offset=+31.25mV
11010: Vo offset=+37.5mV
11001: Vo offset=+43.75mV
11000: Vo offset=+50mV
10111: Vo offset=+56.25mV

TI
10110: Vo offset=+62.5mV
10101: Vo offset=+68.75mV
10100: Vo offset=+75mV
10011: Vo offset=+81.25mV

EN
10010: Vo offset=+87.5mV
10001: Vo offset=+93.75mV
00000: Vo offset=0mV (default)
00001: Vo offset=-6.25mV
00010: Vo offset=-12.5mV
00011: Vo offset=-18.75mV
00100: Vo offset=-25mV
00101: Vo offset=-31.25mV
00110: Vo offset=-37.5mV
00111: Vo offset=-43.75mV
ID
NF
01000: Vo offset=-50mV
01001: Vo offset=-56.25mV
01010: Vo offset=-62.5mV
01011: Vo offset=-68.75mV
01100: Vo offset=-75mV
CO

01101: Vo offset=-81.25mV
01110: Vo offset=-87.5mV
01111: Vo offset=-93.75mV
10000: Vo offset=-100mV
9:5 RG_VCORE1_TRIM Fine-tunes R2R DAC reference
H 11111: Vo offset=+6.25mV
11110: Vo offset=+12.5mV
K

11101: Vo offset=+18.75mV
11100: Vo offset=+25mV
11011: Vo offset=+31.25mV
TE

11010: Vo offset=+37.5mV
11001: Vo offset=+43.75mV
11000: Vo offset=+50mV
10111: Vo offset=+56.25mV
10110: Vo offset=+62.5mV
IA

10101: Vo offset=+68.75mV
10100: Vo offset=+75mV
10011: Vo offset=+81.25mV
10010: Vo offset=+87.5mV
10001: Vo offset=+93.75mV
ED

00000: Vo offset=0mV (default)

00001: Vo offset=-6.25mV
00010: Vo offset=-12.5mV
00011: Vo offset=-18.75mV
00100: Vo offset=-25mV
M

00101: Vo offset=-31.25mV
00110: Vo offset=-37.5mV
00111: Vo offset=-43.75mV
01000: Vo offset=-50mV
01001: Vo offset=-56.25mV
01010: Vo offset=-62.5mV
01011: Vo offset=-68.75mV
01100: Vo offset=-75mV
01101: Vo offset=-81.25mV

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Bit(s) Name Description

01110: Vo offset=-87.5mV
01111: Vo offset=-93.75mV

AL
10000: Vo offset=-100mV
4:0 RG_VPROC_TRIM Fine-tunes R2R DAC reference
L 11111: Vo offset=+6.25mV
11110: Vo offset=+12.5mV
11101: Vo offset=+18.75mV

TI
11100: Vo offset=+25mV
11011: Vo offset=+31.25mV
11010: Vo offset=+37.5mV
11001: Vo offset=+43.75mV

EN
11000: Vo offset=+50mV
10111: Vo offset=+56.25mV
10110: Vo offset=+62.5mV
10101: Vo offset=+68.75mV
10100: Vo offset=+75mV
10011: Vo offset=+81.25mV
10010: Vo offset=+87.5mV
10001: Vo offset=+93.75mV
ID
00000: Vo offset=0mV (default)
00001: Vo offset=-6.25mV
NF
00010: Vo offset=-12.5mV
00011: Vo offset=-18.75mV
00100: Vo offset=-25mV
00101: Vo offset=-31.25mV
00110: Vo offset=-37.5mV
00111: Vo offset=-43.75mV
CO

01000: Vo offset=-50mV
01001: Vo offset=-56.25mV
01010: Vo offset=-62.5mV
01011: Vo offset=-68.75mV
01100: Vo offset=-75mV
01101: Vo offset=-81.25mV
01110: Vo offset=-87.5mV
K

01111: Vo offset=-93.75mV
10000: Vo offset=-100mV
TE

SMPS_TOP_
0432 SMPS_TOP control register 2 0000
ANA_CON2
IA

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RG_VSYS22_TRIMH RG_VLTE_TRIML RG_VLTE_TRIMH
Type RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ED

Bit(s) Name Description

13:10 RG_VSYS22_TRIM Fine-tunes R2R DAC reference
H 1111: Vo offset=+6.25mV
M

1110: Vo offset=+12.5mV
1101: Vo offset=+18.75mV
1100: Vo offset=+25mV
1011: Vo offset=+31.25mV
1010: Vo offset=+37.5mV
1001: Vo offset=+43.75mV
0000: Vo offset=0mV (default)
0001: Vo offset=-6.25mV
0010: Vo offset=-12.5mV

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Bit(s) Name Description

0011: Vo offset=-18.75mV
0100: Vo offset=-25mV

AL
0101: Vo offset=-31.25mV
0110: Vo offset=-37.5mV
0111: Vo offset=-43.75mV
1000: Vo offset=-50mV
9:5 RG_VLTE_TRIML Fine-tunes R2R DAC reference

TI
11111: Vo offset=+6.25mV
11110: Vo offset=+12.5mV
11101: Vo offset=+18.75mV
11100: Vo offset=+25mV

EN
11011: Vo offset=+31.25mV
11010: Vo offset=+37.5mV
11001: Vo offset=+43.75mV
11000: Vo offset=+50mV
10111: Vo offset=+56.25mV
10110: Vo offset=+62.5mV
10101: Vo offset=+68.75mV
10100: Vo offset=+75mV
10011: Vo offset=+81.25mV
10010: Vo offset=+87.5mV
ID
NF
10001: Vo offset=+93.75mV
00000: Vo offset=0mV (default)
00001: Vo offset=-6.25mV
00010: Vo offset=-12.5mV
00011: Vo offset=-18.75mV
00100: Vo offset=-25mV
CO

00101: Vo offset=-31.25mV
00110: Vo offset=-37.5mV
00111: Vo offset=-43.75mV
01000: Vo offset=-50mV
01001: Vo offset=-56.25mV
01010: Vo offset=-62.5mV
01011: Vo offset=-68.75mV
K

01100: Vo offset=-75mV
01101: Vo offset=-81.25mV
01110: Vo offset=-87.5mV
TE

01111: Vo offset=-93.75mV
10000: Vo offset=-100mV
4:0 RG_VLTE_TRIMH Fine-tunes R2R DAC reference
11111: Vo offset=+6.25mV
11110: Vo offset=+12.5mV
IA

11101: Vo offset=+18.75mV
11100: Vo offset=+25mV
11011: Vo offset=+31.25mV
11010: Vo offset=+37.5mV
ED

11001: Vo offset=+43.75mV
11000: Vo offset=+50mV
10111: Vo offset=+56.25mV
10110: Vo offset=+62.5mV
10101: Vo offset=+68.75mV
10100: Vo offset=+75mV
M

10011: Vo offset=+81.25mV
10010: Vo offset=+87.5mV
10001: Vo offset=+93.75mV
00000: Vo offset=0mV (default)
00001: Vo offset=-6.25mV
00010: Vo offset=-12.5mV
00011: Vo offset=-18.75mV
00100: Vo offset=-25mV

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Bit(s) Name Description

00101: Vo offset=-31.25mV
00110: Vo offset=-37.5mV

AL
00111: Vo offset=-43.75mV
01000: Vo offset=-50mV
01001: Vo offset=-56.25mV
01010: Vo offset=-62.5mV
01011: Vo offset=-68.75mV
01100: Vo offset=-75mV

TI
01101: Vo offset=-81.25mV
01110: Vo offset=-87.5mV
01111: Vo offset=-93.75mV
10000: Vo offset=-100mV

EN
SMPS_TOP_
0434 SMPS_TOP control register 3 0000

Bit
Name
Type
15
ANA_CON3
14 13 12
RG_VPA_TRIML
RW
11 10 9
ID 8 7
RG_VPA_TRIMH
RW
6 5 4 3 2
RG_VSYS22_TRIML
RW
1 0
NF
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit(s) Name Description

13:9 RG_VPA_TRIML Fine-tunes R2R DAC reference
CO

11111: Vo offset=+6.25mV
11110: Vo offset=+12.5mV
11101: Vo offset=+18.75mV
11100: Vo offset=+25mV
11011: Vo offset=+31.25mV
11010: Vo offset=+37.5mV
11001: Vo offset=+43.75mV
K

11000: Vo offset=+50mV
10111: Vo offset=+56.25mV
10110: Vo offset=+62.5mV
TE

10101: Vo offset=+68.75mV
10100: Vo offset=+75mV
10011: Vo offset=+81.25mV
10010: Vo offset=+87.5mV
10001: Vo offset=+93.75mV
00000: Vo offset=0mV (default)
IA

00001: Vo offset=-6.25mV
00010: Vo offset=-12.5mV
00011: Vo offset=-18.75mV
00100: Vo offset=-25mV
ED

00101: Vo offset=-31.25mV
00110: Vo offset=-37.5mV
00111: Vo offset=-43.75mV
01000: Vo offset=-50mV
01001: Vo offset=-56.25mV
01010: Vo offset=-62.5mV
M

01011: Vo offset=-68.75mV
01100: Vo offset=-75mV
01101: Vo offset=-81.25mV
01110: Vo offset=-87.5mV
01111: Vo offset=-93.75mV
10000: Vo offset=-100mV
8:4 RG_VPA_TRIMH Fine-tunes R2R DAC reference
11111: Vo offset=+6.25mV

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Bit(s) Name Description

11110: Vo offset=+12.5mV
11101: Vo offset=+18.75mV

AL
11100: Vo offset=+25mV
11011: Vo offset=+31.25mV
11010: Vo offset=+37.5mV
11001: Vo offset=+43.75mV
11000: Vo offset=+50mV
10111: Vo offset=+56.25mV

TI
10110: Vo offset=+62.5mV
10101: Vo offset=+68.75mV
10100: Vo offset=+75mV
10011: Vo offset=+81.25mV

01101: Vo offset=-81.25mV
01110: Vo offset=-87.5mV
01111: Vo offset=-93.75mV
10000: Vo offset=-100mV
3:0 RG_VSYS22_TRIM Fine-tunes R2R DAC reference
L 1111: Vo offset=+6.25mV
1110: Vo offset=+12.5mV
K

1101: Vo offset=+18.75mV
1100: Vo offset=+25mV
1011: Vo offset=+31.25mV
TE

1010: Vo offset=+37.5mV
1001: Vo offset=+43.75mV
0000: Vo offset=0mV (default)
0001: Vo offset=-6.25mV
0010: Vo offset=-12.5mV
IA

0011: Vo offset=-18.75mV
0100: Vo offset=-25mV
0101: Vo offset=-31.25mV
0110: Vo offset=-37.5mV
0111: Vo offset=-43.75mV
ED

1000: Vo offset=-50mV
M

SMPS_TOP_
0436 SMPS_TOP control register 4 0000
ANA_CON4
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RG_VSRAM_TRIML RG_VSRAM_TRIMH
Type RW RW
Reset 0 0 0 0 0 0 0 0 0 0

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Bit(s) Name Description

9:5 RG_VSRAM_TRIM Fine-tunes R2R DAC reference
L 11111: Vo offset=+6.25mV

AL
11110: Vo offset=+12.5mV
11101: Vo offset=+18.75mV
11100: Vo offset=+25mV
11011: Vo offset=+31.25mV
11010: Vo offset=+37.5mV

TI
11001: Vo offset=+43.75mV
11000: Vo offset=+50mV
10111: Vo offset=+56.25mV
10110: Vo offset=+62.5mV

EN
10101: Vo offset=+68.75mV
10100: Vo offset=+75mV
10011: Vo offset=+81.25mV
10010: Vo offset=+87.5mV
10001: Vo offset=+93.75mV
00000: Vo offset=0mV (default)
00001: Vo offset=-6.25mV
00010: Vo offset=-12.5mV
00011: Vo offset=-18.75mV
00100: Vo offset=-25mV
00101: Vo offset=-31.25mV
ID
NF
00110: Vo offset=-37.5mV
00111: Vo offset=-43.75mV
01000: Vo offset=-50mV
01001: Vo offset=-56.25mV
01010: Vo offset=-62.5mV
CO

01011: Vo offset=-68.75mV
01100: Vo offset=-75mV
01101: Vo offset=-81.25mV
01110: Vo offset=-87.5mV
01111: Vo offset=-93.75mV
10000: Vo offset=-100mV
4:0 RG_VSRAM_TRIM Fine-tunes R2R DAC reference
K

H 11111: Vo offset=+6.25mV
11110: Vo offset=+12.5mV
TE

11101: Vo offset=+18.75mV
11100: Vo offset=+25mV
11011: Vo offset=+31.25mV
11010: Vo offset=+37.5mV
11001: Vo offset=+43.75mV
11000: Vo offset=+50mV
IA

10111: Vo offset=+56.25mV
10110: Vo offset=+62.5mV
10101: Vo offset=+68.75mV
10100: Vo offset=+75mV
ED

10011: Vo offset=+81.25mV
10010: Vo offset=+87.5mV
10001: Vo offset=+93.75mV
00000: Vo offset=0mV (default)
00001: Vo offset=-6.25mV
00010: Vo offset=-12.5mV
M

00011: Vo offset=-18.75mV
00100: Vo offset=-25mV
00101: Vo offset=-31.25mV
00110: Vo offset=-37.5mV
00111: Vo offset=-43.75mV
01000: Vo offset=-50mV
01001: Vo offset=-56.25mV
01010: Vo offset=-62.5mV

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Bit(s) Name Description

01011: Vo offset=-68.75mV
01100: Vo offset=-75mV

AL
01101: Vo offset=-81.25mV
01110: Vo offset=-87.5mV
01111: Vo offset=-93.75mV
10000: Vo offset=-100mV

TI
SMPS_TOP_
0438 SMPS_TOP Control Register 5 0000
ANA_CON5

EN
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RG_VPA_ RG_VLTE_VSL RG_VCORE1_V RG_VPROC_VS
Name RG_VPA_TRIM_REF
BURSTH EEP SLEEP LEEP
Type RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit(s)
15:14
Name
RG_VPA_BURSTH
Description
PWM/BURST threshold
ID
NF
00: VH=0.50V (default)
01: VH=0.45V
10: VH=0.55V
11: VH=0.60V
13:11 RG_VLTE_VSLEEP Selects sleep mode voltage
CO

000: VSLEEP
001: VSLEEP - 12.5mV
010: VSLEEP - 12.5mV*2
011: VSLEEP - 12.5mV*3
100: VSLEEP + 12.5mV*4
101: VSLEEP + 12.5mV*3
110: VSLEEP + 12.5mV*2
K

111: VSLEEP + 12.5mV

10:8 RG_VCORE1_VSLE Selects sleep mode voltage
TE

EP 000: VSLEEP
001: VSLEEP - 12.5mV
010: VSLEEP - 12.5mV*2
011: VSLEEP - 12.5mV*3
100: VSLEEP + 12.5mV*4
101: VSLEEP + 12.5mV*3
IA

110: VSLEEP + 12.5mV*2

111: VSLEEP + 12.5mV
7:5 RG_VPROC_VSLEE Selects sleep mode voltage
P
ED

000: VSLEEP
001: VSLEEP - 12.5mV
010: VSLEEP - 12.5mV*2
011: VSLEEP - 12.5mV*3
100: VSLEEP + 12.5mV*4
101: VSLEEP + 12.5mV*3
M

110: VSLEEP + 12.5mV*2

111: VSLEEP + 12.5mV
4:0 RG_VPA_TRIM_RE Fine-tunes R2R DAC reference
F 11111: Vo offset=+6.25mV
11110: Vo offset=+12.5mV
11101: Vo offset=+18.75mV
11100: Vo offset=+25mV
11011: Vo offset=+31.25mV

MediaTek Confidential © 2015 MediaTek Inc. Page 116 of 304

Bit(s) Name Description

11010: Vo offset=+37.5mV
11001: Vo offset=+43.75mV

AL
11000: Vo offset=+50mV
10111: Vo offset=+56.25mV
10110: Vo offset=+62.5mV
10101: Vo offset=+68.75mV
10100: Vo offset=+75mV
10011: Vo offset=+81.25mV

TI
10010: Vo offset=+87.5mV
10001: Vo offset=+93.75mV
00000: Vo offset=0mV (default)
00001: Vo offset=-6.25mV

EN
00010: Vo offset=-12.5mV
00011: Vo offset=-18.75mV
00100: Vo offset=-25mV
00101: Vo offset=-31.25mV
00110: Vo offset=-37.5mV
00111: Vo offset=-43.75mV
01000: Vo offset=-50mV
01001: Vo offset=-56.25mV
01010: Vo offset=-62.5mV
01011: Vo offset=-68.75mV
ID
NF
01100: Vo offset=-75mV
01101: Vo offset=-81.25mV
01110: Vo offset=-87.5mV
01111: Vo offset=-93.75mV
10000: Vo offset=-100mV
CO

SMPS_TOP_
043A SMPS_TOP Control Register 6 0000
ANA_CON6
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
K

RG_
DMY
RG_VSRAM_DVF RG_VPA_B
Name 100 S1_VSLEEP URSTL
TE

MA_
EN
Type RW RW RW
Reset 0 0 0 0 0 0
IA

Bit(s) Name Description

15 RG_DMY100MA_E Selects sleep mode voltage
N 0: DMY load off
1: DMY load on
ED

4:2 RG_VSRAM_DVFS1 Selects sleep mode voltage

_VSLEEP 000: VSLEEP
001: VSLEEP - 12.5mV
010: VSLEEP - 12.5mV*2
011: VSLEEP - 12.5mV*3
M

100: VSLEEP + 12.5mV*4

101: VSLEEP + 12.5mV*3
110: VSLEEP + 12.5mV*2
111: VSLEEP + 12.5mV
1:0 RG_VPA_BURSTL PWM/BURST threshold
00: VH=0.35V (default)
01: VH=0.30V
10: VH=0.40V

MediaTek Confidential © 2015 MediaTek Inc. Page 117 of 304

Bit(s) Name Description

11: VH=0.45V

AL
SMPS_TOP_
043C SMPS_TOP Control Register 7 0000
ANA_CON7

TI
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RG_DMY1
Name 00MA_SEL
Type RW

EN
Reset 0 0

Bit(s) Name Description

1:0 RG_DMY100MA_S PWM/BURST threshold
EL 00: typ Iload (default)
01: 10/8
10: 6/8
11: 4/8
ID
NF
VCORE_ANA
0440 VCORE_ANA Control Register 0 32A2
_CON0
CO

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RG_
RG_
VCO
VCO
RE1
RE1_ RG_VCOR
RG_VCORE1_CS RG_VCORE1_RZ _VR
Name RG_VCORE1_CSL 1P35 E1_MIN_O
R SEL F18_
UP_ FF
SST
SEL
K

ART
_EN
_EN
Type RW RW RW RW RW RW
Reset 1 1 0 0 1 0 1 0 1 0 0 0 1 0
TE

Bit(s) Name Description

13:10 RG_VCORE1_CSL Adjusts over current limit
IA

4'b0000: 6.4A
4'b1000: 5.8A
4'b1100: 5.2A
4'b1110: 4.6A
4'b1110: 4.0A
ED

9:7 RG_VCORE1_CSR Adjusts current sense ratio

3'b000: 18K (800mV)
3'b001: 15.75K (700mV)
3'b010: 13.5K (600mV)
3'b011: 11.25K (500mV)
M

3'b100: 9K (400mV)
3'b101: 6.75K (300mV)
3'b110: 4.5K (200mV)
3'b111: 2.25K (100mV)
6:4 RG_VCORE1_RZSE Adjusts compensation R
L 3'b000: 300 kohm
3'b001: 500 kohm
3'b010: 600 kohm

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Bit(s) Name Description

3'b011: 700 kohm
3'b100: 800 kohm

AL
3'b101: 900 kohm
3'b110: 1000 kohm
3'b111: 1200 kohm
3 RG_VCORE1_1P35 Selects RDIV
UP_SEL_EN 1'b0: vo<1.35v

TI
1'b1: vo>=1.35v
2 RG_VCORE1_VRF1 Not used
8_SSTART_EN

EN
1:0 RG_VCORE1_MIN_ Not used
OFF

0442

Bit 15
VCORE_ANA
_CON1
14 13
RG_
12
VCORE_ANA Control Register 1

RG_
11 10 9
ID 8 7 6 5 4 3 2 1
101A

0
NF
VCO VCO
RE1_ RE1 RG_VCOR
Name NDI _MO
RG_VCORE1_ZXOS_TRIM
E1_ZX_OS
RG_VCORE1_SLP
S_E DES
N ET
Type RW RW RW RW RW
CO

Reset 1 0 0 0 0 0 0 0 1 1 0 1 0

Bit(s) Name Description

12 RG_VCORE1_NDIS Enables power down NMOS
_EN 1'b1: Enable (default)
K

1'b0: Disable
11 RG_VCORE1_MOD 1'b1: Force PWM mode
ESET 1'b0: Auto mode
TE

10:5 RG_VCORE1_ZXOS 1LSB=175mA

_TRIM LX zero-crossing offset trimming
6'b000001: +1LSB
6'b000010: +2LSB
6'b000100: +4LSB
IA

6'b001000: -1LSB
6'b010000: -2LSB
6'b100000: -4LSB
4:3 RG_VCORE1_ZX_O nlim offset adjustment combined with RG_VCORE1_RSV[7:6]
ED

S RG_VCORE1_RSV[7:6]+RG_VCORE1_ZX_OS[1:0]
1LSB = 175mA
1110: -1LSB
1101: -2LSB
1011: -4LSB
M

0111: +8LSB
2:0 RG_VCORE1_SLP Adjusts slope compensation
3'b000: 1uA
3'b001: 1.5uA
3'b010: 2uA
3'b011: 2.5uA
3'b100: 3uA
3'b101: 3.5uA

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Bit(s) Name Description

3'b110: 4uA
3'b111: 4.5uA

AL
VCORE_ANA
0444 VCORE_ANA Control Register 2 0820
_CON2

TI
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RG_VCORE1_CSM_P RG_VCORE1_CSM_N
Type RW RW

EN
Reset 1 0 0 0 0 0 1 0 0 0 0 0

Bit(s) Name Description

11:6 RG_VCORE1_CSM Adjusts current measurement
_P [5]: IMAX=1.5V or 1V
1b'0: 1.5V
1b'1: 1V
[4]: Enable test mode
6`bXX0000 +0%
ID
NF
6`bXX0001 -3%
6`bXX0010 -6%
6`bXX0011 -9%
6`bXX0100 -12%
6`bXX0101 -15%
CO

6`bXX0110 -18%
6`bXX0111 -21%
6`bXX1000 +24%
6`bXX1001 +21%
6`bXX1010 +18%
6`bXX1011 +15%
6`bXX1100 +12%
K

6`bXX1101 +9%
6`bXX1110 +6%
6`bXX1111 +3%
TE

1'b0: Valley current sense

1'b1: Peak current sense
5:0 RG_VCORE1_CSM Adjusts current measurement
_N [5]: IMAX=1.5V or 1V
1b'0: 1.5V
IA

1b'1: 1V
[4]: Enable test mode
6`bXX0000 +0%
6`bXX0001 -3%
6`bXX0010 -6%
ED

6`bXX0011 -9%
6`bXX0100 -12%
6`bXX0101 -15%
6`bXX0110 -18%
6`bXX0111 -21%
M

6`bXX1000 +24%
6`bXX1001 +21%
6`bXX1010 +18%
6`bXX1011 +15%
6`bXX1100 +12%
6`bXX1101 +9%
6`bXX1110 +6%
6`bXX1111 +3%
1'b0: Disable

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Bit(s) Name Description

1'b1: Enable

AL
VCORE_ANA
0446 VCORE_ANA Control Register 3 04F0
_CON3

TI
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RG_VCORE1_P
Name FM_RIP
RG_VCORE1_RSV
Type RW RW

EN
Reset 1 0 0 1 1 1 1 0 0 0 0

Bit(s) Name Description

10:8 RG_VCORE1_PFM PFM ripple control bit
_RIP 1LSB = 6.25mV
3'b000: +0LSB
3'b001: +1LSB
3'b010: +2LSB
3'b011: +3LSB
ID
NF
3'b100: +4LSB
3'b101: +5LSB
3'b110: +6LSB
3'b111: +7LSB
7:0 RG_VCORE1_RSV Reserved:
CO

[7]: For nlim trimmimg

[6]: For nlim trimmimg
[5]: HS on- speed increase
[4]: Power good function gating
[3]: HS driver decection threshold voltage
[2]: VBAT<2.8V, increase powermos slew rate
[1]: nlim gating
K

[0]: In PFM mode, increase slew rate

0: Check output drop voltage (comparator)
1: Check NMOS threshold
TE

VCORE_ANA
0448 VCORE_ANA Control Register 4 000B
IA

_CON4
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RG_
VCO
ED

RE1
Name _DT
RG_VCORE1_TRAN_BST
S_E
NB
Type RW RW
Reset 0 0 0 1 0 1 1
M

Bit(s) Name Description

6 RG_VCORE1_DTS_ Differential to single buffer disable signal
ENB
5:0 RG_VCORE1_TRA PFM -> PWM transient boost EN (1=EN)
N_BST [5]: Reserved
[4]: Drop

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Bit(s) Name Description

[3:2]:
00: 0 preset duty

AL
01: Preset duty low
10: Preset duty med
11: Preset duty high
[1]: AVP
[0]: BW extension

TI
VSYS22_AN

EN
044A VSYS22_ANA Control Register 0 0C12
A_CON0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RG_ RG_
RG_
RG_ VSY VSY
VSY
VSY S22_ S22_
S22_ RG_VSYS2
Name
S22_
AUT
O_M
ODE
RG_VSYS22_CSR

ID RG_VSYS22_RZS
EL
1P35
UP_
SEL
_EN
VRF1
8_SS
TAR
T_E
N
NVT
_BU
FF_
OFF
_EN
2_MIN_OF
F
NF
Type RW RW RW RW RW RW RW
Reset 0 0 1 1 0 0 0 1 0 0 1 0

Bit(s) Name Description

13 RG_VSYS22_AUTO Not used

_MODE
12:10 RG_VSYS22_CSR Adjusts current sense ratio
3'b000: 234mV
3'b001: 208mV
3'b010: 182mV
K

3'b011: 156mV (default)

3'b100: 130mV
3'b101: 104mV
3'b110: 78mV
TE

3'b111: 52mV
7:5 RG_VSYS22_RZSE Adjusts compensation R
L 3'b000: 700 kohm (default)
3'b001: 300 kohm
IA

3'b010: 200 kohm

3'b011: 500 kohm
3'b100: 800 kohm
3'b101: 900 kohm
3'b110: 1000 kohm
ED

3'b111: 1200 kohm

4 RG_VSYS22_1P35U Selects Vo>=1.35v
P_SEL_EN 1'b0: Vo<1.35v
1'b1: Vo>=1.35v
M

3 RG_VSYS22_VRF18 Enables VSYS22 soft-start time

_SSTART_EN 1'b0: Disable
1'b1: Enable
2 RG_VSYS22_NVT_ Not used
BUFF_OFF_EN
1:0 RG_VSYS22_MIN_ Not used
OFF

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VSYS22_AN
044C VSYS22_ANA Control Register 1 041C

AL
A_CON1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RG_ RG_
VSY VSY
S22_ S22_ RG_VSYS2
Name RG_VSYS22_SLP RG_VSYS22_CSL
NDI MOD 2_ZX_OS

TI
S_E ESE
N T
Type RW RW RW RW RW
Reset 1 0 0 0 0 0 1 1 1 0 0

EN
Bit(s) Name Description
10 RG_VSYS22_NDIS Enables NMOS discharge
_EN 1'b1: Enable NMOS discharge (default)

9 RG_VSYS22_MOD
ESET
1'b0: Disable NMOS discharge
Selects force PWM mode
1'b1: Force PWM mode
1'b0: Auto mode
ID
NF
8:7 RG_VSYS22_ZX_O nlim offset adjustment combined with RG_VSYS22_RSV[7:6]
S RG_VSYS22_RSV[7:6]+RG_VSYS22_ZX_OS[1:0]
1LSB = 170mA
0001: -1LSB
0010: -2LSB
CO

0100: -4LSB
1000: +8LSB
6:4 RG_VSYS22_SLP Adjusts slope compensation
3'b000: 1uA
3'b001: 1.5uA (default)
3'b010: 2uA
K

3'b011: 2.5uA
3'b100: 3uA
3'b101: 3.5uA
TE

3'b110: 4uA
3'b111: 4.5uA
3:0 RG_VSYS22_CSL Adjusts over current limit
4'b0000: 1.2A
4'b1000: 2A
IA

4'b1100: 3A (default)
4'b1110: 4A
4'b1111: 4.8A
ED

VSYS22_AN
044E VSYS22_ANA Control Register 2 0000
A_CON2
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M

Name RG_VSYS22_CSM_P RG_VSYS22_CSM_N

Type RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0

Bit(s) Name Description

11:6 RG_VSYS22_CSM_ Adjusts current measurement
P 6`bXX0000 +0%

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Bit(s) Name Description

6`bXX0001 -3%
6`bXX0010 -6%

AL
6`bXX0011 -9%
6`bXX0100 -12%
6`bXX0101 -15%
6`bXX0110 -18%
6`bXX0111 -21%
6`bXX1000 +24%

TI
6`bXX1001 +21%
6`bXX1010 +18%
6`bXX1011 +15%
6`bXX1100 +12%

EN
6`bXX1101 +9%
6`bXX1110 +6%
6`bXX1111 +3%
5:0 RG_VSYS22_CSM_ Adjusts current measurement
N 6`bXX0000 +0%
6`bXX0001 -3%
6`bXX0010 -6%
6`bXX0011 -9%
6`bXX0100 -12%
ID
NF
6`bXX0101 -15%
6`bXX0110 -18%
6`bXX0111 -21%
6`bXX1000 +24%
6`bXX1001 +21%
6`bXX1010 +18%
CO

6`bXX1011 +15%
6`bXX1100 +12%
6`bXX1101 +9%
6`bXX1110 +6%
6`bXX1111 +3%
K

VSYS22_AN
TE

0450 VSYS22_ANA Control Register 3 0000

A_CON3
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RG_VSYS22_ZXOS_TRIM RG_VSYS22_RSV
Type RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IA

Bit(s) Name Description

13:8 RG_VSYS22_ZXOS LX zero-crossing offset trimming
ED

_TRIM 1LSB=150mA
6'b000001: +1LSB
6'b000010: +2LSB
6'b000100: +4LSB
6'b001000: -1LSB
M

6'b010000: -2LSB
6'b100000: -4LSB
7:0 RG_VSYS22_RSV Reserved
[7]: For nlim trimmimg
[6]: For nlim trimmimg
[5]: HS on- speed increase
[4]: For power good ibias enable
[3]: HS driver decection threshold voltage

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Bit(s) Name Description

[2]: VBAT<2.8V, increase powermos slew rate
[1]: nlim gating

AL
[0]: In PFM mode, increase slew rate

VSYS22_AN

TI
0452 VSYS22_ANA Control Register 4 005A
A_CON4
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RG_

EN
VSY
S22_ RG_VSYS22_PF
Name RG_VSYS22_TRAN_BST
DTS M_RIP
_EN
B
Type RW RW RW
Reset

Bit(s) Name Description

ID 0 0 1 0 1 1 0 1 0
NF
9 RG_VSYS22_DTS_ Differential to single buffer disable signal
ENB
8:3 RG_VSYS22_TRAN PFM -> PWM transient boost EN (1=EN)
_BST [5]: Reserved
[4]: Drop
CO

[3:2]:
00: No preset duty
01: Peset duty low
10: Preset duty med
11: Preset duty high
[1]: AVP
[0]: BW extension
K

2:0 RG_VSYS22_PFM_ PFM ripple control bit

RIP 1LSB = 6.25mV
3'b000: +0LSB
TE

3'b001: +1LSB
3'b010: +2LSB
3'b011: +3LSB
3'b100: +4LSB
3'b101: +5LSB
IA

3'b110: +6LSB
3'b111: +7LSB
ED

VPROC_ANA
0454 VPROC_ANA Control Register 0 2262
_CON0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RG_
M

RG_
RG_ VPR
VPR
VPR OC_
OC_ RG_VPRO
OC_ RG_VPROC_RZS VRF
Name RG_VPROC_CSL RG_VPROC_CSR 1P35 C_MIN_OF
AUT EL 18_S
UP_ F
O_M STA
SEL
ODE RT_
_EN
EN
Type RW RW RW RW RW RW RW
Reset 0 1 0 0 0 1 0 0 1 1 0 0 0 1 0

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Bit(s) Name Description

AL
14 RG_VPROC_AUTO 1'b1: Disable OP tran-boost function
_MODE 1'b0: Normal
13:10 RG_VPROC_CSL Adjusts over current limit
4'b0000: 8A
4'b1000: 7A(default)

TI
4'b1100: 6A
4'b1110: 5A
4'b1111: 4A
9:7 RG_VPROC_CSR Adjusts current sense ratio

EN
3'b000: 15.75K; 233mV/A
3'b001: 13.5K; 200mV/A
3'b010: 11.25K; 167mV/A
3'b011: 9K; 133mV/A
3'b100: 6.75K (default); 100mV/A
3'b101: 4.5K; 67mV/A

6:4 RG_VPROC_RZSEL
3'b110: 2.25K; 33mV/A
3'b111: 0K
Adjusts compensation R
3'b000: 400 kohm
ID
NF
3'b001: 800 kohm
3'b010: 1200 kohm
3'b011: 1400 kohm
3'b100: 1500 kohm
3'b101: 1600 kohm
CO

3'b110: 1800 kohm (default)

3'b111: 1900 kohm
3 RG_VPROC_1P35U vo>=1.35v
P_SEL_EN 1'b0: vo<1.35V, valley current sense
1'b1: vo>=1.35V, peak current sense
2 RG_VPROC_VRF18 Not used
K

_SSTART_EN
1:0 RG_VPROC_MIN_ Not used
OFF
TE

VPROC_ANA
0456 VPROC_ANA Control Register 1 1004
IA

_CON1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RG_
RG_ RG_
VCO
ED

VPR VPR
RE1
OC_ OC_ RG_VPRO
Name _AU
NDI MOD
RG_VPROC_ZXOS_TRIM
C_ZX_OS
RG_VPROC_SLP
TO_
S_E ESE
MOD
N T
E
Type RW RW RW RW RW RW
M

Reset 0 1 0 0 0 0 0 0 0 0 0 1 0 0

Bit(s) Name Description

13 RG_VCORE1_AUT Not used
O_MODE
12 RG_VPROC_NDIS_ Enables NMOS discharge
EN 1'b1: Enable NMOS discharge (default)

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Bit(s) Name Description

1'b0: Disable NMOS discharge
11 RG_VPROC_MODE Selects force PWM mode

AL
SET 1'b1: Force PWM mode
1'b0: Auto mode
10:5 RG_VPROC_ZXOS 1LSB=260mA
_TRIM LX zero-crossing offset trimming

TI
6'b000001: +1LSB
6'b000010: +2LSB
6'b000100: +4LSB
6'b001000: -1LSB
6'b010000: -2LSB

EN
6'b100000: -4LSB
4:3 RG_VPROC_ZX_O Nlim trimimg bits(combined with RG_VPROC_RSV[7],[6], as
S RG_VPROC_RSV[7],[6],zx_os[1],[0])
2'b0100: -5m
2'b 1000: -1.66

2:0 RG_VPROC_SLP
2'b1110: -1.74
2'b1101: -1.62
2'b1100: -1.5
Adjusts slope compensation
ID
NF
3'b000: 1uA
3'b001: 1.5uA
3'b010: 2uA
3'b011: 2.5uA
3'b100: 3uA (default)
CO

3'b101: 3.5uA
3'b110: 4uA
3'b111: 4.5uA
K

VPROC_ANA
0458 VPROC_ANA Control Register 2 0000
_CON2
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TE

Name RG_VPROC_CSM_P RG_VPROC_CSM_N

Type RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0
IA

Bit(s) Name Description

11:6 RG_VPROC_CSM_ Adjusts current measurement
P [0]: IMAX=1.5V or 1V
1b'0: 1.5V
ED

1b'1: 1V
[5]: Test peak/valley current
1'b0: Valley
1'b1: Peak
6`bXX0000 +0%
M

6`bXX0001 -3%
6`bXX0010 -6%
6`bXX0011 -9%
6`bXX0100 -12%
6`bXX0101 -15%
6`bXX0110 -18%
6`bXX0111 -21%
6`bXX1000 +24%
6`bXX1001 +21%

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Bit(s) Name Description

6`bXX1010 +18%
6`bXX1011 +15%

AL
6`bXX1100 +12%
6`bXX1101 +9%
6`bXX1110 +6%
6`bXX1111 +3%
5:0 RG_VPROC_CSM_ Adjusts current measurement

TI
N [0]: IMAX=1.5V or 1V
1b'0: 1.5V
1b'1: 1V
[5]: Enable test mode

EN
1'b0: Disable
1'b1: Enable
6`bXX0000 +0%
6`bXX0001 -3%
6`bXX0010 -6%
6`bXX0011 -9%
6`bXX0100 -12%
6`bXX0101 -15%
6`bXX0110 -18%
6`bXX0111 -21%
ID
NF
6`bXX1000 +24%
6`bXX1001 +21%
6`bXX1010 +18%
6`bXX1011 +15%
6`bXX1100 +12%
6`bXX1101 +9%
CO

6`bXX1110 +6%
6`bXX1111 +3%

VPROC_ANA
K

045A VPROC_ANA Control Register 3 04F0

_CON3
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TE

RG_VPROC_PF
Name M_RIP
RG_VPROC_RSV
Type RW RW
Reset 1 0 0 1 1 1 1 0 0 0 0
IA

Bit(s) Name Description

10:8 RG_VPROC_PFM_ PFM ripple control bit
RIP 1 LSB=6.25mV
3'b000: +0LSB
ED

3'b001: +1LSB
3'b010: +2LSB
3'b011: +3LSB
3'b100: +4LSB
3'b101: +5LSB
M

3'b110: +6LSB
3'b111: +7LSB
7:0 RG_VPROC_RSV Reserved
[7]: For nlim trimming
[6]: For nlim trimming
[5]: HS on- speed increase
[4]: Power good function gating
0: Check output drop voltage (COMPARATOR)

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Bit(s) Name Description

1: Check NMOS threshold
[3]: HS driver detection threshold voltage

AL
[2]: VBAT<2.8V, increase powermos slew rate
[1]: nlim gating
[0]: In PFM mode, increase slew rate

TI
VPROC_ANA
045C VPROC_ANA Control Register 4 000B
_CON4

EN
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RG_
VPR
OC_
Name DTS
RG_VPROC_TRAN_BST
_EN

Type
Reset ID B
RW
0 0 0 1
RW
0 1 1
NF
Bit(s) Name Description
6 RG_VPROC_DTS_E Differential to single buffer disable signal
NB
5:0 RG_VPROC_TRAN PFM -> PWM transient boost EN (1=EN)
CO

_BST [5]: reserved, no used

[4]: reserved, no used
[3]:reserved, no used
[2]:reserved, no used
[1]: AVP
[0]: BW extension
K

OSC32_ANA
TE

045E OSC32 Control Register 0 3BC7

_CON0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RG_ RG_ RG_ RG_
RG_ RG_
EOS EOS EOS EOS RG_
XOS LPD
IA

Name C_L C_L C_C

C_P
C_P RG_EOSC_CALI
_RE
LPD RG_XOSC_CALI
PD_ PD_ HOP WD _EN
WDB SET
RST EN _EN B
Type RW RW RW RW RW RW RW RW RW
Reset 0 0 1 1 1 0 1 1 1 1 0 0 0 1 1 1
ED

Bit(s) Name Description

15 RG_EOSC_LPD_RS Resets low power detection
T 0: Does not reset
M

1: Reset low power detection output to 1

14 RG_EOSC_LPD_E Enables OSC32 low power detection
N
13 RG_EOSC_CHOP_ Enables chopper
EN
12 RG_XOSC_PWDB EOSC PWDB
0: Power down

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Bit(s) Name Description

1: Power on
11 RG_EOSC_PWDB EOSC PWDB

AL
0: Power down
1: Power on
10:6 RG_EOSC_CALI Calibrates charging cap
5 RG_LPD_RESET Resets low power detection

TI
0: Does not reset
1: Reset low power detection output to 1
4 RG_LPD_EN Enables OSC32 low power detection

EN
3:0 RG_XOSC_CALI Calibrates GM
Default: 4'b0111
Setting the 2nd step to 4'b0000 is suggested.

0460

Bit 15
OSC32_ANA
_CON1
14 13 12
OSC32 Control Register 1

11 10 9
ID 8 7 6 5 4 3 2 1
0000

0
NF
RG_
EOS
RG_EOSC_ RG_EOSC_
Name C_V
RSV OPT
CT_
EN
Type RW RW RW
CO

Reset 0 0 0 0 0

Bit(s) Name Description

4:3 RG_EOSC_RSV EOSC32 RSV
2:1 RG_EOSC_OPT EOSC32 LPD OPT
K

0 RG_EOSC_VCT_EN Enables EOSC32 threshold tracking

0: Disable
TE

1: Enable

VPA_ANA_C
IA

0462 VPA_ANA Control Register 0 0000

ON0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RG_VPA_ RG_VPA_ RG_VPA_ RG_VPA_ RG_VPA_ RG_VPA_
Name
SLP CSL CSMIR CSR CC RZSEL
ED

Type RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0

Bit(s) Name Description

11:10 RG_VPA_SLP Adjusts slope compensation

00: 1.5uA (default)
01: 1uA
10: 2.5uA
11: 2uA
9:8 RG_VPA_CSL Adjusts over current limit
00: 1.6A
01: 1.2A

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Bit(s) Name Description

10: 2.0A
11: 2.4A

AL
7:6 RG_VPA_CSMIR 00: 1.0X
01: 1.5X
10: 2.0X
11: 2.5X
5:4 RG_VPA_CSR Adjusts current sense ratio

TI
00: 1x (default)
01: 0.5x
10: 1.25x
11: 0.75x

EN
3:2 RG_VPA_CC Adjusts compensation C
00: 8pF (default)
01: 6pF
10: 3pF
11: 1pF
1:0 RG_VPA_RZSEL Adjusts compensation R
00: 900kohm (default)
01: 700kohm
10: 1.1Mohm
ID
NF
11: 1.3Mohm
CO

VPA_ANA_C
0464 VPA_ANA Control Register 1 8000
ON1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RG_ RG_ RG_
RG_
VPA RG_VPA_S VPA VPA
RG_VPA_S VPA RG_VPA_Z
Name _ND LEW_NMO LEW
_MO _BW
_HZ X_OS
RG_VPA_ZX_OS_TRIM
IS_E S DES EX_
K

P
N ET GAT
Type RW RW RW RW RW RW RW RW
Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
TE

Bit(s) Name Description

15 RG_VPA_NDIS_EN Enables power down NMOS
IA

14:13 RG_VPA_SLEW_N Controls lgate slew rate

MOS 00: ~1ns (default)
01: ~2ns
10: ~5ns
11: ~10ns
ED

12:11 RG_VPA_SLEW Controls ugate slew rate

00: ~1ns (default)
01: ~2ns
10: ~5ns
11: ~10ns
M

10 RG_VPA_MODESE 0: Auto mode

T 1: Force PWM mode
9 RG_VPA_BWEX_G BW extension function gating
AT 0: BW extension on (default)
1: BW extension off
8 RG_VPA_HZP HZ prevention function gating
0: HZ prevention on (default)

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Bit(s) Name Description

1: HZ prevention off
7:6 RG_VPA_ZX_OS Adjusts positive offset for LX zero-crossing detection

AL
00: +200mV (default)
01: +150mV
10: +250mV
11: +300mV
5:0 RG_VPA_ZX_OS_T Adjusts offset for LX zero-crossing detection

TI
RIM 0000: -200mV (default)
0001: -150mV
0010: -250mV
0011: -300mV

EN
1101: -800mV
1111: -850mV

0466

Bit 15
VPA_ANA_C
ON2
14 13 12
VPA_ANA Control Register 2

11 10 9
ID 8 7 6 5 4 3 2 1
0002

0
NF
RG_
RG_VPA_V RG_VPA_
Name RG_VPA_RSV1 VPA
BAT_DEL MIN_ON
_EN
Type RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 1 0
CO

Bit(s) Name Description

12:5 RG_VPA_RSV1 RG_VPA_RSV[0]: BW extension gating
RG_VPA_RSV[4:1]: Zero crossing detection point adjustment
RG_VPA_RSV[5]: HZ prevention gating
RG_VPA_RSV[6]: CS adjustment
K

4 RG_VPA_EN V3GPA enable signal

0: Disable
1: Enable
TE

3:2 RG_VPA_VBAT_D Detects lowdrop out threshold

EL 00: VR=0.6V (default)
01: VR=0.55V
10: VR=0.65V
IA

11: VR=0.70V
1:0 RG_VPA_MIN_ON
ED

VPA_ANA_C
0468 VPA_ANA Control Register 3 0000
ON3
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RG_VPA_RSV2
M

Type RW
Reset 0 0 0 0 0 0 0 0

Bit(s) Name Description

7:0 RG_VPA_RSV2 RG_VPA_RSV[0]: BW extension gating
RG_VPA_RSV[4:1]: Zero crossing detection point adjustment
RG_VPA_RSV[5]: HZ prevention gating

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Bit(s) Name Description

RG_VPA_RSV[6]: CS adjustment

AL
VLTE_ANA_
046A VLTE_ANA Control Register 0 32A2
CON0

TI
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RG_ RG_
VLT VLT
E_1P E_V
RG_VLTE_RZSE RG_VLTE_
Name RG_VLTE_CSL RG_VLTE_CSR 35U RF18

EN
L MIN_OFF
P_S _SST
EL_ ART
EN _EN
Type RW RW RW RW RW RW
Reset 1 1 0 0 1 0 1 0 1 0 0 0 1 0

Bit(s)
13:10
Name
RG_VLTE_CSL
Description
ID
Over current limit adjustment
NF
4'b0000: 3.6A
4'b0001: 3.7A
4'b0010: 3.8A
4'b0011: 4A
4'b0100: 4.2A
4'b0101: 4.4A
CO

4'b0110: 4.6A
4'b0111: 4.8A
4'b1000: 5A
4'b1001: 5.3A
4'b1010: 5.6A
4'b1011: 6A
4'b1100: 6.4A
K

4'b1101: 6.9A
4'b1110: 7.4A
4'b1111: 8A
TE

4'b0000: 3.6A
4'b0001: 3.7A
4'b0010: 3.8A
4'b0011: 4A
4'b0100: 4.2A
IA

4'b0101: 4.4A
4'b0110: 4.6A
4'b0111: 4.8A
4'b1000: 5A
4'b1001: 5.3A
ED

4'b1010: 5.6A
4'b1011: 6A
4'b1100: 6.4A
4'b1101: 6.9A
4'b1110: 7.4A
M

4'b1111: 8A
9:7 RG_VLTE_CSR Current sense ratio adjustment
3'b000: 18K (800mV)
3'b001: 15.75K (700mV)
3'b010:13.5K (600mV)
3'b011: 11.25K (500mV)
3'b100: 9K (400mV)
3'b101: 6.75K (300mV)

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Bit(s) Name Description

3'b110: 4.5K (200mV)
3'b111: 2.25K (100mV)

AL
3'b000: 18K (800mV)
3'b001: 15.75K (700mV)
3'b010: 13.5K (600mV)
3'b011: 11.25K (500mV)
3'b100: 9K (400mV)
3'b101: 6.75K (300mV)

TI
3'b110: 4.5K (200mV)
3'b111: 2.25K (100mV)
6:4 RG_VLTE_RZSEL Compensation R adjustment

EN
3'b000: 300 kohm
3'b001: 500 kohm
3'b010: 600 kohm
3'b011: 700 kohm
3'b100: 800 kohm
3'b101: 900 kohm
3'b110: 1000 kohm
3'b111: 1200 kohm
3'b000: 300 kohm
3'b001: 500 kohm
ID
NF
3'b010: 600 kohm
3'b011: 700 kohm
3'b100: 800 kohm
3'b101: 900 kohm
3'b110: 1000 kohm
3'b111: 1200 kohm
CO

3 RG_VLTE_1P35UP Rdiv select

_SEL_EN 1'b0: vo<1.35v
1'b1: vo>=1.35v
1'b0: vo<1.35v
1'b1: vo>=1.35v
2 RG_VLTE_VRF18_ Not used
K

SSTART_EN
1:0 RG_VLTE_MIN_O Not used
TE

VLTE_ANA_
IA

046C VLTE_ANA Control Register 1 101A

CON1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RG_
RG_ RG_
VLT
ED

VLT VLT
E_A RG_VLTE_
Name UTO
E_N E_M RG_VLTE_ZXOS_TRIM
ZX_OS
RG_VLTE_SLP
DIS_ ODE
_MO
EN SET
DE
Type RW RW RW RW RW RW
Reset 0 1 0 0 0 0 0 0 0 1 1 0 1 0
M

Bit(s) Name Description

13 RG_VLTE_AUTO_ no used
MODE
12 RG_VLTE_NDIS_E Enables NMOS discharge
N 1'b1: Enable NMOS discharge (default)

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Bit(s) Name Description

1'b0: Disable NMOS discharge
11 RG_VLTE_MODES Selects force PWM mode

AL
ET 1'b1: Force PWM mode
1'b0: Auto mode
10:5 RG_VLTE_ZXOS_T 1LSB=170mA
RIM LX zero-crossing offset trimming

TI
6'b000001: +1LSB
6'b000010: +2LSB
6'b000100: +4LSB
6'b001000: -1LSB
6'b010000: -2LSB

EN
6'b100000: -4LSB
4:3 RG_VLTE_ZX_OS nlim offset adjustment combine with RG_VLTE_RSV[7:6]
RG_VLTE_RSV[7:6]+RG_VLTE_ZX_OS[1:0]
1LSB = 175mA
1110: -1LSB

2:0 RG_VLTE_SLP
1101: -2LSB
1011: -4LSB
0111: +8LSB
Adjusts slope compensation
ID
NF
3'b000: 2.0u
3'b001: 2.5u
3'b010: 3.0u
3'b011: 3.5u
3'b100: 4.0u
CO

3'b101: 4.5u
3'b110: 5.0u
3'b111: 5.5u
K

VLTE_ANA_
046E VLTE_ANA Control Register 2 0820
CON2
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TE

Name RG_VLTE_CSM_P RG_VLTE_CSM_N

Type RW RW
Reset 1 0 0 0 0 0 1 0 0 0 0 0
IA

Bit(s) Name Description

11:6 RG_VLTE_CSM_P Adjusts current measurement
[5]: IMAX=1.5V or 1V
1b'0: 1.5V
ED

1b'1: 1V
[4]: Enable test mode
1'b0: Valley current sense
1'b1: Peak current sense
6`bXX0000 +0%
M

6`bXX0001 -3%
6`bXX0010 -6%
6`bXX0011 -9%
6`bXX0100 -12%
6`bXX0101 -15%
6`bXX0110 -18%
6`bXX0111 -21%
6`bXX1000 +24%
6`bXX1001 +21%

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Bit(s) Name Description

6`bXX1010 +18%
6`bXX1011 +15%

AL
6`bXX1100 +12%
6`bXX1101 +9%
6`bXX1110 +6%
6`bXX1111 +3%
5:0 RG_VLTE_CSM_N Adjusts current measurement

TI
[5]: IMAX=1.5V or 1V
1b'0: 1.5V
1b'1: 1V
[4]: Enable test mode

6`bXX1110 +6%
6`bXX1111 +3%

VLTE_ANA_
K

0470 VLTE_ANA Control Register 3 04F0

CON3
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TE

RG_VLTE_PFM
Name _RIP
RG_VLTE_RSV
Type RW RW
Reset 1 0 0 1 1 1 1 0 0 0 0
IA

Bit(s) Name Description

10:8 RG_VLTE_PFM_RI PFM ripple control bit
P 1LSB = 6.25mV
3'b000: +0LSB
ED

3'b001: +1LSB
3'b010: +2LSB
3'b011: +3LSB
3'b100: +4LSB
3'b101: +5LSB
M

3'b110: +6LSB
3'b111: +7LSB
7:0 RG_VLTE_RSV Reserved
[7]: For nlim trimmimg
[6]: For nlim trimmimg
[5]: HS on- speed increase
[4]: Power good function gating
0: Check output drop voltage (comparator)

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Bit(s) Name Description

1: Check NMOS threshold
[3]: HS driver detection threshold voltage

AL
[2]: VBAT<2.8V, increase powermos slew rate
[1]: nlim gating
[0]: In PFM mode, increase slew rate

TI
VLTE_ANA_
0472 VLTE_ANA Control Register 4 000B
CON4

EN
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RG_
VLT
Name E_D RG_VLTE_TRAN_BST
TS_
ENB
Type
Reset

Bit(s) Name Description

ID RW
0 0 0 1
RW
0 1 1
NF
6 RG_VLTE_DTS_EN Differential to single buffer disable signal
B
5:0 RG_VLTE_TRAN_ PFM -> PWM transient boost EN (1=EN)
BST [5]: Reserved
CO

[4]: Drop
[3:2]:
00: 0 preset duty
01: Preset duty low
10: Preset duty med
11: Preset duty high
[1]: AVP
K

[0]: BW extension
TE

VPROC_CON
048A VPROC Control Register 11 0058
11
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IA

Name VPROC_VOSEL
Type RW
Reset 1 0 1 1 0 0 0
ED

Bit(s) Name Description

6:0 VPROC_VOSEL Selects VOUT in SW mode
Voltage = 0.6+0.00625*step
M

VSRAM_CO
04B2 VSRAM Control Register 11 0060
N11
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name VSRAM_VOSEL_RSV
Type RW
Reset 1 1 0 0 0 0 0

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Bit(s) Name Description

AL
6:0 VSRAM_VOSEL_RS Not used
V

TI
VLTE_CON1
04DA VLTE Control Register 11 0048
1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name VLTE_VOSEL

EN
Type RW
Reset 1 0 0 1 0 0 0

Bit(s) Name Description

6:0 VLTE_VOSEL Voltage= 0.6+0.00625*step
ID
NF
VCORE1_CO
0616 VCORE1 Control Register 11 0058
N11
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name VCORE1_VOSEL
CO

Type RW
Reset 1 0 1 1 0 0 0

Bit(s) Name Description

VCORE1_VOSEL Selects VOUT in SW mode
6:0
Voltage = 0.6+0.00625*step
K
TE

VSYS22_CO
063E VSYS22 Control Register 11 0040
N11
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
IA

VSYS22_VOSEL
Type RW
Reset 1 0 0 0 0 0 0
ED

Bit(s) Name Description

6:0 VSYS22_VOSEL Selects VOUT in SW mode
Voltage = 1.4+0.00625*step
M

0666 VPA_CON11 VPA Control Register 11 0000

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name VPA_VOSEL
Type RW
Reset 0 0 0 0 0 0

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Bit(s) Name Description

5:0 VPA_VOSEL Selects VOUT in SW mode

AL
0800 ZCD_CON0 ZCD Control Register 0 0000
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

TI
RG_
AUD
RG_
ZCD
RG_AUDZ AUD
RG_AUDZCDMU TIM RG_AUDZCDGAI
Name CDGAINST ZCD
XSEL_VAUDP15 EOU NSTEPTIME

EN
EPSIZE ENA
TMO
BLE
DES
EL
Type RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0

Bit(s)
10:8
Name
RG_AUDZCDMUXS
EL_VAUDP15
Description
ID
Selects zero crossing detection mux
NF
000: Left line in and Right line in
001: Headphone L and headphone R
010: Handset
011: IV buffer
100: bypass ZCD
101: Bypass ZCD
CO

110: Bypass ZCD

111: Bypass ZCD
6 RG_AUDZCDTIME
OUTMODESEL
5:4 RG_AUDZCDGAIN Gain step to change internal gain of ZCD
STEPSIZE 00: 1dB
K

01: 2dB
10: 4dB
11: 8dB
TE

3:1 RG_AUDZCDGAIN Gain step time to change internal gain of ZCD

STEPTIME 000: 0us
001: 250us
010: 500us
011: 1ms
IA

100: 2ms
101: 4ms
110: 8ms
111: 16ms
ED

0 RG_AUDZCDENAB Enables zero crossing detection (ZCD)

LE 0: Disable
1: Enable
M

0802 ZCD_CON1 ZCD Control Register 1 0F9F

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RG_AUDLORGAIN RG_AUDLOLGAIN
Type RW RW
Reset 1 1 1 1 1 1 1 1 1 1

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Bit(s) Name Description

11:7 RG_AUDLORGAIN 00000: +8dB
00001: +7dB

AL
10010: -10dB
11111: -40dB (mute)
4:0 RG_AUDLOLGAIN 00000: +8dB
00001: +7dB
10010: -10dB

TI
11111: -40dB (mute)

EN
0804 ZCD_CON2 ZCD Control Register 2 0F9F
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RG_AUDHPRGAIN RG_AUDHPLGAIN
Type RW RW
Reset

ID
1 1 1 1 1 1 1 1 1 1

Bit(s) Name Description

11:7 RG_AUDHPRGAIN 00000: +8dB
NF
00001: +7dB
10010: -10dB
11111: -40dB (mute)
4:0 RG_AUDHPLGAIN 00000: +8dB
00001: +7dB
CO

10010: -10dB
11111: -40dB (mute)

0806 ZCD_CON3 ZCD Control Register 3 001F

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RG_AUDHSGAIN
TE

Type RW
Reset 1 1 1 1 1

Bit(s) Name Description

RG_AUDHSGAIN 00000: +8dB

00001: +7dB
4:0
10010: -10dB
11111: -40dB (mute)
ED

0808 ZCD_CON4 ZCD Control Register 4 0707

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M

RG_AUDIVRGA RG_AUDIVLGA
Name
IN IN
Type RW RW
Reset 1 1 1 1 1 1

Bit(s) Name Description

10:8 RG_AUDIVRGAIN 000: +5dB

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Bit(s) Name Description

001: +4dB
010: +3dB

AL
011: +2dB
100: +1dB
101: 0dB
110: -1dB
111: -2dB

TI
2:0 RG_AUDIVLGAIN 000: +5dB
001: +4dB
010: +3dB
011: +2dB

EN
100: +1dB
101: 0dB
110: -1dB
111: -2dB

080A
Bit 15
ZCD_CON5
14 13 12
ZCD Control Register 5
11 10 9
ID 8 7 6 5 4 3 2 1
3F3F
0
NF
Name RG_AUDINTGAIN2 RG_AUDINTGAIN1
Type RO RO
Reset 1 1 1 1 1 1 1 1 1 1 1 1

Bit(s) Name Description

13:8 RG_AUDINTGAIN2
5:0 RG_AUDINTGAIN1
K

ISINK0_CO
080C ISINK0 Control Register 0 0000
N0
TE

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name ISINK_DIM0_FSEL
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IA

Bit(s) Name Description

15:0 ISINK_DIM0_FSEL Selects ISINK0 dimming frequency
Backlight: (@2MHz)
2: 20kHz
ED

61: 1kHz
311: 200Hz
12499: 5Hz
31249: 2Hz
62499: 1Hz
M

Indicator: (@32kHz)
0: 1kHz
4: 200Hz
199: 5Hz
499: 2Hz
999: 1Hz
1999: 0.5Hz
4999: 0.2Hz
9999: 0.1Hz

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AL
ISINK0_CO
080E ISINK0 Control Register 1 0000
N1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ISINK_CH0_ST
Name EP
ISINK_DIM0_DUTY

TI
Type RW RW
Reset 0 0 0 0 0 0 0 0

Bit(s) Name Description

EN
14:12 ISINK_CH0_STEP Coarse 6 step current level for ISINK CH0
000: 4mA
001: 8mA
010: 12mA
011: 16mA
100: 20mA
101: 24mA
110: 24mA
111: 24mA
ID
NF
11:7 ISINK_DIM0_DUT ISINK ON-duty of dimming0 control
Y N: (N+1)/32
0: 1/32
1: 2/32
2: 3/32
CO

31: 32/32

ISINK0_CO
0810 ISINK0 Control Register 2 0000
N2
K

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ISINK_BREATH0_TR1 ISINK_BREATH0_TR ISINK_BREATH0_TF1 ISINK_BREATH0_TF2
Name
TE

_SEL 2_SEL _SEL _SEL

Type RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit(s) Name Description

15:12 ISINK_BREATH0_ Selects ISINK0 breath mode rising time for duty 0%~30%
TR1_SEL 0: 0.123s
1: 0.338s
2: 0.523s
ED

3: 0.707s
4: 0.926s
5: 1.107s
6: 1.291s
7: 1.507s
M

8: 1.691s
9: 1.876s
10: 2.091s
11: 2.276s
12: 2.460s
13: 2.676s
14: 2.860s
15: 3.075s

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Bit(s) Name Description

11:8 ISINK_BREATH0_ Selects ISINK0 breath mode rising time for duty 31%~100%
TR2_SEL 0: 0.123s

AL
1: 0.338s
2: 0.523s
3: 0.707s
4: 0.926s
5: 1.107s

TI
6: 1.291s
7: 1.507s
8: 1.691s
9: 1.876s

EN
10: 2.091s
11: 2.276s
12: 2.460s
13: 2.676s
14: 2.860s
15: 3.075s
7:4 ISINK_BREATH0_
TF1_SEL 0: 0.123s
1: 0.338s
2: 0.523s
ID
Selects ISINK0 breath mode falling time for duty 0%~30%
NF
3: 0.707s
4: 0.926s
5: 1.107s
6: 1.291s
7: 1.507s
CO

8: 1.691s
9: 1.876s
10: 2.091s
11: 2.276s
12: 2.460s
13: 2.676s
14: 2.860s
K

15: 3.075s
3:0 ISINK_BREATH0_ Selects ISINK0 breath mode falling time for duty 31%~100%
TF2_SEL 0: 0.123s
TE

1: 0.338s
2: 0.523s
3: 0.707s
4: 0.926s
5: 1.107s
IA

6: 1.291s
7: 1.507s
8: 1.691s
9: 1.876s
10: 2.091s
ED

11: 2.276s
12: 2.460s
13: 2.676s
14: 2.860s
15: 3.075s
M

ISINK0_CO
0812 ISINK0 Control Register 3 0000
N3
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name ISINK_BREATH0_TO ISINK_BREATH0_TO

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N_SEL FF_SEL
Type RW RW
Reset 0 0 0 0 0 0 0 0

AL
Bit(s) Name Description
11:8 ISINK_BREATH0_ Selects ISINK0 breath mode Ton time
TON_SEL 0: 0.123s
1: 0.338s

TI
2: 0.523s
3: 0.707s
4: 0.926s
5: 1.107s

EN
6: 1.291s
7: 1.507s
8: 1.691s
9: 1.876s
10: 2.091s
11: 2.276s
12: 2.460s
13: 2.676s
14: 2.860s
15: 3.075s
ID
NF
3:0 ISINK_BREATH0_ Selects ISINK0 breath mode Toff time
TOFF_SEL 0: 0.246s
1: 0.677s
2: 1.046s
3: 1.417s
CO

4: 1.845s
5: 2.214s
6: 2.583s
7: 3.014s
8: 3.383s
9: 3.752s
10: 4.183s
K

11: 4.552s
12: 4.921s
13: 5.351s
TE

14: 5.720s
15: 6.151s
IA

ISINK1_CON
0814 ISINK1 Control Register 0 0000
0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ED

Name ISINK_DIM1_FSEL
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit(s) Name Description

15:0 ISINK_DIM1_FSEL Selects ISINK1 dimming frequency

Backlight: (@2MHz)
2: 20kHz
61: 1kHz
311: 200Hz
12499: 5Hz
31249: 2Hz
62499: 1Hz

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Bit(s) Name Description

Indicator: (@32kHz)
0: 1kHz

AL
4: 200Hz
199: 5Hz
499: 2Hz
999: 1Hz
1999: 0.5Hz
4999: 0.2Hz

TI
9999: 0.1Hz

EN
ISINK1_CON
0816 ISINK1 Control Register 1 0000
1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ISINK_CH1_STE
Name
Type
Reset 0
P
RW
0 0 0
ISINK_DIM1_DUTY

0
RW
0 ID 0 0
NF
Bit(s) Name Description
14:12 ISINK_CH1_STEP Coarse 6 step current level for ISINK CH1
000: 4mA
001: 8mA
CO

010: 12mA
011: 16mA
100: 20mA
101: 24mA
110: 24mA
111: 24mA
11:7 ISINK_DIM1_DUT ISINK ON-duty of dimming1 control
K

Y N: (N+1)/32
0: 1/32
1: 2/32
TE

2: 3/32
31: 32/32
IA

ISINK1_CON
0818 ISINK1 Control Register 2 0000
2
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ED

ISINK_BREATH1_TR1 ISINK_BREATH1_TR2 ISINK_BREATH1_TF1 ISINK_BREATH1_TF2

Name
_SEL _SEL _SEL _SEL
Type RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
M

Bit(s) Name Description

15:12 ISINK_BREATH1_T Selects ISINK1 breath mode rising time for duty 0%~30%
R1_SEL 0: 0.123s
1: 0.338s
2: 0.523s
3: 0.707s
4: 0.926s
5: 1.107s

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Bit(s) Name Description

6: 1.291s
7: 1.507s

AL
8: 1.691s
9: 1.876s
10: 2.091s
11: 2.276s
12: 2.460s
13: 2.676s

TI
14: 2.860s
15: 3.075s
11:8 ISINK_BREATH1_T Selects ISINK1 breath mode rising time for duty 31%~100%

EN
R2_SEL 0: 0.123s
1: 0.338s
2: 0.523s
3: 0.707s
4: 0.926s
5: 1.107s
6: 1.291s
7: 1.507s
8: 1.691s
9: 1.876s
ID
NF
10: 2.091s
11: 2.276s
12: 2.460s
13: 2.676s
14: 2.860s
15: 3.075s
CO

7:4 ISINK_BREATH1_T Selects ISINK1 breath mode falling time for duty 0%~30%
F1_SEL 0: 0.123s
1: 0.338s
2: 0.523s
3: 0.707s
4: 0.926s
K

5: 1.107s
6: 1.291s
7: 1.507s
TE

8: 1.691s
9: 1.876s
10: 2.091s
11: 2.276s
12: 2.460s
13: 2.676s
IA

14: 2.860s
15: 3.075s
3:0 ISINK_BREATH1_T Selects ISINK1 breath mode falling time for duty 31%~100%
F2_SEL 0: 0.123s
ED

1: 0.338s
2: 0.523s
3: 0.707s
4: 0.926s
5: 1.107s
M

6: 1.291s
7: 1.507s
8: 1.691s
9: 1.876s
10: 2.091s
11: 2.276s
12: 2.460s
13: 2.676s
14: 2.860s

MediaTek Confidential © 2015 MediaTek Inc. Page 146 of 304

Bit(s) Name Description

15: 3.075s

AL
ISINK1_CON
081A ISINK1 Control Register 3 0000
3

TI
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ISINK_BREATH1_TO ISINK_BREATH1_TOF
Name N_SEL F_SEL
Type RW RW

EN
Reset 0 0 0 0 0 0 0 0

Bit(s) Name Description

11:8 ISINK_BREATH1_T Selects ISINK1 breath mode Ton time
ON_SEL 0: 0.123s
1: 0.338s
2: 0.523s
3: 0.707s
4: 0.926s
ID
NF
5: 1.107s
6: 1.291s
7: 1.507s
8: 1.691s
9: 1.876s
CO

10: 2.091s
11: 2.276s
12: 2.460s
13: 2.676s
14: 2.860s
15: 3.075s
3:0 ISINK_BREATH1_T Selects ISINK1 breath mode Toff time
K

OFF_SEL 0: 0.246s
1: 0.677s
2: 1.046s
TE

3: 1.417s
4: 1.845s
5: 2.214s
6: 2.583s
7: 3.014s
IA

8: 3.383s
9: 3.752s
10: 4.183s
11: 4.552s
12: 4.921s
ED

13: 5.351s
14: 5.720s
15: 6.151s
M

ISINK2_CO
081C ISINK2 Control Register 1 0000
N1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ISINK_CH2_ST
Name
EP
Type RW

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Reset 0 0 0

Bit(s) Name Description

AL
14:12 ISINK_CH2_STEP Coarse 6 step current level for ISINK CH2
000: 4mA
001: 8mA
010: 12mA
011: 16mA

TI
100: 20mA
101: 24mA
110: 24mA
111: 24mA

EN
ISINK3_CO
081E ISINK3 Control Register 1 0000

Bit
Name
15
N1
14 13
ISINK_CH3_ST
EP
12 11 10 9
ID 8 7 6 5 4 3 2 1 0
NF
Type RW
Reset 0 0 0

Bit(s) Name Description

14:12 ISINK_CH3_STEP Coarse 6 step current level for ISINK CH3

000: 4mA
001: 8mA
010: 12mA
011: 16mA
100: 20mA
101: 24mA
K

110: 24mA
111: 24mA
TE

ISINK_PHA
0824 ISINK PHASE DELAY 0000
SE_DLY
IA

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ISIN ISIN
K_P K_P
ISINK_PH
HAS HAS
Name ASE_DLY_
E1_ E0_
ED

TC
DLY DLY
_EN _EN
Type RW RW RW
Reset 0 0 0 0
M

Bit(s) Name Description

5:4 ISINK_PHASE_DL Selects ISINK channel backlight phase delay
Y_TC Freq: 2MHz/32kHz
2'b00: 1T (0.5us/31.25us)
2'b01: 2T (1us/62.5us)
2'b10: 3T (1.5us/93.75us)
2'b11: 4T (2us/125us)

MediaTek Confidential © 2015 MediaTek Inc. Page 148 of 304

Bit(s) Name Description

1 ISINK_PHASE1_DL Controls ISINK1 phase delay
Y_EN 1'b1: Enable phase delay

AL
1'b0: Disable
0 ISINK_PHASE0_D Controls ISINK0 phase delay
LY_EN 1'b1: Enable phase delay
1'b0: Disable

TI
ISINK_SFST

EN
0826 ISINK Soft Start 0000
R
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ISIN ISIN
K_S K_S
ISINK_SFS ISINK_SFS
Name FST FST
TR0_TC TR1_TC

Type
Reset 0
RW
0
R0_
EN
RW
0 0
RW
0
R1_
EN
RW
0
ID
NF
Bit(s) Name Description
14:13 ISINK_SFSTR0_TC Controls ISINK0 soft start timing step
Freq: 2MHz/32kHz
2'b00: 1T (0.5us/31.25us)
CO

2'b01: 2T (1us/62.5us)
2'b10: 3T (1.5us/93.75us)
2'b11: 4T (2us/125us)
12 ISINK_SFSTR0_EN Controls ISINK0 soft start
1'b1: Enable after start current step
1'b0: Disable
K

10:9 ISINK_SFSTR1_TC Controls ISINK1 soft start timing step

Freq: 2MHz/32kHz
2'b00: 1T (0.5us/31.25us)
TE

2'b01: 2T (1us/62.5us)
2'b10: 3T (1.5us/93.75us)
2'b11: 4T (2us/125us)
8 ISINK_SFSTR1_EN Controls ISINK1 soft start
IA

1'b1: Enable after start current step

1'b0: Disable
ED

ISINK_EN_C
0828 ISINK Enable Control 0000
TRL
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ISIN ISIN ISIN ISIN ISIN ISIN ISIN ISIN
M

ISIN ISIN ISIN ISIN

K_C K_C K_C K_C K_C K_C K_C K_C
K_C K_C K_C K_C
Name H3_ H2_ H1_ H0_ HOP HOP HOP HOP
H3_ H2_ H1_ H0_
BIAS BIAS BIAS BIAS 3_E 2_E 1_E 0_E
EN EN EN EN
_EN _EN _EN _EN N N N N
Type RW RW RW RW RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0

Bit(s) Name Description

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Bit(s) Name Description

11 ISINK_CH3_BIAS_ Enables ISINK Channel 3 bias CLK
EN 1'b0: Disable

AL
1'b1: Enable
10 ISINK_CH2_BIAS_ Enables ISINK Channel 2 CHOP CLK
EN 1'b0: Disable
1'b1: Enable

TI
9 ISINK_CH1_BIAS_ Enables ISINK Channel 1 CHOP CLK
EN 1'b0: Disable
1'b1: Enable
8 ISINK_CH0_BIAS_ Enables ISINK Channel 0 CHOP CLK

EN
EN 1'b0: Disable
1'b1: Enable
7 ISINK_CHOP3_EN Enables ISINK Channel 3 CHOP CLK
1'b0: Disable
1'b1: Enable
6 ISINK_CHOP2_EN
ID
Enables ISINK Channel 2 CHOP CLK
1'b0: Disable
1'b1: Enable
NF
5 ISINK_CHOP1_EN Enables ISINK Channel 1 CHOP CLK
1'b0: Disable
1'b1: Enable
4 ISINK_CHOP0_EN Enables ISINK Channel 0 CHOP CLK
1'b0: Disable
CO

1'b1: Enable
3 ISINK_CH3_EN Turns on ISINK Channel 3
1'b0: Disable
1'b1: Enable
2 ISINK_CH2_EN Turns on ISINK Channel 2
1'b0: Disable
K

1'b1: Enable
1 ISINK_CH1_EN Turns on ISINK Channel 1
TE

1'b0: Disable
1'b1: Enable
0 ISINK_CH0_EN Turns on ISINK Channel 0
1'b0: Disable
1'b1: Enable
IA

ISINK_MOD
ED

082A ISINK Mode Control 0000

E_CTRL
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ISINK_CH ISINK_CH1
Name 0_MODE _MODE
M

Type RW RW
Reset 0 0 0 0

Bit(s) Name Description

15:14 ISINK_CH0_MODE Selects ISINK Channel 0 enable mode
2'b00: PWM mode
2'b01: Breath mode

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Bit(s) Name Description

2'b10: Register mode
2'b11: Register mode

AL
13:12 ISINK_CH1_MODE Selects ISINK Channel 1 enable mode
2'b00: PWM mode
2'b01: Breath mode
2'b10: Register mode
2'b11: Register mode

TI
EN
VTCXO_0_C
0A00 VTCXO_0 Control Register 0 8102
ON0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RG_ RG_
QI_ RG_ RG_
QI_ QI_ QI_ VTC RG_ VTC
VTC VTC VTC

ID
VTC VTC VTC XO_ VTC XO_
XO_ XO_ XO_
Name XO_ XO_ XO_ 0_M XO_ 0_M
0_O 0_O 0_O
0_E 0_S 0_M ODE 0_E ODE
CFB CFB N_C
N TB ODE _CT N _SE
_EN _EN TRL
RL T
NF
Type RO RO RO RW RO RW RW RW RW
Reset 1 0 0 0 0 0 0 1 0

Bit(s) Name Description

15 QI_VTCXO_0_EN VTCXO0 enable status

1'b1: Enable
1'b0: Disable
14 QI_VTCXO_0_STB VTCXO0 soft-start status
11 QI_VTCXO_0_OCF OCFB status
B_EN 1'b1: Over current occurs.
K

1'b0: No over current occurs.

10 RG_VTCXO_0_OC OCFB Enable
FB_EN 1'b1: Enable
TE

1'b0: Disable
7 QI_VTCXO_0_MO VTCXO0 low power mode status
DE 1'b0: Normal mode
1'b1: Low power mode
IA

3 RG_VTCXO_0_ON VTCXO0 enable control

_CTRL 1'b0: SW control by RG_VTCXO_0_EN
1'b1: HW control by SRCLKEN
2 RG_VTCXO_0_MO VTCXO0 low power mode control
ED

DE_CTRL 1'b0: SW control by VTCXO0_MODE_SET

1'b1: HW control by SRCLKEN
1 RG_VTCXO_0_EN VTCXO0 enable
1'b1: Dnable
1'b0: Disable
M

0 RG_VTCXO_0_MO VTCXO0 low power mode

DE_SET 1'b0: Normal mode
1'b1: Low power mode

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VTCXO_1_C
0A02 VTCOX_1 Control Register 0 2120
ON0

AL
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RG_ RG_
QI_ RG_ RG_
QI_ QI_ QI_ VTC RG_ VTC
VTC VTC VTC
VTC VTC VTC XO_ VTC XO_
XO_ XO_ XO_
Name XO_ XO_ 1_O 1_O
XO_
1_O
1_M XO_ 1_M
1_E 1_ST 1_M ODE 1_E ODE
CFB CFB N_C

TI
N B ODE _CT N _SE
_EN _EN TRL
RL T
Type RO RO RO RW RO RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0

EN
Bit(s) Name Description
15 QI_VTCXO_1_EN VTCXO1 enable status
1'b1: Enable
1'b0: Disable
14
11
QI_VTCXO_1_STB
QI_VTCXO_1_OCF
B_EN
VTCXO1 soft-start status
OCFB status
1'b1: Over current occurs.
ID
NF
1'b0: No over current occurs.
10 RG_VTCXO_1_OCF OCFB Enable
B_EN 1'b1: Enable
1'b0: Disable
7 QI_VTCXO_1_MOD VTCXO1 low power mode status
CO

E 1'b0: Normal mode

1'b1: Low power mode
3 RG_VTCXO_1_ON VTCXO1 enable control
_CTRL 1'b0: SW control by RG_VTCXO2_EN
1'b1: HW control by SRCLKEN
K

2 RG_VTCXO_1_MO VTCXO1 low power mode control

DE_CTRL 1'b0: SW control by VTCXO1_MODE_SET
1'b1: HW control by SRCLKEN
TE

1 RG_VTCXO_1_EN VTCXO1 enable

1'b1: Enable
1'b0: Disable
0 RG_VTCXO_1_MO VTCXO1 low power mode
DE_SET
IA

1'b0: Normal mode

1'b1: Low power mode
ED

VAUD28_CO
0A04 VAUD28 Control Register 0 8102
N0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RG_
M

QI_ RG_ RG_ RG_

QI_ QI_ VAU
QI_ VAU VAU VAU RG_ VAU
VAU VAU D28
VAU D28 D28 D28 VAU D28
Name D28 D28 _OC _OC
D28
_ON
_MO
D28 _MO
_ST _MO DE_
_EN FB_ FB_ _CT _EN DE_
B DE CTR
EN EN RL SET
L
Type RO RO RO RW RO RW RW RW RW
Reset 1 0 0 0 0 0 0 1 0

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Bit(s) Name Description

15 QI_VAUD28_EN VAUD28 enable status
1'b1: Enable

AL
1'b0: Disable
14 QI_VAUD28_STB VAUD28 soft-start status
11 QI_VAUD28_OCFB OCFB status
_EN 1'b1: Over current occurs.

TI
1'b0: No over current occurs.
10 RG_VAUD28_OCF OCFB Enable
B_EN 1'b1: Enable
1'b0: Disable

EN
7 QI_VAUD28_MOD VAUD28 low power mode status
E 1'b0: Normal mode
1'b1: Low power mode
3 RG_VAUD28_ON_ VAUD28 enable control

2
CTRL

RG_VAUD28_MOD
E_CTRL
ID
1'b0: SW control by RG_VAUD28_EN
1'b1: HW control by SRCLKEN
VAUD28 low power mode control
1'b0: SW control by VAUD28_MODE_SET
NF
1'b1: HW control by SRCLKEN
1 RG_VAUD28_EN Enables VAUD28
1'b1: Enable
1'b0: Disable
0 RG_VAUD28_MOD VAUD28 low power mode
CO

E_SET 1'b0: Normal mode

1'b1: Low power mode

VAUX18_CO
K

0A06 VAUX18 Control Register 0 8102

N0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TE

QI_ RG_ RG_ RG_ RG_

QI_
QI_ QI_ VAU VAU VAU VAU RG_ VAU
VAU
VAU VAU X18_ X18_ X18_ X18_ VAU X18_
Name X18_
X18_ X18_ OCF OCF ON_ MOD X18_ MOD
MOD
EN STB B_E B_E CTR E_C EN E_S
E
N N L TRL ET
IA

Type RO RO RO RW RO RW RW RW RW
Reset 1 0 0 0 0 0 0 1 0
ED

Bit(s) Name Description

15 QI_VAUX18_EN VAUX18 enable status
1'b1: Enable
1'b0: Disable
14 QI_VAUX18_STB VAUX18 soft-start status
M

11 QI_VAUX18_OCFB OCFB status

_EN 1'b1: Over current occurs.
1'b0: No over current occurs.
10 RG_VAUX18_OCFB Enables OCFB
_EN 1'b1: Enable
1'b0: Disable
7 QI_VAUX18_MOD VAUX18 low power mode status

MediaTek Confidential © 2015 MediaTek Inc. Page 153 of 304

Bit(s) Name Description

E 1'b0: Normal mode
1'b1: Low power mode

AL
3 RG_VAUX18_ON_ VAUX18 enable control
CTRL 1'b0: SW control by RG_VAUXA28_EN
1'b1: HW control by SRCLKEN
2 RG_VAUX18_MOD VAUX18 low power mode control
E_CTRL

TI
1'b0: SW control by VAUXA28_MODE_SET
1'b1: HW control by SRCLKEN
1 RG_VAUX18_EN Enables VAUX18
1'b1: Enable

EN
1'b0: Disable
0 RG_VAUX18_MOD VAUX18 low power mode
E_SET 1'b0: Normal mode
1'b1: Low power mode

0A08
VRF18_0_C
ON0
VRF18_0 Control Register 0
ID 0100
NF
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RG_
QI_ RG_ RG_ RG_
QI_ QI_ VRF
QI_ VRF VRF VRF1 RG_ VRF
VRF VRF 18_0
Name VRF 18_0 18_0 18_0
18_0
8_0
_MO
VRF 18_0
CO

18_0 _OC _OC _ON 18_0 _MO

_ST _MO DE_
_EN FB_ FB_ _CT _EN DE_
B DE CTR
EN EN RL SET
L
Type RO RO RO RW RO RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0
K

Bit(s) Name Description

15 QI_VRF18_0_EN VRF18_0 enable status
1'b1: Enable
TE

1'b0: Disable
14 QI_VRF18_0_STB VRF18_0 soft-start status
11 QI_VRF18_0_OCF OCFB status
B_EN 1'b1: Over current occurs.
IA

1'b0: No over current occurs.

10 RG_VRF18_0_OCF Enables OCFB
B_EN 1'b1: Enable
1'b0: Disable
ED

7 QI_VRF18_0_MOD VRF18_0 low power mode status

E 1'b0: Normal mode
1'b1: Low power mode
3 RG_VRF18_0_ON_ VRF18_0 enable control
M

CTRL 1'b0: SW control by RG_VBIF28_EN

1'b1: HW control by SRCLKEN
2 RG_VRF18_0_MO VRF18_0 low power mode control
DE_CTRL 1'b0: SW control by VBIF28_MODE_SET
1'b1: HW control by SRCLKEN
1 RG_VRF18_0_EN Enables VRF18_0
1'b1: Enable

MediaTek Confidential © 2015 MediaTek Inc. Page 154 of 304

Bit(s) Name Description

1'b0: Disable
0 RG_VRF18_0_MO VRF18_0 low power mode

AL
DE_SET 1'b0: Normal mode
1'b1: Low power mode

TI
VRF18_0_C
0A0A VRF18_0 Control Register 1 5000
ON1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

EN
QI_ RG_
VRF VRF
18_0 18_0
_FA _FA
Name ST_ ST_
TRA TRA

Type
Reset
N_E
N
RO
0
N_E
N
RW
1
ID
NF
Bit(s) Name Description
15 QI_VRF18_0_FAST Fast transient enable status
_TRAN_EN
CO

12 RG_VRF18_0_FAS Enables fast transient

T_TRAN_EN 1'b1: Enable
1'b0: Disable
K

VCAMA_CO
0A0C VCAMA Control Register 0 0100
N0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TE

QI_ RG_
QI_ QI_ VCA VCA RG_
VCA VCA MA_ MA_ VCA
Name MA_ MA_ OCF OCF MA_
EN STB B_E B_E EN
IA

N N
Type RO RO RO RW RW
Reset 0 0 0 0 0
ED

Bit(s) Name Description

15 QI_VCAMA_EN Enables VCAMA
1'b1: Enable
1'b0: Disable
M

14 QI_VCAMA_STB VCAMA soft-start status

11 QI_VCAMA_OCFB_ OCFB status
EN 1'b1: Over current occurs.
1'b0: No over current occurs.
10 RG_VCAMA_OCFB Enables OCFB
_EN 1'b1: Enable
1'b0: Disable

MediaTek Confidential © 2015 MediaTek Inc. Page 155 of 304

Bit(s) Name Description

1 RG_VCAMA_EN Enables VCAMA
1'b1: Enable

AL
1'b0: Disable

TI
VCN28_CON
0A0E VCN28 Control Register 0 0100
0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
QI_ RG_ RG_ RG_ RG_

EN
QI_
QI_ QI_ VCN VCN VCN VCN RG_ VCN
VCN
VCN VCN 28_ 28_ 28_ 28_ VCN 28_
Name 28_ 28_S OCF OCF
28_
ON_ MOD 28_ MOD
MOD
EN TB B_E B_E CTR E_C EN E_S
E
N N L TRL ET
Type RO RO RO RW RO RW RW RW RW
Reset

Bit(s)
0

Name
0 0 0

Description
ID 0 0 0 0 0
NF
15 QI_VCN28_EN VCN28 enable status
1'b1: Enable
1'b0: Disable
14 QI_VCN28_STB VCN28 soft-start status
CO

11 QI_VCN28_OCFB_ OCFB status

EN 1'b1: Over current occurs.
1'b0: No over current occurs.
10 RG_VCN28_OCFB_ Enables OCFB
EN 1'b1: Enable
1'b0: Disable
K

7 QI_VCN28_MODE VCN28 low power mode status

1'b0: Normal mode
1'b1: Low power mode
TE

3 RG_VCN28_ON_C VCN28 enable control

TRL 1'b0: SW control by RG_VCN28_EN
1'b1: HW control by SRCLKEN
2 RG_VCN28_MODE VCN28 low power mode control
_CTRL
IA

1'b0: SW control by VCN28_MODE_SET

1'b1: HW control by SRCLKEN
1 RG_VCN28_EN Enables VCN28
1'b1: Enable
ED

1'b0: Disable
0 RG_VCN28_MODE VCN28 low power mode
_SET 1'b0: Normal mode
1'b1: Low power mode
M

VCN33_CON
0A10 VCN33 Control Register 0 0100
0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
QI_ QI_ QI_ RG_ QI_ RG_ RG_
Name
VCN VCN VCN VCN VCN VCN VCN

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33_E 33_S 33_ 33_ 33_ 33_ 33_

N TB OCF OCF MOD MOD MOD
B_E B_E E E_C E_S
N N TRL ET

AL
Type RO RO RO RW RO RW RW
Reset 0 0 0 0 0 0 0

Bit(s) Name Description

TI
15 QI_VCN33_EN VCN33 enable status
1'b1: Enable
1'b0: Disable
14 QI_VCN33_STB VCN33 soft-start status

EN
11 QI_VCN33_OCFB_ OCFB status
EN 1'b1: Over current occurs.
1'b0: No over current occurs.
10 RG_VCN33_OCFB_ Enables OCFB

7
EN

QI_VCN33_MODE
1'b1: Enable
1'b0: Disable
VCN33 low power mode status
1'b0: Normal mode
ID
NF
1'b1: Low power mode
2 RG_VCN33_MODE VCN33 low power mode control
_CTRL 1'b0: SW control by VCN33_MODE_SET
1'b1: HW control by SRCLKEN
CO

0 RG_VCN33_MODE VCN33 low power mode

_SET 1'b0: Normal mode
1'b1: Low power mode
K

VCN33_CON
0A12 VCN33 Control Register 1 0000
1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TE

RG_
VCN RG_
RG_VCN33
33_ VCN
_SRCLK_E
Name ON_ 33_E
N_SEL_WI
CTR N_W
FI
L_W IFI
IA

IFI
Type RW RW RW
Reset 0 0 0 0
ED

Bit(s) Name Description

13:12 RG_VCN33_SRCLK Selects HW srclk enable
_EN_SEL_WIFI 2'b00: SRCLKEN_IN0
2'b01: SRCLKEN_IN1
M

2'b10: SRCLKEN_IN0 or SRCLKEN_IN1

2'b11: SRCLKEN_IN0 and SRCLKEN_IN1
3 RG_VCN33_ON_C VCN33 enable control
TRL_WIFI 1'b0: SW control by RG_VCN33_EN
1'b1: HW control by SRCLKEN
1 RG_VCN33_EN_W Enables VCN33
IFI 1'b1: Enable

MediaTek Confidential © 2015 MediaTek Inc. Page 157 of 304

Bit(s) Name Description

1'b0: Disable

AL
VCN33_CON
0A14 VCN33 Control Register 2 0000
2

TI
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RG_
VCN RG_
RG_VCN33 33_ VCN
Name _SRCLK_E ON_ 33_E

EN
N_SEL_BT CTR N_B
L_B T
T
Type RW RW RW
Reset 0 0 0 0

Bit(s)
13:12
Name
RG_VCN33_SRCLK
_EN_SEL_BT
Description
Selects HW srclk enable
ID
NF
2'b00: SRCLKEN_IN0
2'b01: SRCLKEN_IN1
2'b10: SRCLKEN_IN0 or SRCLKEN_IN1
2'b11: SRCLKEN_IN0 and SRCLKEN_IN1
3 RG_VCN33_ON_C VCN33 BT enable control
CO

TRL_BT 1'b0: SW control by RG_VCN33_EN

1'b1: HW control by SRCLKEN
1 RG_VCN33_EN_BT Enables VCN33 BT
1'b1: Enable
1'b0: Disable
K

VRF18_1_CO
TE

0A16 VRF18_1 Control Register 0 0100

N0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RG_
QI_ RG_ RG_ RG_
QI_ QI_ VRF
QI_ VRF VRF VRF1 RG_ VRF
VRF VRF 18_1
IA

VRF 18_1 18_1 8_1_ VRF 18_1

Name 18_1 18_1 _OC _OC
18_1
ON_
_MO
18_1 _MO
_ST _MO DE_
_EN FB_ FB_ CTR _EN DE_
B DE CTR
EN EN L SET
L
Type RO RO RO RW RO RW RW RW RW
ED

Reset 0 0 0 0 0 0 0 0 0

Bit(s) Name Description

15 QI_VRF18_1_EN VRF18_1 enable status
M

1'b1: Enable
1'b0: Disable
14 QI_VRF18_1_STB VRF18_1 soft-start status
11 QI_VRF18_1_OCFB OCFB status
_EN 1'b1: Over current occurs.
1'b0: No over current occurs.
10 RG_VRF18_1_OCF Enables OCFB

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Bit(s) Name Description

B_EN 1'b1: Enable
1'b0: Disable

AL
7 QI_VRF18_1_MOD VRF18_1 low power mode status
E 1'b0: Normal mode
1'b1: Low power mode
3 RG_VRF18_1_ON_ VRF18_1 enable control
CTRL

TI
1'b0: SW control by RG_VRF18_1_EN
1'b1: HW control by SRCLKEN
2 RG_VRF18_1_MOD VRF18_1 low power mode control
E_CTRL 1'b0: SW control by VRF18_1_MODE_SET

EN
1'b1: HW control by SRCLKEN
1 RG_VRF18_1_EN Enables VRF18_1
1'b1: Enable
1'b0: Disable
0 RG_VRF18_1_MOD VRF18_1 low power mode
E_SET 1'b0: Normal mode
1'b1: Low power mode ID
NF
VRF18_1_CO
0A18 VRF18_1 Control Register 1 5000
N1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CO

QI_ RG_
VRF VRF
18_1 18_1
_FA _FA
Name ST_ ST_
TRA TRA
N_E N_E
K

N N
Type RO RW
Reset 0 1
TE

Bit(s) Name Description

15 QI_VRF18_1_FAST Fast transient enable status
_TRAN_EN
IA

12 RG_VRF18_1_FAST Enables fast transient

_TRAN_EN 1'b1: Enable
1'b0: Disable
ED

VUSB33_CO
0A1A USB33 Control Register 0 8102
N0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M

RG_
QI_ RG_ RG_ RG_
QI_ QI_ VUS
QI_ VUS VUS VUS RG_ VUS
VUS VUS B33
VUS B33 B33 B33_ VUS B33_
Name B33
B33
_OC _OC
B33
ON_
_MO
B33 MOD
_ST _MO DE_
_EN FB_ FB_ CTR _EN E_S
B DE CTR
EN EN L ET
L
Type RO RO RO RW RO RW RW RW RW
Reset 1 0 0 0 0 0 0 1 0

MediaTek Confidential © 2015 MediaTek Inc. Page 159 of 304

Bit(s) Name Description

AL
15 QI_VUSB33_EN VUSB33 enable status
1'b1: Enable
1'b0: Disable
14 QI_VUSB33_STB VSUB33 soft-start status
11 QI_VUSB33_OCFB OCFB status

TI
_EN 1'b1: Over current occurs.
1'b0: No over current occurs.
10 RG_VUSB33_OCFB Enables OCFB
_EN

EN
1'b1: Enable
1'b0: Disable
7 QI_VUSB33_MODE VUSB33 low power mode status
1'b0: Normal mode
1'b1: Low power mode
3

2
RG_VUSB33_ON_C
TRL

RG_VUSB33_MOD
VUSB33 enable control

ID
1'b0: SW control by RG_VUSB33_EN
1'b1: HW control by SRCLKEN
VUSB33 low power mode control
NF
E_CTRL 1'b0: SW control by VUSB33_MODE_SET
1'b1: HW control by SRCLKEN
1 RG_VUSB33_EN Enables VUSB33
1'b1: Enable
CO

1'b0: Disable
0 RG_VUSB33_MOD VUSB33 low power mode
E_SET 1'b0: Normal mode
1'b1: Low power mode
K

VMCH_CON
0A1C VMCH Control Register 0 8102
0
TE

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RG_ RG_
QI_ RG_ RG_
QI_ QI_ QI_ VMC RG_ VMC
VMC VMC VMC
Name VMC VMC H_O H_O
VMC
H_O
H_M VMC H_M
H_E H_S H_M ODE H_E ODE
CFB CFB N_C
IA

N TB ODE _CT N _SE

_EN _EN TRL
RL T
Type RO RO RO RW RO RW RW RW RW
Reset 1 0 0 0 0 0 0 1 0
ED

Bit(s) Name Description

15 QI_VMCH_EN VMCH enable status
1'b1: Enable
1'b0: Disable
M

14 QI_VMCH_STB VMCH soft-start status

11 QI_VMCH_OCFB_ OCFB status
EN 1'b1: Over current occurs.
1'b0: No over current occurs.
10 RG_VMCH_OCFB_ Enables OCFB
EN 1'b1: Enable
1'b0: Disable

MediaTek Confidential © 2015 MediaTek Inc. Page 160 of 304

Bit(s) Name Description

7 QI_VMCH_MODE VMCH low power mode status
1'b0: Normal mode

AL
1'b1: Low power mode
3 RG_VMCH_ON_CT VMCH enable control
RL 1'b0: SW control by RG_VMCH_EN
1'b1: HW control by SRCLKEN

TI
2 RG_VMCH_MODE VMCH low power mode control
_CTRL 1'b0: SW control by VMCH_MODE_SET
1'b1: HW control by SRCLKEN
1 RG_VMCH_EN Enables VMCH

EN
1'b1: Enable
1'b0: Disable
0 RG_VMCH_MODE VMCH low power mode
_SET 1'b0: Normal mode
1'b1: Low power mode

ID
NF
VMCH_CON
0A1E VMCH Control Register 1 5000
1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
QI_ RG_
VMC VMC
CO

H_F H_F
Name AST AST
_TR _TR
AN_ AN_
EN EN
Type RO RW
Reset 0 1
K

Bit(s) Name Description

15 QI_VMCH_FAST_T Fast transient enable status

RAN_EN
12 RG_VMCH_FAST_ Enables fast transient
TRAN_EN 1'b1: Enable
1'b0: Disable
IA

0A20 VMC_CON0 VMC Control Register 0 8102

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RG_
QI_ RG_ RG_ RG_
QI_ QI_ VMC
QI_ VMC VMC VMC RG_ VMC
VMC VMC _MO
Name VMC _ST _OC _OC
_MO
_ON
DE_
VMC _MO
_EN FB_ FB_ _CT _EN DE_
M

B DE CTR
EN EN RL SET
L
Type RO RO RO RW RO RW RW RW RW
Reset 1 0 0 0 0 0 0 1 0

Bit(s) Name Description

15 QI_VMC_EN VMC enable status

MediaTek Confidential © 2015 MediaTek Inc. Page 161 of 304

Bit(s) Name Description

1'b1: Enable
1'b0: Disable

AL
14 QI_VMC_STB VMC soft-start status
11 QI_VMC_OCFB_E OCFB status
N 1'b1: Over current occurs.
1'b0: No over current occurs.

TI
10 RG_VMC_OCFB_E Enables OCFB
N 1'b1: Enable
1'b0: Disable
7 QI_VMC_MODE VMC low power mode status

EN
1'b0: Normal mode
1'b1: Low power mode
3 RG_VMC_ON_CTR VMC enable control
L 1'b0: SW control by RG_VMC_EN
1'b1: HW control by SRCLKEN
2 RG_VMC_MODE_
CTRL
VMC low power mode control
ID
1'b0: SW control by VMC_MODE_SET
1'b1: HW control by SRCLKEN
NF
1 RG_VMC_EN Enables VMC
1'b1: Enable
1'b0: Disable
0 RG_VMC_MODE_S VMC low power mode
ET 1'b0: Normal mode
CO

1'b1: Low power mode

0A22 VMC_CON1 VMC Control Register 1 001B

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RG_
VMC
Name _TR
TE

ANS
_EN
Type RW
Reset 1
IA

Bit(s) Name Description

0 RG_VMC_TRANS_ Controls pulse generation
EN 1'b0: Disable
ED

1'b1: Enable

VEMC_3V3_
M

0A24 VEMC_3V3 Control Register 0 8102

CON0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
QI_ RG_ QI_ RG_ RG_ RG_
QI_ QI_ RG_
VEM VEM VEM VEM VEM VEM
VEM VEM VEM
C_3 C_3 C_3 C_3 C_3 C_3
Name C_3 C_3 V3_ V3_ V3_ V3_ V3_
C_3
V3_
V3_ V3_ V3_
OCF OCF MOD ON_ MOD MOD
EN STB EN
B_E B_E E CTR E_C E_S

MediaTek Confidential © 2015 MediaTek Inc. Page 162 of 304

N N L TRL ET
Type RO RO RO RW RO RW RW RW RW
Reset 1 0 0 0 0 0 0 1 0

AL
Bit(s) Name Description
15 QI_VEMC_3V3_EN VEMC33 enable status
1'b1: Enable
1'b0: Disable

TI
14 QI_VEMC_3V3_ST VEMC33 soft-start status
B
11 QI_VEMC_3V3_OC OCFB status

EN
FB_EN 1'b1: Over current occurs.
1'b0: No over current occurs.
10 RG_VEMC_3V3_O Enables OCFB
CFB_EN 1'b1: Enable
1'b0: Disable
7 QI_VEMC_3V3_M
ODE
VEMC33 low power mode status
1'b0: Normal mode
1'b1: Low power mode
ID
NF
3 RG_VEMC_3V3_O VEMC33 enable control
N_CTRL 1'b0: SW control by RG_VEMC33_EN
1'b1: HW control by SRCLKEN
2 RG_VEMC_3V3_M VEMC33 low power mode control
ODE_CTRL 1'b0: SW control by VEMC33_MODE_SET
CO

1'b1: HW control by SRCLKEN

1 RG_VEMC_3V3_E Enables VEMC33
N 1'b1: Enable
1'b0: Disable
0 RG_VEMC_3V3_M VEMC33 low power mode
ODE_SET 1'b0: Normal mode
K

1'b1: Low power mode

VEMC_3V3_
0A26 VEMC_3V3 Control Register 1 5000
CON1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IA

QI_ RG_
VEM VEM
C_3 C_3
V3_ V3_
Name FAS
ED

FAS
T_T T_T
RAN RAN
_EN _EN
Type RO RW
Reset 0 1
M

Bit(s) Name Description

15 QI_VEMC_3V3_FA Fast transient enable status
ST_TRAN_EN
12 RG_VEMC_3V3_FA Enables fast transient
ST_TRAN_EN 1'b1: Enable
1'b0: Disable

MediaTek Confidential © 2015 MediaTek Inc. Page 163 of 304

AL
VIO28_CON
0A28 VIO28 Control Register 0 8122
0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RG_ RG_
QI_ RG_ RG_
QI_ QI_ QI_ VIO2 RG_ VIO2
VIO2 VIO2 VIO2

TI
VIO2 VIO2 VIO2 8_M VIO2 8_M
Name 8_E 8_S 8_O 8_O
8_M
8_O
ODE 8_E ODE
CFB CFB N_C
N TB ODE _CT N _SE
_EN _EN TRL
RL T
Type RO RO RO RW RO RW RW RW RW

EN
Reset 1 0 0 0 0 0 0 1 0

Bit(s) Name Description

15 QI_VIO28_EN VIO28 enable status

14 QI_VIO28_STB
1'b1: Enable
1'b0: Disable
VIO28 soft-start status
ID
NF
11 QI_VIO28_OCFB_ OCFB status
EN 1'b1: Over current occurs.
1'b0: No over current occurs.
10 RG_VIO28_OCFB_ Enables OCFB
EN 1'b1: Enable
CO

1'b0: Disable
7 QI_VIO28_MODE VIO28 low power mode status
1'b0: Normal mode
1'b1: Low power mode
3 RG_VIO28_ON_CT VIO28 enable control
RL 1'b0: SW control by RG_VIO28_EN
K

1'b1: HW control by SRCLKEN

2 RG_VIO28_MODE VIO28 low power mode control
_CTRL
TE

1'b0: SW control by VIO28_MODE_SET

1'b1: HW control by SRCLKEN
1 RG_VIO28_EN Enables VIO28
1'b1: Enable
1'b0: Disable
IA

0 RG_VIO28_MODE VIO28 low power mode

_SET 1'b0: Normal mode
1'b1: Low power mode
ED

VCAMAF_C
0A2A VCAMAF Control Register 0 0120
ON0
M

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RG_
QI_ RG_ RG_
QI_ QI_ VCA
QI_ VCA VCA RG_ VCA
VCA VCA MAF
VCA MAF MAF VCA MAF
Name MAF MAF _MO
MAF _OC _OC MAF _MO
_ST _MO DE_
_EN FB_ FB_ _EN DE_
B DE CTR
EN EN SET
L
Type RO RO RO RW RO RW RW RW

MediaTek Confidential © 2015 MediaTek Inc. Page 164 of 304

Reset 0 0 0 0 0 0 0 0

Bit(s) Name Description

AL
15 QI_VCAMAF_EN VCAM_AF enable status
1'b1: Enable
1'b0: Disable
14 QI_VCAMAF_STB VCAM_AF soft-start status

TI
11 QI_VCAMAF_OCFB OCFB status
_EN 1'b1: Over current occurs.
1'b0: No over current occurs.

EN
10 RG_VCAMAF_OCF Enables OCFB
B_EN 1'b1: Enable
1'b0: Disable
7 QI_VCAMAF_MOD VCAM_AF low power mode status
E 1'b0: Normal mode

2 RG_VCAMAF_MO
DE_CTRL
1'b1: Low power mode

ID
VCAM_AF low power mode control
1'b0: SW control by VCAM_AF_MODE_SET
1'b1: HW control by SRCLKEN
NF
1 RG_VCAMAF_EN Enables VCAM_AF
1'b1: Enable
1'b0: Disable
0 RG_VCAMAF_MO VCAM_AF low power mode
CO

DE_SET 1'b0: Normal mode

1'b1: Low power mode

0A2C VGP1_CON0 VGP1 Control Register 0 0100

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RG_ RG_
QI_ RG_ RG_
QI_ QI_ QI_ VGP RG_ VGP
VGP VGP VGP
TE

VGP VGP VGP 1_M VGP 1_M

Name 1_O 1_O 1_O
1_E 1_ST 1_M ODE 1_E ODE
CFB CFB N_C
N B ODE _CT N _SE
_EN _EN TRL
RL T
Type RO RO RO RW RO RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0
IA

Bit(s) Name Description

15 QI_VGP1_EN VGP1 enable status
ED

1'b1: Enable
1'b0: Disable
14 QI_VGP1_STB VGP1 soft-start status
11 QI_VGP1_OCFB_E OCFB status
N
M

1'b1: Over current occurs.

1'b0: No over current occurs.
10 RG_VGP1_OCFB_E Enables OCFB
N 1'b1: Enable
1'b0: Disable
7 QI_VGP1_MODE VGP1 low power mode status
1'b0: Normal mode
1'b1: Low power mode

MediaTek Confidential © 2015 MediaTek Inc. Page 165 of 304

Bit(s) Name Description

3 RG_VGP1_ON_CTR VGP1 enable control
L 1'b0: SW control by RG_VGP1_EN

AL
1'b1: HW control by SRCLKEN
2 RG_VGP1_MODE_ VGP1 low power mode control
CTRL 1'b0: SW control by VGP1_MODE_SET
1'b1: HW control by SRCLKEN

TI
1 RG_VGP1_EN Enables VGP1
1'b1: Enable
1'b0: Disable
0 RG_VGP1_MODE_ VGP1 low power mode

EN
SET 1'b0: Normal mode
1'b1: Low power mode

0A2E
Bit
QI_
15
VGP1_CON1
14 13
RG_
12
VGP1 Control Register 1
11 10 9 ID 8 7 6 5 4 3 2 1
5000
0
NF
VGP VGP
1_FA 1_FA
Name ST_ ST_
TRA TRA
N_E N_E
N N
CO

Type RO RW
Reset 0 1

Bit(s) Name Description

15 QI_VGP1_FAST_TR Fast transient enable status
AN_EN
K

12 RG_VGP1_FAST_T Enables fast transient

RAN_EN 1'b1: Enable
1'b0: Disable
TE

VEFUSE_CO
IA

0A30 VEFUSE Control Register 0 0100

N0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RG_
QI_ RG_ RG_
QI_ QI_ VEF
ED

QI_ VEF VEF RG_ VEF

VEF VEF USE
Nam VEF
USE
USE USE
USE _MO
VEF USE
e USE
_ST
_OC _OC
_MO DE_
USE _MO
_EN FB_ FB_ _EN DE_
B DE CTR
EN EN SET
L
Type RO RO RO RW RO RW RW RW
M

Reset 0 0 0 0 0 0 0 0

Bit(s) Name Description

15 QI_VEFUSE_EN VEFUSE enable status
1'b1: Enable
1'b0: Disable

MediaTek Confidential © 2015 MediaTek Inc. Page 166 of 304

Bit(s) Name Description

14 QI_VEFUSE_STB VEFUSE soft-start status

AL
11 QI_VEFUSE_OCFB OCFB status
_EN 1'b1: Over current occurs.
1'b0: No over current occurs.
10 RG_VEFUSE_OCFB Enables OCFB
_EN 1'b1: Enable

TI
1'b0: Disable
7 QI_VEFUSE_MOD VEFUSE low power mode status
E 1'b0: Normal mode
1'b1: Low power mode

EN
2 RG_VEFUSE_MOD VEFUSE low power mode control
E_CTRL 1'b0: SW control by VEFUSE_MODE_SET
1'b1: HW control by SRCLKEN
1 RG_VEFUSE_EN Enables VEFUSE

0 RG_VEFUSE_MOD
E_SET
1'b1: Enable
1'b0: Disable
VEFUSE low power mode
1'b0: Normal mode
ID
NF
1'b1: Low power mode

VSIM1_CON
CO

0A32 VSIM1 Control Register 0 0100

0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RG_ RG_ RG_
QI_
QI_ QI_ VSI VSI RG_ VSI
VSI
VSI VSI M1_ M1_ VSI M1_
Name M1_
M1_ M1_ ON_ MOD M1_ MOD
MOD
K

EN STB CTR E_C EN E_S

E
L TRL ET
Type RO RO RO RW RW RW RW
Reset 0 0 0 0 0 0 0
TE

Bit(s) Name Description

15 QI_VSIM1_EN VSIM1 enable status
IA

1'b1: Enable
1'b0: Disable
14 QI_VSIM1_STB VSIM1 soft-start status
7 QI_VSIM1_MODE VSIM1 low power mode status
ED

1'b0: Normal mode

1'b1: Low power mode
3 RG_VSIM1_ON_CT VSIM1 enable control
RL 1'b0: SW control by RG_VSIM1_EN
1'b1: HW control by SRCLKEN
M

2 RG_VSIM1_MODE VSIM1 low power mode control

_CTRL 1'b0: SW control by VSIM1_MODE_SET
1'b1: HW control by SRCLKEN
1 RG_VSIM1_EN Enables VSIM1
1'b1: Enable
1'b0: Disable
0 RG_VSIM1_MODE VSIM1 low power mode

MediaTek Confidential © 2015 MediaTek Inc. Page 167 of 304

Bit(s) Name Description

_SET 1'b0: Normal mode
1'b1: Low power mode

AL
VSIM2_CON
0A34 VSIM2 Control Register 0 0100
0

TI
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
QI_ RG_ RG_ RG_ RG_
QI_
QI_ QI_ VSI VSI VSI VSI RG_ VSI
VSI

EN
VSI VSI M2_ M2_ M2_ M2_ VSI M2_
Name M2_ M2_ OCF OCF
M2_
ON_ MOD M2_ MOD
MOD
EN STB B_E B_E CTR E_C EN E_S
E
N N L TRL ET
Type RO RO RO RW RO RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0

Bit(s)
15
Name
QI_VSIM2_EN
Description
VSIM2 enable status
ID
NF
1'b1: Enable
1'b0: Disable
14 QI_VSIM2_STB VSIM2 soft-start status
11 QI_VSIM2_OCFB_ OCFB status
EN 1'b1: Over current occurs.
CO

1'b0: No over current occurs.

10 RG_VSIM2_OCFB_ Enables OCFB
EN 1'b1: Enable
1'b0: Disable
7 QI_VSIM2_MODE VSIM2 low power mode status
K

1'b0: Normal mode

1'b1: Low power mode
3 RG_VSIM2_ON_CT VSIM2 enable control
TE

RL 1'b0: SW control by RG_VSIM2_EN

1'b1: HW control by SRCLKEN
2 RG_VSIM2_MODE VSIM2 low power mode control
_CTRL 1'b0: SW control by VSIM2_MODE_SET
1'b1: HW control by SRCLKEN
IA

1 RG_VSIM2_EN Enables VSIM2

1'b1: Enable
1'b0: Disable
ED

0 RG_VSIM2_MODE VSIM2 low power mode

_SET 1'b0: Normal mode
1'b1: Low power mode
M

VIO18_CON
0A36 VIO18 Control Register 0 8102
0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
QI_ QI_ QI_ RG_ QI_ RG_ RG_ RG_ RG_
VIO1 VIO1 VIO1 VIO1 VIO1 VIO1 VIO1 VIO1 VIO1
Name 8_E 8_S 8_O 8_O 8_M 8_O 8_M 8_E 8_M
N TB CFB CFB ODE N_C ODE N ODE

MediaTek Confidential © 2015 MediaTek Inc. Page 168 of 304

_EN _EN TRL _CT _SE

RL T
Type RO RO RO RW RO RW RW RW RW
Reset 1 0 0 0 0 0 0 1 0

AL
Bit(s) Name Description
15 QI_VIO18_EN VIO18 enable status
1'b1: Enable

TI
1'b0: Disable
14 QI_VIO18_STB VIO18 soft-start status
11 QI_VIO18_OCFB_E OCFB status

EN
N 1'b1: Over current occurs.
1'b0: No over current occurs.
10 RG_VIO18_OCFB_ Enables OCFB
EN 1'b1: Enable
1'b0: Disable
7 QI_VIO18_MODE VIO18 low power mode status
1'b0: Normal mode
1'b1: Low power mode
ID
NF
3 RG_VIO18_ON_CT VIO18 enable control
RL 1'b0: SW control by RG_VAUD28_EN
1'b1: HW control by SRCLKEN
2 RG_VIO18_MODE_ VIO18 low power mode control
CTRL 1'b0: SW control by VAUD28_MODE_SET
CO

1'b1: HW control by SRCLKEN

1 RG_VIO18_EN Enables VIO18
1'b1: Enable
1'b0: Disable
0 RG_VIO18_MODE_ VIO18 low power mode
SET 1'b0: Normal mode
K

1'b1: Low power mode

0A38 VIBR_CON0 VIBR Control Register 0 0100

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RG_ RG_
IA

QI_ RG_
QI_ QI_ QI_ VIB RG_ VIB
VIB VIB
VIB VIB VIB R_M VIB R_M
Name R_E R_S
R_O R_O
R_M ODE R_E ODE
CFB CFB
N TB ODE _CT N _SE
_EN _EN
RL T
ED

Type RO RO RO RW RO RW RW RW
Reset 0 0 0 0 0 0 0 0

Bit(s) Name Description

15 QI_VIBR_EN VIBR enable status

1'b1: Enable
1'b0: Disable
14 QI_VIBR_STB VIBR soft-start status
11 QI_VIBR_OCFB_E OCFB status
N 1'b1: Over current occurs.
1'b0: No over current occurs.

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Bit(s) Name Description

10 RG_VIBR_OCFB_E Enables OCFB
N 1'b1: Enable

AL
1'b0: Disable
7 QI_VIBR_MODE VCN18 low power mode status
1'b0: Normal mode
1'b1: Low power mode

TI
2 RG_VIBR_MODE_ VCN18 low power mode control
CTRL 1'b0: SW control by VCN18_MODE_SET
1'b1: HW control by SRCLKEN
1 RG_VIBR_EN Enables VIBR

EN
1'b1: Enable
1'b0: Disable
0 RG_VIBR_MODE_ VCN18 low power mode
SET 1'b0: Normal mode
1'b1: Low power mode

ID
NF
VCN18_CON
0A3A VCN18 Control Register 0 0100
0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RG_ RG_
QI_ RG_ QI_ RG_
QI_ QI_ VCN RG_ VCN
VCN VCN VCN VCN
CO

VCN VCN 18_ VCN 18_

Name 18_E 18_S 18_O 18_O 18_ 18_O
MOD 18_E MOD
CFB CFB MOD N_C
N TB E_C N E_S
_EN _EN E TRL
TRL ET
Type RO RO RO RW RO RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0
K

Bit(s) Name Description

15 QI_VCN18_EN VCN18 enable status
TE

1'b1: Enable
1'b0: Disable
14 QI_VCN18_STB VCN18 soft-start status
11 QI_VCN18_OCFB_ OCFB status
EN
IA

1'b1: Over current occurs.

1'b0: No over current occurs.
10 RG_VCN18_OCFB_ Enables OCFB
EN 1'b1: Enable
ED

1'b0: Disable
7 QI_VCN18_MODE VCN18 low power mode status
1'b0: Normal mode
1'b1: Low power mode
3 RG_VCN18_ON_CT VCN18 enable control
M

RL 1'b0: SW control by RG_VCN18_EN

1'b1: HW control by SRCLKEN
2 RG_VCN18_MODE VCN18 low power mode control
_CTRL 1'b0: SW control by VCN18_MODE_SET
1'b1: HW control by SRCLKEN
1 RG_VCN18_EN Enables VCN18
1'b1: Enable

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Bit(s) Name Description

1'b0: Disable
0 RG_VCN18_MODE VCN18 low power mode

AL
_SET 1'b0: Normal mode
1'b1: Low power mode

TI
VCAM_CON
0A3C VCMAD Control Register 0 0100
0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

EN
QI_ RG_ RG_ RG_
QI_
QI_ QI_ VCA VCA VCA RG_ VCA
VCA
VCA VCA MD_ MD_ MD_ VCA MD_
Name MD_ MD_ OCF OCF
MD_
MOD MD_ MOD
MOD
EN STB B_E B_E E_C EN E_S
E
N N TRL ET
Type
Reset
RO
0
RO
0
RO
0
RW
0
ID RO
0
RW
0
RW
0
RW
0
NF
Bit(s) Name Description
15 QI_VCAMD_EN VCAMD enable status
1'b1: Enable
1'b0: Disable
14 QI_VCAMD_STB VCAMD soft-start status
CO

11 QI_VCAMD_OCFB OCFB status

_EN 1'b1: Over current occurs.
1'b0: No over current occurs.
10 RG_VCAMD_OCFB Enables OCFB
_EN 1'b1: Enable
K

1'b0: Disable
7 QI_VCAMD_MODE VCAMD low power mode status
1'b0: Normal mode
TE

1'b1: Low power mode

2 RG_VCAMD_MOD VCAMD low power mode control
E_CTRL 1'b0: SW control by VCAMD_MODE_SET
1'b1: HW control by SRCLKEN
IA

1 RG_VCAMD_EN Enables VCAMD

1'b1: Enable
1'b0: Disable
0 RG_VCAMD_MOD VCAMD low power mode
ED

E_SET 1'b0: Normal mode

1'b1: Low power mode
M

VCAMIO_CO
0A3E VCAMIO Control Register 0 0100
N0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
QI_ QI_ RG_ QI_ RG_ RG_
QI_ RG_
VCA VCA VCA VCA VCA VCA
VCA VCA
Name MIO
MIO MIO MIO MIO MIO
MIO
MIO
_ST _OC _OC _MO _MO _MO
_EN _EN
B FB_ FB_ DE DE_ DE_

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EN EN CTR SET
L
Type RO RO RO RW RO RW RW RW
Reset 0 0 0 0 0 0 0 0

AL
Bit(s) Name Description
15 QI_VCAMIO_EN VCAMDIO enable status
1'b1: Enable

TI
1'b0: Disable
14 QI_VCAMIO_STB VCAMDIO soft-start status
11 QI_VCAMIO_OCFB OCFB status

EN
_EN 1'b1: Over current occurs.
1'b0: No over current occurs.
10 RG_VCAMIO_OCF Enables OCFB
B_EN 1'b1: Enable
1'b0: Disable
7 QI_VCAMIO_MOD
E 1'b0: Normal mode
1'b1: Low power mode
ID
VCAM_IO low power mode status
NF
2 RG_VCAMIO_MOD VCAM_IO low power mode control
E_CTRL 1'b0: SW control by VCAMD_MODE_SET
1'b1: HW control by SRCLKEN
1 RG_VCAMIO_EN Enables VCAM_IO
1'b1: Enable
CO

1'b0: Disable
0 RG_VCAMIO_MOD VCAM_IO low power mode
E_SET 1'b0: Normal mode
1'b1: Low power mode
K

LDO_VSRA
0A40 LDO_VSRAM Control Register 0 8102
M_CON0
TE

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
QI_ RG_ RG_ RG_ RG_
QI_
QI_ QI_ VSR VSR VSR VSR RG_ VSR
VSR
VSR VSR AM_ AM_ AM_ AM_ VSR AM_
Name AM_ AM_ OCF OCF
AM_
ON_ MOD AM_ MOD
IA

MOD
EN STB B_E B_E CTR E_C EN E_S
E
N N L TRL ET
Type RO RO RO RW RO RW RW RW RW
Reset 1 0 0 0 0 0 0 1 0
ED

Bit(s) Name Description

15 QI_VSRAM_EN VSRAM enable status
1'b1: Enable
M

1'b0: Disable
14 QI_VSRAM_STB VSRAM soft-start status
11 QI_VSRAM_OCFB_ OCFB status
EN 1'b1: Over current occurs.
1'b0: No over current occurs.
10 RG_VSRAM_OCFB Enables OCFB
_EN 1'b1: Enable

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Bit(s) Name Description

1'b0: Disable
7 QI_VSRAM_MODE VSRAM low power mode status

AL
1'b0: Normal mode
1'b1: Low power mode
3 RG_VSRAM_ON_C VSRAM enable control
TRL 1'b0: SW control by RG_VSRAM_EN

TI
1'b1: HW control by SRCLKEN
2 RG_VSRAM_MOD VSRAM low power mode control
E_CTRL 1'b0: SW control by VSRAM_MODE_SET
1'b1: HW control by SRCLKEN

EN
1 RG_VSRAM_EN Enables VSRAM
1'b1: Enable
1'b0: Disable
0 RG_VSRAM_MOD VSRAM low power mode
E_SET 1'b0: Normal mode
1'b1: Low power mode
ID
NF
LDO_VSRA
0A42 LDO_VSRAM Control Register 1 5000
M_CON1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
QI_ RG_
CO

VSR VSR
AM_ AM_
Name FAS FAS
T_T T_T
RAN RAN
_EN _EN
Type RO RW
K

Reset 0 1

Bit(s) Name Description

15 QI_VSRAM_FAST_ Fast transient enable status

TRAN_EN
12 RG_VSRAM_FAST Enables fast transient
_TRAN_EN 1'b1: Enable
IA

1'b0: Disable
ED

VTREF_CON
0A44 VTREF Control Register 0 0000
0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RG_
QI_T RG_
M

QI_T TRE
REF TRE
Name REF F_O
_ST F_E
_EN N_C
B N
TRL
Type RO RO RW RW
Reset 0 0 0 0

Bit(s) Name Description

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Bit(s) Name Description

15 QI_TREF_EN TREF enable status
1'b1: Enable

AL
1'b0: Disable
14 QI_TREF_STB
3 RG_TREF_ON_CT TREF enable control
RL 1'b0: SW control by RG_TREF_EN

TI
1'b1: HW control by SRCLKEN
1 RG_TREF_EN Enables TREF
1'b1: Enable
1'b0: Disable

EN
0A46 VM_CON0 VM Control Register 0 8102
Bit 15

QI_
Name VM_ VM_
EN
14

QI_

STB
13 12
QI_
VM_
OCF
B_E
11 10
RG_
VM_
OCF
B_E
9

ID 8
QI_
VM_
MOD
7 6 5 4 3
RG_ RG_
2
RG_
VM_ VM_ RG_ VM_
ON_ MOD VM_ MOD
CTR E_C EN E_S
1 0
NF
E
N N L TRL ET
Type RO RO RO RW RO RW RW RW RW
Reset 1 0 0 0 0 0 0 1 0

Bit(s) Name Description

15 QI_VM_EN VM enable status

1'b1: Enable
1'b0: Disable
14 QI_VM_STB VM soft-start status
11 QI_VM_OCFB_EN OCFB status
K

1'b1: Over current occurs.

1'b0: No over current occurs.
10 RG_VM_OCFB_EN Enables OCFB
TE

1'b1: Enable
1'b0: Disable
7 QI_VM_MODE VM low power mode status
1'b0: Normal mode
IA

1'b1: Low power mode

3 RG_VM_ON_CTRL VM enable control
1'b0: SW control by RG_VM_EN
1'b1: HW control by SRCLKEN
ED

2 RG_VM_MODE_CT VM low power mode control

RL 1'b0: SW control by VM_MODE_SET
1'b1: HW control by SRCLKEN
1 RG_VM_EN Enables VM
M

1'b1: Enable
1'b0: Disable
0 RG_VM_MODE_SE VM low power mode
T 1'b0: Normal mode
1'b1: Low power mode

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0A48 VM_CON1 VM Control Register 1 5000

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

AL
QI_ RG_
VM_ VM_
Name FAS FAS
T_T T_T
RAN RAN
_EN _EN
Type RO RW

TI
Reset 0 1

Bit(s) Name Description

EN
15 QI_VM_FAST_TRA Fast transient enable status
N_EN
12 RG_VM_FAST_TR Enables fast transient
AN_EN 1'b1: Enable
1'b0: Disable

ID
NF
0A4A VRTC_CON0 VRTC Control Register 0 8002
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
QI_ RG_
VRT VRT
Name
C_E C_E
CO

N N
Type RO RW
Reset 1 1

Bit(s) Name Description

15 QI_VRTC_EN VRTC enable status
K

1 RG_VRTC_EN Enables VRTC

1'b1: Enable
TE

1'b0: Disable

ALDO_ANA_
IA

0A4E ADLDO Control Register 0 8000

CON0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RG_
VAU
ED

Name X18_ RG_VAUX18_CAL

NDI
S_E
N
Type RW RW
Reset 1 0 0 0 0
M

Bit(s) Name Description

15 RG_VAUX18_NDIS Enables power down NMOS
_EN 1'b1: Enable
1'b0: Disable)
11:8 RG_VAUX18_CAL Calibrates voltage

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Bit(s) Name Description

(4'b0000: 0mV)
4'b0000: 0mV

AL
4'b0001: -20mV
4'b0010: -40mV
4'b0011: -60mV
4'b0100: -80mV
4'b0101: -100mV
4'b0110: -120mV

TI
4'b0111: -140mV
4'b1000: 160mV
4'b1001: 140mV
4'b1010: 120mV

EN
4'b1011: 100mV
4'b1100: 80mV
4'b1101: 60mV
4'b1110: 40mV
4'b1111: 20mV

0A50
ADLDO_AN
ADLDO Control Register 1
ID 8000
NF
A_CON1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RG_
VTC
XO_
Name 0_N
CO

RG_VTCXO_0_CAL
DIS_
EN
Type RW RW
Reset 1 0 0 0 0
K

Bit(s) Name Description

15 RG_VTCXO_0_NDI Enables LDO output power-down
S_EN 1'b0: Disable output power-down
TE

1'b1: Enable output power-down

11:8 RG_VTCXO_0_CAL Calibrates LDO voltage
(4'b0000: 0mV)
4'b0000: 0mV
4'b0001: -20mV
IA

4'b0010: -40mV
4'b0011: -60mV
4'b0100: -80mV
4'b0101: -100mV
ED

4'b0110: -120mV
4'b0111: -140mV
4'b1000: +160mV
4'b1001: +140mV
4'b1010: +120mV
4'b1011: +100mV
M

4'b1100: +80mV
4'b1101: +60mV
4'b1110: +40mV
4'b1111: +20mV

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ADLDO_AN
0A52 ADLDO Control Register 2 8000
A_CON2

AL
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RG_
VTC
XO_
Name RG_VTCXO_1_CAL
1_N
DIS_

TI
EN
Type RW RW
Reset 1 0 0 0 0

EN
Bit(s) Name Description
15 RG_VTCXO_1_NDI Enables LDO output power-down
S_EN 1'b0: Disable output power-down
1'b1: Enable output power-down
11:8 RG_VTCXO_1_CAL Calibrates LDO voltage
(4'b0000:
4'b0000:
4'b0001:
4'b0010:
ID 0mV)
0mV
-20mV
-40mV
NF
4'b0011: -60mV
4'b0100: -80mV
4'b0101: -100mV
4'b0110: -120mV
4'b0111: -140mV
CO

4'b1000: +160mV
4'b1001: +140mV
4'b1010: +120mV
4'b1011: +100mV
4'b1100: +80mV
4'b1101: +60mV
4'b1110: +40mV
K

4'b1111: +20mV
TE

ADLDO_AN
0A54 ADLDO Control Register 3 8000
A_CON3
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IA

RG_
VAU
Name D28 RG_VAUD28_CAL
_ND
IS_E
ED

N
Type RW RW
Reset 1 0 0 0 0

Bit(s) Name Description

15 RG_VAUD28_NDIS Enables LDO output power-down

_EN 1'b0: Disable output power-down
1'b1: Enable output power-down
11:8 RG_VAUD28_CAL Calibrates LDO voltage
(4'b0000: 0mV)
4'b0000: 0mV
4'b0001: -20mV

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Bit(s) Name Description

4'b0010: -40mV
4'b0011: -60mV

AL
4'b0100: -80mV
4'b0101: -100mV
4'b0110: -120mV
4'b0111: -140mV
4'b1000: +160mV
4'b1001: +140mV

TI
4'b1010: +120mV
4'b1011: +100mV
4'b1100: +80mV
4'b1101: +60mV

EN
4'b1110: +40mV
4'b1111: +20mV

0A56

Bit 15
ADLDO_AN
A_CON4
14 13 12
ADLDO Control Register 4

11 10 9
ID 8 7 6 5 4 3 2 1
8000

0
NF
RG_
VCN
28_
Name NDI
RG_VCN28_CAL
S_E
N
CO

Type RW RW
Reset 1 0 0 0 0

Bit(s) Name Description

15 RG_VCN28_NDIS_ Enables LDO output power-down
EN 1'b0: Disable output power-down
K

1'b1: Enable output power-down

11:8 RG_VCN28_CAL Calibrates LDO voltage
TE

(4'b0000: 0mV)
4'b0000: 0mV
4'b0001: -20mV
4'b0010: -40mV
4'b0011: -60mV
4'b0100: -80mV
IA

4'b0101: -100mV
4'b0110: -120mV
4'b0111: -140mV
4'b1000: +160mV
ED

4'b1001: +140mV
4'b1010: +120mV
4'b1011: +100mV
4'b1100: +80mV
4'b1101: +60mV
4'b1110: +40mV
M

4'b1111: +20mV

ADLDO_AN
0A58 ADLDO Control Register 5 8030
A_CON5
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

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RG_
VCA
RG_VCA
MA_
Name NDI RG_VCAMA_CAL MA_VOS

AL
EL
S_E
N
Type RW RW RW
Reset 1 0 0 0 0 1 1

TI
Bit(s) Name Description
15 RG_VCAMA_NDIS Enables LDO output power-down
_EN 1'b0: Disable output power-down

EN
1'b1: Enable output power-down
11:8 RG_VCAMA_CAL Calibrate LDO voltage
(4'b0000: 0mV)
4'b0000: 0mV
4'b0001: -20mV
4'b0010: -40mV
4'b0011: -60mV
4'b0100: -80mV
4'b0101: -100mV
4'b0110: -120mV
ID
NF
4'b0111: -140mV
4'b1000: +160mV
4'b1001: +140mV
4'b1010: +120mV
4'b1011: +100mV
CO

4'b1100: +80mV
4'b1101: +60mV
4'b1110: +40mV
4'b1111: +20mV
5:4 RG_VCAMA_VOSE Selects voltage
L 2b'00: 1.5V
2b'01: 1.8V
K

2b'10: 2.5V
2b'11: 2.8V
TE

ADLDO_AN
0A5A ADLDO Control Register 6 8000
A_CON6
IA

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RG_
VCN
33_ RG_VCN33_VO
Name RG_VCN33_CAL
ED

NDI SEL
S_E
N
Type RW RW RW
Reset 1 0 0 0 0 0 0 0
M

Bit(s) Name Description

15 RG_VCN33_NDIS_ Enables LDO output power-down
EN 1'b0: Disable output power-down
1'b1: Enable output power-down
11:8 RG_VCN33_CAL Calibrates LDO voltage
(4'b0000: 0mV)
4'b0000: 0mV

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Bit(s) Name Description

4'b0001: -20mV
4'b0010: -40mV

AL
4'b0011: -60mV
4'b0100: -80mV
4'b0101: -100mV
4'b0110: -120mV
4'b0111: -140mV
4'b1000: +160mV

TI
4'b1001: +140mV
4'b1010: +120mV
4'b1011: +100mV
4'b1100: +80mV

EN
4'b1101: +60mV
4'b1110: +40mV
4'b1111: +20mV
6:4 RG_VCN33_VOSEL Selects output voltage
3'b000: 3.3V
3'b001: 3.4V
3'b010: 3.5V
3'b011: 3.6V ID
NF
ADLDO_AN
0A5C ADLDO Control Register 7 8000
A_CON7
CO

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RG_
VUS
B33
Name _ND RG_VUSB33_CAL
IS_E
N
Type RW RW
K

Reset 1 0 0 0 0
TE

Bit(s) Name Description

15 RG_VUSB33_NDIS Enables LDO output power-down
_EN 1'b0: Disable output power-down
1'b1: Enable output power-down
IA

12:9 RG_VUSB33_CAL Calibrates LDO voltage

(4'b0000: 0mV)
4'b0000: 0mV
4'b0001: -20mV
ED

4'b0010: -40mV
4'b0011: -60mV
4'b0100: -80mV
4'b0101: -100mV
4'b0110: -120mV
4'b0111: -140mV
M

4'b1000: +160mV
4'b1001: +140mV
4'b1010: +120mV
4'b1011: +100mV
4'b1100: +80mV
4'b1101: +60mV
4'b1110: +40mV
4'b1111: +20mV

MediaTek Confidential © 2015 MediaTek Inc. Page 180 of 304

AL
ADLDO_AN
0A5E ADLDO Control Register 8 8030
A_CON8
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RG_
VEF

TI
USE RG_VEFUSE_V
Name _ND RG_VEFUSE_CAL
OSEL
IS_E
N
Type RW RW RW

EN
Reset 1 0 0 0 0 0 1 1

Bit(s) Name Description

15 RG_VEFUSE_NDIS Enables power down NMOS

11:8
_EN

RG_VEFUSE_CAL
1'b1: Enable
1'b0: Disable
Calibrates voltage
(4'b0000: 0mV)
ID
NF
4'b0000: 0mV
4'b0001: -20mV
4'b0010: -40mV
4'b0011: -60mV
4'b0100: -80mV
CO

4'b0101: -100mV
4'b0110: -120mV
4'b0111: -140mV
4'b1000: 160mV
4'b1001: 140mV
4'b1010: 120mV
4'b1011: 100mV
K

4'b1100: 80mV
4'b1101: 60mV
4'b1110: 40mV
TE

4'b1111: 20mV
6:4 RG_VEFUSE_VOSE Selects output voltage
L 3'b011: 1.8V
3'b100: 1.9V
3'b101: 2.0V
IA

3'b110: 2.1V
3'b111: 2.2V
ED

ADLDO_AN
0A60 ADLDO Control Register 9 8020
A_CON9
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M

RG_
VSI
M1_ RG_VSIM1_VOS
Name NDI
RG_VSIM1_CAL
EL
S_E
N
Type RW RW RW
Reset 1 0 0 0 0 0 1 0

MediaTek Confidential © 2015 MediaTek Inc. Page 181 of 304

Bit(s) Name Description

15 RG_VSIM1_NDIS_ Enables LDO output power-down
EN 1'b0: Disable output power-down

AL
1'b1: Enable output power-down
11:8 RG_VSIM1_CAL Calibrates LDO voltage
(4'b0000: 0mV)
4'b0000: 0mV
4'b0001: -20mV

TI
4'b0010: -40mV
4'b0011: -60mV
4'b0100: -80mV
4'b0101: -100mV

EN
4'b0110: -120mV
4'b0111: -140mV
4'b1000: +160mV
4'b1001: +140mV
4'b1010: +120mV
4'b1011: +100mV
4'b1100: +80mV
4'b1101: +60mV
4'b1110: +40mV
4'b1111: +20mV
ID
NF
6:4 RG_VSIM1_VOSEL Output selection signal
3'b001: 1.7V
3'b010: 1.8V
3'b011: 1.86V
3'b101: 2.76V
CO

3'b110: 3.0V
3'b111: 3.1V

ADLDO_AN
K

0A62 ADLDO Control Register 10 8020

A_CON10
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TE

RG_
VSI
M2_ RG_VSIM2_VO
Name NDI RG_VSIM2_CAL
SEL
S_E
N
IA

Type RW RW RW
Reset 1 0 0 0 0 0 1 0

Bit(s) Name Description

15 RG_VSIM2_NDIS_ Enables LDO output power-down

EN 1'b0: Disable output power-down
1'b1: Enable output power-down
11:8 RG_VSIM2_CAL Calibrates LDO voltage
M

(4'b0000: 0mV)
4'b0000: 0mV
4'b0001: -20mV
4'b0010: -40mV
4'b0011: -60mV
4'b0100: -80mV
4'b0101: -100mV
4'b0110: -120mV
4'b0111: -140mV

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Bit(s) Name Description

4'b1000: +160mV
4'b1001: +140mV

AL
4'b1010: +120mV
4'b1011: +100mV
4'b1100: +80mV
4'b1101: +60mV
4'b1110: +40mV
4'b1111: +20mV

TI
6:4 RG_VSIM2_VOSEL Output selection signal
3'b001: 1.7 V
3'b010: 1.8 V

EN
3'b011: 1.86 V
3'b101: 2.76V
3'b110: 3.0 V
3'b111: 3.1 V

0A64
ADLDO_AN
A_CON11
ADLDO Control Register 11
ID 8010
NF
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RG_
VEM
C_3 RG_VEM
Name V3_ RG_VEMC_3V3_CAL C_3V3_V
CO

NDI OSEL
S_E
N
Type RW RW RW
Reset 1 0 0 0 0 0 1

Bit(s) Name Description

15 RG_VEMC_3V3_N Enables power down NMOS

DIS_EN 1'b1: Enable
TE

1'b0: Disable
11:8 RG_VEMC_3V3_C Calibrates voltage
AL (4'b0000: 0mV)
4'b0000: 0mV
4'b0001: -20mV
IA

4'b0010: -40mV
4'b0011: -60mV
4'b0100: -80mV
4'b0101: -100mV
4'b0110: -120mV
ED

4'b0111: -140mV
4'b1000: 160mV
4'b1001: 140mV
4'b1010: 120mV
4'b1011: 100mV
M

4'b1100: 80mV
4'b1101: 60mV
4'b1110: 40mV
4'b1111: 20mV
5:4 RG_VEMC_3V3_V Selects output voltage
OSEL 2b'01: 2.9V
2b'10: 3V
2b'11: 3.3V

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AL
ADLDO_AN
0A66 ADLDO Control Register 12 8000
A_CON12
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RG_
VMC
RG_VMC

TI
Name H_N RG_VMCH_CAL
H_VOSEL
DIS_
EN
Type RW RW RW
Reset 1 0 0 0 0 0 0

EN
Bit(s) Name Description
15 RG_VMCH_NDIS_ Enables power down NMOS
EN 1'b1: Enable

11:8 RG_VMCH_CAL
1'b0: Disable
Calibrates voltage
(4'b0000: 0mV)
4'b0000: 0mV
ID
NF
4'b0001: -20mV
4'b0010: -40mV
4'b0011: -60mV
4'b0100: -80mV
4'b0101: -100mV
CO

4'b0110: -120mV
4'b0111: -140mV
4'b1000: 160mV
4'b1001: 140mV
4'b1010: 120mV
4'b1011: 100mV
4'b1100: 80mV
K

4'b1101: 60mV
4'b1110: 40mV
4'b1111: 20mV
TE

5:4 RG_VMCH_VOSEL Selects output voltage

(2'b00: 2.9V)
2'b00: 2.9V
2'b01: 3.3V
2'b10: 3.3V
IA

ADLDO_AN
ED

0A68 ADLDO Control Register 13 0070

A_CON13
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RG_ADLDO_RS RG_ADLDO_RS
Name V_H V_L
M

Type RW RW
Reset 1 1 1 0 0 0

Bit(s) Name Description

6:4 RG_ADLDO_RSV_
H
2:0 RG_ADLDO_RSV_

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Bit(s) Name Description

AL
DLDO_ANA
0A6A DLDO Control Register 0 8010
_CON0

TI
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RG_
VMC
RG_VMC
Name _ND RG_VMC_CAL
_VOSEL
IS_E

EN
N
Type RW RW RW
Reset 1 0 0 0 0 0 1

Bit(s)
15
Name
RG_VMC_NDIS_E
N
Description
Enables power down NMOS
1'b1: Enable
1'b0: Disable
ID
NF
11:8 RG_VMC_CAL Calibrates voltage
(4'b0000: 0mV)
4'b0000: 0mV
4'b0001: -20mV
4'b0010: -40mV
CO

4'b0011: -60mV
4'b0100: -80mV
4'b0101: -100mV
4'b0110: -120mV
4'b0111: -140mV
4'b1000: 160mV
4'b1001: 140mV
K

4'b1010: 120mV
4'b1011: 100mV
4'b1100: 80mV
TE

4'b1101: 60mV
4'b1110: 40mV
4'b1111: 20mV
5:4 RG_VMC_VOSEL Selects output voltage
(2'b01: 2.9V)
IA

2'b00: 1.8V
2'b01: 2.9V
2'b10: 3.0V
2'b11: 3.3V
ED

DLDO_ANA
0A6C DLDO Control Register 1 8050
_CON1
M

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RG_
VCA
MAF RG_VCAMAF_V
Name _ND RG_VCAMAF_CAL
OSEL
IS_E
N
Type RW RW RW

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Reset 1 0 0 0 0 1 0 1

Bit(s) Name Description

AL
15 RG_VCAMAF_NDI Enables power down NMOS
S_EN 1'b1: Enable
1'b0: Disable
11:8 RG_VCAMAF_CAL Calibrates voltage

TI
(4'b0000: 0mV)
4'b0000: 0mV
4'b0001: -20mV
4'b0010: -40mV

EN
4'b0011: -60mV
4'b0100: -80mV
4'b0101: -100mV
4'b0110: -120mV
4'b0111: -140mV
4'b1000: 160mV
4'b1001: 140mV
4'b1010: 120mV
4'b1011: 100mV
4'b1100: 80mV
ID
NF
4'b1101: 60mV
4'b1110: 40mV
4'b1111: 20mV
6:4 RG_VCAMAF_VOS Selects output voltage
EL (3'b101: 2.8V)
CO

3'b000: 1.2V
3'b001: 1.3V
3'b010: 1.5V
3'b011: 1.8V
3'b100: 2.0V
3'b101: 2.8V
3'b110: 3.0V
K

3'b111: 3.3V
TE

DLDO_ANA
0A6E DLDO Control Register 2 8050
_CON2
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IA

RG_
VIB
RG_VIBR_VOS
Name R_N RG_VIBR_CAL
EL
DIS_
EN
ED

Type RW RW RW
Reset 1 0 0 0 0 1 0 1

Bit(s) Name Description

15 RG_VIBR_NDIS_E Enables power down NMOS

N 1'b1: Enable
1'b0: Disable
11:8 RG_VIBR_CAL Calibrates voltage
(4'b0000: 0mV)
4'b0000: 0mV
4'b0001: -20mV
4'b0010: -40mV

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Bit(s) Name Description

4'b0011: -60mV
4'b0100: -80mV

AL
4'b0101: -100mV
4'b0110: -120mV
4'b0111: -140mV
4'b1000: 160mV
4'b1001: 140mV
4'b1010: 120mV

TI
4'b1011: 100mV
4'b1100: 80mV
4'b1101: 60mV
4'b1110: 40mV

EN
4'b1111: 20mV
6:4 RG_VIBR_VOSEL Selects output voltage
(3'b101: 2.8V)
3'b000: 1.2V
3'b001: 1.3V
3'b010: 1.5V
3'b011: 1.8V
3'b100: 2.0V
3'b101: 2.8V
ID
NF
3'b110: 3.0V
3'b111: 3.3V
CO

DLDO_ANA
0A70 DLDO Control Register 3 8000
_CON3
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RG_
VIO2
Name 8_N RG_VIO28_CAL
K

DIS_
EN
Type RW RW
Reset 1 0 0 0 0
TE

Bit(s) Name Description

15 RG_VIO28_NDIS_ Enables power down NMOS
EN
IA

1'b1: Enable
1'b0: Disable
11:8 RG_VIO28_CAL Calibrates voltage
(4'b0000: 0mV)
ED

4'b0000: 0mV
4'b0001: -20mV
4'b0010: -40mV
4'b0011: -60mV
4'b0100: -80mV
4'b0101: -100mV
M

4'b0110: -120mV
4'b0111: -140mV
4'b1000: 160mV
4'b1001: 140mV
4'b1010: 120mV
4'b1011: 100mV
4'b1100: 80mV
4'b1101: 60mV
4'b1110: 40mV

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Bit(s) Name Description

4'b1111: 20mV

AL
DLDO_ANA
0A72 DLDO Control Register 4 8050
_CON4

TI
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RG_
VGP
RG_VGP1_VOSE
Name 1_N RG_VGP1_CAL
L
DIS_

EN
EN
Type RW RW RW
Reset 1 0 0 0 0 1 0 1

Bit(s)
15
Name
RG_VGP1_NDIS_E
N
Description
Enables power down NMOS
1'b1: Enable
1'b0: Disable
ID
NF
11:8 RG_VGP1_CAL Calibrates voltage
(4'b0000: 0mV)
4'b0000: 0mV
4'b0001: -20mV
4'b0010: -40mV
CO

4'b0011: -60mV
4'b0100: -80mV
4'b0101: -100mV
4'b0110: -120mV
4'b0111: -140mV
4'b1000: 160mV
4'b1001: 140mV
K

4'b1010: 120mV
4'b1011: 100mV
4'b1100: 80mV
TE

4'b1101: 60mV
4'b1110: 40mV
4'b1111: 20mV
6:4 RG_VGP1_VOSEL Selects output voltage
(3'b101: 2.8V)
IA

3'b000: 1.2V
3'b001: 1.3V
3'b010: 1.5V
3'b011: 1.8V
ED

3'b100: 2.5V
3'b101: 2.8V
3'b110: 3.0V
3'b111: 3.3V
M

DLDO_ANA
0A74 DLDO Control Register 5 0030
_CON5
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RG_DLDO RG_DLD
Name
_RSV_H O_RSV_L
Type RW RW

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Reset 1 1 0 0

Bit(s) Name Description

AL
5:4 RG_DLDO_RSV_H
1:0 RG_DLDO_RSV_L

TI
SLDO_ANA_
0A76 SLDO Control Register 0 0000
CON0

EN
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RG_VM_
Name VOSEL
Type RW
Reset 0 0

Bit(s)
1:0
Name
RG_VM_VOSEL
Description
Selects output voltage
2'b00: 1.24V
ID
NF
2'b01: 1.39V
2'b10: 1.54V
CO

SLDO_ANA_
0A78 SLDO Control Register 1 8000
CON1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RG_
VM_
Name NDI RG_VM_CAL
K

S_E
N
Type RW RW
TE

Reset 1 0 0 0 0

Bit(s) Name Description

15 RG_VM_NDIS_EN Enables power down NMOS
IA

1'b1: Enable
1'b0: Disable
11:8 RG_VM_CAL Calibrates voltage
(4'b0000: 0mV)
ED

4'b0000: 0mV
4'b0001: -20mV
4'b0010: -40mV
4'b0011: -60mV
4'b0100: -80mV
M

4'b0101: -100mV
4'b0110: -120mV
4'b0111: -140mV
4'b1000: 160mV
4'b1001: 140mV
4'b1010: 120mV
4'b1011: 100mV
4'b1100: 80mV
4'b1101: 60mV

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Bit(s) Name Description

4'b1110: 40mV
4'b1111: 20mV

AL
SLDO_ANA_
0A7A SLDO Control Register 2 8040
CON2

TI
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RG_
VCA

EN
MD_ RG_VCAMD_V
Name NDI RG_VCAMD_CAL
OSEL
S_E
N
Type RW RW RW
Reset 1 0 0 0 0 1 0 0

Bit(s)
15
Name
RG_VCAMD_NDIS
Description
Enables power down NMOS
ID
NF
_EN 1'b1: Enable
1'b0: Disable
11:8 RG_VCAMD_CAL Calibrates voltage
(4'b0000: 0mV)
4'b0000: 0mV
CO

4'b0001: -20mV
4'b0010: -40mV
4'b0011: -60mV
4'b0100: -80mV
4'b0101: -100mV
4'b0110: -120mV
4'b0111: -140mV
K

4'b1000: 160mV
4'b1001: 140mV
4'b1010: 120mV
TE

4'b1011: 100mV
4'b1100: 80mV
4'b1101: 60mV
4'b1110: 40mV
4'b1111: 20mV
IA

6:4 RG_VCAMD_VOSE Selects output voltage

L (3'b100: 1.3V)
3'b000: 0.9V
3'b001: 1.0V
ED

3'b010: 1.1V
3'b011: 1.22V
3'b100: 1.3V
3'b101: 1.5V
M

SLDO_ANA_
0A7C SLDO Control Register 3 8000
CON3
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RG_
Name VRF RG_VRF18_0_CAL
18_0

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_ND
IS_E
N
Type RW RW

AL
Reset 1 0 0 0 0

Bit(s) Name Description

15 RG_VRF18_0_NDI Enables power down NMOS

TI
S_EN 1'b1: Enable
1'b0: Disable
11:8 RG_VRF18_0_CAL Calibrates voltage
(4'b0000: 0mV)

EN
4'b0000: 0mV
4'b0001: -20mV
4'b0010: -40mV
4'b0011: -60mV
4'b0100: -80mV
4'b0101: -100mV
4'b0110: -120mV
4'b0111: -140mV
4'b1000: 160mV
4'b1001: 140mV
ID
NF
4'b1010: 120mV
4'b1011: 100mV
4'b1100: 80mV
4'b1101: 60mV
4'b1110: 40mV
CO

4'b1111: 20mV

SLDO_ANA_
0A7E SLDO Control Register 4 8030
CON4
K

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RG_
VRF
TE

18_1 RG_VRF18
Name _ND RG_VRF18_1_CAL
_1_VOSEL
IS_E
N
Type RW RW RW
IA

Reset 1 0 0 0 0 1 1

Bit(s) Name Description

15 RG_VRF18_1_NDIS Enables power down NMOS

_EN 1'b1: Enable
1'b0: Disable
11:8 RG_VRF18_1_CAL Calibrates voltage
(4'b0000: 0mV)
M

4'b0000: 0mV
4'b0001: -20mV
4'b0010: -40mV
4'b0011: -60mV
4'b0100: -80mV
4'b0101: -100mV
4'b0110: -120mV
4'b0111: -140mV
4'b1000: 160mV

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Bit(s) Name Description

4'b1001: 140mV
4'b1010: 120mV

AL
4'b1011: 100mV
4'b1100: 80mV
4'b1101: 60mV
4'b1110: 40mV
4'b1111: 20mV

TI
5:4 RG_VRF18_1_VOS RG_VRF18_1_VOSEL[1:0]&RG_SLDO_RSV_L<2>
EL 2'b00 & RG_SLDO_RSV_L<2>=1: 1.2 v
2'b01 & RG_SLDO_RSV_L<2>=1: 1.3 v
2'b10 & RG_SLDO_RSV_L<2>=1: 1.5 v

EN
2'b11 & RG_SLDO_RSV_L<2>=1: 1.8 v
2'b11 & RG_SLDO_RSV_L<2>=0: 1.825 v

0A80

Bit
RG_
15
SLDO_ANA_
CON5
14 13 12
SLDO Control Register 5

11 10 9
ID 8 7 6 5 4 3 2 1
8000

0
NF
VIO1
Nam 8_N RG_VIO18_CAL
e DIS_
EN
Type RW RW
Reset 1 0 0 0 0
CO

Bit(s) Name Description

15 RG_VIO18_NDIS_E Enables power down NMOS
N 1'b1: Enable
1'b0: Disable
K

11:8 RG_VIO18_CAL Calibrates voltage

(4'b0000: 0mV)
4'b0000: 0mV
TE

4'b0001: -20mV
4'b0010: -40mV
4'b0011: -60mV
4'b0100: -80mV
4'b0101: -100mV
IA

4'b0110: -120mV
4'b0111: -140mV
4'b1000: 160mV
4'b1001: 140mV
ED

4'b1010: 120mV
4'b1011: 100mV
4'b1100: 80mV
4'b1101: 60mV
4'b1110: 40mV
4'b1111: 20mV
M

SLDO_ANA_
0A82 SLDO Control Register 6 8000
CON6
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RG_ RG_VCN18_CAL

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VCN
18_
NDI
S_E

AL
N
Type RW RW
Reset 1 0 0 0 0

Bit(s) Name Description

TI
15 RG_VCN18_NDIS_ Enables power down NMOS
EN 1'b1: Enable
1'b0: Disable

EN
11:8 RG_VCN18_CAL Calibrates voltage
(4'b0000: 0mV)
4'b0000: 0mV
4'b0001: -20mV
4'b0010: -40mV
4'b0011: -60mV
4'b0100: -80mV
4'b0101: -100mV
4'b0110: -120mV
4'b0111: -140mV
ID
NF
4'b1000: 160mV
4'b1001: 140mV
4'b1010: 120mV
4'b1011: 100mV
4'b1100: 80mV
CO

4'b1101: 60mV
4'b1110: 40mV
4'b1111: 20mV
K

SLDO_ANA_
0A84 SLDO Control Register 7 8030
CON7
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TE

RG_
VCA
MIO RG_VCAMI
Name _ND RG_VCAMIO_CAL
O_VOSEL
IS_E
N
IA

Type RW RW RW
Reset 1 0 0 0 0 1 1
ED

Bit(s) Name Description

15 RG_VCAMIO_NDIS Enables power down NMOS
_EN 1'b1: Enable
1'b0: Disable
11:8 RG_VCAMIO_CAL Calibrates voltage
M

(4'b0000: 0mV)
4'b0000: 0mV
4'b0001: -20mV
4'b0010: -40mV
4'b0011: -60mV
4'b0100: -80mV
4'b0101: -100mV
4'b0110: -120mV

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Bit(s) Name Description

4'b0111: -140mV
4'b1000: 160mV

AL
4'b1001: 140mV
4'b1010: 120mV
4'b1011: 100mV
4'b1100: 80mV
4'b1101: 60mV
4'b1110: 40mV

TI
4'b1111: 20mV
5:4 RG_VCAMIO_VOS Selects output voltage
EL (2'b11: 1.8V)

EN
2'b00: 1.2V
2'b01: 1.3V
2'b10: 1.5V
2'b11: 1.8V

0A86
SLDO_ANA_
CON8
SLDO Control Register 8
ID 0070
NF
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RG_SLDO_RSV_ RG_SLDO_RSV_
Name
H L
Type RW RW
Reset 1 1 1 0 0 0
CO

Bit(s) Name Description

6:4 RG_SLDO_RSV_H
2:0 RG_SLDO_RSV_L RG_SLDO_RSV_L[2] is used in conjunction with
RG_VRF18_1_VOSEL[1:0].
K
TE

SLDO_ANA_
0A88 SLDO Control Register 9 0060
CON9
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RG_VSRAM_VOSEL
IA

Type RW
Reset 1 1 0 0 0 0 0

Bit(s) Name Description

6:0 RG_VSRAM_VOSE Selects LDO voltage

L (7'b0000000: 0.6V)
7'b0000000: 0.6V
7'b0000001: 0.6V + 6.25mV
7'b0000010: 0.6V + 6.25mV*2
M

7'b0000011: 0.6V + 6.25mV*3

7'b0000100: 0.6V + 6.25mV*4
7'b0000101: 0.6V + 6.25mV*5
7'b0000110: 0.6V + 6.25mV*6
7'b0000111: 0.6V + 6.25mV*7
7'b0001000: 0.6V + 6.25mV*8
7'b0001001: 0.6V + 6.25mV*9
7'b0001010: 0.6V + 6.25mV*10

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Bit(s) Name Description

7'b0001011: 0.6V + 6.25mV*11
7'b0001100: 0.6V + 6.25mV*12

AL
7'b0001101: 0.6V + 6.25mV*13
7'b0001110: 0.6V + 6.25mV*14
7'b0001111: 0.6V + 6.25mV*15
7'b0010000: 0.6V + 6.25mV*16
7'b0010001: 0.6V + 6.25mV*17
7'b0010010: 0.6V + 6.25mV*18

TI
7'b0010011: 0.6V + 6.25mV*19
7'b0010100: 0.6V + 6.25mV*20
7'b0010101: 0.6V + 6.25mV*21
7'b0010110: 0.6V + 6.25mV*22

EN
7'b0010111: 0.6V + 6.25mV23
7'b0011000: 0.6V + 6.25mV*24
7'b0011001: 0.6V + 6.25mV*25
7'b0011010: 0.6V + 6.25mV*26
7'b0011011: 0.6V + 6.25mV*27
7'b0011100: 0.6V + 6.25mV*28
7'b0011101: 0.6V + 6.25mV*29
7'b0011110: 0.6V + 6.25mV*30
7'b0011111: 0.6V + 6.25mV*31
7'b0100000: 0.6V + 6.25mV*32
ID
NF
7'b0100001: 0.6V + 6.25mV*33
7'b0100010: 0.6V + 6.25mV*34
7'b0100011: 0.6V + 6.25mV*35
7'b0100100: 0.6V + 6.25mV*36
7'b0100101: 0.6V + 6.25mV*37
CO

7'b0100110: 0.6V + 6.25mV*38

7'b0100111: 0.6V + 6.25mV*39
7'b0101000: 0.6V + 6.25mV*40
7'b0101001: 0.6V + 6.25mV*41
7'b0101010: 0.6V + 6.25mV*42
7'b0101011: 0.6V + 6.25mV*45
7'b0101100: 0.6V + 6.25mV*44
K

7'b0101101: 0.6V + 6.25mV*45

7'b0101110: 0.6V + 6.25mV*46
7'b0101111: 0.6V + 6.25mV*47
TE

7'b0110000: 0.6V + 6.25mV*48

7'b0110001: 0.6V + 6.25mV*49
7'b0110010: 0.6V + 6.25mV*50
7'b0110011: 0.6V + 6.25mV*51
7'b0110100: 0.6V + 6.25mV*52
7'b0110101: 0.6V + 6.25mV*53
IA

7'b0110110: 0.6V + 6.25mV*54

7'b0110111: 0.6V + 6.25mV*55
7'b0111000: 0.6V + 6.25mV*56
7'b0111001: 0.6V + 6.25mV*57
ED

7'b0111010: 0.6V + 6.25mV*58

7'b0111011: 0.6V + 6.25mV*59
7'b0111100: 0.6V + 6.25mV*60
7'b0111101: 0.6V + 6.25mV*61
7'b0111110: 0.6V + 6.25mV*62
7'b0111111: 0.6V + 6.25mV*63
M

7'b1000000: 0.6V + 6.25mV*64

7'b1000001: 0.6V + 6.25mV*65
7'b1000010: 0.6V + 6.25mV*66
7'b1000011: 0.6V + 6.25mV*67
7'b1000100: 0.6V + 6.25mV*68
7'b1000101: 0.6V + 6.25mV*69
7'b1000110: 0.6V + 6.25mV*70
7'b1000111: 0.6V + 6.25mV*71

MediaTek Confidential © 2015 MediaTek Inc. Page 195 of 304

Bit(s) Name Description

7'b1001000: 0.6V + 6.25mV*72
7'b1001001: 0.6V + 6.25mV*73

AL
7'b1001010: 0.6V + 6.25mV*74
7'b1001011: 0.6V + 6.25mV*75
7'b1001100: 0.6V + 6.25mV*76
7'b1001101: 0.6V + 6.25mV*77
7'b1001110: 0.6V + 6.25mV*78
7'b1001111: 0.6V + 6.25mV*79

TI
7'b1010000: 0.6V + 6.25mV*80
7'b1010001: 0.6V + 6.25mV*81
7'b1010010: 0.6V + 6.25mV*82
7'b1010011: 0.6V + 6.25mV*93

EN
7'b1010100: 0.6V + 6.25mV*84
7'b1010101: 0.6V + 6.25mV*85
7'b1010110: 0.6V + 6.25mV*86
7'b1010111: 0.6V + 6.25mV*87
7'b1011000: 0.6V + 6.25mV*88
7'b1011001: 0.6V + 6.25mV*89
7'b1011010: 0.6V + 6.25mV*90
7'b1011011: 0.6V + 6.25mV*91
7'b1011100: 0.6V + 6.25mV*92
7'b1011101: 0.6V + 6.25mV*93
ID
NF
7'b1011110: 0.6V + 6.25mV*94
7'b1011111: 0.6V + 6.25mV*95
7'b1100000: 0.6V + 6.25mV*96
7'b1100001: 0.6V + 6.25mV*97
7'b1100010: 0.6V + 6.25mV*98
CO

7'b1100011: 0.6V + 6.25mV*99

7'b1100100: 0.6V + 6.25mV*100
7'b1100101: 0.6V + 6.25mV*101
7'b1100110: 0.6V + 6.25mV*102
7'b1100111: 0.6V + 6.25mV*103
7'b1101000: 0.6V + 6.25mV*104
7'b1101001: 0.6V + 6.25mV*105
K

7'b1101010: 0.6V + 6.25mV*106

7'b1101011: 0.6V + 6.25mV*107
7'b1101100: 0.6V + 6.25mV*108
TE

7'b1101101: 0.6V + 6.25mV*109

7'b1101110: 0.6V + 6.25mV*110
7'b1101111: 0.6V + 6.25mV*111
7'b1110000: 0.6V + 6.25mV*112
7'b1110001: 0.6V + 6.25mV*113
7'b1110010: 0.6V + 6.25mV*114
IA

7'b1110011: 0.6V + 6.25mV*115

7'b1110100: 0.6V + 6.25mV*116
7'b1110101: 0.6V + 6.25mV*117
7'b1110110: 0.6V + 6.25mV*118
ED

7'b1110111: 0.6V + 6.25mV*119

7'b1111000: 0.6V + 6.25mV*120
7'b1111001: 0.6V + 6.25mV*121
7'b1111010: 0.6V + 6.25mV*122
7'b1111011: 0.6V + 6.25mV*123
7'b1111100: 0.6V + 6.25mV*124
M

7'b1111101: 0.6V + 6.25mV*125

7'b1111110: 0.6V + 6.25mV*126
7'b1111111: 0.6V + 6.25mV*127

MediaTek Confidential © 2015 MediaTek Inc. Page 196 of 304

SLDO_ANA_
0A8A SLDO Control Register10 8000
CON10

AL
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RG_ RG_
VSR VSR
RG_VSRA
AM_ AM_
Name M_NDIS_P
NDI PLC
LCUR
S_E UR_

TI
N EN
Type RW RW RW
Reset 1 0 0 0

EN
Bit(s) Name Description
15 RG_VSRAM_NDIS Enables LDO output power down NMOS discharge
_EN 1'b0: Disable output power-down
1'b1: Enable output power-down
2:1 RG_VSRAM_NDIS
_PLCUR (2'b00: 100mA)
2'b00: 100mA
2'b01: 130mA
2'b10: 130mA
ID
Selects discharge current for DVFS tracking
NF
2'b11: 160mA
0 RG_VSRAM_PLCU Improves VSRAM fast-transient
R_EN 0: Disable
1: Enable
CO

0A90 SPK_CON0 Speaker Control Register 0 0000

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPK SPK
K

SPK
_OU _TH SPK
_OC SPK SPK
RG_SPK_G T_S ER_ _TRI
Name _SH MOD _EN
AINL TAG SHD M_E
DN_ E_L _L
TE

E_S N_L N_L

DL
EL _EN
Type RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
IA

Bit(s) Name Description

13:12 RG_SPK_GAINL Controls speaker L-ch volume
2'b00: Mute
2'b01: -6dB
ED

2'b10: -3dB
2'b11: 0dB
10 SPK_OUT_STAGE_ Selects OUTSTAGE after trimming enabled
SEL 1'b0: Disable
1'b1: Enable
M

9 SPK_THER_SHDN Enables speaker L-ch thermal shut-down

_L_EN 1'b0: Disable
1'b1: Enable
8 SPK_OC_SHDN_D Class D mode L-ch OC event shut-down
L 1'b0: Normal
1'b1: Shut down (turn off SPK output stage)
3 SPK_TRIM_EN_L Enables class D mode L-ch trimming

MediaTek Confidential © 2015 MediaTek Inc. Page 197 of 304

Bit(s) Name Description

1'b0: Disable
1'b1: Enable

AL
2 SPKMODE_L Selects speaker L-ch driver mode
1'b0: Class D mode
1'b1: Class AB mode
0 SPK_EN_L Enables speaker amp. L-ch

TI
1'b0: Disable
1'b1: Enable

EN
0A92 SPK_CON1 Speaker Control Register 1 0000
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPK
SPK SPK SPK
_OF

ID
_TRI _LE _OF
FSE
Name M_D T_L
AD_ SPK_OFFSET_L_SW FSE
ONE L_S T_L
_MO
_L W _OV
DE
Type RO RW RW RW RO
NF
Reset 0 0 0 0 0 0 0 0 0

Bit(s) Name Description

15 SPK_TRIM_DONE Class D mode L-ch trimming done
CO

_L 1'b0: Not yet

1'b1: Done
14 SPK_OFFSET_L_M Selects SPK_OFFSET_L mode
ODE 1'b0: Calibration
1'b1: Software register mode
13 SPK_LEAD_L_SW Class D L-ch PWM polarity flag
K

12:8 SPK_OFFSET_L_S Speaker amplifier left channel offset trimming bit

W 5'b00000: 0mV
TE

5'b00001: 0.6mV
5'b00010: 1.2mV
xxx: xxxV (omit)
5'b11111: 18.6mV
7 SPK_OFFSET_L_O SPK_OFFSET_L overflow
IA

V
ED

0A94 SPK_CON2 Speaker Control Register 2 0014

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RG_ RG_ RG_ RG_
RG_ RG_ RG_
SPK SPK SPK SPK
SPK SPK SPK
AB_ _TE RG_SPKAB RG_SPK_S _FO _INT
Name _OC _DR RCV
M

OC_ ST_ _OBIAS_L LEW_L RCE G_R

_EN C_E _EN
EN_ EN_ _EN ST_
_L N_L _L
L L _L L
Type RW RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 1 0 1 0 0

Bit(s) Name Description

MediaTek Confidential © 2015 MediaTek Inc. Page 198 of 304

Bit(s) Name Description

10 RG_SPK_OC_EN_L Enables class D L-ch over-current protection
1'b0: Disable

AL
1'b1: Enable
9 RG_SPKAB_OC_E Enables class AB mode L-ch Over-current protection
N_L
8 RG_SPK_TEST_EN Enables test input into SPK stage

TI
_L (Not used)
7 RG_SPK_DRC_EN Reserved
_L (Not used)

EN
6 RG_SPKRCV_EN_L Reserved
1'b0: Disable
1'b1: Enable
5:4 RG_SPKAB_OBIAS Controls L-ch classAB SPK bias
_L 00: 2I

3:2 RG_SPK_SLEW_L
11: 8I step=2I

ID
Controls class D L-ch slew rate
00: 3/4 (default)10.8n /8.3n (rise/fall)
01: 4/4 8.8n /6.3n
NF
10: 1/4 16.4n /15n
11: 2/4 3.8n/12.6n
1 RG_SPK_FORCE_E Forces L-ch class D output state
N_L 1'b0: Disable
1'b1: Enable
CO

0 RG_SPK_INTG_RS Controls speaker L-ch integrator reset

T_L 1'b0: No reset
1'b1: Reset on
K

0A9C SPK_CON6 Speaker Control Register 6 0000

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TE

SPK SPK
_AB _D_
SPK_OC_T SPK_OC_ SPK_TRIM
Name _OC OC_ SPK_TRIM_WND
HD WND _THD
_L_ L_D
DEG EG
Type RO RO RW RW RW RW
IA

Reset 0 0 0 0 0 0 0 0 0 0 0

Bit(s) Name Description

15 SPK_AB_OC_L_DE Class AB L-ch OC flag with deglitch

G
14 SPK_D_OC_L_DEG Class D L-ch OC flag with deglitch
11:10 SPK_OC_THD Threshold setting in the decision window for SPK over current
status
M

2'b00: 4/8
2'b01: 3/8
2'b10: 2/8
2'b11: 1/8
9:8 SPK_OC_WND Decision window setting for SPK over current status
2'b00: 16us
2'b01: 32us
2'b10: 64us

MediaTek Confidential © 2015 MediaTek Inc. Page 199 of 304

Bit(s) Name Description

2'b11: 128us
5:4 SPK_TRIM_THD Threshold setting in the decision window for SPK offset status

AL
2'b00: 4/8
2'b01: 3/8
2'b10: 2/8
2'b11: 1/8
2:0 SPK_TRIM_WND Decision window setting for SPK offset status

TI
3'b000: 16us
3'b001: 32us
3'b010: 64us
3'b011: 128us

EN
3'b100: 256us
3'b101: 512us
3'b110: 1024us
3'b111: 2048us

0A9E SPK_CON7 Speaker Control Register 7

ID 4531
NF
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name SPK_TRIM_DIV SPK_TD3 SPK_TD2 SPK_TD1
Type RW RW RW RW
Reset 1 0 0 0 1 0 1 0 0 1 1 0 0 0 1
CO

Bit(s) Name Description

14:12 SPK_TRIM_DIV Divider of AD_NI_SPK_CK_PWM for trimming counter clock
3'b000: 8
3'b001: 16
3'b010: 32
3'b011: 64
K

3'b100: 128
3'b101: 256
3'b110: 512
TE

3'b111: 1024
11:8 SPK_TD3 Time delay3 for TRIM_EN
4'd0: 0ms
4'd1: 1ms
4'd2: 2ms
IA

4'dN: nms
4'd15: 15ms
7:4 SPK_TD2 Time delay2 for OUTSTG_EN
4'd0: 0ms
ED

4'd1: 1ms
4'd2: 2ms
4'dN: nms
4'd15: 15ms
3:0 SPK_TD1 Time delay1 for VCM_FAST
M

4'd0: 0ms
4'd1: 1ms
4'd2: 2ms
4'dN: nms
4'd15: 15ms

MediaTek Confidential © 2015 MediaTek Inc. Page 200 of 304

0AA0 SPK_CON8 Speaker Control Register 8 0000

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

AL
RG_ RG_ RG_
RG_ RG_ RG_ RG_
SPK SPK SPK
SPK SPK SPK SPK
_VC _EN _EN RG_SPK_I RG_BTL_
Name _OC AB_ _FB _VC RG_SPK_CCODE
M_I _VIE _VIE BIAS_SEL SET
TH_ OVD RC_ M_S
BSE W_C W_V
D RV EN EL
L LK CM
Type RW RW RW RW RW RW RW RW RW RW

TI
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit(s) Name Description

EN
14 RG_SPK_OCTH_D Speaker OC threshold level for D-mode
1'b0: Low (0.9A)
1'b1: High (1.5A)
13 RG_SPKAB_OVDR Output stage shoot-through current prevention in over-drive

12
V

RG_SPK_FBRC_EN
condition of class AB mode
1'b0: Disable
1'b1: Enable ID
Feedback grounded capacitor connection in class D state
NF
1'b0: Disable
1'b1: Enable
11 RG_SPK_VCM_IBS Selects speaker on-chip filter bias current level
EL 1'b0: Normal bias (low BW)
1'b1: Doubled bias (high BW)
CO

10 RG_SPK_VCM_SEL Selects speaker VCM source

1'b0: 0.5*AVDD43
1'b1: IR, I from BG
9 RG_SPK_EN_VIE Enables monitor class D PWM CLK
W_CLK
8 RG_SPK_EN_VIE Enables monitor speaker VCM reference voltage
K

W_VCM
7:4 RG_SPK_CCODE Class D modulation frequency control code
TE

x000: 288k
x001: 418.8k
x010: 541k
x011: 656k
x100: 766k
IA

x101: 966k
x110: 1.148M
x111: 1.646M
3:2 RG_SPK_IBIAS_SE Controls internal bias current generator
ED

L 2'b00: Default
2'b01: -20%
2'b10: +20%
2'b11: +10%
1:0 RG_BTL_SET Sets up class D BTL output when RG_FORCE_EN=1
M

<1> 1: SPK+ NMOS on; 0: SPK+ PMOS on

<0> 1: SPK- NMOS on; 0: SPK- PMOS on

0AA2 SPK_CON9 Speaker Control Register 9 2000

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

MediaTek Confidential © 2015 MediaTek Inc. Page 201 of 304

SPK SPK SPK

_TE _TE _VC SPK
Name ST_ ST_ M_F _RS RG_SPKPGA_GAINL
MOD MOD AST V0

AL
E1 E0 _EN
Type RW RW RW RW RW
Reset 0 0 1 0 0 0 0 0

Bit(s) Name Description

TI
15 SPK_TEST_MODE1 SPK testmode 1
14 SPK_TEST_MODE0 SPK testmode 0
13 SPK_VCM_FAST_E Enables QI_SPK_VCM_FAST in hardware mode

EN
N
12 SPK_RSV0
11:8 RG_SPKPGA_GAIN Controls speaker L PGA gain
L 4'b0000: Mute
4'b0001: 0dB
4'b0010: 4dB
4'b0011: 5dB
4'b0100: 6dB
4'b0101: 7dB
ID
NF
4'b0110: 8dB
4'b0111: 9dB
4'b1000: 10dB
4'b1001: 11dB
4'b1010: 12dB
CO

4'b1011: 13dB
4'b1100: 14dB
4'b1101: 15dB
4'b1110: 16dB
4'b1111: 17dB
K

0AA4 SPK_CON10 Speaker Control Register 10 0000

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name SPK_TD_DONE SPK_TD_WAIT
Type RW RW
Reset 0 0 0 0 0 0
IA

Bit(s) Name Description

6:4 SPK_TD_DONE Done time
3'b000: 10us
ED

3'b001: 50us
3'b010: 100us
3'b011: 300us
3'b100: 500us
3'b101: 1000us
3'b110: 1500us
M

3'b111: 2000us
2:0 SPK_TD_WAIT Wait time
3'b000: 10us
3'b001: 50us
3'b010: 100us
3'b011: 300us
3'b100: 500us
3'b101: 1000us

MediaTek Confidential © 2015 MediaTek Inc. Page 202 of 304

Bit(s) Name Description

3'b110: 1500us
3'b111: 2000us

AL
0AA6 SPK_CON11 Speaker Control Register 11 0000

TI
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPK SPK SPK
SPK SPK
_TRI _OU SPK _DE SPK SPK SPK
_TRI _VC
M_S TST _EN POP MOD _RS _EN
Name TOP M_E
G_E _L_ _EN E_L T_L
M_F
_MO

EN
N_L AST
_L_ N_L SW _L_ _SW _SW DE
_SW _SW
SW _SW SW
Type RW RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0

Bit(s)
15
Name
SPK_TRIM_STOP_
L_SW
Description
ID
Class D mode offset trimming stop flag for L-ch
NF
13 SPK_TRIM_EN_L_ Class D mode L-ch offset trimming start flag
SW
11 SPK_OUTSTG_EN_ Speaker left channel output stage enable control
L_SW
9 SPK_EN_L_SW Enables speaker amp. L-ch
CO

1'b0: Disable
1'b1: Enable
7 SPK_DEPOP_EN_L Class D L-ch mode depop enabled flag
_SW
5 SPKMODE_L_SW Selects speaker L-ch driver mode
1'b0: Class D mode
K

1'b1: Class AB mode

3 SPK_RST_L_SW Resets class D L-ch
TE

1'b0: Normal
1'b1: Reset
1 SPK_VCM_FAST_S Speeds up speaker VCM settling when enabled
W 1'b0: Normal
1'b1: Fast charging
IA

0 SPK_EN_MODE Selects speaker enable sequence

1'b0: HW
1'b1: SW (register mode)
ED

0AA8 SPK_CON12 Speaker Control Register 12 0000

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M

RG_ RG_
RG_ SPK SPK
SPK _ISE _ISE
RG_SPK_ISENSE RG_SPK_ISENSE
Name _ISE NSE
_GAINSEL _REFSEL
NSE
NSE _PD _TE
_EN RES ST_
ET EN
Type RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0

MediaTek Confidential © 2015 MediaTek Inc. Page 203 of 304

Bit(s) Name Description

AL
15 RG_SPK_ISENSE_ Enables class AB current sensing circuit
EN 1'b0: Disable
1'b1: Enable
14 RG_SPK_ISENSE_ Resets class AB current sensing peak detection
PDRESET 1'b0: Disable

TI
1'b1: Enable
13:11 RG_SPK_ISENSE_ Selects class AB current sensing circuit gain
GAINSEL 3'b000: 0dB
3'b001: 6dB

EN
3'b010: 12dB
3'b011: 18dB
3'b100: 24dB
3'b101: 30dB
3'b110~3'b111: Reserved
10:8 RG_SPK_ISENSE_
REFSEL 3'b000: AVSS43_SPK
ID
selects class AB current sensing circuit reference

3'b001: NMOS gate voltage @40uA

3'b010: NMOS gate voltage @80uA
NF
3'b011: NMOS gate voltage @120uA
3'b100: NMOS gate voltage @160uA
3'b101: NMOS gate voltage @200uA
3'b110: NMOS gate voltage @240uA
3'b111: NMOS gate voltage @280uA
CO

7 RG_SPK_ISENSE_ (Not used)

TEST_EN 1'b0: Disable
1'b1: Enable
K

0AAA SPK_CON13 Speaker Control Register 13 0000

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RG_SPK_RSV0 RG_SPK_RSV1
TE

Type RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit(s) Name Description

15:8 RG_SPK_RSV0 [15:14]: Not used

[13]: Enable Class-AB CLP
[12:11]: Additional control on offset trimming circuit
2'b00: Normal operation (triangle modulation waveform)
ED

2'b11: Trimming operation (sawtooth modulation waveform)

[10]: RG_TRIM_INV
1'b1: Inverting phase
1'b0: Default phase
[9]: Enable Class-AB DFC (EN_AB_DFC)
[8]: Enable PGA DLCK (EN_PGA_DLCK)
M

7:0 RG_SPK_RSV1 (Not used)

0AAC SPK_CON14 Speaker Control Register 14 0000

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

MediaTek Confidential © 2015 MediaTek Inc. Page 204 of 304

RG_ RG_
SPK SPK
_AB _AB RG_SPK_A
Name RG_SPK_RSV2 D_C D_V BD_VOLSE

AL
URS OLS N_GAIN
EN_ EN_
SEL EN
Type RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0

TI
Bit(s) Name Description
15:8 RG_SPK_RSV2 (Not used)

EN
7 RG_SPK_ABD_CU (Not used)
RSEN_SEL
6 RG_SPK_ABD_VO Controls class ABD voltage sensing
LSEN_EN 1'b0: Disable
1'b1: Enable
5:4 RG_SPK_ABD_VO
LSEN_GAIN 2'b00: -6dB
2'bx1: -18dB
2'b10: -12dB
ID
Controls class ABD voltage sensing gain
NF

0AAE SPK_CON15 Speaker Control Register 15 0000

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RG_SPK_TRIM1 RG_SPK_TRIM2
Type RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit(s) Name Description

15:8 RG_SPK_TRIM1 (Not used)

7:0 RG_SPK_TRIM2 (Not used)
TE

0AB0 SPK_CON16 Speaker Control Register 16 0000

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IA

RG_
RG_
SPK
SPK
_AB RG_SPK_A RG_SPK_D
RG_SPK_AB_CURSEN_RSET _D_ RG_SPK_D_CURSEN_RSETS
Name _CU B_CURSEN
SEL CUR
_CURSEN_
EL
ED

RSE _GAIN GAIN

SEN
N_E
_EN
N
Type RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
M

Bit(s) Name Description

15 RG_SPK_AB_CURS Controls class AB current sensing
EN_EN 1'b0: Disable
1'b1: Enable
14:13 RG_SPK_AB_CURS Controls class AB current sensing grain
EN_GAIN 2'b00: -6dB
2'bx1: -18dB

MediaTek Confidential © 2015 MediaTek Inc. Page 205 of 304

Bit(s) Name Description

2'b10: -12dB
12:8 RG_SPK_AB_CURS (Not used)

AL
EN_RSETSEL
7 RG_SPK_D_CURSE (Not used)
N_EN
6:5 RG_SPK_D_CURSE (Not used)

TI
N_GAIN
4:0 RG_SPK_D_CURSE (Not used)
N_RSETSEL

EN
SPK_ANA_C
0AB2 SPK Control Register 0 0000
ON0
Bit
Name
Type
Reset
15 14 13
RG_SPKPGA_GAIN

0 0
RW
0 0
12 11 10 9

ID 8 7 6 5 4 3 2 1 0
NF
Bit(s) Name Description
14:11 RG_SPKPGA_GAIN Controls speaker PGA gain
0000: Mute
0001: 0dB
CO

0010: 4dB
0011: 5dB
0100: 6dB
0101: 7dB
0110: 8dB
0111: 9dB
1000: 10dB
K

1001: 11dB
1010: 12dB
1011: 13dB
TE

1100: 14dB
1101: 15dB
1110: 16dB
1111: 17dB
IA

SPK_ANA_C
0AB4 SPK Control Register 1 0000
ON1
ED

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RG_
ISEN
SE_
Name RG_SPK_RSV
PD_
M

RES
ET
Type RW RW
Reset 0 0 0 0 0 0 0 0 0

Bit(s) Name Description

11 RG_ISENSE_PD_R Resets class AB current sensing peak detector

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Bit(s) Name Description

ESET 0: Disable
1: Enable

AL
7:0 RG_SPK_RSV Reserved

TI
SPK_ANA_C
0AB6 SPK Control Register 3 0000
ON3
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RG_

EN
RG_ RG_
AUD
AUD AUD
IVLS
IVL IVLP
RG_AUDIVLMUX TAR
Name MUT
SEL_VAUDP12 TUP
WR
E_V UP_
_VA
AUD VAU
UDP
P12 DP12
Type
Reset
RW
0 0 ID
RW
0 0
12
RW
0
RW
0
NF
Bit(s) Name Description
9 RG_AUDIVLMUTE Enables audio left channel I-V buffer mute
_VAUDP12
8:6 RG_AUDIVLMUXS Selects audio left channel IV buffer mux
CO

EL_VAUDP12 Positive/negative pins:

000: Open/Open
001: FM stereo mode
010: FM mono mode
011: Open/Open
100: Audio playback mode
101: Audio + FM stereo mode
K

110: Audio + FM mono mode

111: Audio playback mode
5 RG_AUDIVLSTART Enables audio left channel I-V buffer startup
TE

UP_VAUDP12
4 RG_AUDIVLPWRU Powers up audio left channel I-V buffer
P_VAUDP12
IA

0C00 OTP_CON0 OTP Control Register 0 0000

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ED

Name RG_OTP_PA
Type RW
Reset 0 0 0 0 0 0

Bit(s) Name Description

5:0 RG_OTP_PA OTP PA

0C02 OTP_CON1 OTP Control Register 1 0000

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

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Name RG_OTP_PDIN
Type RW
Reset 0 0 0 0 0 0 0 0

AL
Bit(s) Name Description
7:0 RG_OTP_PDIN OTP PDIN

TI
0C04 OTP_CON2 OTP Control Register 2 0000
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

EN
RG_OTP_
Name PTM
Type RW
Reset 0 0

Bit(s)
1:0
Name
RG_OTP_PTM
Description
OTP PTM ID
NF
0C06 OTP_CON3 OTP Control Register 3 0000
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CO

RG_OTP_
Name
PWE
Type RW
Reset 0 0

Bit(s) Name Description

1:0 RG_OTP_PWE OTP PWE

0C08 OTP_CON4 OTP Control Register 4 0000

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RG_
IA

OTP
Name
_PP
ROG
Type RW
Reset 0
ED

Bit(s) Name Description

0 RG_OTP_PPROG OTP PPROG
M

0C0A OTP_CON5 OTP Control Register 5 0000

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RG_
OTP
Name
_PW
E_S

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RC
Type RW
Reset 0

AL
Bit(s) Name Description
0 RG_OTP_PWE_SR Selects OTP write (fusing) PWE source
C 0: From IO pad
1: From register

TI
EN
0C0C OTP_CON6 OTP Control Register 6 0000
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RG_OTP_PROG_PKEY
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit(s)
15:0
Name
RG_OTP_PROG_P
Description
OTP write (fusing) match key
ID
NF
KEY

0C0E OTP_CON7 OTP Control Register 7 0000

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Nam RG_OTP_RD_PKEY
e
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
K

Bit(s) Name Description

15:0 RG_OTP_RD_PKE OTP read match key
TE

0C10 OTP_CON8 OTP Control Register 8 0000

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RG_
OTP
Name _RD
ED

_TRI
G
Type RW
Reset 0
M

Bit(s) Name Description

0 RG_OTP_RD_TRIG OTP SW read trigger

0C12 OTP_CON9 OTP Control Register 9 0000

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Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RG_
RD_
RDY

AL
Name
_BY
PAS
S
Type RW
Reset 0

TI
Bit(s) Name Description
0 RG_RD_RDY_BYP Bypasses OTP read ready delay
ASS

EN
0: Does not bypass
1: Bypass

0C14
Bit 15
OTP_CON10
14 13 12
OTP Control Register 10
11 10 9
ID 8 7 6 5 4 3 2 1
0000
0
RG_
SKIP
NF
Name _OT
P_O
UT
Type RW
Reset 0
CO

Bit(s) Name Description

0 RG_SKIP_OTP_OU Skips reading from EFUSE macro
T 0: Does not skip
1: Skip
K

0C16 OTP_CON11 OTP Control Register 11 0000

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RG_
OTP
Name _RD
_SW
IA

Type RW
Reset 0
ED

Bit(s) Name Description

0 RG_OTP_RD_SW SW trigger read mode
0: Not SW trigger read mode
1: SW trigger read mode
M

0C18 OTP_CON12 OTP Control Register 12 0000

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RG_OTP_DOUT_SW
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

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Bit(s) Name Description

AL
15:0 RG_OTP_DOUT_S Current SW trigger read value
W

TI
0C1A OTP_CON13 OTP Control Register 13 0000
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RG_ RG_
OTP OTP

EN
Name _RD _RD
_AC _BU
K SY
Type RO RO
Reset 0 0

Bit(s)
2
0
Name
RG_OTP_RD_ACK
RG_OTP_RD_BUS
Description
OTP read ack
OTP busy status
ID
NF
Y
CO

0C1C OTP_CON14 OTP Control Register 14 0000

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RG_OTP_PA_SW
Type RO
Reset 0 0 0 0 0
K

Bit(s) Name Description

4:0 RG_OTP_PA_SW Current SW trigger read row
TE

OTP_DOUT_
0C1E OTP dout 0 15 0000
0_15
IA

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RG_OTP_DOUT_0_15
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ED

Bit(s) Name Description

15:0 RG_OTP_DOUT_0
_15
M

OTP_DOUT_
0C20 OTP dout 16 31 0000
16_31
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RG_OTP_DOUT_16_31

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Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

AL
Bit(s) Name Description
15:0 RG_OTP_DOUT_16
_31

TI
OTP_DOUT_
0C22 OTP dout 32 47 0000
32_47

EN
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RG_OTP_DOUT_32_47
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit(s)
15:0
Name
RG_OTP_DOUT_3
2_47
Description
ID
NF

OTP_DOUT_
0C24 OTP dout 48 63 0000
48_63
CO

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RG_OTP_DOUT_48_63
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
K

Bit(s) Name Description

15:0 RG_OTP_DOUT_4
8_63
TE

OTP_DOUT_
0C26 OTP dout 64 79 0000
IA

64_79
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RG_OTP_DOUT_64_79
Type RO
ED

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit(s) Name Description

15:0 RG_OTP_DOUT_6
M

4_79

OTP_DOUT_
0C28 OTP dout 80 95 0000
80_95
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

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Name RG_OTP_DOUT_80_95
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

AL
Bit(s) Name Description
15:0 RG_OTP_DOUT_8
0_95

TI
OTP_DOUT_
0C2A OTP dout 96 111 0000

EN
96_111
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RG_OTP_DOUT_96_111
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit(s)
15:0
Name
RG_OTP_DOUT_9
Description ID
NF
6_111

OTP_DOUT_
CO

0C2C OTP dout 112 127 0000

112_127
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RG_OTP_DOUT_112_127
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
K

Bit(s) Name Description

15:0 RG_OTP_DOUT_11
TE

2_127
IA

OTP_DOUT_
0C2E OTP dout 128 143 0000
128_143
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RG_OTP_DOUT_128_143
ED

Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit(s) Name Description

15:0 RG_OTP_DOUT_12
8_143

OTP_DOUT_
0C30 OTP dout 144 159 0000
144_159

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Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RG_OTP_DOUT_144_159
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

AL
Bit(s) Name Description
15:0 RG_OTP_DOUT_14
4_159

TI
EN
OTP_DOUT_
0C32 OTP dout 160 175 0000
160_175
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RG_OTP_DOUT_160_175
Type RO
Reset

Bit(s)
0

Name
0 0 0 0

Description
0 0 0

ID
0 0 0 0 0 0 0 0
NF
15:0 RG_OTP_DOUT_16
0_175
CO

OTP_DOUT_
0C34 OTP dout 176 191 0000
176_191
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RG_OTP_DOUT_176_191
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
K

Bit(s) Name Description

RG_OTP_DOUT_17
15:0
6_191
IA

OTP_DOUT_
0C36 OTP dout 192 207 0000
192_207
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ED

Name RG_OTP_DOUT_192_207
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit(s) Name Description

RG_OTP_DOUT_19
15:0
2_207

OTP_DOUT_
0C38 OTP dout 208 223 0000
208_223

AL
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RG_OTP_DOUT_208_223
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TI
Bit(s) Name Description
15:0 RG_OTP_DOUT_2
08_223

EN
OTP_DOUT_
0C3A OTP dout 224 239 0000
224_239
Bit
Name
Type
Reset
15

0
14

0
13

0
12

0
11

0
10

0
9
ID 8
RG_OTP_DOUT_224_239

0 0
RO
0 0
7 6 5

0
4

0
3

0
2

0
1

0
0

0
NF
Bit(s) Name Description
15:0 RG_OTP_DOUT_2
24_239
CO

OTP_DOUT_
0C3C OTP dout 240 255 0000
240_255
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
K

Name RG_OTP_DOUT_240_255
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
TE

Bit(s) Name Description

15:0 RG_OTP_DOUT_2
40_255
IA
ED

OTP_DOUT_
0C3E OTP dout 256 271 0000
256_271
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RG_OTP_DOUT_256_271
Type RO
M

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit(s) Name Description

15:0 RG_OTP_DOUT_25
6_271

OTP_DOUT_
0C40 OTP dout 272 287 0000
272_287

AL
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RG_OTP_DOUT_272_287
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TI
Bit(s) Name Description
15:0 RG_OTP_DOUT_27
2_287

EN
OTP_DOUT_
0C42 OTP dout 288 303 0000
288_303
Bit
Name
Type
Reset
15

0
14

0
13

0
12

0
11

0
10

0
9
ID 8
RG_OTP_DOUT_288_303

0 0
RO
0 0
7 6 5

0
4

0
3

0
2

0
1

0
0

0
NF
Bit(s) Name Description
15:0 RG_OTP_DOUT_2
88_303
CO

OTP_DOUT_
0C44 OTP dout 304 319 0000
304_319
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
K

Name RG_OTP_DOUT_304_319
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
TE

Bit(s) Name Description

15:0 RG_OTP_DOUT_3
04_319
IA
ED

OTP_DOUT_
0C46 OTP dout 320 335 0000
320_335
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RG_OTP_DOUT_320_335
Type RO
M

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit(s) Name Description

15:0 RG_OTP_DOUT_3
20_335

OTP_DOUT_
0C48 OTP dout 336 351 0000
336_351

AL
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RG_OTP_DOUT_336_351
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TI
Bit(s) Name Description
15:0 RG_OTP_DOUT_33
6_351

EN
OTP_DOUT_
0C4A OTP dout 352 367 0000
352_367
Bit
Name
Type
Reset
15

0
14

0
13

0
12

0
11

0
10

0
9
ID 8
RG_OTP_DOUT_352_367

0 0
RO
0 0
7 6 5

0
4

0
3

0
2

0
1

0
0

0
NF
Bit(s) Name Description
15:0 RG_OTP_DOUT_35
2_367
CO

OTP_DOUT_
0C4C OTP dout 368 383 0000
368_383
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
K

Name RG_OTP_DOUT_368_383
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
TE

Bit(s) Name Description

15:0 RG_OTP_DOUT_3
68_383
IA
ED

OTP_DOUT_
0C4E OTP dout 384 399 0000
384_399
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RG_OTP_DOUT_384_399
Type RO
M

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit(s) Name Description

15:0 RG_OTP_DOUT_3
84_399

OTP_DOUT_
0C50 OTP dout 400 415 0000
400_415

AL
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RG_OTP_DOUT_400_415
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TI
Bit(s) Name Description
RG_OTP_DOUT_4
15:0
00_415

EN
OTP_DOUT_
0C52 OTP dout 416 431 0000
416_431
Bit
Name
Type
Reset
15

0
14

0
13

0
12

0
11

0
10

0
9
ID 8
RG_OTP_DOUT_416_431

0 0
RO
0 0
7 6 5

0
4

0
3

0
2

0
1

0
0

0
NF
Bit(s) Name Description
15:0 RG_OTP_DOUT_41
6_431
CO

OTP_DOUT_
0C54 OTP dout 432 447 0000
432_447
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
K

Name RG_OTP_DOUT_432_447
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
TE

Bit(s) Name Description

15:0 RG_OTP_DOUT_4
32_447
IA
ED

OTP_DOUT_
0C56 OTP dout 448 463 0000
448_463
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RG_OTP_DOUT_448_463
Type RO
M

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit(s) Name Description

15:0 RG_OTP_DOUT_4
48_463

OTP_DOUT_
0C58 OTP dout 464 479 0000
464_479

AL
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RG_OTP_DOUT_464_479
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TI
Bit(s) Name Description
15:0 RG_OTP_DOUT_4
64_479

EN
OTP_DOUT_
0C5A OTP dout 480 495 0000
480_495
Bit
Name
Type
Reset
15

0
14

0
13

0
12

0
11

0
10

0
9
ID 8
RG_OTP_DOUT_480_495

0 0
RO
0 0
7 6 5

0
4

0
3

0
2

0
1

0
0

0
NF
Bit(s) Name Description
15:0 RG_OTP_DOUT_4
80_495
CO

OTP_DOUT_
0C5C OTP dout 496 511 0000
496_511
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
K

Name RG_OTP_DOUT_496_511
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
TE

Bit(s) Name Description

15:0 RG_OTP_DOUT_4
96_511
IA
ED

OTP_VAL_0
0C5E OTP val 0 15 0048
_15
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RG_OTP_VAL_0_15
Type RW
M

Reset 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0

Bit(s) Name Description

15:0 RG_OTP_VAL_0_1
5

OTP_VAL_1
0C60 OTP val 16 31 00B0
6_31

AL
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RG_OTP_VAL_16_31
Type RW
Reset 0 0 0 0 0 0 0 0 1 0 1 1 0 0 0 0

TI
Bit(s) Name Description
15:0 RG_OTP_VAL_16_
31

EN
OTP_VAL_3
0C62 OTP val 32 47 0160
2_47
Bit
Name
Type
Reset
15

0
14

0
13

0
12

0
11

0
10

0
9
ID 8
RG_OTP_VAL_32_47

0 1
RW
0 1
7 6 5

1
4

0
3

0
2

0
1

0
0

0
NF
Bit(s) Name Description
15:0 RG_OTP_VAL_32_
47
CO

OTP_VAL_4
0C64 OTP val 48 63 0000
8_63
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
K

Name RG_OTP_VAL_48_63
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
TE

Bit(s) Name Description

15:0 RG_OTP_VAL_48_
63
IA
ED

OTP_VAL_6
0C66 OTP val 64 79 0000
4_79
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RG_OTP_VAL_64_79
Type RW
M

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit(s) Name Description

15:0 RG_OTP_VAL_64_
79

OTP_VAL_8
0C68 OTP val 80 95 0000
0_95

AL
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RG_OTP_VAL_80_95
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TI
Bit(s) Name Description
15:0 RG_OTP_VAL_80_
95

EN
OTP_VAL_9
0C6A OTP val 96 111 0000
6_111
Bit
Name
Type
Reset
15

0
14

0
13

0
12

0
11

0
10

0
9
ID 8
RG_OTP_VAL_96_111

0 0
RW
0 0
7 6 5

0
4

0
3

0
2

0
1

0
0

0
NF
Bit(s) Name Description
15:0 RG_OTP_VAL_96_
111
CO

OTP_VAL_11
0C6C OTP val 112 127 0000
2_127
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
K

Name RG_OTP_VAL_112_127
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
TE

Bit(s) Name Description

15:0 RG_OTP_VAL_112
_127
IA
ED

OTP_VAL_1
0C6E OTP val 128 143 000C
28_143
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RG_OTP_VAL_128_143
Type RW
M

Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0

Bit(s) Name Description

15:0 RG_OTP_VAL_128
_143

OTP_VAL_1
0C70 OTP val 144 159 D000
44_159

AL
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RG_OTP_VAL_144_159
Type RW
Reset 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0

TI
Bit(s) Name Description
15:0 RG_OTP_VAL_144
_159

EN
OTP_VAL_1
0C72 OTP val 160 175 8000
60_175
Bit
Name
Type
Reset
15

1
14

0
13

0
12

0
11

0
10

0
9
ID 8
RG_OTP_VAL_160_175

0 0
RW
0 0
7 6 5

0
4

0
3

0
2

0
1

0
0

0
NF
Bit(s) Name Description
15:0 RG_OTP_VAL_160
_175
CO

OTP_VAL_17
0C74 OTP val 176 191 0001
6_191
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
K

Name RG_OTP_VAL_176_191
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
TE

Bit(s) Name Description

15:0 RG_OTP_VAL_176
_191
IA
ED

OTP_VAL_1
0C76 OTP val 192 207 0000
92_207
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RG_OTP_VAL_192_207
Type RW
M

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit(s) Name Description

RG_OTP_VAL_192
15:0
_207

OTP_VAL_2
0C78 OTP val 208 223 0000
08_223

AL
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RG_OTP_VAL_208_223
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TI
Bit(s) Name Description
15:0 RG_OTP_VAL_208
_223

EN
OTP_VAL_2
0C7A OTP val 224 239 0000
24_239
Bit
Name
Type
Reset
15

0
14

0
13

0
12

0
11

0
10

0
9
ID 8
RG_OTP_VAL_224_239

0 0
RW
0 0
7 6 5

0
4

0
3

0
2

0
1

0
0

0
NF
Bit(s) Name Description
15:0 RG_OTP_VAL_224
_239
CO

OTP_VAL_2
0C7C OTP val 240 255 0000
40_255
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
K

Name RG_OTP_VAL_240_255
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
TE

Bit(s) Name Description

15:0 RG_OTP_VAL_240
_255
IA
ED

OTP_VAL_2
0C7E OTP val 256 271 0000
56_271
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RG_OTP_VAL_256_271
Type RW
M

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit(s) Name Description

15:0 RG_OTP_VAL_256
_271

OTP_VAL_2
0C80 OTP val 272 287 0000
72_287

AL
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RG_OTP_VAL_272_287
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TI
Bit(s) Name Description
15:0 RG_OTP_VAL_272
_287

EN
OTP_VAL_2
0C82 OTP val 288 303 0000
88_303
Bit
Name
Type
Reset
15

0
14

0
13

0
12

0
11

0
10

0
9
ID 8
RG_OTP_VAL_288_303

0 0
RW
0 0
7 6 5

0
4

0
3

0
2

0
1

0
0

0
NF
Bit(s) Name Description
15:0 RG_OTP_VAL_288
_303
CO

OTP_VAL_3
0C84 OTP val 304 319 0000
04_319
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
K

Name RG_OTP_VAL_304_319
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
TE

Bit(s) Name Description

15:0 RG_OTP_VAL_304
_319
IA
ED

OTP_VAL_3
0C86 OTP val 320 335 0000
20_335
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RG_OTP_VAL_320_335
Type RW
M

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit(s) Name Description

15:0 RG_OTP_VAL_320
_335

OTP_VAL_3
0C88 OTP val 336 351 0000
36_351

AL
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RG_OTP_VAL_336_351
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TI
Bit(s) Name Description
15:0 RG_OTP_VAL_336
_351

EN
OTP_VAL_3
0C8A OTP val 352 367 0000
52_367
Bit
Name
Type
Reset
15

0
14

0
13

0
12

0
11

0
10

0
9
ID 8
RG_OTP_VAL_352_367

0 0
RW
0 0
7 6 5

0
4

0
3

0
2

0
1

0
0

0
NF
Bit(s) Name Description
15:0 RG_OTP_VAL_352
_367
CO

OTP_VAL_3
0C8C OTP val 368 383 0000
68_383
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
K

Name RG_OTP_VAL_368_383
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
TE

Bit(s) Name Description

15:0 RG_OTP_VAL_368
_383
IA
ED

OTP_VAL_3
0C8E OTP val 384 399 0000
84_399
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RG_OTP_VAL_384_399
Type RW
M

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit(s) Name Description

15:0 RG_OTP_VAL_384
_399

OTP_VAL_4
0C90 OTP val 400 415 0000
00_415

AL
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RG_OTP_VAL_400_415
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TI
Bit(s) Name Description
15:0 RG_OTP_VAL_400
_415

EN
OTP_VAL_4
0C92 OTP val 416 431 0000
16_431
Bit
Name
Type
Reset
15

0
14

0
13

0
12

0
11

0
10

0
9
ID 8
RG_OTP_VAL_416_431

0 0
RW
0 0
7 6 5

0
4

0
3

0
2

0
1

0
0

0
NF
Bit(s) Name Description
RG_OTP_VAL_416
15:0
_431
CO

OTP_VAL_4
0C94 OTP val 432 447 0000
32_447
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
K

Name RG_OTP_VAL_432_447
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
TE

Bit(s) Name Description

15:0 RG_OTP_VAL_432
_447
IA
ED

OTP_VAL_4
0C96 OTP val 448 463 0000
48_463
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RG_OTP_VAL_448_463
Type RW
M

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit(s) Name Description

15:0 RG_OTP_VAL_448
_463

OTP_VAL_4
0C98 OTP val 464 479 0000
64_479

AL
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RG_OTP_VAL_464_479
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TI
Bit(s) Name Description
15:0 RG_OTP_VAL_464
_479

EN
OTP_VAL_4
0C9A OTP val 480 495 0000
80_495
Bit
Name
Type
Reset
15

0
14

0
13

0
12

0
11

0
10

0
9
ID 8
RG_OTP_VAL_480_495

0 0
RW
0 0
7 6 5

0
4

0
3

0
2

0
1

0
0

0
NF
Bit(s) Name Description
15:0 RG_OTP_VAL_480
_495
CO

OTP_VAL_4
0C9C OTP val 496 511 0000
96_511
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
K

Name RG_OTP_VAL_496_511
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
TE

Bit(s) Name Description

15:0 RG_OTP_VAL_496
_511
IA
ED

FGADC_CON
0CA6 FGADC Control Register 1 0000
1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name FG_CAR_31_16
Type RO
M

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit(s) Name Description

15:0 FG_CAR_31_16 Current charge value[31:16]

FGADC_CON
0CA8 FGADC Control Register 2 0000
2

AL
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name FG_CAR_15_00
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TI
Bit(s) Name Description
15:0 FG_CAR_15_00 Current charge value[15:0]

EN
FGADC_CON
0CAA FGADC Control Register 3 0000
3
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
Type
Reset 0 0 0 0 0 ID 0
FG_NTER_29_16

0
RO
0 0 0 0 0 0 0
NF
Bit(s) Name Description
13:0 FG_NTER_29_16 Current charge time value[29:16]
CO

FGADC_CON
0CAC FGADC Control Register 4 0000
4
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name FG_NTER_15_00
Type RO
K

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
TE

Bit(s) Name Description

15:0 FG_NTER_15_00 Current charge time value[15:0]
IA

FGADC_CON
0CB2 FGADC Control Register 7 0000
7
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ED

Name FG_CURRENT_OUT
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
M

Bit(s) Name Description

15:0 FG_CURRENT_OU Current output charge of first stage[15:0]
T

FGADC_CON
0CB8 FGADC Control Register 10 0000
10

AL
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RG_
FGI
Name RG_SPARE RG_FGANALOGTEST
NTM
ODE
Type RW RW RW

TI
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit(s) Name Description

EN
12:5 RG_SPARE Reserved bits
4 RG_FGINTMODE 0: Battery bottom mode
1: Battery top mode
3:0 RG_FGANALOGTE FGADC test bits
ST

AUDDEC_A
ID
NF
0CDC AUDDEC Control Register 0 0000
NA_CON0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RG_ RG_ RG_ RG_ RG_ RG_ RG_
RG_ RG_ RG_
AUD AUD AUD AUD AUD AUD AUD
AUD AUD AUD
CO

HPR HPL HSS RG_AUDH RG_AUDH RG_AUDH _DA _DA DAC DAC
HPR HPL HSP
Name SCDI SCDI CDIS PRMUXIN PLMUXIN SMUXINP
PWR PWR WR
C_P C_P RPW LPW
SAB SAB ABL PUTSEL_V PUTSEL_V UTSEL_VA WL_ WR_ RUP RUP
UP_ UP_ UP_
LE_ LE_ E_V AUDP15 AUDP15 UDP15 UP_ UP_ _VA _VA
VAU VAU VAU
VAU VAU AUD VA2 VA2 UDP UDP
DP15 DP15 DP15
DP15 DP15 P15 8 8 15 15
Type RW RW RW RW RW RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
K

Bit(s) Name Description

15 RG_AUDHPRSCDIS Disables headphone right short circuit protection

ABLE_VAUDP15
14 RG_AUDHPLSCDIS Disables headphone left short circuit protection
ABLE_VAUDP15
IA

13 RG_AUDHSSCDISA Disables headset short circuit protection

BLE_VAUDP15
12:11 RG_AUDHPRMUXI Selects audio right headphone input multiplexer
NPUTSEL_VAUDP1 Positive/negative pins:
ED

5 00: Open/Open
01: LoudSPK playback
10: Audio playback
11: Test mode
10:9 RG_AUDHPLMUXI Selects audio left headphone input multiplexer
M

NPUTSEL_VAUDP1 Positive/negative pins:

5 00: Open/Open
01: LoudSPK playback
10: Audio playback
11: Test mode
8:7 RG_AUDHSMUXIN Selects audio handset input multiplexer Positive/negative pins:
PUTSEL_VAUDP15 00: Open/Open
01: Mute (input grounded)

Bit(s) Name Description

10: Voice playback
11: Test mode

AL
6 RG_AUDHPRPWR Powers up audio right headphone
UP_VAUDP15
5 RG_AUDHPLPWR Powers up audio left headphone
UP_VAUDP15

TI
4 RG_AUDHSPWRUP Powers up audio headset
_VAUDP15
3 RG_AUD_DAC_PW Controls power-down for left channel audio biasgen
L_UP_VA28 0: Power down

EN
1: Enable
2 RG_AUD_DAC_PW Controls power-down for right channel audio biasgen
R_UP_VA28 0: Power down
1: Enable
1 RG_AUDDACRPWR Controls power-down for right-channel audio DAC

0
UP_VAUDP15

RG_AUDDACLPWR
UP_VAUDP15
0: Power down
1: Enable ID
Controls power-down for left-channel audio DAC
NF
0: Power down
1: Enable
CO

AUDDEC_A
0CDE AUDDEC Control Register 1 0000
NA_CON1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RG_ RG_ RG_ RG_
RG_ RG_ RG_ RG_ RG_ RG_ RG_ RG_ RG_ RG_ RG_
PRE AUD AUD AUD
HSO HSI HSO HSI HPO HPO HPI HPO HPI AUD AUD
CHA HSB HPR HPL
UTP NPU UTP NPU UT_ UTP NPU UTP NPU HSS HPS
K

RGE SCC BSC BSC

UTR TRE UTS TST SHO UTR TRE UTS TST TAR TAR
Name BUF URR CUR CUR
ESE SET TBE BEN RTV ESE SET TBE BEN TUP TUP
_EN ENT REN REN
T0_ 0_V NH_ H_V CM_ T0_ 0_V NH_ H_V _VA _VA
_VA _VA T_V T_V
TE

VAU AUD VAU AUD VAU VAU AUD VAU AUD UDP UDP
UDP UDP AUD AUD
DP15 P15 DP15 P15 DP15 DP15 P15 DP15 P15 15 15
15 15 P15 P15
Type RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IA

Bit(s) Name Description

14 RG_HSOUTPUTRE Resets HS driver DE outputs to 0V ground
SET0_VAUDP15 0: Does not reset
ED

1: Reset
13 RG_HSINPUTRESE Resets HS driver DE inputs to 0V ground
T0_VAUDP15 0: Does not reset
1: Reset
12 RG_HSOUTPUTST HS driver output stability enhancement option
M

BENH_VAUDP15 0: No enhancement
1: Enhance
11 RG_HSINPUTSTBE HS driver input stability enhancement option
NH_VAUDP15 0: No enhancement
1: Enhance
10 RG_HPOUT_SHOR Shorts HP output to VCM (DCC: 0V; ACC: 1.4V)
TVCM_VAUDP15 0: Does not short to VCM

Bit(s) Name Description

1: Short to VCM
9 RG_HPOUTPUTRE Resets HPL/R driver SE output to 0V ground

AL
SET0_VAUDP15 0: Does not reset
1: Reset
8 RG_HPINPUTRESE Resets HP driver input to ground
T0_VAUDP15 0: Does not reset

TI
1: Reset
7 RG_HPOUTPUTST HP driver output stability enhancement option
BENH_VAUDP15 0: No enhancement
1: Enhance

EN
6 RG_HPINPUTSTBE HP driver input stability enhancement option
NH_VAUDP15 0: No enhancement
1: Enhance
5 RG_PRECHARGEB Enables pre-charge buffer stage 2
UF_EN_VAUDP15

4 RG_AUDHSSTART
UP_VAUDP15
0: Disable
1: Enable
ID
Forces Startup mode in HS Amp if required
NF
3 RG_AUDHPSTART Forces Startup mode in HP Amps if required
UP_VAUDP15
2 RG_AUDHSBSCCU Audio handset BSC current
RRENT_VAUDP15
1 RG_AUDHPRBSCC Audio right headphone BSC current
CO

URRENT_VAUDP15
0 RG_AUDHPLBSCC Audio left headphone BSC current
URRENT_VAUDP15
K

AUDDEC_A
0CE0 AUDDEC Control Register 2 0001
NA_CON2
TE

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RG_ RG_
AUD HSO
RG_AUDH RG_AUDH HPT UT_ RG_HPOU
PRFINETR PLFINETRI RIM RG_AUDHPRTRIM_VA RG_AUDHPLTRIM_VA SHO TSTB_RSE
Name IM_VAUD M_VAUDP _EN UDP15 UDP15 RTV L_VAUDP1
IA

P15 15 _VA CM_ 5

UDP VAU
15 DP15
Type RW RW RW RW RW RW RW
Reset
ED

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

Bit(s) Name Description

15:14 RG_AUDHPRFINE Fine trims offset voltage of HPR
TRIM_VAUDP15
M

01: -0.5mV
10: +0.5mV
13:12 RG_AUDHPLFINET Fine trims offset voltage of HPL
RIM_VAUDP15 01: -0.5mV
10: +0.5mV
11 RG_AUDHPTRIM_ Enable control of trimming circuit of HP
EN_VAUDP15 0: Disable trimming circuit
1: Enable trimming circuit

Bit(s) Name Description

10:7 RG_AUDHPRTRIM Trims offset voltage of HPR
_VAUDP15 0000: 0V

AL
0001: -0.5mV
0010: -1.5mV
0011: -2.5mV
0100: -3.5mV
0101: -4.5mV

TI
0110: -5.5mV
0111: -6.5mV
1001: 0.5mV
1010: 1.5mV

EN
1011: 2.5mV
1100: 3.5mV
1101: 4.5mV
1110: 5.5mV
1111: 6.5mV
6:3 RG_AUDHPLTRIM Trims offset voltage of HPL
_VAUDP15 0000: 0V
0001: -0.5mV
0010: -1.5mV
0011: -2.5mV
ID
NF
0100: -3.5mV
0101: -4.5mV
0110: -5.5mV
0111: -6.5mV
1001: 0.5mV
CO

1010: 1.5mV
1011: 2.5mV
1100: 3.5mV
1101: 4.5mV
1110: 5.5mV
1111: 6.5mV
2 RG_HSOUT_SHOR Shorts HS output to VCM (DCC: 0V; ACC: 1.4V)
K

TVCM_VAUDP15 0: Does not short to VCM

1: Short to VCM
TE

1:0 RG_HPOUTSTB_R Selects OUTSTB resistance

SEL_VAUDP15 00: 250
01: 470
10: 1.5k
IA

AUDDEC_A
0CE2 AUDDEC Control Register 3 0000
NA_CON3
ED

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RG_ RG_
AUD AUD
RG_AUDH RG_AUDH
HPS RG_AUDT TRI
PSPKDET_ PSPKDET_
PKD RIMBUF_ RG_AUDTRIMBUF_INP MBU
Name OUTPUTM INPUTMU
M

ET_ GAINSEL_ UTMUXSEL_VAUDP15 F_E

UXSEL_VA XSEL_VAU
EN_ VAUDP15 N_V
UDP15 DP15
VAU AUD
DP15 P15
Type RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0

Bit(s) Name Description

11:10 RG_AUDHPSPKDE Selects audio headphone speaker detection output mux
T_OUTPUTMUXSE 00: Open

AL
L_VAUDP15 01: HPL
10: HPR
11: Unused
9:8 RG_AUDHPSPKDE Enables audio headphone speaker detection input mux
T_INPUTMUXSEL_ 00: Open

TI
VAUDP15 01: DACLP
10: DACLN
11: DACRP

EN
7 RG_AUDHPSPKDE Enables audio headphone speaker detection
T_EN_VAUDP15
6:5 RG_AUDTRIMBUF Selects audio offset trimming buffer gain
_GAINSEL_VAUDP 00: 0dB
15 01: 6dB

4:1 RG_AUDTRIMBUF
_INPUTMUXSEL_
VAUDP15
10: 12dB
11: 18dB
ID
Selects audio offset trimming buffer mux
0000: Open
NF
0001: HPL
0010: HPR
0011: HSP
0100: HSN
0101: IV_P
0110: IV_N
CO

0111: AVSS32
1000: AVSS32
1001: AVSS32
1010~1111: Unused
0 RG_AUDTRIMBUF Enables audio offset trimming buffer
_EN_VAUDP15
K
TE

AUDDEC_A
0CE4 AUDDEC Control Register 4 0000
NA_CON4
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RG_ABIDEC_RESERVED_VAUDP15 RG_ABIDEC_RESERVED_VA28
IA

Type RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit(s) Name Description

15:8 RG_ABIDEC_RESE Reserved one byte in VAUDP15 domain

RVED_VAUDP15
7:0 RG_ABIDEC_RESE Reserved one byte in VA28 domain
RVED_VA28
M

AUDDEC_A
0CE6 AUDDEC Control Register 5 5520
NA_CON5
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RG_AUDBIASADJ_1_VAUDP15 RG_AUDBIASADJ_0_VAUDP15
Type RW RW

Reset 0 1 0 1 0 1 0 1 0 0 1 0

Bit(s) Name Description

AL
15:10 RG_AUDBIASADJ_ Audio bias adjustment 1
1_VAUDP15 [5:4] ZCD bias current setting
00: 3uA
01: 4uA
10: 5uA

TI
11: 6uA
[3:2] HS ibias setting
00: 4uA
01: 5uA

EN
10: 6uA
11: 7uA
[1:0]: HPL/R ibias setting
00: 4uA
01: 5uA

9:4 RG_AUDBIASADJ_
0_VAUDP15
10: 6uA
11: 7uA
Audio bias adjustment 0 ID
[2:0] Headphone left/right DR bias current setting
NF
[5:3] Handset DR bias current setting.
DR bias settings:
000: 4uA
001: 5uA
010: 6uA
011: 7uA
CO

100: 8uA
101: 9A
110: 10uA
111: 11uA,
K

AUDDEC_A
0CE8 AUDDEC Control Register 6 0001
NA_CON6
TE

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RG_ RG_
RG_ RG_ RG_
LCL RG_ HCL RG_ RG_ RG_ RG_ RG_
RG_ RG_ RG_ SEL SEL AUD
DO_ LCL DO_ HCL VA3 LCL RG_ RG_ RST RST
HCL LCL SEL _EN _DE IBIA
REM DO_ REM DO_ 3RE DO_ LCL HCL B_E B_D
IA

Name DO_ DO_

OTE PDD OTE PDD FGE ENC DO_ DO_
_DE COD COD
NCO ECO
SPW
VOS VOS LAY ER_ ER_ RDN
_SE IS_E _SE IS_E N_E _EN EN_ EN_ DER DER
EL_ EL_ _VC 96K 96K _VA
NSE N_V NSE N_V N_V _VA VA18 VA18 _VA _VA
VA18 VA18 ORE _VA _VA UDP
_VA A18 _VA A18 A18 28 28 28
28 28 15
18 18
ED

Type RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

Bit(s) Name Description

15 RG_HCLDO_VOSE
L_VA18
14 RG_LCLDO_VOSEL
_VA18
13 RG_LCLDO_REMO Selects LCLDO remote sense function
TE_SENSE_VA18
12 RG_LCLDO_PDDIS Enables LCLDO power-down discharge

Bit(s) Name Description

_EN_VA18
11 RG_HCLDO_REMO Selects HCLDO remote sense function

AL
TE_SENSE_VA18 0: Local sense
1: Remote sense
10 RG_HCLDO_PDDI Enables HCLDO power-down discharge
S_EN_VA18

TI
9 RG_VA33REFGEN_
EN_VA18
8 RG_LCLDO_ENC_ Enables LCLDO_ENC
EN_VA28

EN
7 RG_LCLDO_EN_V Enables LCLDO
A18
6 RG_HCLDO_EN_V Enables HCLDO
A18
5

4
RG_SEL_DELAY_V
CORE

RG_SEL_ENCODE
0: 5ns
1: 10ns
Selects audio ADC clock
ID
Selects AFIFO read clock delay
NF
R_96K_VA28 0: 6.5MHz
1: 13MHz
3 RG_SEL_DECODE Selects audio DAC clock
R_96K_VA28 0: 6.5MHz
1: 13MHz
CO

2 RG_RSTB_ENCOD Resets audio encoder

ER_VA28 0: Reset
1: Normal
1 RG_RSTB_DECOD Resets audio decoder
ER_VA28 0: Reset
1: Normal
K

0 RG_AUDIBIASPWR Controls power-down for IbiasDistrib circuit.

DN_VAUDP15 0: Enable
TE

1: Disable

AUDDEC_A
IA

0CEA AUDDEC Control Register 7 0000

NA_CON7
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RG_
RG_
LCL
ED

RG_ LCL
RG_ DO_
VA2 DO_
NVR ENC
8RE ENC
EG_ RG_AUDPMU_RESERV RG_AUDPMU_RESERV RG_AUDPMU_RESERV _RE
Name EN_ ED_VAUDP15 ED_VA18 ED_VA28
FGE
MOT
_PD
N_E DIS_
VAU E_S
N_V EN_
DP15 ENS
M

A28 VA2
E_V
8
A28
Type RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit(s) Name Description

15 RG_NVREG_EN_V Enables NVREG

Bit(s) Name Description

AUDP15
14:11 RG_AUDPMU_RES Reserved half byte for VAUDP15 domain

AL
ERVED_VAUDP15
10:7 RG_AUDPMU_RES Reserved half byte for VA18 domain
ERVED_VA18
6:3 RG_AUDPMU_RES Reserved half byte for VA28 domain

TI
ERVED_VA28
2 RG_VA28REFGEN_ Enables VA28 Ref. gen.
EN_VA28
1 RG_LCLDO_ENC_ Selects LCLDO_ENC remote sense function

EN
REMOTE_SENSE_
VA28
0 RG_LCLDO_ENC_ Enables LCLDO_ENC power-down discharge
PDDIS_EN_VA28

0CEC
AUDDEC_A
NA_CON8
AUDDEC Control Register 8
ID 0000
NF
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RG_
RG_
NVR
AUD
EG_
GLB
PUL
CO

Name _PW
L0V
RDN
_VA
_VA
UDP
28
15
Type RW RW
Reset 0 0
K

Bit(s) Name Description

1 RG_AUDGLB_PWR Controls power-down for audio global bias circuit
TE

DN_VA28 0: Enable
1: Disable; default on
0 RG_NVREG_PULL 0: DCC mode. Switch is opened; NV output is -0.95V
0V_VAUDP15 1: ACC mode. Switch is closed; NV reg output is pulled to GND.
IA

AUDENC_A
0CEE AUDENC Control Register 0 0000
ED

NA_CON0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RG_
RG_
AUD RG_
RG_ AUD RG_
PRE AUD
RG_AUDA AUD RG_AUDP RG_AUDP PRE AUD
M

AMP PRE
Name DCLINPUT ADC REAMPLIN REAMPLV AMP PRE
LDC AMP
SEL LPW PUTSEL SCALE LPG AMP
RPE LDC
RUP ATE LON
CHA CEN
ST
RGE
Type RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0

Bit(s) Name Description

10:9 RG_AUDADCLINP Selects audio L ADC input
UTSEL 00: Idle

AL
01: AIN0
10: Left preamplifier
11: Idle
8 RG_AUDADCLPWR Powers up audio L ADC
UP 0: Power down

TI
1: Power on
7:6 RG_AUDPREAMPL Selects audio L preamplifier input
INPUTSEL 00: None

EN
01: AIN0
10: AIN1
11: AIN2
5:4 RG_AUDPREAMPL Audio L preamplifier PGA DC output voltage scale
VSCALE
3

2
RG_AUDPREAMPL
PGATEST

RG_AUDPREAMPL
0: Disable
1: Enable ID
Enables audio L preamplifier PGA test

Audio L preamplifier PGA DC couple input precharge

NF
DCRPECHARGE 0: Disable
1: Enable
1 RG_AUDPREAMPL Audio L DC couple input
DCCEN 0: AC couple input
1: DC couple input
CO

0 RG_AUDPREAMPL Enables audio L preamplifier

ON 0: Disable
1: Enable
K

AUDENC_A
0CF0 AUDENC Control Register 1 0000
NA_CON1
TE

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RG_
RG_
AUD RG_
RG_ AUD RG_
PRE AUD
RG_AUDA AUD RG_AUDP RG_AUDP PRE AUD
AMP PRE
Name DCRINPUT ADC REAMPRI REAMPRV AMP PRE
IA

RDC AMP
SEL RPW NPUTSEL SCALE RPG AMP
RPE RDC
RUP ATE RON
CHA CEN
ST
RGE
Type RW RW RW RW RW RW RW RW
ED

Reset 0 0 0 0 0 0 0 0 0 0 0

Bit(s) Name Description

10:9 RG_AUDADCRINP Selects audio R ADC input
M

UTSEL 00: Idle

01: AIN0
10: Right preamplifier
11: Idle
8 RG_AUDADCRPWR Powers up audio R ADC
UP 0: Power down
1: Power on

Bit(s) Name Description

7:6 RG_AUDPREAMPR Selects audio R preamplifier input
INPUTSEL 00: None

AL
01: AIN0
10: AIN1
11: AIN2
5:4 RG_AUDPREAMPR Audio R preamplifier PGA DC output voltage scale
VSCALE

TI
3 RG_AUDPREAMPR Enables audio R preamplifier PGA test
PGATEST 0: Disable
1: Enable

EN
2 RG_AUDPREAMPR Audio R preamplifier PGA DC couple input precharge
DCRPECHARGE 0: Disable
1: Enable
1 RG_AUDPREAMPR Audio R DC couple input
DCCEN 0: AC couple input

0 RG_AUDPREAMPR
ON
1: DC couple input
Enables audio R preamplifier
0: Disable
1: Enable
ID
NF

AUDENC_A
0CF2 AUDENC Control Register 2 0000
CO

NA_CON2
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RG_ RG_
RG_ RG_ RG_
AUD AUD RG_
RG_AUDA RG_AUDA AUD AUD AUD
RG_AUDA RG_AUDA RG_AUDP ADC ADC AUD
DC2NDSTA DC1STSTA ADC PRE GLB
Name DCFLASHI DCREFBUF GEIDDTES GEIDDTES REAMPID
FLA
2ND 1STS
AMP MAD
ULH
DDTEST IDDTEST DTEST STA TAG ALF
K

T T SHL LPE LPW

GEL ELP BIAS
PEN N EN
PEN EN
Type RW RW RW RW RW RW RW RW RW RW RW
TE

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit(s) Name Description

15:14 RG_AUDADCFLAS Selects audio ADC flash Idd current test
IA

HIDDTEST 00: 100%

01: 80%
10: 120%
11: 140%
ED

13:12 RG_AUDADCREFB Selects audio ADC reference buffer Idd current test
UFIDDTEST 00: 100%
01: 80%
10: 120%
11: 140%
M

11:10 RG_AUDADC2NDS Adjusts audio ADC 2nd & 3rd stage Idd
TAGEIDDTEST 00: 100%
01: 80%
10: 120%
11: 140%
9:8 RG_AUDADC1STST Adjusts audio ADC 1st stage Idd
AGEIDDTEST 00: 100%
01: 80%

Bit(s) Name Description

10: 120%
11: 140%

AL
7:6 RG_AUDPREAMPI Adjusts audio preamplifier Idd
DDTEST 00: 100%
01: 75%
10: 125%
11: 150%

TI
5 RG_AUDADCFLAS Enables audio ADC flash low power
HLPEN 0: Normal
1: Enable

EN
4 RG_AUDADC2NDS Enables audio ADC 2nd & 3rd low power
TAGELPEN 0: Normal
1: Enable
3 RG_AUDADC1STST Enables audio ADC 1st stage low power
AGELPEN 0: Normal

2 RG_AUDPREAMPL
PEN
1: Enable

0: Disable
1: Enable
ID
Audio preamplifier PGA low power mode
NF
1 RG_AUDGLBMADL Audio preamplifier PGA low power mode
PWEN 0: Disable
1: Enable
0 RG_AUDULHALFB Enables audio uplink halfbias
CO

IAS 0: Normal
1: Enable

AUDENC_A
0CF4 AUDENC Control Register 3 0000
K

NA_CON3
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RG_
TE

RG_ RG_ RG_

RG_ DCC RG_
DCC AUD AUD
AUD VCM RG_AUDA RG_AUDA AUD
VCM PRE ADC
Name SPA BUF DCCLKGE DCCLKSO ADC
BUF AMP DAC
REP LPM NMODE URCE CLK
LPS AAF 0P25
GA ODS SEL
WEN EN FS
EL
IA

Type RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0
ED

Bit(s) Name Description

11 RG_AUDSPAREPG Spare control bits for PGA
A
10 RG_DCCVCMBUFL Enables audio preamplifier PGA DCC VCM buffer SW
PSWEN
M

9 RG_DCCVCMBUFL Audio preamplifier PGA DCC VCM buffer LP MODSEL

PMODSEL
8 RG_AUDPREAMPA Audio preamplifier PGA with AAF input in DC couple mode
AFEN 0: Disable
1: Enable
5:4 RG_AUDADCCLKG Audio ADC clock gen. mode
ENMODE 00: Divided by 2 (normal)

Bit(s) Name Description

01: Divided by 4
10: Divided by 8

AL
11: Not divided
3:2 RG_AUDADCCLKS Audio ADC clock source
OURCE 00: 26MHz from CLKSQ
01: 12.58MHz from 32kHz PLL
10: 12MHz Ring oscillator

TI
11: None
1 RG_AUDADCCLKS Selects audio ADC clock
EL 0: 13MHz clock in; 6.5MHz data out
1: 26MHz clock in; 13MHz data out

EN
0 RG_AUDADCDAC0 Enables audio ADC FBDAC 0.25FS
P25FS 0: 13MHz clock in; 6.5MHz data out
1: 3.25MHz clock in; 1.625MHz data out

0CF6
AUDENC_A
NA_CON4
AUDENC Control Register 4
ID 0800
NF
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RG_ RG_
RG_ RG_
RG_ RG_ RG_ RG_ AUD AUD
RG_ RG_ AUD RG_ RG_ AUD
AUD AUD AUD AUD ADC ADC
AUD AUD RG_AUDA ADC AUD AUD ADC
ADC ADC ADC ADC 3RD 2ND
Name ADC ADC DCDACIDD DAC ADC ADC 1STS
CO

DAC FFB NOP FSR STA STA

NOD DAC TEST FBC BYP WID TAG
TES YPA ATE ESE GER GER
EM NRZ URR ASS ECM ESD
T SS ST T ESE ESE
ENT ENB
T T
Type RW RW RW RW RW RW RW RW RW RW RW RW RW
Reset 0 0 1 0 0 0 0 0 0 0 0 0 0 0
K

Bit(s) Name Description

13 RG_AUDADCDACT Audio ADC DAC test
TE

EST 0: Disable
1: Enable data in RG_AUDADCTESTDATA[15:0] to be passed to DAC
12 RG_AUDADCNODE Audio ADC DEM test
M
11 RG_AUDADCDACN Audio ADC DAC in non return to zero mode
IA

RZ 0: RZ mode (2I)
1: NRZ mod (I)
10:9 RG_AUDADCDACI Selects audio ADC-DAC Idd current test
DDTEST
ED

00: Normal
11: -20% DAC f/b current
8 RG_AUDADCDACF Audio ADC feedback coefficient
BCURRENT
7 RG_AUDADCFFBY Bypasses audio ADC feed forward
M

PASS 0: No bypass. Allow feedforward coefficient to pass signal to ADC flash.

1: Bypass. Does not allow ADC i/p signal to feedforward flash.
6 RG_AUDADCBYPA Enables audio ADC input resistor bypass
SS 0: Disable
1: Enable
5 RG_AUDADCNOPA Audio ADC no preamp test
TEST 0: Normal ADC gain

Bit(s) Name Description

1: 6dB ADC gain
4 RG_AUDADCWIDE Enables audio ADC wide common mode

AL
CM 0: Normal
1: Enable
3 RG_AUDADCFSRE Selects audio encoder FS reset block model
SET

TI
2 RG_AUDADC3RDS Resets audio ADC 3rd stage
TAGERESET 0: Normal
1: Reset
1 RG_AUDADC2NDS Resets audio ADC 2nd stage

EN
TAGERESET 0: Normal
1: Reset
0 RG_AUDADC1STST Audio ADC 1st stage source degenerate enableb
AGESDENB 0: Enable
1: Disable

ID
NF
AUDENC_A
0CF8 AUDENC Control Register 5 0000
NA_CON5
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RG_AUDADCTESTDATA
Type RW
CO

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit(s) Name Description

15:0 RG_AUDADCTEST Audio ADC test data bits for both phases of DRTZ DAC
DATA Can enable any current source you choose.
K
TE

AUDENC_A
0CFA AUDENC Control Register 6 0555
NA_CON6
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RG_ RG_
IA

AUD AUD
RCT RCT
Name RG_AUDRCTUNER RG_AUDRCTUNEL
UNE UNE
RSE LSE
L L
ED

Type RW RW RW RW
Reset 0 1 0 1 0 1 0 1 0 1 0 1

Bit(s) Name Description

13 RG_AUDRCTUNER Selects audio R ADC RC tuning

SEL 0: Use auto cal tune bits
1: Use RG_AUDRCTUNEL[4:0]
10:6 RG_AUDRCTUNER Audio R ADC RC tuned value
See RG_AUDRCTUNELSE.
5 RG_AUDRCTUNEL Selects audio L ADC RC tuning
SEL 0: Use auto cal tune bits
1: Use RG_AUDRCTUNEL[4:0]

Bit(s) Name Description

4:0 RG_AUDRCTUNEL Audio L ADC RC tuned value
See RG_AUDRCTUNELSE.

AL
AUDENC_A
0CFC AUDENC Control Register 7 0000

TI
NA_CON7
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RG_AUDENCSPAREV RG_AUDENCSPAREV
Name RG_AUDSPAREVA18 RG_AUDSPAREVA28
A18 A28

EN
Type RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit(s) Name Description

15:12

11:8
RG_AUDENCSPAR
EVA18
RG_AUDENCSPAR
EVA28
ID
Spare control bits for AVDD12 voltage domain

Spare control bits for AVDD25 voltage domain

NF
7:4 RG_AUDSPAREVA1 Spare control bits for AVDD12 voltage domain
8
3:0 RG_AUDSPAREVA Spare control bits for AVDD25 voltage domain
28
CO

AUDENC_A
0CFE AUDENC Control Register 8 0004
NA_CON8
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
K

RG_ RG_
RG_
RG_AUDDI RG_AUDDI DMI AUD
RG_DMICMONS DMI RG_AUDDI
Name RG_AUDSPAREVMIC
EL CMO
GMICNDU GMICPDU CHP
GMICBIAS
DIG
TY TY CLK MIC
TE

NEN
EN EN
Type RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
IA

Bit(s) Name Description

15:12 RG_AUDSPAREVM Spare control bits for AVDD25MIC voltage domain
IC
11:9 RG_DMICMONSEL Enables digital microphone monitor path
ED

0: Disable
1: Enable
8 RG_DMICMONEN Enables digital microphone monitor path
0: Disable
1: Enable (26MHz)
M

7:6 RG_AUDDIGMICN Controls digital microphone negative duty

DUTY
5:4 RG_AUDDIGMICP Controls digital microphone positive duty
DUTY
3 RG_DMICHPCLKE Enables digital microphone monitor path selection
N 0: DCC CLK
1: CLKSQ

Bit(s) Name Description

2:1 RG_AUDDIGMICBI Controls digital microphone slew rate
AS 11>10>01>00

AL
0 RG_AUDDIGMICE Enables digital microphone
N 0: Disable
1: Enable

TI
AUDENC_A
0D00 AUDENC Control Register 9 0000
NA_CON9

EN
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RG_ RG_ RG_ RG_ RG_ RG_
RG_ RG_ RG_
RG_ AUD AUD AUD AUD AUD AUD
AUD AUD AUD
BAN MIC MIC MIC MIC MIC MIC
MIC RG_AUDMICBIA PWD PWD
Name DGA
BIAS SVREF
BIAS BIAS BIAS
BMI
BIAS BIAS BIAS
BMI

Type
Reset
PGE
N

RW
0
LOW
PEN
RW
0 0
RW
0 0
1BYP
ASS
EN
RW
0
ID 1DCS
WNE
N
RW
0
1DCS
WPE
N
RW
0
CBIA
S1
RW
0
0BY
PAS
SEN
RW
0
0DC
SWN
EN
RW
0
0DC
SWP
EN
RW
0
CBIA
S0
RW
0
NF
Bit(s) Name Description
12 RG_BANDGAPGEN Remote sense to bandgap ground
0: Disable
CO

1: Enable
11 RG_AUDMICBIASL Enables MIC Bias 0 low power
OWPEN 0: High power mode
1: Low power mode
10:8 RG_AUDMICBIASV Selects MIC Bias 0 output voltage selection
REF 000: 1.7V
K

001: 1.8V
010: 1.9V
011: 2.0V
TE

100: 2.1V
101: 2.3V
110: 2.4V
111: 2.5V
7 RG_AUDMICBIAS1 Enables MIC Bias 1 bypass 2P8V
IA

BYPASSEN 0: Disable
1: Enable
6 RG_AUDMICBIAS1 MIC Bias 1 DC couple switch N
DCSWNEN
ED

0: External
1: Internal
5 RG_AUDMICBIAS1 MIC Bias 1 DC couple switch P
DCSWPEN 0: External
1: Internal
M

4 RG_AUDPWDBMIC Powers down MIC Bias 1

BIAS1 0: Power down
1: Power on
3 RG_AUDMICBIAS0 Enables MIC Bias 0 bypass 2P8V
BYPASSEN 0: Disable
1: Enable
2 RG_AUDMICBIAS0 MIC Bias 0 DC couple switch N

Bit(s) Name Description

DCSWNEN 0: External
1: Internal

AL
1 RG_AUDMICBIAS0 MIC Bias 0 DC couple switch P
DCSWPEN 0: External
1: Internal
0 RG_AUDPWDBMIC Powers down MIC Bias 0
BIAS0

TI
0: Power down
1: Power on

EN
AUDENC_A
0D02 AUDENC Control Register 10 0000
NA_CON10
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RG_AUDPREA RG_AUDPREA
Name
Type
Reset ID 0
MPRGAIN
RW
0 0 0
MPLGAIN
RW
0 0
NF
Bit(s) Name Description
6:4 RG_AUDPREAMPR Adjusts audio R preamplifier gain
GAIN 000: 0dB
001: 6dB
CO

010: 12dB
011: 18dB
100: 24dB
2:0 RG_AUDPREAMPL Adjusts audio L preamplifier gain
GAIN 000: 0dB
001: 6dB
K

010: 12dB
011: 18dB
100: 24dB
TE

AUDNCP_CL
0D04 AUDNCP_CLKDIV Control Register 0 0000
KDIV_CON0
IA

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RG_
DIV
Name CKS
ED

_CH
G
Type RW
Reset 0
M

Bit(s) Name Description

0 RG_DIVCKS_CHG

AUDNCP_CL
0D06 AUDNCP_CLKDIV Control Register 1 0000
KDIV_CON1

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RG_
DIV
Name
CKS

AL
_ON
Type RW
Reset 0

Bit(s) Name Description

TI
0 RG_DIVCKS_ON

EN
AUDNCP_CL
0D08 AUDNCP_CLKDIV Control Register 2 0020
KDIV_CON2
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
Type
Reset ID 0 0 0
RG_DIVCKS_PRG

1
RW
0 0 0 0 0
NF
Bit(s) Name Description
8:0 RG_DIVCKS_PRG
CO

AUDNCP_CL
0D0A AUDNCP_CLKDIV Control Register 3 0001
KDIV_CON3
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RG_
DIV
K

CKS
Name _PW
D_N
CP
TE

Type RW
Reset 1

Bit(s) Name Description

0 RG_DIVCKS_PWD
_NCP
ED

AUDNCP_CL
0D0C AUDNCP_CLKDIV Control Register 4 0000
KDIV_CON4
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M

RG_DIVCK
S_PWD_N
Name
CP_ST_SE
L
Type RW
Reset 0 0

Bit(s) Name Description

1:0 RG_DIVCKS_PWD
_NCP_ST_SEL

AL
AUXADC_A
0E00 AUXADC ADC Register 0 0000

TI
DC0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AUX
ADC

EN
_AD
Name C_R AUXADC_ADC_OUT_CH0
DY_
CH0
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit(s)
15
Name
AUXADC_ADC_RD
Description ID
AUXADC channel 0 output data ready
NF
Y_CH0 0: AUXADC data proceeding
1: AUXADC data ready
14:0 AUXADC_ADC_OU AUXADC channel 0 output data
T_CH0
CO

AUXADC_A
0E02 AUXADC ADC Register 1 0000
DC1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
K

AUX
ADC
_AD
Name C_R AUXADC_ADC_OUT_CH1
TE

DY_
CH1
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IA

Bit(s) Name Description

15 AUXADC_ADC_RD AUXADC channel 1 output data ready
Y_CH1 0: AUXADC data proceeding
ED

1: AUXADC data ready

14:0 AUXADC_ADC_OU AUXADC channel 1 output data
T_CH1
M

AUXADC_A
0E04 AUXADC ADC Register 2 0000
DC2
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AUX
Name ADC AUXADC_ADC_OUT_CH2
_AD
C_R

DY_
CH2
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0

AL
Bit(s) Name Description
15 AUXADC_ADC_RD AUXADC channel 2 output data ready
Y_CH2 0: AUXADC data proceeding

TI
1: AUXADC data ready
11:0 AUXADC_ADC_OU AUXADC channel 2 output data
T_CH2

EN
AUXADC_A
0E06 AUXADC ADC Register 3 0000
DC3
Bit
AUX
ADC
_AD
Name C_R
15 14 13 12 11 10 9
ID 8 7 6

AUXADC_ADC_OUT_CH3
5 4 3 2 1 0
NF
DY_
CH3
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0
CO

Bit(s) Name Description

15 AUXADC_ADC_RD AUXADC channel 3 output data ready
Y_CH3 0: AUXADC data proceeding
1: AUXADC data ready
11:0 AUXADC_ADC_OU AUXADC channel 3 output data
K

T_CH3
TE

AUXADC_A
0E08 AUXADC ADC Register 4 0000
DC4
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IA

AUX
ADC
Name _AD AUXADC_ADC_OUT_CH4
C_R
DY_
ED

CH4
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit(s) Name Description

15 AUXADC_ADC_RD AUXADC channel 4 output data ready

Y_CH4 0: AUXADC data proceeding
1: AUXADC data ready
11:0 AUXADC_ADC_OU AUXADC channel 4 output data
T_CH4

AUXADC_A
0E0A AUXADC ADC Register 5 0000

AL
DC5
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AUX
ADC
Name _AD AUXADC_ADC_OUT_CH5
C_R

TI
DY_
CH5
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0

EN
Bit(s) Name Description
15 AUXADC_ADC_RD AUXADC channel 5 output data ready
Y_CH5 0: AUXADC data proceeding

11:0 AUXADC_ADC_OU
T_CH5
1: AUXADC data ready
AUXADC channel 5 output data
ID
NF
AUXADC_A
0E0C AUXADC ADC Register 6 0000
DC6
CO

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AUX
ADC
Name _AD AUXADC_ADC_OUT_CH6
C_R
DY_
CH6
Type RO RO
K

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0
TE

Bit(s) Name Description

15 AUXADC_ADC_RD AUXADC channel 6 output data ready
Y_CH6 0: AUXADC data proceeding
1: AUXADC data ready
IA

11:0 AUXADC_ADC_OU AUXADC channel 6 output data

T_CH6
ED

AUXADC_A
0E0E AUXADC ADC Register 7 0000
DC7
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AUX
M

ADC
Name _AD AUXADC_ADC_OUT_CH7
C_R
DY_
CH7
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit(s) Name Description

15 AUXADC_ADC_RD AUXADC channel 7 output data ready
Y_CH7 0: AUXADC data proceeding

AL
1: AUXADC data ready
14:0 AUXADC_ADC_OU AUXADC channel 7 output data
T_CH7

TI
AUXADC_A
0E10 AUXADC ADC Register 8 0000
DC8

EN
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AUX
ADC
_AD
Name C_R AUXADC_ADC_OUT_CH8

ID
DY_
CH8
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0
NF
Bit(s) Name Description
15 AUXADC_ADC_RD AUXADC channel 8 output data ready
Y_CH8 0: AUXADC data proceeding
1: AUXADC data ready
CO

11:0 AUXADC_ADC_OU AUXADC channel 8 output data

T_CH8

AUXADC_A
K

0E12 AUXADC ADC Register 9 0000

DC9
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TE

AUX
ADC
_AD
Name C_R AUXADC_ADC_OUT_CH9
DY_
CH9
IA

Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit(s) Name Description

15 AUXADC_ADC_RD AUXADC channel 9 output data ready

Y_CH9 0: AUXADC data proceeding
1: AUXADC data ready
11:0 AUXADC_ADC_OU AUXADC channel 9 output data
M

T_CH9

AUXADC_A
0E14 AUXADC ADC Register 10 0000
DC10
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

AUX
ADC
_AD
Name C_R AUXADC_ADC_OUT_CH10

AL
DY_
CH1
0
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0

TI
Bit(s) Name Description
15 AUXADC_ADC_RD AUXADC channel 10 output data ready
Y_CH10 0: AUXADC data proceeding

EN
1: AUXADC data ready
11:0 AUXADC_ADC_OU AUXADC channel 10 output data
T_CH10

0E16
AUXADC_A
DC11
AUXADC ADC Register 11
ID 0000
NF
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AUX
ADC
_AD
Name C_R AUXADC_ADC_OUT_CH11
CO

DY_
CH11
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit(s) Name Description

15 AUXADC_ADC_RD AUXADC channel 11 output data ready

Y_CH11 0: AUXADC data proceeding
1: AUXADC data ready
TE

11:0 AUXADC_ADC_OU AUXADC channel 11 output data

T_CH11
IA

AUXADC_A
0E18 AUXADC ADC Register 12 0000
DC12
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ED

AUX
ADC
_AD
Name C_R AUXADC_ADC_OUT_CH12_15
DY_
CH1
M

2_15
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit(s) Name Description

15 AUXADC_ADC_RD AUXADC channel 12_15 output data ready
Y_CH12_15 0: AUXADC data proceeding

Bit(s) Name Description

1: AUXADC data ready
11:0 AUXADC_ADC_OU AUXADC channel 12_15 output data

AL
T_CH12_15

TI
AUXADC_A
0E1A AUXADC ADC Register 13 0000
DC13
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AUX

EN
ADC
_AD
C_R
Name DY_ AUXADC_ADC_OUT_THR_HW
THR
_H

Type
Reset
W
RO
0 0 0 0 ID 0 0 0
RO
0 0 0 0 0 0
NF
Bit(s) Name Description
15 AUXADC_ADC_RD AUXADC channel 4 output data ready
Y_THR_HW 0: AUXADC data proceeding
1: AUXADC data ready
CO

11:0 AUXADC_ADC_OU AUXADC channel 4 output data

T_THR_HW

AUXADC_A
0E1C AUXADC ADC Register 14 0000
K

DC14
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AUX
TE

ADC
_AD
Name C_R AUXADC_ADC_OUT_LBAT
DY_
LBA
T
IA

Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0
ED

Bit(s) Name Description

15 AUXADC_ADC_RD AUXADC low battery output data ready
Y_LBAT 0: AUXADC data proceeding
1: AUXADC data ready
11:0 AUXADC_ADC_OU AUXADC low battery output data
M

T_LBAT

AUXADC_A
0E1E AUXADC ADC Register 15 0000
DC15
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

AUX
ADC
_AD
Name C_R AUXADC_ADC_OUT_LBAT2

AL
DY_
LBA
T2
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0

TI
Bit(s) Name Description
15 AUXADC_ADC_RD AUXADC low battery output data ready
Y_LBAT2 0: AUXADC data proceeding

EN
1: AUXADC data ready
11:0 AUXADC_ADC_OU AUXADC low battery output data
T_LBAT2

0E20
AUXADC_A
DC16
AUXADC ADC Register 16
ID 0000
NF
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AUX
ADC
_AD
C_R
CO

Name DY_ AUXADC_ADC_OUT_CH7_BY_GPS

CH7
_BY
_GP
S
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
K

Bit(s) Name Description

15 AUXADC_ADC_RD AUXADC channel 7 output data ready
TE

Y_CH7_BY_GPS 0: AUXADC data proceeding

1: AUXADC data ready
14:0 AUXADC_ADC_OU AUXADC channel 7 output data
T_CH7_BY_GPS
IA

AUXADC_A
ED

0E22 AUXADC ADC Register 17 0000

DC17
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AUX
ADC
_AD
M

Name C_R AUXADC_ADC_OUT_CH7_BY_MD

DY_
CH7
_BY
_MD
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit(s) Name Description

15 AUXADC_ADC_RD AUXADC channel 7 output data ready
Y_CH7_BY_MD 0: AUXADC data proceeding

AL
1: AUXADC data ready
14:0 AUXADC_ADC_OU AUXADC channel 7 output data
T_CH7_BY_MD

TI
AUXADC_A
0E24 AUXADC ADC Register 18 0000
DC18

EN
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AUX
ADC
_AD
C_R
Name DY_ AUXADC_ADC_OUT_CH7_BY_AP

Type
CH7
_BY
_AP
RO
ID RO
NF
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit(s) Name Description

15 AUXADC_ADC_RD AUXADC channel 7 output data ready
CO

Y_CH7_BY_AP 0: AUXADC data proceeding

1: AUXADC data ready
14:0 AUXADC_ADC_OU AUXADC channel 7 output data
T_CH7_BY_AP
K

AUXADC_A
0E26 AUXADC ADC Register 19 0000
DC19
TE

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AUX
ADC
_AD
C_R
IA

Name DY_ AUXADC_ADC_OUT_CH4_BY_MD

CH4
_BY
_MD
Type RO RO
ED

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit(s) Name Description

15 AUXADC_ADC_RD AUXADC channel 4 output data ready
M

Y_CH4_BY_MD 0: AUXADC data proceeding

1: AUXADC data ready
11:0 AUXADC_ADC_OU AUXADC channel 4 output data
T_CH4_BY_MD

AUXADC_A
0E28 AUXADC ADC Register 20 0000
DC20

AL
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AUX
ADC
_AD
C_R
Name DY_ AUXADC_ADC_OUT_WAKEUP_PCHR

TI
WA
KEU
P_P
CHR
Type RO RO

EN
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit(s) Name Description

15 AUXADC_ADC_RD AUXADC wakeup output data ready

14:0
Y_WAKEUP_PCHR

AUXADC_ADC_OU
T_WAKEUP_PCHR
0: AUXADC data proceeding
1: AUXADC data ready
AUXADC wakeup output data
ID
NF

AUXADC_A
0E2A AUXADC ADC Register 21 0000
CO

DC21
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AUX
ADC
_AD
C_R
Name DY_ AUXADC_ADC_OUT_WAKEUP_SWCHR
K

WA
KEU
P_S
WC
TE

HR
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IA

Bit(s) Name Description

15 AUXADC_ADC_RD AUXADC wakeup output data ready
Y_WAKEUP_SWCH 0: AUXADC data proceeding
R 1: AUXADC data ready
ED

14:0 AUXADC_ADC_OU AUXADC wakeup output data

T_WAKEUP_SWCH
R
M

AUXADC_A
0E2C AUXADC ADC Register 22 0000
DC22
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AUX
ADC
Name _AD AUXADC_ADC_OUT_CH0_BY_MD
C_R

DY_
CH0
_BY
_MD

AL
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit(s) Name Description

TI
15 AUXADC_ADC_RD AUXADC channel output data ready
Y_CH0_BY_MD 0: AUXADC data proceeding
1: AUXADC data ready
14:0 AUXADC_ADC_OU AUXADC channel output data

EN
T_CH0_BY_MD

AUXADC_A
0E2E

Bit
AUX
15
DC23
14 13 12
AUXADC ADC Register 23

11 10 9 ID 8 7 6 5 4 3 2 1
0000

0
NF
ADC
_AD
C_R
Name DY_ AUXADC_ADC_OUT_CH0_BY_AP
CH0
_BY
CO

_AP
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit(s) Name Description

15 AUXADC_ADC_RD AUXADC channel output data ready
K

Y_CH0_BY_AP 0: AUXADC data proceeding

1: AUXADC data ready
14:0 AUXADC_ADC_OU AUXADC channel output data
TE

T_CH0_BY_AP
IA

AUXADC_A
0E30 AUXADC ADC Register 24 0000
DC24
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AUX
ED

ADC
_AD
Name C_R AUXADC_ADC_OUT_CH1_BY_MD
DY_
CH1
_BY
M

_MD
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit(s) Name Description

15 AUXADC_ADC_RD AUXADC channel output data ready
Y_CH1_BY_MD 0: AUXADC data proceeding

Bit(s) Name Description

1: AUXADC data ready
14:0 AUXADC_ADC_OU AUXADC channel output data

AL
T_CH1_BY_MD

TI
AUXADC_A
0E32 AUXADC ADC Register 25 0000
DC25
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AUX

EN
ADC
_AD
C_R
Name DY_ AUXADC_ADC_OUT_CH1_BY_AP
CH1
_BY

Type
Reset
_AP
RO
0 0 0 0 0 0 0 ID 0
RO
0 0 0 0 0 0 0 0
NF
Bit(s) Name Description
15 AUXADC_ADC_RD AUXADC channel output data ready
Y_CH1_BY_AP 0: AUXADC data proceeding
1: AUXADC data ready
CO

14:0 AUXADC_ADC_OU AUXADC channel output data

T_CH1_BY_AP

AUXADC_A
0E34 AUXADC ADC Register 26 0000
K

DC26
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AUX
TE

ADC
_AD
C_R
Name DY_ AUXADC_ADC_OUT_VISMPS0
VIS
MPS
IA

0
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0
ED

Bit(s) Name Description

15 AUXADC_ADC_RD AUXADC vismps output data ready
Y_VISMPS0 0: AUXADC vismps data proceeding
1: AUXADC vismps data ready
M

11:0 AUXADC_ADC_OU AUXADC vismps output data

T_VISMPS0

AUXADC_A
0E36 AUXADC ADC Register 27 0000
DC27

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AUX
ADC
_AD

AL
Nam
C_R AUXADC_ADC_OUT_FGADC1
e
DY_
FGA
DC1
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TI
Bit(s) Name Description
15 AUXADC_ADC_RD AUXADC output data ready (BATSNS)

EN
Y_FGADC1 0: AUXADC data proceeding
1: AUXADC data ready
14:0 AUXADC_ADC_OU AUXADC output data
T_FGADC1

0E38
AUXADC_A
AUXADC ADC Register 28
ID 0000
NF
DC28
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AUX
ADC
_AD
CO

Name C_R AUXADC_ADC_OUT_FGADC2

DY_
FGA
DC2
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
K

Bit(s) Name Description

15 AUXADC_ADC_RD AUXADC output data ready (ISENSE)
TE

Y_FGADC2 0: AUXADC data proceeding

1: AUXADC data ready
14:0 AUXADC_ADC_OU AUXADC output data
T_FGADC2
IA

AUXADC_A
0E3A AUXADC ADC Register 29 0000
DC29
ED

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AUX
ADC
_AD
Name C_R AUXADC_ADC_OUT_IMP
M

DY_
IMP
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit(s) Name Description

15 AUXADC_ADC_RD AUXADC output data ready

Bit(s) Name Description

Y_IMP 0: AUXADC data proceeding
1: AUXADC data ready

AL
14:0 AUXADC_ADC_OU AUXADC output data
T_IMP

TI
AUXADC_A
0E3C AUXADC ADC Register 30 0000
DC30
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

EN
AUX
ADC
_AD
C_R
Name DY_ AUXADC_ADC_OUT_IMP_AVG
IMP

Type
Reset
_AV
G
RO
0 0 0 0 0 0 0
ID 0
RO
0 0 0 0 0 0 0 0
NF
Bit(s) Name Description
15 AUXADC_ADC_RD AUXADC output data ready
Y_IMP_AVG 0: AUXADC data proceeding
CO

1: AUXADC data ready

14:0 AUXADC_ADC_OU AUXADC output data
T_IMP_AVG
K

AUXADC_A
0E3E AUXADC ADC Register 31 0000
DC31
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TE

Name AUXADC_ADC_OUT_RAW
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IA

Bit(s) Name Description

14:0 AUXADC_ADC_OU AUXADC channel output raw data
T_RAW
ED

AUXADC_A
0E40 AUXADC ADC Register 32 0000
DC32
M

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AUX
ADC
_AD
Name C_R AUXADC_ADC_OUT_MDRT
DY_
MDR
T
Type RO RO

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit(s) Name Description

AL
15 AUXADC_ADC_RD AUXADC output data ready
Y_MDRT 0: AUXADC data proceeding
1: AUXADC data ready
14:0 AUXADC_ADC_OU AUXADC output data

TI
T_MDRT

EN
AUXADC_A
0E42 AUXADC ADC Register 33 0000
DC33
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AUX
ADC
_AD
Name C_R
DY_
MDB
ID
AUXADC_ADC_OUT_MDBG
NF
G
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit(s) Name Description

15 AUXADC_ADC_RD AUXADC output data ready

Y_MDBG 0: AUXADC data proceeding
1: AUXADC data ready
14:0 AUXADC_ADC_OU AUXADC output data
T_MDBG
K
TE

AUXADC_B
0E44 AUXADC_BUF0 0000
UF0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AUX
ADC
IA

_BU
Name F_R AUXADC_BUF_OUT_00
DY_
00
Type RO RO
ED

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit(s) Name Description

15 AUXADC_BUF_RD AUXADC_BUF_00
M

Y_00 0: AUXADC data proceeding

1: AUXADC data ready
14:0 AUXADC_BUF_OU
T_00

AUXADC_B
0E46 AUXADC_BUF1 0000
UF1

AL
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AUX
ADC
Name _BU AUXADC_BUF_OUT_01
F_R
DY_

TI
01
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EN
Bit(s) Name Description
15 AUXADC_BUF_RD AUXADC_BUF_01
Y_01 0: AUXADC data proceeding
1: AUXADC data ready
14:0 AUXADC_BUF_OU
T_01
ID
NF
AUXADC_B
0E48 AUXADC_BUF2 0000
UF2
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CO

AUX
ADC
Name _BU AUXADC_BUF_OUT_02
F_R
DY_
02
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
K

Bit(s) Name Description

15 AUXADC_BUF_RD AUXADC_BUF_02
Y_02 0: AUXADC data proceeding
1: AUXADC data ready
14:0 AUXADC_BUF_OU
T_02
IA
ED

AUXADC_B
0E4A AUXADC_BUF3 0000
UF3
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AUX
ADC
M

_BU
Name F_R AUXADC_BUF_OUT_03
DY_
03
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit(s) Name Description

15 AUXADC_BUF_RD AUXADC_BUF_03
Y_03 0: AUXADC data proceeding

AL
1: AUXADC data ready
14:0 AUXADC_BUF_OU
T_03

TI
AUXADC_B
0E4C AUXADC_BUF4 0000
UF4

EN
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AUX
ADC
_BU
Name F_R AUXADC_BUF_OUT_04

ID
DY_
04
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
NF
Bit(s) Name Description
15 AUXADC_BUF_RD AUXADC_BUF_04
Y_04 0: AUXADC data proceeding
1: AUXADC data ready
CO

14:0 AUXADC_BUF_OU
T_04

AUXADC_B
K

0E4E AUXADC_BUF5 0000

UF5
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TE

AUX
ADC
_BU
Name F_R AUXADC_BUF_OUT_05
DY_
05
IA

Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit(s) Name Description

15 AUXADC_BUF_RD AUXADC_BUF_05
Y_05 0: AUXADC data proceeding
1: AUXADC data ready
14:0 AUXADC_BUF_OU
M

T_05

AUXADC_B
0E50 AUXADC_BUF6 0000
UF6
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

AUX
ADC
_BU
Name F_R AUXADC_BUF_OUT_06

AL
DY_
06
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TI
Bit(s) Name Description
15 AUXADC_BUF_RD AUXADC_BUF_06
Y_06 0: AUXADC data proceeding

EN
1: AUXADC data ready
14:0 AUXADC_BUF_OU
T_06

0E52

Bit 15
AUXADC_B
UF7
14 13 12
AUXADC_BUF7

11 10 9
ID 8 7 6 5 4 3 2 1
0000

0
NF
AUX
ADC
_BU
Name F_R AUXADC_BUF_OUT_07
DY_
CO

07
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit(s) Name Description

15 AUXADC_BUF_RD AUXADC_BUF_07
K

Y_07 0: AUXADC data proceeding

1: AUXADC data ready
14:0 AUXADC_BUF_OU
TE

T_07
IA

AUXADC_B
0E54 AUXADC_BUF8 0000
UF8
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AUX
ED

ADC
Name _BU AUXADC_BUF_OUT_08
F_R
DY_
08
Type RO RO
M

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit(s) Name Description

15 AUXADC_BUF_RD AUXADC_BUF_08
Y_08 0: AUXADC data proceeding
1: AUXADC data ready

Bit(s) Name Description

14:0 AUXADC_BUF_OU
T_08

AL
AUXADC_B
0E56 AUXADC_BUF9 0000

TI
UF9
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AUX
ADC

EN
_BU
Name F_R AUXADC_BUF_OUT_09
DY_
09
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit(s)
15
Name
AUXADC_BUF_RD
Description
AUXADC_BUF_09
ID
NF
Y_09 0: AUXADC data proceeding
1: AUXADC data ready
14:0 AUXADC_BUF_OU
T_09
CO

AUXADC_B
0E58 AUXADC_BUF10 0000
UF10
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
K

AUX
ADC
_BU
Name F_R AUXADC_BUF_OUT_10
TE

DY_
10
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IA

Bit(s) Name Description

15 AUXADC_BUF_RD AUXADC_BUF_10
Y_10 0: AUXADC data proceeding
ED

1: AUXADC data ready

14:0 AUXADC_BUF_OU
T_10
M

AUXADC_B
0E5A AUXADC_BUF11 0000
UF11
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AUX
Name ADC AUXADC_BUF_OUT_11
_BU
F_R

DY_
11
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

AL
Bit(s) Name Description
15 AUXADC_BUF_RD AUXADC_BUF_11
Y_11 0: AUXADC data proceeding

TI
1: AUXADC data ready
14:0 AUXADC_BUF_OU
T_11

EN
AUXADC_B
0E5C AUXADC_BUF12 0000
UF12
Bit
AUX
ADC
_BU
Name F_R
15 14 13 12 11 10 9
ID 8 7

AUXADC_BUF_OUT_12
6 5 4 3 2 1 0
NF
DY_
12
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CO

Bit(s) Name Description

15 AUXADC_BUF_RD AUXADC_BUF_12
Y_12 0: AUXADC data proceeding
1: AUXADC data ready
14:0 AUXADC_BUF_OU
K

T_12
TE

AUXADC_B
0E5E AUXADC_BUF13 0000
UF13
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IA

AUX
ADC
Name _BU AUXADC_BUF_OUT_13
F_R
DY_
ED

13
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit(s) Name Description

15 AUXADC_BUF_RD AUXADC_BUF_13
Y_13 0: AUXADC data proceeding
1: AUXADC data ready
14:0 AUXADC_BUF_OU
T_13

AUXADC_B
0E60 AUXADC_BUF14 0000

AL
UF14
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AUX
ADC
Name _BU AUXADC_BUF_OUT_14
F_R

TI
DY_
14
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EN
Bit(s) Name Description
15 AUXADC_BUF_RD AUXADC_BUF_14
Y_14 0: AUXADC data proceeding

14:0 AUXADC_BUF_OU
T_14
1: AUXADC data ready

ID
NF
AUXADC_B
0E62 AUXADC_BUF15 0000
UF15
CO

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AUX
ADC
Name _BU AUXADC_BUF_OUT_15
F_R
DY_
15
Type RO RO
K

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
TE

Bit(s) Name Description

15 AUXADC_BUF_RD AUXADC_BUF_15
Y_15 0: AUXADC data proceeding
1: AUXADC data ready
IA

14:0 AUXADC_BUF_OU
T_15
ED

AUXADC_B
0E64 AUXADC_BUF16 0000
UF16
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AUX
M

ADC
Name _BU AUXADC_BUF_OUT_16
F_R
DY_
16
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit(s) Name Description

15 AUXADC_BUF_RD AUXADC_BUF_16
Y_16 0: AUXADC data proceeding

AL
1: AUXADC data ready
14:0 AUXADC_BUF_OU
T_16

TI
AUXADC_B
0E66 AUXADC_BUF17 0000
UF17

EN
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AUX
ADC
_BU
Name F_R AUXADC_BUF_OUT_17

ID
DY_
17
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
NF
Bit(s) Name Description
15 AUXADC_BUF_RD AUXADC_BUF_17
Y_17 0: AUXADC data proceeding
1: AUXADC data ready
CO

14:0 AUXADC_BUF_OU
T_17

AUXADC_B
K

0E68 AUXADC_BUF18 0000

UF18
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TE

AUX
ADC
_BU
Name F_R AUXADC_BUF_OUT_18
DY_
18
IA

Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit(s) Name Description

15 AUXADC_BUF_RD AUXADC_BUF_18
Y_18 0: AUXADC data proceeding
1: AUXADC data ready
14:0 AUXADC_BUF_OU
M

T_18

AUXADC_B
0E6A AUXADC_BUF19 0000
UF19
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

AUX
ADC
_BU
Name F_R AUXADC_BUF_OUT_19

AL
DY_
19
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TI
Bit(s) Name Description
15 AUXADC_BUF_RD AUXADC_BUF_19
Y_19 0: AUXADC data proceeding

EN
1: AUXADC data ready
14:0 AUXADC_BUF_OU
T_19

0E6C

Bit 15
AUXADC_B
UF20
14 13 12
AUXADC_BUF20

11 10 9
ID 8 7 6 5 4 3 2 1
0000

0
NF
AUX
ADC
_BU
Name F_R AUXADC_BUF_OUT_20
DY_
CO

20
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit(s) Name Description

15 AUXADC_BUF_RD AUXADC_BUF_20
K

Y_20 0: AUXADC data proceeding

1: AUXADC data ready
14:0 AUXADC_BUF_OU
TE

T_20
IA

AUXADC_B
0E6E AUXADC_BUF21 0000
UF21
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AUX
ED

ADC
Name _BU AUXADC_BUF_OUT_21
F_R
DY_
21
Type RO RO
M

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit(s) Name Description

15 AUXADC_BUF_RD AUXADC_BUF_21
Y_21 0: AUXADC data proceeding
1: AUXADC data ready

Bit(s) Name Description

14:0 AUXADC_BUF_OU
T_21

AL
AUXADC_B
0E70 AUXADC_BUF22 0000

TI
UF22
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AUX
ADC

EN
_BU
Name F_R AUXADC_BUF_OUT_22
DY_
22
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit(s)
15
Name
AUXADC_BUF_RD
Description
AUXADC_BUF_22
ID
NF
Y_22 0: AUXADC data proceeding
1: AUXADC data ready
14:0 AUXADC_BUF_OU
T_22
CO

AUXADC_B
0E72 AUXADC_BUF23 0000
UF23
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
K

AUX
ADC
_BU
Name F_R AUXADC_BUF_OUT_23
TE

DY_
23
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IA

Bit(s) Name Description

15 AUXADC_BUF_RD AUXADC_BUF_23
Y_23 0: AUXADC data proceeding
ED

1: AUXADC data ready

14:0 AUXADC_BUF_OU
T_23
M

AUXADC_B
0E74 AUXADC_BUF24 0000
UF24
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AUX
Name ADC AUXADC_BUF_OUT_24
_BU
F_R

DY_
24
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

AL
Bit(s) Name Description
15 AUXADC_BUF_RD AUXADC_BUF_24
Y_24 0: AUXADC data proceeding

TI
1: AUXADC data ready
14:0 AUXADC_BUF_OU
T_24

EN
AUXADC_B
0E76 AUXADC_BUF25 0000
UF25
Bit
AUX
ADC
_BU
Name F_R
15 14 13 12 11 10 9
ID 8 7

AUXADC_BUF_OUT_25
6 5 4 3 2 1 0
NF
DY_
25
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CO

Bit(s) Name Description

15 AUXADC_BUF_RD AUXADC_BUF_25
Y_25 0: AUXADC data proceeding
1: AUXADC data ready
14:0 AUXADC_BUF_OU
K

T_25
TE

AUXADC_B
0E78 AUXADC_BUF26 0000
UF26
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IA

AUX
ADC
Name _BU AUXADC_BUF_OUT_26
F_R
DY_
ED

26
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit(s) Name Description

15 AUXADC_BUF_RD AUXADC_BUF_26
Y_26 0: AUXADC data proceeding
1: AUXADC data ready
14:0 AUXADC_BUF_OU
T_26

AUXADC_B
0E7A AUXADC_BUF27 0000

AL
UF27
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AUX
ADC
Name _BU AUXADC_BUF_OUT_27
F_R

TI
DY_
27
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EN
Bit(s) Name Description
15 AUXADC_BUF_RD AUXADC_BUF_27
Y_27 0: AUXADC data proceeding

14:0 AUXADC_BUF_OU
T_27
1: AUXADC data ready

ID
NF
AUXADC_B
0E7C AUXADC_BUF28 0000
UF28
CO

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AUX
ADC
Name _BU AUXADC_BUF_OUT_28
F_R
DY_
28
Type RO RO
K

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
TE

Bit(s) Name Description

15 AUXADC_BUF_RD AUXADC_BUF_28
Y_28 0: AUXADC data proceeding
1: AUXADC data ready
IA

14:0 AUXADC_BUF_OU
T_28
ED

AUXADC_B
0E7E AUXADC_BUF29 0000
UF29
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AUX
M

ADC
Name _BU AUXADC_BUF_OUT_29
F_R
DY_
29
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit(s) Name Description

15 AUXADC_BUF_RD AUXADC_BUF_29
Y_29 0: AUXADC data proceeding

AL
1: AUXADC data ready
14:0 AUXADC_BUF_OU
T_29

TI
AUXADC_B
0E80 AUXADC_BUF30 0000
UF30

EN
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AUX
ADC
_BU
Name F_R AUXADC_BUF_OUT_30

ID
DY_
30
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
NF
Bit(s) Name Description
15 AUXADC_BUF_RD AUXADC_BUF_30
Y_30 0: AUXADC data proceeding
1: AUXADC data ready
CO

14:0 AUXADC_BUF_OU
T_30

AUXADC_B
K

0E82 AUXADC_BUF31 0000

UF31
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TE

AUX
ADC
_BU
Name F_R AUXADC_BUF_OUT_31
DY_
31
IA

Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit(s) Name Description

15 AUXADC_BUF_RD AUXADC_BUF_31
Y_31 0: AUXADC data proceeding
1: AUXADC data ready
14:0 AUXADC_BUF_OU
M

T_31

AUXADC_ST
0E84 AUXADC_STA0 0000
A0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

AUX AUX
AUX AUX
ADC ADC
ADC ADC
_AD _AD
_AD _AD
C_B C_B

AL
C_B C_B
Name USY USY AUXADC_ADC_BUSY_IN
USY USY
_IN_ _IN_
_IN_ _IN_
WA VIS
LBA LBA
KEU MPS
T2 T
P 0
Type RO RO RO RO RO

TI
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit(s) Name Description

EN
15 AUXADC_ADC_BU ADC busy status
SY_IN_WAKEUP 0: Idle
1: Busy
14 AUXADC_ADC_BU ADC busy status
SY_IN_VISMPS0 0: Idle

13 AUXADC_ADC_BU
SY_IN_LBAT2
1: Busy
ADC busy status
0: Idle
1: Busy
ID
NF
12 AUXADC_ADC_BU ADC busy status
SY_IN_LBAT 0: Idle
1: Busy
11:0 AUXADC_ADC_BU AUXADC ADC busy status
CO

SY_IN bit[11] = CH11 ~ bit[0] = CH0

0: Idle
1: Busy
K

AUXADC_ST
0E86 AUXADC_STA1 0000
A1
TE

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AUX
AUX AUX AUX AUX AUX AUX AUX AUX
ADC AUX AUX
ADC ADC ADC ADC ADC ADC ADC ADC
_AD ADC ADC
_AD _AD _AD _AD _AD _AD _AD _AD
C_B _AD _AD
C_B C_B C_B C_B C_B C_B C_B C_B
Name USY USY C_B
USY USY USY USY
C_B
USY USY USY
IA

_IN_ USY USY

_IN_ _IN_ _IN_ _IN_ _IN_ _IN_ _IN_ _IN_
THR _IN_ _IN_
THR GPS GPS FGA FGA SHA MDB MDR
_H GPS IMP
_MD _MD _AP DC2 DC1 RE G T
W
Type RO RO RO RO RO RO RO RO RO RO RO
ED

Reset 0 0 0 0 0 0 0 0 0 0 0

Bit(s) Name Description

15 AUXADC_ADC_BU ADC busy status
M

SY_IN_THR_MD 0: Idle
1: Busy
14 AUXADC_ADC_BU ADC busy status
SY_IN_THR_HW 0: Idle
1: Busy
13 AUXADC_ADC_BU ADC busy status
SY_IN_GPS 0: Idle

Bit(s) Name Description

1: Busy
12 AUXADC_ADC_BU ADC busy status

AL
SY_IN_GPS_MD 0: Idle
1: Busy
11 AUXADC_ADC_BU ADC busy status
SY_IN_GPS_AP 0: Idle

TI
1: Busy
10 AUXADC_ADC_BU ADC busy status
SY_IN_FGADC2 0: Idle
1: Busy

EN
9 AUXADC_ADC_BU ADC busy status
SY_IN_FGADC1 0: Idle
1: Busy
8 AUXADC_ADC_BU ADC busy status
SY_IN_IMP

7 AUXADC_ADC_BU
SY_IN_SHARE
0: Idle
1: Busy
ADC busy status
0: Idle
ID
NF
1: Busy
6 AUXADC_ADC_BU ADC busy status
SY_IN_MDBG 0: Idle
1: Busy
5 AUXADC_ADC_BU ADC busy status
CO

SY_IN_MDRT 0: Idle
1: Busy

AUXADC_VI
K

0EF4 AUXADC_VISMPS0_5 8000

SMPS0_5
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TE

Name AUXADC_VISMPS0_VOLT_MIN
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0

Bit(s) Name Description

11:0 AUXADC_VISMPS0 VISMPS0 detection voltage setting

_VOLT_MIN
ED

AUXADC_LB
0F02 AUXADC_LBAT2_5 8000
AT2_5
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M

Name AUXADC_LBAT2_VOLT_MIN
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0

Bit(s) Name Description

11:0 AUXADC_LBAT2_V LBAT2 detection voltage setting
OLT_MIN

AL
ACCDET_CO
0F14 ACCDET control register 0 0010
N0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RG_ AUD RG_
RG_ RG_
AUD ACC AUD RG_ RG_
AUD RG_ AUD

TI
ACC DET ACC AUD AUD
ACC AUD RG_ ACC
DET AUX DET ACC ACC
DET ACC RG_AUDACCDET ACC DET
Name MIC ADC MIC DET DET
VIN1 DET SWCTRL DET ANA
BIAS SWC BIAS VTH VTH
PUL TVD SEL SWC
0PU TRL 1PU ACA BCA

EN
LLO ET TRL
LLL _SE LLL L L
W ENB
OW L OW
Type RW RW RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 1 0 0 0 0

Bit(s)
12
Name
RG_AUDACCDETM
ICBIAS0PULLLOW
Description
ID
Pulls low MIC Bias 0 pads when MICBIAS is off
1'b0: Disable
1'b1: Enable
NF
11 AUDACCDETAUXA 1'b0: HW mode
DCSWCTRL_SEL 1'b1: SW mode
9 RG_AUDACCDETVI Pulls low VIN1 pads when MICBIAS is off
N1PULLLOW 1'b0: Disable
CO

1'b1: Enable
8 RG_AUDACCDETT Places audio accessory detection into TV mode
VDET
7 RG_AUDACCDETM Pulls low MIC Bias 1 pads when MICBIAS is off
ICBIAS1PULLLOW 1'b0: Disable
1'b1: Enable
K

6:4 RG_AUDACCDETS Controls ACCDET to AUXADC switch

WCTRL 001: Normal mode
TE

010: 200K
100: 100K
Others: Not allowed
3 RG_ACCDETSEL Selects ACCDET input
1'b0: ACCDET pin
IA

1'b1: MICP pin

2 RG_AUDACCDETA
NASWCTRLENB
1 RG_AUDACCDETV Calibrates audio accessory detection voltage threshold A
ED

THACAL
0 RG_AUDACCDETV Calibrates audio accessory detection voltage threshold B
THBCAL
M

ACCDET_CO
0F16 ACCDET Control Register 1 0000
N1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
accd ACC ACC ACC ACC ACC ACC
Name et_a DET DET DET DET DET DET
nasw _NE _NE _EIN _EI _SE _EN

ctrl_ GVD GVD T_S NTD Q_I

sel ET_ ET_ EQ_I ET_ NIT
EN_ EN NIT EN
CTR

AL
L
Type RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0

Bit(s) Name Description

TI
6 accdet_anaswctrl_se Selects who controls connection between AUXADC and ACCDET
l when in hook-key status
1'b0: AUXADC

EN
1'b1: ACCDET
5 ACCDET_NEGVDE Initializes status default value
T_EN_CTRL 1'b0: HW mode
1'b1: SW mode
4 ACCDET_NEGVDE Enables negative debounce

3
T_EN

ACCDET_EINT_SE
Q_INIT
1'b0: Disable
1'b1: Enable
ID
Initializes EINT status default value
1'b0: Disable
NF
1'b1: Enable
2 ACCDET_EINTDET Enables EINT detection
_EN 1'b0: Disable
1'b1: Enable
CO

1 ACCDET_SEQ_INI Initializes ACCDET status default value

T 1'b0: Normal mode
1'b1: Initialized mode
0 ACCDET_EN Enables ACCDET
Must be set to 0 before switched to TV mode.
1'b0: Disable
K

1'b1: Enable
TE

ACCDET_CO
0F18 ACCDET control register 2 0000
N2
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IA

ACC
ACC ACC ACC
DET
DET DET DET
_MB
_EIN _VT _CM
Name IAS_
T_P H_P P_P
PW
ED

WM WM WM
M_E
_EN _EN _EN
N
Type RW RW RW RW
Reset 0 0 0 0
M

Bit(s) Name Description

3 ACCDET_EINT_PW Enables PWM of ACCDET EINT unit
M_EN Disabled in TV mode
1'b0: Disable
1'b1: Enable
2 ACCDET_MBIAS_P Enables PWM of ACCDET MBIAS unit
WM_EN Disabled in TV mode

Bit(s) Name Description

1'b0: Disable
1'b1: Enable

AL
1 ACCDET_VTH_PW Enables PWM of ACCDET voltage threshold unit
M_EN Disabled in TV mode
1'b0: Disable
1'b1: Enable
0 ACCDET_CMP_PW Enables PWM of ACCDET comparator

TI
M_EN 1'b0: Disable
1'b1: Enable

EN
ACCDET_CO
0F1A ACCDET Control Register 3 0000
N3
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
Type
Reset 0 0 0 0 0 0 0 0 ID
ACCDET_PWM_WIDTH
RW
0 0 0 0 0 0 0 0
NF
Bit(s) Name Description
15:0 ACCDET_PWM_WI ACCDET PWM width
DTH PWM output frequency = 32,768/(PWM_WIDTH+1)Hz
CO

ACCDET_CO
0F1C ACCDET Control Register 4 0000
N4
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
K

Name ACCDET_PWM_THRESH
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
TE

Bit(s) Name Description

ACCDET_PWM_TH ACCDET PWM threshold
15:0 RESH PWM output duty cycle = (PWM_THRESH+1)/(PWM_WIDTH+1)
IA

PWM output high time = (PWM_THRESH+1)/32,768 sec

ACCDET_CO
0F1E ACCDET Control Register 5 0101
N5
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ACC
DET
M

_FA
Name ACCDET_RISE_DELAY
LL_
DEL
AY
Type RW RW
Reset 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1

Bit(s) Name Description

15 ACCDET_FALL_DE Falling delay cycle compared to PWM waveform
LAY To make sure the plug state is stable after ACCDET is disabled, the suitable

AL
falling delay cycle is necessary.
14:0 ACCDET_RISE_DE Rising delay cycle compared to PWM waveform
LAY To make sure the plug state is stable before ACCDET is enabled, the suitable
rising delay cycle is necessary.

TI
ACCDET_CO

EN
0F20 ACCDET Control Register 6 0010
N6
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name ACCDET_DEBOUNCE0
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0

Bit(s)
15:0
Name
ACCDET_DEBOUN
Description ID
De-bounce time control of state 0
NF
CE0 De-bounce time = (DEBOUNCE/freq) sec
In TV mode, freq is bus clock and 32,768Hz in the MIC mode.
CO

ACCDET_CO
0F22 ACCDET Control Register 7 0010
N7
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name ACCDET_DEBOUNCE1
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0
K

Bit(s) Name Description

15:0 ACCDET_DEBOUN De-bounce time control of state 1

CE1 De-bounce time = (DEBOUNCE/freq) sec
In TV mode, freq is bus clock and 32,768Hz in the MIC mode.
IA

ACCDET_CO
0F24 ACCDET Control Register 8 0010
N8
ED

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name ACCDET_DEBOUNCE2
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0
M

Bit(s) Name Description

15:0 ACCDET_DEBOUN De-bounce time control of state 2
CE2 De-bounce time = (DEBOUNCE/freq) sec
In TV mode, freq is bus clock 32,768Hz in the MIC mode.

ACCDET_CO
0F26 ACCDET Control Register 9 0010
N9

AL
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name ACCDET_DEBOUNCE3
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0

TI
Bit(s) Name Description
15:0 ACCDET_DEBOUN De-bounce time control of state 3
CE3 De-bounce time = (DEBOUNCE/freq) sec
In TV mode, freq is bus clock 32,768Hz in the MIC mode.

EN
ACCDET_CO
0F28 ACCDET Control Register 10 0005

Bit
Name
Type
15
N10
14 13 12 11 10 9
ID 8
ACCDET_DEBOUNCE4
RW
7 6 5 4 3 2 1 0
NF
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

Bit(s) Name Description

15:0 ACCDET_DEBOUN De-bounce time to control AUXADC when in state 0
CO

CE4

ACCDET_CO
0F2C ACCDET Control Register 12 0000
N12
K

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ACC
ACC
DET ACC
TE

DET ACC ACC ACC

_EI DET ACC
_NE DET DET DET
NT_I _EI DET
Name RQ_ NT_I
GV_ _IR _EI _NE
_IR
IRQ Q_C NT_I GV_
POL RQ_ Q
_CL LR RQ IRQ
ARIT CLR
R
Y
IA

Type RW RW RW RW RO RO RO
Reset 0 0 0 0 0 0 0
ED

Bit(s) Name Description

15 ACCDET_EINT_IR ACCDET EINT IRQ polarity
Q_POLARITY 1'b0: Falling edge
1'b1: Rising edge
10 ACCDET_EINT_IR Clears ACCDET_EINT interrupt status
M

Q_CLR When ACCDET_EINT interrupt is asserted, IRQ_CLR must be set to 1 to

clear the interrupt status. This bit will pause all activities of ACCDET_EINT
design until both the interrupt status and IRQ_CLR are cleared.
9 ACCDET_NEGV_IR Clears ACCDET_NEGV interrupt status
Q_CLR When ACCDET_NEGV interrupt is asserted, IRQ_CLR must be set to 1 to
clear the interrupt status. This bit will pause all activities of ACCDET_NEGV
design until both the interrupt status and IRQ_CLR are cleared.

Bit(s) Name Description

8 ACCDET_IRQ_CLR Clears ACCDET interrupt status
When ACCDET interrupt is asserted, IRQ_CLR must be set to 1 to clear the

AL
interrupt status. This bit will pause all activities of ACCDET design until both
the interrupt status and IRQ_CLR are cleared.
2 ACCDET_EINT_IR Clears ACCDET_EINT interrupt status
Q

TI
1 ACCDET_NEGV_IR Clears ACCDET_NEGV interrupt status
Q
0 ACCDET_IRQ ACCDET interrupt status
Due to this register is cleared by the hardware, the interrupt edge-sensitive

EN
scheme should be adopted for this design.

ACCDET_CO
0F30

Bit
DA_
AUD
15
N14
14 13 12
ACCDET Control Register 14

11 10 9 ID 8 7 6 5 4 3 2 1
00FF

0
NF
ACC ACC ACC
ACC
DET DET DET
DET
Name AUX _CM _VT _MB
P_C H_C IAS_
ADC
LK LK CLK
SWC
TRL
CO

Type RO RO RO RO
Reset 0 0 0 0

Bit(s) Name Description

15 DA_AUDACCDETA Controls ACCDET to AUXADC switch
K

UXADCSWCTRL
14 ACCDET_CMP_CL Turns on comparator for accessory detection
K
TE

13 ACCDET_VTH_CLK Turns on threshold voltage for accessory detection

12 ACCDET_MBIAS_C Turns on earphone bias voltage for accessory detection
LK
IA

ACCDET_CO
0F32 ACCDET Control Register 15 0061
N15
ED

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ACCDET_E
ACCDET_EINT_P ACCDET_EINT_
Name INT_PWM
WM_THRESH DEBOUNCE
_WIDTH
Type RW RW RW
M

Reset 0 0 0 0 0 1 1 0

Bit(s) Name Description

13:12 ACCDET_EINT_PW ACCDET EINT PWM width
M_WIDTH 2'b00: 4ms
2'b01: 8ms
2'b10: 16ms

Bit(s) Name Description

2'b11: 32ms
10:8 ACCDET_EINT_PW ACCDET EINT PWM threshold

AL
M_THRESH 3'b000: 0.5ms
3'b001: 1ms
3'b010: 2ms
3'b011: 3ms
3'b100: 4ms

TI
3'b101: 8ms
3'b110: 16ms
3'b111: 32ms
6:4 ACCDET_EINT_DE ACCDET EINT debounce time

EN
BOUNCE 3'b000: 1ms
3'b001: 2ms
3'b010: 4ms
3'b011: 8ms
3'b100: 16ms
3'b101: 32ms
3'b110: 256ms
3'b111: 512ms ID
NF
ACCDET_CO
0F34 ACCDET Control Register 16 0161
N16
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CO

ACC
DET
_EI
NT_
Name ACCDET_EINT_PWM_RISE_DELAY PW ACCDET_NEGV_THRESH
M_F
ALL
K

_DE
LAY
Type RW RW RW
Reset
TE

0 0 0 0 0 0 0 1 0 1 1 0 0 0 0 1

Bit(s) Name Description

15:6 ACCDET_EINT_PW Rising delay cycle compared to PWM waveform
IA

M_RISE_DELAY To make sure the plug state is stable before ACCDET_EINT is enabled, the
suitable rising delay cycle is necessary.
5 ACCDET_EINT_PW Falling delay cycle compared to PWM waveform
M_FALL_DELAY To make sure the plug state is stable after ACCDET_EINT is disabled, the
ED

suitable falling delay cycle is necessary.

4:0 ACCDET_NEGV_T ACCDET NVG debounce threshold
HRESH 5'd0: 1/32
5'd1: 2/32
5'd2: 3/32
M

5'd3: 4/32
5'dN: (N+1)/32

ACCDET_CO
0F3A ACCDET Control Register 19 0000
N19

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NI_ NVD
EINT
Name EINT CMP ETE
CMP CTO

AL
OUT
EN UT
Type RO RO RO
Reset 0 0 0

Bit(s) Name Description

TI
15 NI_EINTCMPEN
14 EINTCMPOUT
13 NVDETECTOUT

EN
0F48 CHR_CON0 Charger Control Register 0 0001
Bit

Name
15 14 13 12 11 10 9
ID 8
RGS
_VC
DT_
7 6
RGS
_CH
RDE
5

RG_
CHR
RG_
CSD
AC_
4 3 2 1
RGS RG_
_CH VCD
R_L T_H
0
NF
HV_ _EN DO_ V_E
T EN
DET DET N
Type RO RO RW RW RO RW
Reset 0 0 0 0 0 1
CO

Bit(s) Name Description

7 RGS_VCDT_HV_D Detects charger-in high voltage (with de-bounce)
ET 0: Charge-in voltage < VCDT_HV_VTH
1: Charge-in voltage > VCDT_HV_VTH
5 RGS_CHRDET Detects charger-in
0: No valid charger detected
K

1: Valid charger detected

4 RG_CHR_EN Charger enable setting
TE

Will gate CSDAC_EN, PCHR_AUTO and HWCV_EN.

0: Disable charger
1: Enable charger
3 RG_CSDAC_EN Enables CS DAC
0: Disable CS DAC
IA

1: Enable CS DAC
1 RGS_CHR_LDO_D Detects charger LDO
ET If not detected, pulse charger cannot work.
0: Invalid charger LDO
ED

1: Valid charger LDO

0 RG_VCDT_HV_EN Enables ChargerIn HV detection function
0: Disable
1: Enable
M

0F4A CHR_CON1 Charger Control Register 1 00F2

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RG_VCDT_HV_VTH RG_VCDT_LV_VTH
Type RW RW
Reset 1 1 1 1 0 0 1 0

Bit(s) Name Description

AL
7:4 RG_VCDT_HV_VT ChargerIn HV detection threshold
H Default 4.3/9.5V for VTHL/VTHH.
0000~1000: 4.2V~4.6V with 50mV/step
1001~1100: 6V~7.5V with 500mV/step
1101~1111: 8.5V~10.5V with 1000mV/step

TI
3:0 RG_VCDT_LV_VT ChargerIn LV detection threshold
H Default 4.3/9.5V for VTHL/VTHH.
0000~1000: 4.2V~4.6V with 50mV/step
1001~1100: 6V~7.5V with 500mV/step

EN
1101~1111: 8.5V~10.5V with 1000mV/step

0F4C CHR_CON2 Charger Control Register 2 0004

Bit

Name
15 14 13 12 11 10 9
ID 8
RGS
_VB
AT_
7 6
RGS
_VB
AT_
RGS
_CS
_DE
5 4 3

RG_
CS_
2
RG_ RG_
VBA VBA
T_C T_C
1 0
NF
CC_ CV_ EN C_E V_E
T
DET DET N N
Type RO RO RO RW RW RW
Reset 0 0 0 0 1 0
CO

Bit(s) Name Description

7 RGS_VBAT_CC_DE Detects VBAT voltage for CC
T 0: VBAT voltage < VBAT_CC_VTH
1: VBAT voltage > VBAT_CC_VTH
6 RGS_VBAT_CV_DE Detects VBAT voltage for CV
T 0: VBAT voltage < VBAT_CV_VTH
K

1: VBAT voltage > VBAT_CV_VTH

5 RGS_CS_DET Detects current sense voltage
TE

0: CS voltage < CS_VTH

1: CS voltage > CS_VTH
3 RG_CS_EN Enables current sense voltage detection comparator
0: Disable
1: Enable
IA

2 RG_VBAT_CC_EN Enables battery CC detection

1 RG_VBAT_CV_EN Enables battery CV detection
0: Disable
1: Enable
ED

0F4E CHR_CON3 Charger Control Register 3 00CD

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RG_VBAT
Name _CC_VTH
RG_VBAT_CV_VTH
Type RW RW
Reset 1 1 0 1 1 0 1

Bit(s) Name Description

7:6 RG_VBAT_CC_VT Battery CC detection threshold
H 00: 3.3V

AL
01: 3.35V
10: 3.4V
11: 3.45V (default)
4:0 RG_VBAT_CV_VT Battery CV detection threshold trimming option
H Default 4.2V. For FT CV threshold trimming but not for fine tuning (pchr_dig

TI
should invert MSB bit; otherwise, BC1.1 2.2V threshold will be wrong.)
00000: 3.7750V
00001: 3.8000V
00010: 3.8500V

EN
00011: 3.9000V
00100: 4.0000V
00101: 4.0500V
00110: 4.1000V
00111: 4.1250V
01000: 4.1375V
01001: 4.1500V
01010: 4.1625V
01011: 4.1750V
01100: 4.1875V
ID
NF
01101: 4.2000V (default)
01110: 4.2125V
01111: 4.2250V
10000: 4.2375V
10001: 4.2500V
CO

10010: 4.2625V
10011: 4.2750V
10100: 4.3000V
10101: 4.3250V
10110: 4.3500V
10111: 4.3750V
11000: 4.4400V
K

11001: 4.4250V
11111: 2.2V (used in BC1.1 application)
TE

0F50 CHR_CON4 Charger Control Register 4 000F

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IA

Name RG_CS_VTH
Type RW
Reset 1 1 1 1
ED

Bit(s) Name Description

3:0 RG_CS_VTH Current sense voltage detection threshold @ Rcs=56mohm
1111: 70mA
1110: 200mA
1101: 300mA
M

1100: 450mA (usbdl)

1011: 550mA
1010: 650mA
1001: 700mA
1000: 800mA
0111: 900mA
0110: 1000mA
0101: 1100mA
0100: 1200mA

Bit(s) Name Description

0011: 1350mA
0010: 1500mA

AL
0001: 1600mA
0000: 2000mA

TI
0F54 CHR_CON6 Charger Control Register 6 0001
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RGS RG_ RG_
_VB VBA VBA

EN
RG_VBAT_OV_V
Name AT_ T_O T_O
TH
OV_ V_D V_E
DET EG N
Type RO RW RW RW
Reset 0 0 0 0 0 1

Bit(s)
6
Name
RGS_VBAT_OV_D
ET
Description
Detects VBAT_OV voltage
ID
NF
0: VBAT voltage < VBAT_OV_VTH
1: VBAT voltage > VBAT_OV_VTH
5 RG_VBAT_OV_DE Enables VBAT OV voltage detection deglitch
G 0: No debounce
1: Debounce one cycle (1us)
CO

3:1 RG_VBAT_OV_VT Battery over-voltage detection threshold (H/L)

H 000: 4.200V/4.150V (default)
001: 4.300V/4.250V
010: 4.400V/4.350V
011: 4.450V/4.400V
1xx: 3.800V/3.800V
K

0 RG_VBAT_OV_EN Battery over-voltage for driving protection

0: Disable
1: Enable
TE

0F56 CHR_CON7 Charger Control Register 7 0001

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RG_
RG_
BAT BAT
BAT RG_
ON_ ON_
ON_ BAT
Name TDE HT_
ED

TDE ON_
T_E EN_
T_E EN
N RSV
N
0
Type RW RW RW RW
Reset 0 0 0 1
M

Bit(s) Name Description

8 RG_BATON_TDET Enables BATON temperature detection via AUXADC
_EN (Gated by CHR_LDO_DET to default 0 in analog domain). This RG is also
used to enable external SWCHR BATON detection.
0: Disable temperature detection related TREF power switch
1: Enable temperature detection related TREF power switch (SW should
enable AUXADC reference buffer before enabling this switch)

Bit(s) Name Description

2 BATON_TDET_EN 0: N/A
1: Enable BATON temperature detection

AL
1 RG_BATON_HT_E Detects battery-on HW high temperature
N_RSV0 0: Disable
1: Enable
0 RG_BATON_EN Enables BATON battery detection comparator

TI
(Gated by CHR_LDO_DET to default 1 in analog domain)
0: Disable
1: Enable (default)

EN
0F5A CHR_CON9 Charger Control Register 9 0000
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ID
RG_
FRC
_CS
Name VTH
_US
NF
BDL
Type RW
Reset 0

Bit(s) Name Description

0 RG_FRC_CSVTH_ Forces CS DAC detection threshold to maximum in USB download

USBDL mode
0: CS_VTH=450mA in USBDL mode
1: CS_VTH=1600mA in USBDL mode
K

0F5C CHR_CON10 Charger Control Register 10 0020

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RGS RG_
_OT OTG
G_B _BV
Name
VALI ALI
D_D D_E
IA

ET N
Type RO RW
Reset 0 1
ED

Bit(s) Name Description

6 RGS_OTG_BVALID Indicates if the session for B-peripheral is valid (0.8V<Vth<4V).
_DET Here VBUS is connected to CHRIN
0: Vbus < 0.8V
M

1: Vbus > 4V
5 RG_OTG_BVALID_ Enables OTG BValid detection
EN 0: Disable
1: Enable

0F60 CHR_CON12 Charger Control Register 12 0000

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

AL
RG_PCHR_FT_
Name
CTRL
Type RW
Reset 0 0 0

TI
Bit(s) Name Description
6:4 RG_PCHR_FT_CTR FT control bits
L Bit[2]: Extend charger detection duration 10ms
Bit[1]: Force TOH/TOL = 3ms/1ms

EN
Bit[0]: Always turn on charger detection (VCDT)

0F62 CHR_CON13 Charger Control Register 13 0010

Bit

Name
15 14 13 12 11 10 9
ID
RG_
CHR
WDT
8 7 6 5
RG_
CHR
WDT
4 3 2

RG_CHRWDT_TD
1 0
NF
_WR _EN
Type RW RW RW
Reset 0 1 0 0 0 0
CO

Bit(s) Name Description

8 RG_CHRWDT_WR Resets charger watchdog timer and updates CHRWDT_TD
0: Reset inactive
1: Reset active and CHRWDT_TD updated to PCHR_DIG
4 RG_CHRWDT_EN Enables charger watchdog timer
Note: UVLO doesn't care this bit and will time out after 3000s.
K

PCHR_TESTMODE can be forced to control watchdog enable by using this

bit.
0: Disable
TE

1: Enable if (CHR_EN(@CHR_CON0) = 1)
3:0 RG_CHRWDT_TD Time constant setting for charger watchdog timer
0: 4 sec
1: 8 sec
2: 16 sec
IA

3: 32 sec
4: 128 sec
5: 256 sec
6: 512 sec
ED

7: 1024 sec
8~15: 3000 sec
M

0F64 CHR_CON14 Charger Control Register 14 0000

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RG_PCHR_RV
Type RW
Reset 0 0 0 0 0 0 0 0

Bit(s) Name Description

7:0 RG_PCHR_RV Reserved for tests

AL
0F66 CHR_CON15 Charger Control Register 15 0000
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

TI
RG_
RGS RG_
CHR
_CH CHR
WDT
Name RW WDT
_FL
DT_ _INT
AG_

EN
OUT _EN
WR
Type RO RW RW
Reset 0 0 0

Bit(s) Name Description

2 RGS_CHRWDT_OU
T Read:
0: No timeout status
ID
Timeout flag for charger watchdog timer
NF
1: Assert timeout status
1 RG_CHRWDT_FLA Clears timeout flag for charger watchdog timer
G_WR Read:
0: N/A (while RGS_CHRWDT_OUT=0)
1: Clear timeout flag when RGS_CHRWDT_OUT=1
CO

0 RG_CHRWDT_INT Interrupt enable setting for charger watchdog timer

_EN 0: Disable
1: Enable
K

0F68 CHR_CON16 Charger Control Register 16 0000

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TE

RG_
ADC RG_
RG_ RG_
RG_ IN_ ADC
ADC ADC RG_ RG_
ADC VSE IN_
IN_ IN_ USB USB
Name IN_C
VSE VBA
N_E VSE
DL_ DL_
HR_ XT_ N_M
N_E T_E SET RST
IA

EN BAT UX_
N N
ON_ EN
EN
Type RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0
ED

Bit(s) Name Description

12 RG_ADCIN_CHR_ Enables AUXADC input source for CHR
EN 0: Disable
M

1: Enable
11 RG_ADCIN_VSEN_ Enables AUXADC input source for VSEN
EN 0: Disable
1: Enable
10 RG_ADCIN_VBAT_ Enables AUXADC input source for VBAT
EN 0: Disable
1: Enable

Bit(s) Name Description

9 RG_ADCIN_VSEN_ Enables AUXADC input source for external source to be switched
EXT_BATON_EN to AUXADC's Ch3

AL
0: Disable
1: Enable
8 RG_ADCIN_VSEN_ Enables AUXADC input source for VSEN to be switched to VBAT's
MUX_EN divider
0: Disable

TI
1: Enable
3 RG_USBDL_SET Controls USBDL_MODE software setup
0: No effect

EN
1: Force to enter USBDL mode
2 RG_USBDL_RST Controls USBDL_MODE software reset
0: No effect
1: Force to leave USBDL mode (the priority is lower than USBDL_DET.)

0F6A CHR_CON17 Charger Control Register 17

ID 0002
NF
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RG_
UVL
Name O_V RG_UVLO_VTHL
H_L
AT
CO

Type RW RW
Reset 0 0 0 0 1 0

Bit(s) Name Description

7 RG_UVLO_VH_LA UVLO VH latch signal
T 0: Disable
K

1: Enable
4:0 RG_UVLO_VTHL Selects UVLO low threshold
TE

00000: 2.5V
00001: 2.55V
00010: 2.6V (default)
00011: 2.65V
00100: 2.7V
IA

00101: 2.75V
00110: 2.8V
00111: 2.85V
01000: 2.9V
ED

0F6C CHR_CON18 Charger Control Register 18 0003

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M

Name RG_LBAT_INT_VTH
Type RW
Reset 0 0 0 1 1

Bit(s) Name Description

4:0 RG_LBAT_INT_VT LBAT_INT threshold voltage
H 00000: 2.5V

Bit(s) Name Description

00001: 2.55V
00010: 2.6V (default)

AL
00011: 2.65V
00100: 2.7V
00101: 2.75V
00110: 2.8V
00111: 2.85V
01000: 2.9V

TI
01001: 2.95V
01010: 3.0V
01011: 3.05V
01100: 3.1V

EN
01101: 3.15V
01110: 3.2V
01111: 3.25V
11000: 3.3V
11001: 3.35V
11010: 3.4V

ID
NF
0F6E CHR_CON19 Charger Control Register 19 0000
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RG_
RG_
BGR
BGR
_UN
Name _UN RG_BGR_RSEL
CO

CHO
CHO
P_P
P
H
Type RW RW RW
Reset 0 0 0 0 0

Bit(s) Name Description

5 RG_BGR_UNCHOP BGR unchop mode

0: Chop mode
TE

1: Unchop mode
4 RG_BGR_UNCHOP Selects BGR unchop mode phase
_PH 0: Select phase 0 path in unchop mode
1: Select phase 1 path in unchop mode
IA

2:0 RG_BGR_RSEL Selects BGR resistor (R0 = R1)

R2=85K, and VBG=(R0/R2)*dVBE+VBE
0: c0, 780K (default)
1: c1, 820K
2: c2, 860K
ED

3: c3, 900K
4: cm4, 620K
5: cm3, 660K
6: cm2, 700K
7: cm1, 740K
M

0F70 CHR_CON20 Charger Control Register 20 0000

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RGS RG_ RG_
RG_BC11_
Name _BC1 BC11 BC11
VSRC_EN
1_C _RS _BB

MP_ T _CT
OUT RL
Type RO RW RW RW
Reset 0 0 0 0 0

AL
Bit(s) Name Description
7 RGS_BC11_CMP_O Detects comparison result of BC11 charger
UT 0: DP or DM < BC11_VREF_VTH

TI
1: DP or DM > BC11_VREF_VTH
3:2 RG_BC11_VSRC_E BC11 voltage source
N Set VDP_SRC = 0.6V.

EN
0: Disable voltage
1: Enable voltage source to DM
2: Enable voltage source to DP
3: Forbidden
1 RG_BC11_RST Resets BC11 detection mechanism in PCHR_DIG

0 RG_BC11_BB_CTR
L
0: No effect

ID
1: BC11 detection mechanism is disabled in PCHR_DIG.
Forces BC11 charger detection controlled by baseband
0: BC11 detection by PCHR_DIG (hardware mode)
NF
1: BC11 detection by baseband (software mode)

0F72 CHR_CON21 Charger Control Register 21 0000

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RG_
BC11
RG_BC11_I RG_BC11_I RG_BC11_ RG_BC11_
Name _BIA
PU_EN PD_EN CMP_EN VREF_VTH
S_E
N
Type RW RW RW RW RW
K

Reset 0 0 0 0 0 0 0 0 0
TE

Bit(s) Name Description

8 RG_BC11_BIAS_EN Enables BC11 detection bias circuit
0: Disable
1: Enable
IA

7:6 RG_BC11_IPU_EN Enables BC11 7~15uA pull up current

0: Disable pull-up current
1: Enable pull-up current to DM
2: Enable pull-up current to DP
ED

3: Forbidden
5:4 RG_BC11_IPD_EN BC11 50~150uA pull-down current
0: Disable pull-down current
1: Enable pull-down current to DM
2: Enable pull-down current to DP
M

3: Forbidden
3:2 RG_BC11_CMP_EN BC11 comparator connection
0: Disable comparator
1: Enable comparator to DM
2: Enable comparator to DP
3: Forbidden
1:0 RG_BC11_VREF_V VREF threshold voltage for comparator
TH 0: VREF_VTH=0.325V

Bit(s) Name Description

1: VREF_VTH=1.2V
2, 3: VREF_VTH=2.6V (for Apple adaptor)

AL
0F74 CHR_CON22 Charger Control Register 22 0022

TI
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RG_CSDAC_ST RG_CSDAC_ST
Name P_DEC P_INC
Type RW RW
Reset 0 1 0 0 1 0

EN
Bit(s) Name Description
6:4 RG_CSDAC_STP_D CV HW Mode decreased code per step
EC 1/1/2/3/4/5/6/7 code/ per-step
2:0 RG_CSDAC_STP_I
NC ID
CV HW Mode increased code per step
1/1/2/3/4/5/6/7 code/ per-step
NF
0F76 CHR_CON23 Charger Control Register 23 0024
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
CO

RG_CSDAC_STP RG_CSDAC_DLY
Type RW RW
Reset 0 1 0 1 0 0

Bit(s) Name Description

6:4 RG_CSDAC_STP Current DAC output step timer
K

1/1/2/3/4/5/6/7 code/ per-step

2:0 RG_CSDAC_DLY Controls current DAC output detection delay
TE

16/32/64/128/256/512/1024/2048us
(512us default, reused in HW CV mode)
IA

0F78 CHR_CON24 Charger Control Register 24 0044

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RG_
CHR RG_
ED

IND CHR
Name RG_LOW_ICH_DB
_DI IND
MMI _ON
NG
Type RW RW RW
Reset 0 1 0 0 0 1 0 0
M

Bit(s) Name Description

7 RG_CHRIND_DIM Enables pre-charge indicator dimming
MING 0: Disable
1: Enable
6 RG_CHRIND_ON Pre-charge indicator on

Bit(s) Name Description

(Gated by CHR_LDO_DET to default 0 in analog domain)
0: Disable indicator

AL
1: Enable indicator
5:0 RG_LOW_ICH_DB Plug out HW detection debounce time (base=16ms)
Debounce time: Code*16ms

TI
0F7A CHR_CON25 Charger Control Register 25 0010
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

EN
RG_ RG_ RG_
RG_ RG_ RG_
ULC TRA CSD
HW VCD CV_
Name _DE CKI AC_
CV_ T_M MOD
T_E NG_ MOD
EN ODE E
N EN E
Type RW RW RW RW RW RW
Reset

Bit(s) Name Description

ID 0 0 1 0 0 0
NF
7 RG_ULC_DET_EN Enables charger plug-out auto detection
This function has to be applied with RG_HWCV_EN=1.
0: Disable
1: Enable
6 RG_HWCV_EN Enables hardware CV current tracking
CO

0: Disable
1: Enable
4 RG_TRACKING_E 0: Current calibration use CS_VTH[n] and CS_VTH[n-1] as
N high/low threshold.
1: Current calibration use CS_VTH[n] and LTH as high/low threshold.
2 RG_CSDAC_MODE 0: If not entering CC, charging is in AUTO mode.
K

1: If leaving UVLO, charging is controlled by RG_CSDAC_EN (same as CC

mode).
TE

1 RG_VCDT_MODE Selects charger detection mode

0: Charger detection can only be active in off state.
1: Charger detection is active in both on and off state.
0 RG_CV_MODE Selects battery CV detection mode
0: CV detection can only be active in off state.
IA

1: CV detection is active in both on and off state.

0F7C CHR_CON26 Charger Control Register 26 0000

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RG_
BGR
Name RG_ICHRG_TRIM _TRI
M

M_E
N
Type RW RW
Reset 0 0 0 0 0

Bit(s) Name Description

7:4 RG_ICHRG_TRIM Charging current trimming

Bit(s) Name Description

0 RG_BGR_TRIM_E Enables bandgap trimming
N 0: Disable BG trimming and bypass voltage buffer

AL
1: Enable BG trimming and voltage buffer

TI
0F7E CHR_CON27 Charger Control Register 27 0000
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RG_BGR_TRIM
Type RW

EN
Reset 0 0 0 0 0

Bit(s) Name Description

4:0 RG_BGR_TRIM Bandgap output voltage trimming

ID
0~15: VBG=1.205V~1.280V with 5mV/step
16~31: VBG=1.125V~1.200V with 5mV/step
NF
0F80 CHR_CON28 Charger Control Register 28 0000
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RG_OVP_TRIM
Type RW
CO

Reset 0 0 0 0

Bit(s) Name Description

3:0 RG_OVP_TRIM Battery over-voltage protection threshold trimming
K

0F82 CHR_CON29 Charger Control Register 29 0000

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RG_ QI_
RG_
BGR BGR
BGR
_TE _EX
Name ST_
_TE
T_B
RG_CHR_OSC_TRIM
IA

ST_
RST UF_
EN
B EN
Type RW RW RW RW
Reset 0 0 0 0 0 0 0 0
ED

Bit(s) Name Description

7 RG_BGR_TEST_RS Bandgap reference FT test mode resetb signal
TB (Also gated by RG_BGR_TEST_EN=0 & PMU_TESTMODE=0) -> GPIO
M

control in test mode

0: Reset
1: Does not reset
6 RG_BGR_TEST_E Bandgap reference FT test mode enable signal
N 0: Normal mode
1: Test mode (should combine PMU_TESTMODE=1)
5 QI_BGR_EXT_BUF Bandgap reference buffer for external usage (MT8320)
_EN 0: Disable

Bit(s) Name Description

1: Enable (default)
4:0 RG_CHR_OSC_TRI PCHR 1MHz clock trimming, osc. frequency @ tt25oC w/o

AL
M trimming
0: 977.2kHz
1: 938.3kHz
2: 903.0kHz
3: 870.9kHz

TI
4: 841.4kHz
5: 814.5kHz
6: 789.7kHz
7: 766.9kHz

EN
8: 745.9kHz
9: 726.2kHz
10: 708.0kHz
11: 691.1kHz
12: 675.2kHz
13: 660.4kHz
14: 646.6kHz
15: 633.6kHz
16: 3.864MHz
17: 3.222MHz
ID
NF
18: 2.768MHz
19: 2.428MHz
20: 2.164MHz
21: 1.953MHz
22: 1.782MHz
23: 1.639MHz
CO

24: 1.518MHz
25: 1.416MHz
26: 1.327MHz
27: 1.249MHz
28: 1.181MHz
29: 1.121MHz
30: 1.068MHz
K

31: 1.020MHz
TE

0F84 CHR_CON30 Charger Control Register 30 0055

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RG_DAC_USBDL_MAX
IA

Type RW
Reset 0 0 0 1 0 1 0 1 0 1

Bit(s) Name Description

9:0 RG_DAC_USBDL_ USBDL maximum current setting

MAX Default: 85 => 0001010101
M

0F86 CHR_CON31 Charger Control Register 31 0000

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PCH RG_
R_C CM_
Name M_V VDE
DEC C_T
_ST RIG

ATU
S
Type RO RW
Reset 0 0

AL
Bit(s) Name Description
4 PCHR_CM_VDEC_ Automatic current procedure status in adaptor output voltage
STATUS decrement communication mode

TI
0: Idle
1: Previous trigger is done
0 RG_CM_VDEC_TR Automatic current procedure trigger in adaptor output voltage
IG decrement communication mode

EN
0: No effect
1: Trigger automatic current procedure in adaptor output voltage decrement
communication mode

0F88
Bit 15
CHR_CON32
14 13 12
Charger Control Register 32
11 10 9
ID 8 7 6 5 4 3 2 1
0000
0
NF
PCH
RG_
R_C
CM_
M_V
Name INC_
VIN
C_T
STA
RIG
TUS
CO

Type RO RW
Reset 0 0

Bit(s) Name Description

4 PCHR_CM_VINC_S Automatic current procedure status in adaptor output voltage
TATUS decrement communication mode
K

0: Idle
1: Previous trigger is done
TE

0 RG_CM_VINC_TRI Automatic current procedure trigger in adaptor output voltage

G increment communication mode
0: No effect
1: Trigger automatic current procedure in adaptor output voltage increment
communication mode
IA

0F8A CHR_CON33 Charger Control Register 33 1D1D

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RG_CM_VDEC_HPRD2 RG_CM_VDEC_HPRD1
Type RW RW
Reset 0 1 1 1 0 1 0 1 1 1 0 1
M

Bit(s) Name Description

13:8 RG_CM_VDEC_HP 2nd high pulse width of the adaptor output voltage decrement
RD2 communication mode
High pulse width = (Setting+1)*10ms
5:0 RG_CM_VDEC_HP 1st high pulse width of the adaptor output voltage decrement
RD1 communication mode

Bit(s) Name Description

High pulse width = (Setting+1)*10ms

AL
0F8C CHR_CON34 Charger Control Register 34 091D
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

TI
Name RG_CM_VDEC_HPRD4 RG_CM_VDEC_HPRD3
Type RW RW
Reset 0 0 1 0 0 1 0 1 1 1 0 1

EN
Bit(s) Name Description
13:8 RG_CM_VDEC_HP 4th high pulse width of the adaptor output voltage decrement
RD4 communication mode
High pulse width = (Setting+1)*10ms
5:0 RG_CM_VDEC_HP
RD3
ID
3rd high pulse width of the adaptor output voltage decrement
communication mode
High pulse width = (Setting+1)*10ms
NF
0F8E CHR_CON35 Charger Control Register 35 3109
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CO

Name RG_CM_VDEC_HPRD6 RG_CM_VDEC_HPRD5

Type RW RW
Reset 1 1 0 0 0 1 0 0 1 0 0 1

Bit(s) Name Description

13:8 RG_CM_VDEC_HP 6th high pulse width of the adaptor output voltage decrement
K

RD6 communication mode

High pulse width = (Setting+1)*10ms
5:0 RG_CM_VDEC_HP 5th high pulse width of the adaptor output voltage decrement
TE

RD5 communication mode

High pulse width = (Setting+1)*10ms
IA

0F90 CHR_CON36 Charger Control Register 36 0909

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RG_CM_VINC_HPRD2 RG_CM_VINC_HPRD1
ED

Type RW RW
Reset 0 0 1 0 0 1 0 0 1 0 0 1

Bit(s) Name Description

13:8 RG_CM_VINC_HP 2nd high pulse width of the adaptor output voltage increment
RD2 communication mode
High pulse width = (Setting+1)*10ms
5:0 RG_CM_VINC_HP 1st high pulse width of the adaptor output voltage increment
RD1 communication mode
High pulse width = (Setting+1)*10ms

0F92 CHR_CON37 Charger Control Register 37 1D1D

AL
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RG_CM_VINC_HPRD4 RG_CM_VINC_HPRD3
Type RW RW
Reset 0 1 1 1 0 1 0 1 1 1 0 1

TI
Bit(s) Name Description
13:8 RG_CM_VINC_HP 4th high pulse width of the adaptor output voltage increment
RD4 communication mode

EN
High pulse width = (Setting+1)*10ms
5:0 RG_CM_VINC_HP 3rd high pulse width of the adaptor output voltage increment
RD3 communication mode
High pulse width = (Setting+1)*10ms

0F94 CHR_CON38 Charger Control Register 38

ID 311D
NF
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RG_CM_VINC_HPRD6 RG_CM_VINC_HPRD5
Type RW RW
Reset 1 1 0 0 0 1 0 1 1 1 0 1
CO

Bit(s) Name Description

13:8 RG_CM_VINC_HP 6th high pulse width of the adaptor output voltage increment
RD6 communication mode
High pulse width = (Setting+1)*10ms
5:0 RG_CM_VINC_HP 5th high pulse width of the adaptor output voltage increment
RD5 communication mode
K

High pulse width = (Setting+1)*10ms

0F96 CHR_CON39 Charger Control Register 39 0009

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RG_CM_LPRD
IA

Type RW
Reset 0 0 1 0 0 1
ED

Bit(s) Name Description

5:0 RG_CM_LPRD Low pulse width in communication mode
Low pulse width = (Setting+1)*10ms
M

0F98 CHR_CON40 Charger Control Register 40 00AF

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RG_CM_CS_VTHH RG_CM_CS_VTHL
Type RW RW
Reset 1 0 1 0 1 1 1 1

Bit(s) Name Description

7:4 RG_CM_CS_VTHH Current sense detection high threshold in communication mode
0000: 2000mA

AL
0001: 1600mA
0010: 1500mA
0011: 1350mA
0100: 1200mA
0101: 1100mA

TI
0110: 1000mA
0111: 900mA
1000: 800mA
1001: 700mA

EN
1010: 650mA
1011: 550mA
1100: 450mA
1101: 300mA
1110: 200mA
1111: 70mA
3:0 RG_CM_CS_VTHL
ID
Current sense detection low threshold in communication mode
0000: 2000mA
0001: 1600mA
0010: 1500mA
NF
0011: 1350mA
0100: 1200mA
0101: 1100mA
0110: 1000mA
0111: 900mA
CO

1000: 800mA
1001: 700mA
1010: 650mA
1011: 550mA
1100: 450mA
1101: 300mA
1110: 200mA
K

1111: 70mA
TE

0F9A CHR_CON41 Charger Control Register 41 0000

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RGS
_BA
IA

Name RG_PCHR_RSV TON

_UN
DET
Type RW RO
ED

Reset 0 0 0 0 0 0 0 0

Bit(s) Name Description

7:1 RG_PCHR_RSV Reserved
M

0 RGS_BATON_UND Battery-On undetected

ET 0: Detected
1: Not detected

0F9C CHR_CON42 Charger Control Register 42 0000

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RG_ RG_
ENV ENV
Name
TEM TEM

AL
_EN _D
Type RW RW
Reset 0 0

Bit(s) Name Description

TI
1 RG_ENVTEM_EN Blocks CHR_DET signal to start_up
0: N/A
1: Enable write

EN
0 RG_ENVTEM_D Blocks CHR_DET signal to start_up
0: Does not block
1: Block

0F9E
BATON_CO
N0
BATON Control Register 0 ID 0000
NF
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RG_
BAT
RG_
ON_
BAT
HT_
Name ON_
EN_
CO

HT_
DLY
EN
_TI
ME
Type RW RW
Reset 0 0
K

Bit(s) Name Description

4 RG_BATON_HT_E BATON high-temperature detection delay time
N_DLY_TIME 1'b0: 6T
TE

1'b1: 12T
0 RG_BATON_HT_E Detects battery-on HW high temperature
N 1'b0: disable
1'b1: enable
IA

0FA0 CHR_CON43 Charger Control Register 43 0000

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RG_ RG_
CM_ CM_
VIN VDE
Name C_IN C_IN
M

T_E T_E
N N
Type RW RW
Reset 0 0

Bit(s) Name Description

11 RG_CM_VINC_INT Enables pump express VDEC INT
_EN

Bit(s) Name Description

9 RG_CM_VDEC_IN Enables pump express VDEC INT
T_EN

AL
TI
EN
ID
NF
CO
K
TE
IA
ED
M

4 Application Notes

AL
4.1 Hardware External Shutdown
The following schematic illustrates the hardware external shut-down function for MT6328 to power

TI
down when the main chip software crashes.

 Short press PWRKEY or HOMEKEY

EN
– INT-> EINT -> software control
– Power-down, sleep mode or the other functions
 Long press shut-down
– Force power-off of PMU
– 5/8/11/14 s with < 1% accuracy
– External reset function with source from:
▪ PWRKEY and HOMEKEY both pressed for a long period of time
ID
NF
– PWRKEY and HOMEKEY do not use same key
▪ PWERKEY pressed for a long period of time
▪ HOMEKEY pressed for a long period of time
CO

– Software disables watchdog counter.

K
TE
IA
ED

Figure 4-1. Hardware external shut-down function

4.2 Configuration for Unused Buck Converter

The figure below shows the configuration for MT6328 VPA buck converters that is not used.

AL
▪ Configuration for VPA not in use:
– VBAT_PA connect to VBAT; GND_PA connect to GND
– VPA & VPA_FB: floating

TI
– RG_VPA_EN = 0 & RG_VPA_NDIS_EN = 1 (software setting)

EN
ID
NF

Figure 4-2. Configuration for unused DC/DC

CO
K
TE
IA
ED
M

5 MT6328 Packaging

AL
5.1 Package Dimensions

TI
EN
ID
NF
CO
K
TE
IA
ED
M

Figure 5-1. Package dimension

Appendix

AL
TI
EN
ID
NF
CO
K
TE
IA
ED
M

This document contains information that is proprietary to MediaTek Inc.
Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited.

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