Analog Integr Circ Sig Process (2010) 62:113–119

DOI 10.1007/s10470-009-9333-7

A 3 V 110 lW 3.1 ppm/°C curvature-compensated CMOS

bandgap reference
Xiaokang Guan Æ Xin Wang Æ Albert Wang Æ
Bin Zhao

Received: 10 December 2008 / Revised: 8 June 2009 / Accepted: 12 June 2009 / Published online: 26 June 2009
Ó The Author(s) 2009. This article is published with open access at Springerlink.com

Abstract This paper presents design of a high-precision circuits. The basic idea of BGR in CMOS technology is to
curvature-compensated bandgap reference (BGR) circuit add a proportional to absolute temperature (PTAT) voltage
implemented in a 0.35 lm CMOS technology. The circuit to the emitter-base voltage (VEB) of a parasitic pnp tran-
delivers an output voltage of 1.09 V and achieves the sistor, so that the first-order temperature dependency in
lowest reported temperature coefficient of *3.1 ppm/°C VEB is compensated by the PTAT voltage, resulting in a
over a wide temperature range of [-20°C/?100°C] after nearly temperature-independent output voltage. Typical
trimming, a power supply rejection ratio p offfiffiffiffiffiffi-80 dB at output voltage of BGR is about 1.2 V at room temperature,
1 kHz and an output noise level of 1.43 lV Hz at 1 kHz. which is close to the bandgap voltage of silicon. However,
The BGR circuit consumes a very low current of 37 lA at for conventional BGR circuits, the higher-order tempera-
3 V and works for a power supply down to 1.5 V. The ture dependency in VEB still exists in output voltage. In
BGR circuit has a die size of 980 lm 9 830 lm. order to further lower the temperature coefficient (TC),
several curvature compensation schemes [1–4] have been
Keywords Bandgap reference
CMOS
reported to compensate the higher-order temperature
Temperature coefficient
Power supply rejection ratio dependency and to reduce the output voltage variation over
the temperature.
This paper presents design of a current-mode curvature-
1 Introduction compensated BGR fabricated in a commercial 0.35 lm
CMOS technology. Several design issues were carefully
Bandgap Reference (BGR) circuits are basic functional studied to optimize the critical BGR specifications, such as
circuit blocks widely used in many integrated circuit (IC) temperature coefficient, power supply rejection ratio
chips, such as, power management, temperature sensors, (PSRR) and power consumption. Section 2 explains the
data converters, voltage regulators and memories, because design details. Section 3 discusses the experimental results
of its excellent temperature stability and insensitivity to flowed by conclusions in Sect. 4.
supply voltage. Since introduced in 1970s, BGR has been
the most popular solution for precision reference source
2 BGR circuit design

2.1 Current mode BGR with curvature compensation

X. Guan
B. Zhao
Freescale Semiconductors, Inc., Irvine, CA, USA Current mode BGR [5] was originally introduced to
implement a voltage reference circuit when power supply is
X. Guan
X. Wang
A. Wang (&) \1.2 V. Figure 1 shows a simplified curvature-compen-
Department of Electrical Engineering, University of California,
sated circuitry based upon the current mode scheme that is
Riverside, CA 92521, USA
e-mail: aw@ee.ucr.edu capable of further reducing the BGR output voltage vari-
URL: http://lics.ee.ucr.edu ation against temperature [6]. By connecting a resistor

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114 Analog Integr Circ Sig Process (2010) 62:113–119

 
T
VEBQ2  VEBQ3 VT ln Tr
I3 ¼ ¼ ð3Þ
R5 R5
rÞ
where the term of VT lnðT=T
R5 can provide corrective current
to compensate the higher-order temperature dependency in
I2. The value of R5 is properly chosen for optimum
curvature compensation as:
R2
R5 ¼ ð4Þ
ðg  1Þ
Theoretically, by properly adjusting the ratios of R1/R2
and R5/R2, one can obtain a simplified expression of the
Vout as:
R4
Vout ¼ VG ðTÞ ð5Þ
R2
It is readily observed from (5) that the variation of Vout
Fig. 1 Simplified schematic of current mode BGR with curvature against the temperature originates from the bandgap volt-
compensation, where parasitic pnp transistors in CMOS are used age VG(T) only. Hence, further reduction the output voltage
variation against temperature requires an accurate mea-
surement and expression of VG(T).
between the emitter and base of BJT transistor Q2, an extra
VEBQ2
current of I2 ¼ R2 is obtained, which is added to the 2.2 Resistor trimming network and trimming
VEBQ2 VEBQ1
PTAT current, I1 ¼ ; to
generate a current with methodology
R1
low sensitivity to the temperature
   variation.

From Fig. 1, given WL M1 ¼ 2 WL M3 ; the Vout can be Due to inevitable process variation and inaccuracy in
derived as: device model of the parasitic pnp transistors, a fine resistor
trimming network is necessary to achieve optimal tem-
Vout ¼ ðI1 þ I2 þ I3 ÞR4 perature performance. Implementation of an accurate
 
VEBQ2  VEBQ1 VEBQ2 VEBQ2  VEBQ3 trimming network for R1, R2 and R5 in this design is shown
¼ þ þ R4 in Fig. 2.
R1 R2 R5 ð1Þ
  In Fig. 2, the value for R is selected by circuit simula-
VT ln N VEBQ2 VEBQ2  VEBQ3
¼ þ þ R4 tion. It is clearly observed that the resistor value can be
R1 R2 R5
increased by 16% with step of 1% of R by cutting off the
where VT = KT/q and N is emitter area ratio of the BJT fuses. Such trimming resolution is high enough to achieve
VEB VEB
transistor Q1 and Q2. In (1), I1 ¼ Q2R1 Q1 ¼ VT RlnðNÞ
1
is the optimal temperature performance. It is noted that MOS
the PTAT current, which can compensate the first-order switch might replace fuse for trimming purpose in general,
temperature dependence in I2. Therefore, sum of I1 and I2 is which, however, has significant turn-on resistance that
almost constant over the temperature. Furthermore, the adversely affects the tuning accuracy desired for high-
nonlinear relationship between VEB and temperature can be performance BGR.
expressed as [7]: The proper resistor network trimming method is given
T below using the output voltage versus temperature curves
VEB ðTÞ ¼ VG ðTÞ  ½VG ðTr Þ  VEB ðTr Þ
Tr
 
T
 ðg  mÞVT ln ð2Þ
Tr
where VG(T) is the bandgap voltage of Si as a function of
temperature, Tr is the reference temperature, g is a
temperature constant dependent on technology and m is
the order of the temperature dependence of the collector
current. Since the emitter currents of Q2 and Q3 are PTAT
and temperature-independent, respectively, the third
current term in (1) can be expressed as: Fig. 2 An accurate resistor trimming network for R1, R2 and R5

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Analog Integr Circ Sig Process (2010) 62:113–119 115

(a) (b)
Vout Vout

Tr Temp Tr Temp

Fig. 3 a Vout(T) curve after R1 and R2 trimming; b Vout(T) curve after

R5 trimming

obtained from a two-step trimming procedure illustrated in

Fig. 3.
In the first step trimming, the ratio of R1 and R2 is fine-
tuned to compensate the first-order temperature depen-
dency in VEBQ2 and to make the highest output voltage
point occur around the reference temperature Tr, as shown
in Fig. 3(a). In the second step trimming, accurate trim-
Fig. 4 New unity-Add Op-Amp schematic used in the BGR circuit
ming of R5 is conducted for higher-order compensation
with the goal of achieving a symmetrical bell shape
Vout(T) curve around the Tr, which is desired to achieve
the lowest temperature coefficient, as illustrated in especially at high frequency, hence achieve the lowest
Fig. 3(b). PSRR ratio. This novel design concept can be understood
using the Op-Amp schematic shown in Fig. 4.
2.3 Power supply rejection ratio (PSRR) Assume that the bias current does not vary with vdd, the
power gain Add would be close to unity around DC.
For the BGR circuit shown in Fig. 1, the power supply However, the Add starts to roll off as frequency increases
rejection ratio (PSRR) can be derived as: when the equivalent impedance of CgdM6 of M6 is com-
    parable to the DC resistance seen between VDD and
vout   1  Add 
PSRR ¼    c  ð6Þ POUT. Adding the capacitor C solves this problem. The
v dd A 
power gain of the Op-Amp at high frequency region can be
where c is a constant dependent on the values of R1–R4 and derived as:
transconductance of Q1 and Q2 that is given as:
gmM4 RoM4 RoM2
2R3 þ ð1=gmQ2 Þ==R2 þ ðR1 þ 1=gmQ1 Þ==R2 Add ðxÞ ¼ 1
ð9Þ
c ¼ R4 ð7Þ gmM4 RoM4 RoM2 þ jxðCþC gdM6 Þ
R3 ½ðR1 þ 1=gmQ1 Þ==R2  ð1=gmQ2 Þ==R2 
where gmM4 is transconductance of transistor M4; and
Add and A in (6) are power gain and open-loop gain of
RoM4 and RoM2 are output resistance of M4 and M2,
the operational amplifier, respectively, and Add is expressed
respectively. From (9), it is readily observed that a large
as:
C value is desired to ensure magnitude of Add close to
voutput of OpAmp
Add ¼ ð8Þ unity. The capacitor C is also used to achieve the required
vdd frequency compensation for the Op-Amp circuit block.
Equation 6 clearly suggests that a large open-loop gain The Op-Amp performance can be further improved by
of the Op Amp will improve PSRR performance of BGR eliminating the negative impact depicted in (10), which is
circuit. However, large A may also cause stability problem. associated with the non-ideal current source in practical
Alternatively, one may choose to make the power gain Add circuit:
as close to unity as possible without increasing the open-
i=2
loop gain to achieve lower PSRR, which is a unique design Add ¼ 1  ð10Þ
vdd gmM7
technique introduced in this work where a large
capacitance is placed between the output node of where i is ripple in the tail current source due to vdd.
Op-Amp and the power supply to ensure a unity Add, Equation 10 clearly indicates that the fluctuation in the

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116 Analog Integr Circ Sig Process (2010) 62:113–119

Fig. 5 BGR self-biased Op-Amp circuit in this design

Table 1 Op-Amp performance summary

Fig. 6 Start-up circuit for the BGR in this work
Parameter Value

DC gain 103 dB 3 Start-up circuitry

Gain-bandwidth product 1.07 MHz
Phase margin 102° 3.1 Experimental verification
Current consumption 2.4 lA
This curvature-compensated BGR circuit is designed and
fabricated in a commercial 0.35 lm CMOS technology.
Extreme care was excised to ensure minimized resistor
non-ideal tail current would drive the Add away from its mismatching and Op-Amp offset voltage. Figure 7 shows
preferred unity value. In order to suppress the undesired i the die photo of the BGR circuit with bonding pads and
variation effect, the curvature-compensated current gener- wires. The die size of the BGR circuit is 980 lm 9
ated by BGR circuit itself is used to bias the Op-Amp block 830 lm including bonding pads.
in this design, as shown in Fig. 5. Careful design of the
telescopic Op-Amp results in the optimal performance as
summarized in Table 1. Simulation study shows that using
self-biasing scheme, the PSRR can be reduced by 20 dB,
compared to the BGR circuit with the Op-Amp biased
traditionally.

2.4 Start-up circuit

The Star-up circuit used in this design is shown in Fig. 6.

The start-up circuit operates as following: if the current in
Q2 and R2 is zero, the p-channel current sources (M1 and
M7) are off. The gate of M8 is then pulled down to
ground, hence injecting a significant current into Q2 and
R2. Once the circuit starts up, current in M7 and R6 will
cause the gate potential of M8 to increase and approach
VDD, which, in turn, turns off the startup circuit. The
same start-up scheme is also used for the Op-Amp biasing
circuit. Fig. 7 Die photo of the BGR circuit in this work

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Analog Integr Circ Sig Process (2010) 62:113–119 117

Figure 10 shows measured PSRR results of the BGR

circuit that achieves a low PSRR of less than -80 dB at
1 kHz. Figure 11 shows the measured noise performance
for the BGR circuit,
pffiffiffiffiffiffi which achieves a low output noise of
about 1.43 lV Hz at 1 kHz that is mainly attributed to
the Flicker noise generated by the MOS transistors in the
circuit (e.g., M1 and M3 in Fig. 1; M1, M2, M7 and M8 in
Fig. 6). The measured performance of the new BGR circuit
is summarized in Table 2 for comparison with the state-of-
art designs, which indicates that this design achieves the
lowest worst case TC compared with reported works in
similar CMOS technologies across similarly wide temper-
ature ranges.

Fig. 8 Measured Vout and total current consumption for the BGR -10
circuit
-20

-30

Sample 1 Sample 2 Sample 3 -40

1.105 -50

1.1 -60

-70
1.095
Vout (V)

-80
1.09
-90

1.085
1 10 100 1k 10k 100k 1M 10M 100M 1G 10G
1.08 Frequency (Hz)

1.075 Fig. 10 Measured PSRR results for the BGR circuit

-20 -10 0 10 20 30 40 50 60 70 80 90 100
Temp (°C)

Fig. 9 Measured temperature variation for three BGR circuit samples

Testing results of packaged samples in ceramic DIP

with removable lid are presented below. Die testing was
somewhat affected by parasitic probing resistance. Full
measurement was conducted for this BGR circuit over a
wide temperature range from -20 to ?100°C. Figure 8
gives the measured output voltage Vout and total current
consumption, showing an output voltage of around
1.09 V and a very low current of only 37 lA at a supply
of VDD = 3 V, respectively. The lowest working supply
voltage for this BGR circuit is 1.5 V. Figure 9 shows
measured Vout variation over wide temperature range of
[-20°C/?100°C]. The maximum measured variation of
Vout is merely 0.4 mV over the full [-20 ?100°C]
temperature range after trimming, which translates into a
very low TC of *3.1 ppm/°C in the worst case. Fig. 11 Measured noise output of the BGR circuit

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Table 2 Comparison of curvature-compensated Bandgap reference circuits

This work Reference [8] Reference [9] Reference [10]

Technology (lm CMOS) 0.35 2 0.6 0.35

Vout (V) 1.09 0.595 1.142 1.112
VDDmin (V) 1.5 1.1 2 1.5
DC Current (lA) 36.7 15 22 55
Temperature Range (°C) -20/?100 -15/?90 0/?100 ?25/?100
TC (ppm/°C) 3.1 20 5.3 10
PSRR -80 dB at 1 kHz N/A -20 dB at 1 kHz N/A

4 Conclusion 7. Tsividis, Y. P. (1980). Accurate analysis of temperature

effects in IC-VBE characteristics with application to bandgap
reference sources. IEEE Journal of Solid-State Circuits, 15,
This paper reports design and implementation of a current 1076–1084.
mode curvature-compensated BGR in a 0.35 lm CMOS 8. Rincon-Mora, G., & Allen, P. E. (1998). A 1.1-V current-mode
technology. The circuit features BGR self-biased Op-Amp, and piecewise-linear curvature-corrected bandgap reference.
unity power gain technique to achieve low PSRR and IEEE Journal of Solid-State Circuits, 33, 1551–1554.
9. Leung, K. N., Mok, P. K. T., & Leung, C. Y. (2003). A 2-V 23-
resistor trimming for low temperature coefficient. Mea- lA 5.3-ppm/°C curvature-compensated CMOS bandgap refer-
surement results show that the BGR circuit delivers an ence. IEEE Journal of Solid-State Circuits, 38, 561–564.
output voltage of 1.09 V, achieves the lowest reported 10. Hsiao, S.-W., Huang, Y.-C., Liang, D., Chen, H.-W. K., & Chen,
worst case TC of 3.1 ppm/°C over a wide temperature H.-S. (2006). A 1.5-V 10-ppm/°C 2nd-order curvature-compen-
sated CMOS bandgap reference with trimming. In Proceedings of
range of [-20°C/?100°C] and power consumption of 2006 IEEE International Symposium on Circuits and Systems,
37 lA at 3.3 V, a low PSSR of less than -80 dB at 1 kHz,
pffiffiffiffiffiffi Island of Kos, Greece, 21–24 May, 2006.
and a low output noise of 1.43 lV Hz at 1 kHz. The
BGR circuit has a die size of 980 lm 9 830 lm and works Xiaokang Guan received his
for a power supply down to 1.5 V. BSEE and MSEE degree in
Electrical Engineering from
Acknowledgments The authors thank AKM for project sponsorship Tianjin University, PR China, in
and design fabrication. 1997 and 2000, respectively. He
received PhD degree from
Open Access This article is distributed under the terms of the Department of Electrical and
Creative Commons Attribution Noncommercial License which per- Computer Engineering, Illinois
mits any noncommercial use, distribution, and reproduction in any Institute of Technology, in
medium, provided the original author(s) and source are credited. 2007. He is currently a Mixed-
Signal IC Design Engineer at
Freescale Semiconductor, Inc.,
References Irvine, CA, USA. His research
interests are mixed-signal, RF
IC design, ESD protection
1. Song, B. S., & Gary, P. R. (1983). A precision curvature-com-
design and multimedia signal processing.
pensated CMOS bandgap reference. IEEE Journal of Solid-State
Circuits, 18, 634–643.
2. Gunawan, M., Meijer, G. C. M., Fonderie, J., & Huijsing, J. H.
(1993). A curvature-corrected low-voltage bandgap reference. Xin Wang received his BS
IEEE Journal of Solid-State Circuits, 28, 667–670. degree from Beijing University
3. Lee, I., Kim, G., & Kim, W. (1994). Exponential curvature- of Posts & Telecommunica-
compensated BiCMOS bandgap references. IEEE Journal of tions, Beijing, China, in 2005
Solid-State Circuits, 29, 1396–1403. and MS degree from Depart-
4. Leung, C. Y., Leung, K. N., & Mok, P. K. T. (2004). Design of a ment of Electrical and Com-
1.5-V high-order curvature-compensated CMOS bandgap refer- puter Engineering, Illinois
ence. In Proceedings of 2004 IEEE International Symposium on Institute of Technology, Chi-
Circuits and Systems, Vancouver, Canada, 23–26 May, 2004. cago, USA in 2007. He is cur-
5. Banba, H., Shiga, H., Umezawa, A., Miyaba, T., Tanzawa, T., rently a PhD candidate at the
Atsumi, S., et al. (1999). A CMOS bandgap reference circuit with Department of Electrical Engi-
sub-1-V operation. IEEE Journal of Solid-State Circuits, 34, 670– neering, University of Califor-
674. nia, Riverside, CA, USA. His
6. Malcovati, P., Maloberti, F., Fiocchi, C., & Pruzzi, M. (2001). research interests are on UWB
Curvature-compensated BiCMOS bandgap with 1-V supply volt- RF transceiver and mixed-signal
age. IEEE Journal of Solid-State Circuits, 36, 1076–1081. IC design and on-chip ESD protection design.

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Analog Integr Circ Sig Process (2010) 62:113–119 119

Albert Wang received the BSEE he fabricated the industry first Cu/low-k (k \ 3) dual-damascene
degree from the Tsinghua Uni- interconnect by developing a successful fabrication process for the
versity, China, and the PhD EE Cu/SiOCH low-k dual-damascene interconnect which has been
degree from The State University widely used in today’s high performance ICs. In his tenure with
of New York at Buffalo in 1985 Conexant and Skyworks, he led and managed the design of analog/
and 1996, respectively. From mixed-signal/power-management ICs and RF transceiver ICs for
1995 to 1998, he was a Staff cellular mobile handsets. Currently he is the Director of Southern
Engineer at National Semicon- California Development Center, Freescale Semiconductor, Irvine,
ductor Corporation. From 1998 CA, where he leads the IC design and product development for
to 2007, He was Assistant and consumer electronics and wireless communications. He has authored
Associate Professor at the and co-authored more than 200 journal publications and conference
Department of Electrical and presentations, has written three book chapters, and holds 45 issued US
Computer Engineering, the Illi- patents. Dr Zhao has served on various IEEE conference committees
nois Institute of Technology, including International Electron Device Meeting (IEDM), IEEE
USA, where he directed the Symposium on VLSI Technology, IEEE Symposium on VLSI Cir-
Integrated Electronics Laboratory. He is currently a Professor of cuits, International Conference on Solid-State and IC Technology
Electrical and Computer Engineering and Director for the Laboratory (ICSICT), and International Conference on ASIC (ASICON). He has
for Integrated Circuits and Systems at the University of California, served as Chairman, Symposium on Advances in Interconnect and
Riverside, USA. His research interests focus on Analog/Mixed-Signal/ Packaging Materials, TMS 2000; Chair, Subcommittee of Integrated
RF ICs, Advanced on-Chip ESD Protection, IC CAD and Modelling, Circuits and Manufacturing, IEDM 2001; Co-Chair, ICSICT Orga-
SoC, and Nano Devices, etc. Wang received the CAREER Award from nizing Committee, 2001–2008; Co-Chair, ASICON Technical Pro-
the National Science Foundation in 2002. He is the author for the book gram Committee, 2007–2009; Guest Editor, IEEE/TMS Journal of
‘‘On-Chip ESD Protection for Integrated Circuits’’ (Kluwer 2002) and Electronic Materials; Guest Editor, IEEE Transactions on Electron
130? peer-reviewed papers in the field, and holds six US patents. Wang Devices; Associate Editor, IEEE Transactions on Circuits and Sys-
is Editor for the IEEE Electron Device Letters and Guest Editor for tems—I and II, respectively; Co-Chair, Technical Working Group of
IEEE Transactions on Microwave Theory and Techniques. He was RF and Analog/Mixed-Signal IC Technologies for Wireless Com-
Associate Editor for the IEEE Transactions on Circuits and Systems I, munications, the International Technology Roadmap for Semicon-
Associate Editor for the IEEE Transactions on Circuits and Systems II, ductors, 2003–2007; Chair, IEEE Johnson Technology Award
Guest Editor for the IEEE Journal of Solid-State Circuits and Guest Committee, 2007–2008; and Chair, IEEE/EDS VLSI Technology and
Editor-in-Chief for the IEEE Transactions on Electron Devices. He is Circuits Committee. He is an IEEE Fellow and an IEEE Distinguished
IEEE Distinguished Lecturer for the Electron Devices Society and Lecturer. He is a recipient of the ECE Reader Award (2008), the
served as IEEE Distinguished Lecturer for the Solid-State Circuits Hearst Semiconductor Applications Award (2008), and the EDN
Society. He currently serves as Vice President for IEEE Electron Innovation Award (2009).
Devices Society. He is committee member for the SIA International
Technology Roadmap for Semiconductor (ITRS), the IEEE EDS VLSI
Technology and Circuits Committee and the IEEE CAS Analog Signal
Processing Technical Committee. He has been serving as Program co-
Chair, Organization co-Chair, Steering Committee Member, TPC
Member, Subcommittee Chair and Session Chair for numerous IEEE
conferences. He speaks frequently at various industrial/academic/
international forums and is a frequent consultant to the IC industry. He
is elected as Fellow of IEEE for contributions to design-for-reliability
and system-on-chip.

Bin Zhao received the B.S.E.E.

degree from Tsinghua Univer-
sity, Beijing, China, in 1985,
and the M.S. and the Ph.D.
degrees from the California
Institute of Technology, Pasa-
dena, CA, in 1988 and 1993,
respectively. He has been with
SEMATECH, Austin, TX,
Rockwell International Corpo-
ration, Newport Beach, CA,
Conexant Systems, Newport
Beach, CA, Skyworks Solu-
tions, Irvine, CA, and Freescale
Semiconductor, Irvine, CA. His
past work and experience have been involved with both VLSI tech-
nology development and analog/mixed-signal/RF IC design. In 1997,

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