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Experiment 2

The document details Experiment 2 conducted by Kanishk Devatwal in February 2025, focusing on obtaining Q values through MATLAB and performing fixed-point operations using Verilog. It describes the generation of signal data, conversion to Q format, and the implementation of addition, subtraction, and multiplication operations in Verilog. Finally, it mentions comparing the results from MATLAB and Verilog to validate the outcomes.

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3 views4 pages

Experiment 2

The document details Experiment 2 conducted by Kanishk Devatwal in February 2025, focusing on obtaining Q values through MATLAB and performing fixed-point operations using Verilog. It describes the generation of signal data, conversion to Q format, and the implementation of addition, subtraction, and multiplication operations in Verilog. Finally, it mentions comparing the results from MATLAB and Verilog to validate the outcomes.

Uploaded by

kanishkdevatwal123
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Experiment 2

Kanishk Devatwal
February 2025

1 Introduction
Getting Q values

From the previous experiment we took the Q(2,14) and Q(4,12) represented
values.
We got 240 samples of data using the given matlab code:
% Signal parameters
f = 1000;
Fs = 4 8 0 0 0 ;
cycles = 5;
samples per cycle = 48;

% Generate time v e c t o r f o r e x a c t l y 5 c y c l e s
num samples = c y c l e s ∗ s a m p l e s p e r c y c l e ;
t = l i n s p a c e ( 0 , c y c l e s / f , num samples ) ;

% Generate t h e s i g n a l
xt = 2 ∗ s i n ( 2 ∗ p i ∗ f ∗ t ) ;

% Convert t o Q( 2 , 1 4 ) format
operand1 = round ( xt ∗ 2 ˆ 1 4 ) / 2 ˆ 1 4 ;

% Convert t o Q( 4 , 1 2 ) format
operand2 = round ( xt ∗ 2 ˆ 1 2 ) / 2 ˆ 1 2 ;

% Save operand1 and operand2 a s row−w i s e t e x t f i l e s


w r i t e m a t r i x ( operand1 ’ , ’ operand1 . txt ’ , ’ D e l i m i t e r ’ , ’ space ’ ) ;
w r i t e m a t r i x ( operand2 ’ , ’ operand2 . txt ’ , ’ D e l i m i t e r ’ , ’ space ’ ) ;
We saved them in 2 files respectively as operand1.txt and operand2.txt.
Fixed Point operation using Verilog code:
We use the above text files as input for our verilog code which add, substract
and multiply the values of text files.
Verilog Code:

1
‘ t i m e s c a l e 1 ns /1 ps
module f i x e d p o i n t o p e r a t i o n s t e s t ;

parameter SIZE = 2 4 0 ; // Adjust t h i s t o match t h e s i z e o f your operand f i l e s

// D e c l a r e a r r a y s f o r o p e r a n d s
r e g s i g n e d [ 1 5 : 0 ] operand1 [ 0 : SIZE − 1 ] ; // Q( 2 , 1 4 )
r e g s i g n e d [ 1 5 : 0 ] operand2 [ 0 : SIZE − 1 ] ; // Q( 4 , 1 2 )

// R e s u l t a r r a y s i n Q( 2 , 1 4 )
reg signed [ 1 5 : 0 ] a d d r e s u l t [ 0 : SIZE − 1 ] ;
reg signed [ 1 5 : 0 ] s u b r e s u l t [ 0 : SIZE − 1 ] ;
reg signed [ 1 5 : 0 ] m u l t r e s u l t [ 0 : SIZE − 1 ] ;

// Temporary r e g i s t e r f o r m u l t i p l i c a t i o n ( w i d e r than 16 b i t s )
r e g s i g n e d [ 3 1 : 0 ] mult temp ;

integer i , ret ;
integer op1 file , op2 file , add file , sub file , mult file ;
real r value ;

// D e c l a r e o p e r a n d 2 s c a l e d o u t s i d e t h e f o r l o o p
reg signed [ 1 5 : 0 ] operand2 scaled ;

i n i t i a l begin
// Open and r e a d operand1 . t x t (Q( 2 , 1 4 ) )
o p 1 f i l e = $ f o p e n ( ” operand1 . t x t ” , ” r ” ) ;
i f ( o p 1 f i l e == 0 ) b e g i n
$ d i s p l a y ( ”ERROR: Could not open operand1 . t x t ” ) ;
$finish ;
end

f o r ( i = 0 ; i < SIZE ; i = i + 1 ) b e g i n
r e t = $ f s c a n f ( o p 1 f i l e , ”% f \n ” , r v a l u e ) ;
operand1 [ i ] = $ r t o i ( r v a l u e ∗ 1 6 3 8 4 . 0 ) ; // Convert t o Q( 2 , 1 4 )
end
$fclose ( op1 file );

// Open and r e a d operand2 . t x t (Q( 4 , 1 2 ) )


o p 2 f i l e = $ f o p e n ( ” operand2 . t x t ” , ” r ” ) ;
i f ( o p 2 f i l e == 0 ) b e g i n
$ d i s p l a y ( ”ERROR: Could not open operand2 . t x t ” ) ;
$finish ;
end

2
f o r ( i = 0 ; i < SIZE ; i = i + 1 ) b e g i n
r e t = $ f s c a n f ( o p 2 f i l e , ”% f \n ” , r v a l u e ) ;
operand2 [ i ] = $ r t o i ( r v a l u e ∗ 4 0 9 6 . 0 ) ; // Convert t o Q( 4 , 1 2 )
end
$fclose ( op2 file );

// Perform f i x e d −p o i n t o p e r a t i o n s
f o r ( i = 0 ; i < SIZE ; i = i + 1 ) b e g i n
// S c a l e operand2 from Q( 4 , 1 2 ) t o Q( 2 , 1 4 ) by m u l t i p l y i n g by 4 ( l e f t −s h i f t
o p e r a n d 2 s c a l e d = operand2 [ i ] <<< 2 ; // S c a l e operand2 [ i ]

// A d d i t i o n i n Q( 2 , 1 4 )
a d d r e s u l t [ i ] = operand1 [ i ] + o p e r a n d 2 s c a l e d ;

// S u b t r a c t i o n i n Q( 2 , 1 4 )
s u b r e s u l t [ i ] = operand1 [ i ] − o p e r a n d 2 s c a l e d ;

// M u l t i p l i c a t i o n :
// Raw r e s u l t i s i n Q( 6 , 2 6 ) , s h i f t r i g h t by 12 b i t s t o b r i n g i t back t o Q
mult temp = operand1 [ i ] ∗ operand2 [ i ] ;
m u l t r e s u l t [ i ] = ( mult temp + ( 1 << 1 1 ) ) >>> 1 2 ; // Add r o u n d i n g b e f o r e
end

// Write r e s u l t s t o output f i l e s
a d d f i l e = $ f o p e n ( ” a d d r e s u l t s . t x t ” , ”w” ) ;
s u b f i l e = $ f o p e n ( ” s u b r e s u l t s . t x t ” , ”w” ) ;
m u l t f i l e = $ f o p e n ( ” m u l t r e s u l t s . t x t ” , ”w” ) ;

f o r ( i = 0 ; i < SIZE ; i = i + 1) begin


$fdisplay ( add file , ”% f ” , a d d r e s u l t [ i ] / 1 6 3 8 4 . 0 ) ; // Convert back t o f
$fdisplay ( sub file , ”% f ” , s u b r e s u l t [ i ] / 1 6 3 8 4 . 0 ) ; // Convert back t o f
$fdisplay ( mult file , ”% f ” , m u l t r e s u l t [ i ] / 1 6 3 8 4 . 0 ) ; // Convert back t o
end

$fclose ( add file );


$fclose ( sub file );
$fclose ( mult file );

$ d i s p l a y ( ” Fixed−p o i n t o p e r a t i o n s c o m p l e t e . R e s u l t s saved . ” ) ;
$finish ;
end

endmodule
Ploting of Matlab results and verilog code
We got output add, sub, multi files now we take these files as input for out

3
Figure 1: Matlab result vs Verilog result

matlab code which make operations in matlab than we compare the results of
matlab operations and the verilog output.

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