XILINX VIRTEX

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VIRTEX

Virtex is the family of FPGA products developed by Xilinx, a part

of Advanced Micro Devices (AMD).

Other current product lines include Kintex (mid-range) and Artix

(low-cost), each including configurations and models optimized for
different applications

Virtex FPGAs are typically programmed in hardware description

languages such as VHDL or Verilog, using the Xilinx ISE or Vivado Design
Suite computer software.
 Features of XILINX VIRTEX
1. Fast, high-density Field-Programmable Gate Arrays - Densities from 50k to 1M system gates –
2. High System performance
3. Multi-standard Select IO interfaces - 16 high-performance interface standards
4. Built-in clock-management circuitry - Four dedicated delay-locked loops (DLLs
5. Hierarchical memory system
6. LUTs configurable as 16-bit RAM, 32-bit RAM, 16-bit dual-ported RAM
7. Flexible architecture that balances speed and density
8. Dedicated carry logic for high-speed arithmetic
9. Dedicated multiplier support
10. Abundant registers/latches with clock enable
11. boundary-scan logic
12. SRAM-based in-system configuration
13. Unlimited re-programmability
14. 0.22 mm 5-layer metal process
VIRTEX
Virtex FPGA Architecture
❑ IOBs - Input/Output Blocks
❑ CLBs - Configurable Logic Blocks
❑ BRAMs - Block SelectRAM
❑ DLLs - Delay-Locked Loops
❑ VersaRing - I/O interface routing resources

The CLBs are arranged in a rectangular

matrix.
The CLBs are surrounded by IO-Blocks
which are configurable drivers or input
buffers for IO-Signals. For the efficient
implementation of RAM structures Virtex
The Virtex FPGA,comprises two major configurable elements:
CONFIGURABLE LOGIC BLOCKS (CLBS) • CLBs provide the functional elements for
constructing logic
INPUT/OUTPUT BLOCKS (IOBS). • IOBs provide the interface between the package pins
and the CLBs CLBs interconnect through a general routing matrix (GRM).

The GRM comprises an array of routing switches located at the intersections of horizontal and
vertical routing channels. Each CLB nests into a VersaBlock that also provides local routing
resources to connect the CLB to the GRM.
The VersaRing I/O interface provides additional routing resources around the periphery of the
device. This routing improves I/O routability and facilitates pin locking.
The Virtex architecture also includes the following circuits that connect to the GRM.
• Dedicated block memories of 4096 bits each
• Clock DLLs for clock-distribution delay compensation and clock domain control
• 3-State buffers (BUFTs) associated with each CLB
Xilinx Virtex FPGA
• Logic configured by values stored in
SRAM cells

• CLBs implement logic in SRAM-stored

truth tables

• CLBs use SRAM-controlled multiplexers

• Routing uses “pass” transistors for

making/breaking connections
between wire segments
Xilinx Virtex CLB
The basic building block
of the Virtex CLB is the
logic cell (LC).

An LC includes a 4-input
function generator[LUT]
,carry logic, and a
storage element.

The output from the

function generator in
each LC drives both the
CLB output and the D
input of the flip-flop.

Each Virtex CLB contains

four LCs, organized in two
similar slices
Detailed view of virtex slice
Virtex function generators are implemented as 4-input
look-up tables (LUTs)
Storage Elements

The storage elements in the Virtex slice are edge-triggered

D-type flip-flops or level-sensitive latches.
In addition to Clock and Clock Enable signals, each Slice has
synchronous set and reset signals
Multiplexers
 Arithmetic Logic
Dedicated carry logic provides fast arithmetic carry capability for high-speed
arithmetic functions.
The Virtex CLB supports two separate carry chains, one per Slice. The arithmetic
logic includes an XOR gate that allows a 1-bit full adder to be implemented within
a LogicCell. In addition, a dedicated AND gate improves the efficiency of
multiplier implementation
Some arithmetic resources like adders,counters,multipliers are required because
special circuitry to speed up arithmetic operations.
• Dedicated carry logic/xor

BUFTs
Each Virtex CLB contains two 3-state drivers (BUFTs) that can drive on-chip busses.
 Block Select RAM
Why RAM?
• To store any intermediate data in an
application.

Virtex FPGAs incorporate several large Block

Select RAM memories.

Block Select RAM memory blocks are

organized in columns.

All Virtex devices contain two such columns,

one along each vertical edge. These
columns extend the full height of the chip.
Each memory block is four CLBs high, and
consequently, a Virtex device 64 CLBs high
contains 16 memory blocks per column, and
a total of 32 blocks.
What is IOB in FPGA?

The input/output block (IOB) is used for communication

between the problem program and the system.

Programmable routing How this programmable routing

takes place? • Adjacent to each CLB stands a
General Routing Matrix(GRM). • GRM is nothing but
switch matrix which get resources from
CLBs,RAM,Multipliers
 Architecture of Virtex IOB
Iobs (I/O blocks), one per user I/O pin,
containing:
Differential input buffer
Tristate output buffer

Configurable pull-up, pull-down, or keeper

circuit [An optional weak-keeper circuit is
connected to each output. When selected,
the circuit monitors the voltage on the pad
and weakly drives the pin High or Low to
match the input signal.
Three flip-flops (for input, output, tristate enable),
Dlls (delay-locked loops for phase-shift
incoming clock signals)
A buffer in the virtex IOB input path routes the
input signal either directly to internal logic or
through an optional input flip-flop.
The output path includes a 3-state output
buffer that drives the output signal onto the
pad.
All pads are protected against damage from
over-voltage transients
 The IOBS are grouped into 8 I/O
banks[bank 0 to bank 7] (2 for each
edge of the device), with each bank
having a separate power supply.

4 global clock buffers

All virtex IOBs support IEEE

1149.1-compatible boundary scan
testing.

Note: Boundary scan is a method for testing

interconnects (wire lines) on printed circuit
boards or sub-blocks inside an integrated
circuit. Boundary scan is also widely used as
a debugging method to watch integrated
circuit pin states, measure voltage, or
analyze sub-blocks inside an integrated
circuit.
 1.Local Routing
VIRTEX Routing
The VersaBlock provides local
routing resources provide the
following three types of
connections.

• Interconnections among the LUTs,

flip-flops, and GRM

• Internal CLB feedback paths that

provide high-speed connections to
LUTs within the same CLB,with
minimal routing delay

• Direct paths that provide

high-speed connections between
horizontally adjacent CLBs.
2. The general routing resources are located in horizontal and vertical
routing channels associated with the rows and columns CLBs.
3. I/O Routing: Virtex devices have additional routing resources around their
periphery that form an interface between the CLB array and the IOBs. This
additional routing, called the VersaRing, facilitates pin-swapping and
pin-locking
4. Dedicated Routing: Some classes of signal require dedicated routing resources
to maximize performance
Horizontal routing resources are provided for on-chip 3-state busses. Four partitionable bus
lines are provided per CLB row, permitting multiple busses within a row.
Two dedicated nets per CLB propagate carry signals vertically to the adjacent CLB
 Reference

Source -Slideplayer:Introduction To VIRTEX II Architecture Presented By: Ankur Agarwal.

Xilinx FPGA

Xilinx: Virtex 2.5 V Field Programmable Gate Arrays Data Sheet v2.5
© 2001 Xilinx, http://www.xilinx.com/legal.htm.
FIELD PROGRAMMABLE GATE ARRAYS:
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