MULTIPLEXER AND DEMULTIPLEXER

Ex.No,5

AIM:

To design and implement the multiplexer and demultiplexer using logic gates and
study of lC 74150 and IC 74154.

APPARATUS REQUIRED:

SL.NO. COMPONENT SPECIFICATION QTY.

3 L/P AND GATE IC 7411 2

2 OR GATE IC7432 1

3. NOT GATE IC 7404

2 IC TRAINER KIT

3 PATCH CORDS
2

THEORY:

MULTIPLEXER:
Multiplexer means transmitting a large number of information units over a smaller
number of channels or lines. A digital multiplexer is a combinational circuit that selects binary
information from one of many input lines and directs it to asingle output line. The selection of a
particular input line is controlled by a set of selection lines. Nomally thereare 2input line and n
selection lines whose bit combination determine which input isselected,

DEMULTIPLEXER:
The function of Demultiplexer is in contrast to multiplexer function. It takes information
from one line and di_tribute_ At to a given number of output lines. For this reason, the
demultiplexer is also known as a data distributor. Decoder can also be used as demultiplexer.
In the 1: 4 demultiplexer circuit, the data input line goes to allof the AND gates. The
data select lines enable only one gate at a time and the data on the data input line will pass
through the selected gate to the associated data output line.
 4:1 MULTIPLEXER

BLOCK DIAGRAM FOR 4:1

MULTIPLEXER:
DO
DATA WP D1 4x1 DATA oIP
D2 MUX
D3

S1 So
DATA SELECT

FUNCTION TABLE:
Si SO INPUTS Y
0 D0 ’ DOS1' S0
0 1 DI ’DI ST' S0
0 D2 ’ D2 SI SO
1 D3 ’ D3 SI SO

Y= DO S1' S0' + D1 S1' S0 + D2 S1 S0° + D3 S1 S0

TRUTH TABLE:

S1 SO Y= 0UTPUT

0 DQ

0 DI

1 D2

D3
CIRCUIT DIAGRAM FOR MULTIPLEXER:

DO D1 D2 D3

V404

74L511

432

74L31l

7432

74LS11

7432

74L511

14 DEMULTIPLEXER

BLOCK DIAGRAM FOR 1:4 DEMULTIPLEXER:

>DO
DATA WP 1x4
>D1 DATA OP
DEMUX >D2
> D3

S1 SO
DATA SELECT

FUNCTION TABLE:

S1 SO INPUT

X’ D0 = X S1' S0
0 X’ DI=XS1' SO
1 0 X’ D2=X S1 S0
X’ D3 =X S1 S0

Y- XS1' s0 + XS1' S0 + XS1 S0' + XS1 S0

 TRUTH TABLE:
INPUT
Si SO
OUTPUT
VP DO DI D2 D3
0
0 0
0 0
1 0 0

1
--e 0
1
0

0
0
0
0 0 0 0
0 0 1 0
0 0 0 0
1 1 0 0 0 1

LOGIC DIAGRAM FOR

DEMULTIPLEXER:
S1 SO I/P

/404 7404a

Do

74L11

D1

74L3l1

D2

74LS1i

D3

74LS1l
 PROCEDURE:
(i) Connections are given as per circuit diagram.
(ii) Logical inputs are given as per circuit diagram.
(iü) Observe the output and verify the truth table.

COLLECE
JAI SHRIRAM ENGINEERING
Descriplion Marks Mark Awarded
Design&Procedure 20 20
oo
|Experineniat Setug 30 30
Executlon and Results 40 37
Viva-Voce 10

Total
100 42

RESULT:

inolomöned suIRÄALIy .