Superlattices and Microstructures 102 (2017) 259e272

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Superlattices and Microstructures

journal homepage: www.elsevier.com/locate/superlattices

Modeling and analysis of sub-surface leakage current in

nano-MOSFET under cutoff regime
Yashu Swami*, Sanjeev Rai
Department of ECE, MNNIT Allahabad, Allahabad, 211004, India

a r t i c l e i n f o a b s t r a c t

Article history: The high leakage current in nano-meter regimes is becoming a significant portion of power
Received 19 December 2016 dissipation in nano-MOSFET circuits as threshold voltage, channel length, and gate oxide
Accepted 20 December 2016 thickness are scaled down to nano-meter range. Precise leakage current valuation and
Available online 23 December 2016
meticulous modeling of the same at nano-meter technology scale is an increasingly a
critical work in designing the low power nano-MOSFET circuits. We present a specific
Keywords:
compact model for sub-threshold regime leakage current in bulk driven nano-MOSFETs.
Leakage current
The proposed logical model is instigated and executed into the latest updated PTM bulk
Sub-surface current
Tunneling
nano-MOSFET model and is found to be in decent accord with technology-CAD simulation
Nano-MOSFET data. This paper also reviews various transistor intrinsic leakage mechanisms for nano-
Modeling MOSFET exclusively in weak inversion, like drain-induced barricade lowering (DIBL),
Short channel effects gate-induced drain leakage (GIDL), gate oxide tunneling (GOT) leakage etc. The root cause
Sub-threshold region of the sub-surface leakage current is mainly due to the nano-scale short channel length
causing sourceedrain coupling even in sub-threshold domain. Consequences leading to
carriers triumphing the barricade between the source and drain. The enhanced model
effectively considers the following parameter dependence in the account for better-quality
value-added results like drain-to-source bias (VDS), gate-to-source bias (VGS), channel
length (LG), source/drain junction depth (Xj), bulk doping concentration (NBULK), and
operating temperature (Top).
© 2016 Elsevier Ltd. All rights reserved.

1. Introduction

The high leakage current in nano-meter regimes is becoming a significant portion of power dissipation in CMOS circuits as
threshold voltage, channel length, and gate oxide thickness are scaled. Consequently, the scrutiny and analysis of different
leakage components is very important for estimation and reduction of leakage. Moreover, the increasing statistical variation
in the process parameters has led to significant deviations in the transistor leakage current across and within different dies.
Designing with the worst case leakage may cause excessive guard-banding, resulting in an inferior performance. This paper
explores various intrinsic leakage mechanisms including weak inversion, gate-oxide tunneling and junction leakage etc.
Different types of leakage currents existing in bulk nano-MOSFETs can be listed as gate-induced drain leakage (GIDL) current,
drain-to-body junction leakage, source-to-body junction leakage currents, and gate leakage current. GIDL is modeled by using
band-to-band tunneling (BTBT) model, and it can be reduced by introducing lightly doped drain (LDD) structure to lower the

* Corresponding author.
E-mail addresses: yashuswami@hotmail.com (Y. Swami), srai@mnnit.ac.in (S. Rai).

http://dx.doi.org/10.1016/j.spmi.2016.12.044
0749-6036/© 2016 Elsevier Ltd. All rights reserved.
260 Y. Swami, S. Rai / Superlattices and Microstructures 102 (2017) 259e272

electric field. All leakage currents in the nano-MOSFETs have been successfully modeled and are available in the latest
updated PTM bulk nano-MOSFET model [1e4].
At nano level technology node, it is also significant to consider the leakage track between the source-drain junctions
underneath the channel, leading to punch through consequence. This effect considering at nano-scale technology, has not
received much attention in the literature from the precise modeling point of view. Although the heavily doped bulk and halo
implantation can overwhelm the punch through effect, they may result in significant band-to-band tunneling (BTBT) leakage
current through drain/source-body junction. Additionally, even though there is a parasitic bipolar-junction transistor (BJT)
formed comprising source-body-drain as emitter-base-collector in the nano-MOSFET transistor, it will not be sensible to
characterize this off-state leakage current to BJT current, because body-source (base-emitter) junction is not forward biased.
Thus, it is vital to have a flawless perception into the physics of off-state leakage current via the path underneath the channel
and the corresponding model. In this research work, we put forward a compact model to define the sub-surface leakage
current by considering drain-to-source bias (VDS), gate-to-source bias (VGS), Channel Length (LG), source/drain junction depth
(Xj), bulk doping concentration (NBULK), and operating temperature (Top) into account for the nano-MOSFET transistor. The
essence of the sub-surface leakage current is that the barricade height between the source and the drain is depressed largely
by VDS, instigating electrons transport across the barricade. The proposed model built into the latest updated PTM bulk nano-
MOSFET model unveils a decent match with technology computer-aided design (TCAD) simulation data [5e8].
Rest of the paper is organized as follows. Section 2 discusses various leakage current avenues in nano-MOSFET transistor.
Section 3 elaborates the dynamics and physics of the sub-surface leakage current. The key factors affecting the sub-surface
leakage current are deeply studied and methodically the analytical model of this leakage current is derived in this section.
Reduction methodologies of the sub-surface leakage are briefly conferred in section 4. The outcomes of the proposed model
are presented in section 5. The section also discusses the results assimilated in the latest updated PTM bulk nano-MOSFET
model by comparing it with TCAD simulations. Finally, concluding remarks are conferred in section 6.

2. Leakage current avenues in nano-MOSFET transistor

As we already know, leakage current in nano-meter regimes has become an exceptionally substantial contributor to power
dissipation of nano-CMOS circuits as the threshold voltage (VTH), gate oxide thickness (Tox), source/drain junction depth (Xj),
channel length (LG) etc. are scaled down with the nano-meter technology node rigorous demanding scaling. Subsequently, the
recognition, exposure, and modeling of diverse leakage mechanisms is particularly vital for assessment and reduction of
leakage power, specifically for low-power applications. Practically stating, the nano-MOSFET delay times decrease by more
than 30% per technology generation, subsequently resulting in doubling of the integrated circuit performance every two
years. The threshold voltage scaling results in considerable upsurge of the sub-surface leakage current. Ioff in nano-MOSFET is
influenced by many transistor parameters like the threshold voltage, channel physical dimensions, channel/surface doping
profile, drain/source junction depth, gate oxide thickness, and VDD. However, Ioff in long-channel devices is dominated by
leakage from the drain-well and well-substrate reverse-bias pn junctions [8e12].
As the drain bias increases, the drain to channel depletion region enlarges, instigating a significant upsurge in the drain
current. This escalation in Ioff is typically due to channel surface current initiated by drain-induced barricade lowering (DIBL)
or due to deep channel punch through currents. All these contrary effects which cause threshold voltage reduction and in-
crease in leakage current in nano-scale devices are entitled under the category of short-channel effects (SCE).
Major contributors to the nano-MOSFET transistor leakage currents are Off-State leakage, gate oxide tunneling (GOT)
leakage and Junction leakage. Injection of hot carriers (HCI) leakage from bulk to the gate oxide and Gate-induced drain
leakage (GIDL) are another significant leakage mechanism at nano scale. We would be emphasizing more on the off-state
leakage to instigate the sub-surface leakage current modeling prominent in cutoff/sub-threshold/weak inversion operating
region.

2.1. Junction tunneling leakage current

Drain to bulk and source to bulk characteristically act as reverse biased PN junctions causing the leakage current, directly
proportional to the doping concentration and the source/drain junction area. Briefly explaining, the junction leakage befalls
through Trap-Assisted Tunneling and Band-to-Band Tunneling mechanism. The BTBT operation occurs due to the minority
carrier diffusion/drift near the edge of the depletion region; Trap-Assisted Tunneling occur due to electron-hole pair gen-
eration in the depletion region of the reverse-biased junction. For a nano-MOSFET transistor, additional leakage can occur
between the drain and well junction from gated diode device action (overlap of the gate to the drain-well pn junctions) or
carrier generation in drain to well depletion regions with influence of the gate on these current components [3]. Fig. 1 shows
the junction tunneling leakage current for various sub-45 nm technologies. We can conclude form the plot that the junction
tunneling leakage is inversely proportional to technology node (channel length). However the gradient on log scale for
various sub-45 nm technologies is nearly equal, representing the leakage appraise rate is closely constant for these nano
technologies.
Due to nano scale channel length, high electric field exist along the channel in lateral direction in nano-MOSFET transistors
[4]. This causes significant current to flow through the junction due to tunneling of electrons from the valence band of the p
region to the conduction band of the n region in shrill curved bandgap, as shown in Fig. 2. The physics behind the BTBT logic is
 Y. Swami, S. Rai / Superlattices and Microstructures 102 (2017) 259e272 261

Fig. 1. Junction tunneling leakage current.

Fig. 2. BTBT leakage mechanism.

that the leakage current flows as total voltage drop across the junction escalates more than the band gap. In other words, at
adequate gate bias, BTBT leakage occurs when the conduction-band of the intrinsic region aligns with the valence-band of the
p-type region (Bulk). Electrons from the valence band of the p-type region tunnel through the conduction band of the
intrinsic region. High doping concentrations and abrupt doping profiles cause significant BTBT current leakage through the
drain-well junction in nano scale devices [5]. Fig. 3 characterizes the energy band diagram of 10 nm technology node n-type
nano-MOSFET.

2.2. Gate-induced drain leakage (GIDL) current

As described earlier, high lateral electric field exist along the channel in nano-MOSFET transistor. GIDL is another
consequence due to this high field effect in the drain junction. As the gate terminal is negatively/weakly biased to force
transistor operate in accumulation/cut-off state, the channel region behaves like a p-region more heavily doped than the bulk,
resulting in the formation of a thin depletion layer at the surface. When gate is at zero or negatively biased and drain terminal
connected to high voltage, results in dramatic increase of effect like avalanche multiplication and BTBT. The narrow depletion
layer passage underneath the gate oxide causes the minority carriers to bombard the drain region causing the GIDL current.
Thinner oxide and higher drain-to-gate bias (VDG) enhance the GIDL effect. High and abrupt drain region doping has adverse
effect on GIDL.

2.3. Hot carrier injection (HCI) leakage current

In nano-MOSFET transistor, the Hot Carrier Injection (HCI) leakage current flowing from Bulk to Gate Oxide also signifi-
cantly contribute to the static power dissipation. Along with the existence of strong lateral electrical field, high vertical
electric field also exist near the (bulk-oxide) Semiconductor/dielectric surface interface [6]. The carriers gain sufficient energy
from the strong electric field to cross the interface potential barricade and enter into the oxide layer. This Short channel effect
is known as hot-carrier injection (HCI Effect). The HCI Leakage current is enhanced by thin oxide layer and strong gate bias.
262 Y. Swami, S. Rai / Superlattices and Microstructures 102 (2017) 259e272

0.4 GATE
SOURCE DRAIN
0.2
0.0 CONDUCTION
for VDS=0.1V
BAND
-0.2 for VDS=0.3V

Energy Band Levels (eV)

-0.4 for VDS=0.5V
-0.6 for VDS=0.7V
-0.8 for VDS=0.9V
-1.0 VALENCE
for VDS=0.1V
-1.2 BAND
for VDS=0.3V
-1.4
for VDS=0.5V
-1.6
for VDS=0.7V
-1.8
for VDS=0.9V
-2.0
-2.2 X-Axis along the Channel Length (um)
0.000 0.005 0.010 0.015 0.020 0.025 0.030

Fig. 3. Energy Band Diagram of nano-MOSFET (Lg ¼ 10 nm).

Fig. 4. HCI leakage current density.

The HCI effect is more prominent in n-type nano-MOSFETs as the electrons have a lower effective mass than that of holes. Low
barricade height of electrons than holes also enhances the HCI effect in n-channel nano-MOSFETs. Fig. 4 signifies the HCI
Leakage current density variation with the change in technology node [9].

2.4. Gate oxide tunneling (GOT) leakage current

In the present day technology, the gate oxide thickness in nano-MOSFETs has been reduced below 1 nm as per the ITRS
roadmap. Fig. 5 exemplifies that the GOT leakage increases with the gate bias. It clearly illustrates that the GOT leakage is
contrary to higher nano technologies (larger channel lengths). Reduction of gate oxide thickness (Tox) results in high vertical
electric field across the oxide. The strong electric field coupled with low oxide thickness results in tunneling of the carriers
from bulk to gate and also from gate to bulk through the gate oxide, resulting in the gate oxide tunneling (GOT) leakage
current. Briefly describing the two different types of tunneling phenomenon contributing in GOT Leakage Current [13].

a) FowlereNordheim Tunneling: In FN tunneling, the carriers tunnel from the inverted silicon surface into the conduction
band of the oxide layer.
b) Direct Tunneling: In direct tunneling, the electrons from the inverted silicon surface, instead of tunneling into the con-
duction band of the oxide layer, directly tunnel to the gate region through the forbidden energy gap of the oxide layer.

2.5. Channel punch through leakage current

In nano-MOSFET transistors, due to the nano-scale channel length, the proximity of the drain and the source junction is
observed. The depletion regions at the drain-bulk junction and the source-bulk junction extend into the channel region.
 Y. Swami, S. Rai / Superlattices and Microstructures 102 (2017) 259e272 263

Fig. 5. Gate oxide tunneling leakage current.

Increase in the drain bias pushes the depletion regions nearer to each other, further leading to the merging of the depletion
regions. This state is of the source/drain depletion region mergence is termed as punch through. This SCE is an extreme case of
channel length modulation and barrier lowering where the depletion layers around the drain and source regions merge into a
single depletion region causing the electron flow from source to drain either along the surface referred as surface punch
through or in the bulk referred as bulk punch through. The field underneath the gate becomes strongly dependent on the
drain-source bias causing high drain current leakage and gate losing the control of the current flow. Punch through causes a
rapidly increasing current with increasing drain-source bias (VDS) with nano-MOSFET operating even in sub-threshold
domain. The factors like short channel length, strong source/drain doping profile, high drain bias enhances the probability
of punch through. However, the junction width asset of nano-MOSFET depresses punch through [14]. Fig. 6 exhibits the
electron concentration contour plots of n-type nano-MOSFETs at zero biased initial condition (VDS¼VGS¼0 V) for various sub
45 nm technologies.

2.6. Off-state leakage current

Off-state leakage/sub-threshold leakage or weak-inversion conduction current in a nano-MOSFET transistor flows between
source and drain terminals even when gate bias is below the threshold voltage (VTH). This leakage current is generally viewed
as a parasitic leakage in a state that would ideally have no current in digital circuits. However, on the other hand, in analog
circuits, weak inversion/cut-off region is an efficient effective operating domain, and is a useful transistor operation mode
around which circuit functions are designed [15].
Contemplating the present day nano-meter technology node scaling, the sub-threshold leakage may exceed 50% of the
total power consumption. The existing models of sub-threshold leakage fail to fully justify the outputs of nano-MOSFET
transistors considering the latest updated PTM bulk nano-MOSFET model and TCAD simulation results. Hence, it is very
necessary to study the physics of sub-threshold leakage to develop a successful model for the same. In Next section, we deeply
study the logic and causes of the off-state leakage current for effective efficient compact modeling for the considered bulk
nano-MOSFET transistor.

Fig. 6. Electron Concentration contour plots of n-type nano-MOSFETs at zero biased initial condition (VDS¼VGS¼0 V) for various sub 45 nm technologies. X-axis
along the channel length in nm. S, G, D denoting Soutce Gate Drain terminals respectively.
264 Y. Swami, S. Rai / Superlattices and Microstructures 102 (2017) 259e272

3. Dynamics of the proposed model

The model device considered for simulation is a simplified square sized n-channel bulk nano-MOSFET structure simulated
in Silvaco TCAD with Channel Length (LG) ¼ 10 nm, gate oxide thickness (Tox) ¼ 1 nm, Bulk Doping Concentration
(NBULK) ¼ 1017 cm3, Junction depth (Xj) ¼ 8 nm. We consider uniform bulk doping throughout for simplification in TCAD
simulations. The peak value of Gaussian doping profile of source and drain considered is 1020 cm3, while that of source and
drain extension is 1019 cm3 in order to diminish the GIDL effect. Both the S/D extensions extend 2 nm under the gate
(underlap), creating a low-resistive contact between the channel and S/D junction. All the other parameters are kept constant
as a function of channel length scaling (EOT ¼ 1 nm, NBULK ¼ 1017cm3). The physical models used for extracting flawless
simulation results include doping-dependent mobility with high-field saturation and degradation, Quantization and Hot
Carrier Injection models, Shockley-Read-Hall & Tunneling models along with analytical model for efficacious temperature
dependent extractions. The model device is characterized at a supply voltage of VDD ¼ 0.9 V [15].
Fig. 7 shows the simulated transfer characteristics of n-channel nano-MOSFETs for different channel lengths at VDS ¼ 0.1 V.
It can be observed in log scale that there is an almost gate bias-independent leakage current in the cutoff/sub-threshold/weak
inversion operating region and depends more on the channel length as shown in Fig. 8. This sub-surface leakage current
cannot be explicated by GIDL, drain-to-body junction tunneling leakage, or parasitic BJT leakage current conception. As
clarified earlier, the GIDL current increases as the gate bias becomes more negative and it can be efficiently curbed by Lightly
Doped Drain (LDD) structure. Furthermore, the drain-to-body junction tunneling leakage in reverse bias is largely inde-
pendent of the channel length. Parasitic BJT current cannot be considered in this configuration since source-to-body p-n
junction is not forward biased. Consequently, it is strongly desired to develop a new innovative model that can successfully
infer this leakage current by considering the vital device parameters into account [16].

3.1. Drain-to-source bias (VDS) leverage

For a long-channel devices, the barricade height is largely controlled by the gate bias and is virtually insensitive to source/
drain bias. The source and drain terminals are detached far enough that their field patters existing between them and their
depletion regions have negligible effect on the channel of the device. Hence, for such devices, the leakage current is ideally
zero and effectively independent of the drain bias in cut-off state. However, in short-channel devices, the source and drain
depletion width in the vertical direction and the drain bias have a strong effect on leakage current. The influence of VDS on the
sub-surface leakage current in the cut-off state of nano-MOSFET is explored in this section.
Fig. 9 and Fig. 10 shows the contour plots of electron current concentration for the model devices with the channel lengths
of 10 nm, 16 nm, 22 nm, 32 nm and 45 nm with the set of values VGS ¼ 0 V, VDS ¼ 0 V and VGS ¼ 0 V, VDS ¼ 0.1 V respectively. It
should be remarkably observed in Fig. 10 that even at VGS ¼ 0 V, the electron current paths exists at a distance away from the
Si-SiO2 surface interface because of a small drain bias of 0.1 V. This leakage current is defined as sub-surface leakage current.
In the same bias conditions, 10 nm model device exhibits the maximum electron current concentration than the other model
devices with 45 nm model device unveils the minima as noticeably shown in Fig. 10. Hence we can accomplish that the sub-
surface leakage current is channel length-dependent. This can be directly attributed to the barricade lowering induced by the
drain bias (VDS), which is similar to drain-induced barricade lowering (DIBL) effect but at the different depths. For nano-
MOSFET transistors, even a small VDS can adequately decrease the barricade height between the source and the drain, so

Fig. 7. Transfer Characteristics of n-channel nano-MOSFETs at VDS ¼ 0.1 V.

 Y. Swami, S. Rai / Superlattices and Microstructures 102 (2017) 259e272 265

Fig. 8. Transfer Characteristics in sub-threshold domain on log scale at VDS ¼ 0.1 V.

Fig. 9. Electron Current Density Contour plots of n-type nano-MOSFETs for various sub 45 nm technologies operating in cutoff domain with VDS ¼ VGS¼0 V. X-axis
along the channel length in nm. S, G, D denoting Soutce Gate Drain terminals respectively.

that the electrons are able to triumph the barricade from the source side and the corresponding current will be similar to the
diode current form. Fig. 15 exhibits the conduction energy band diagram and the extracted barricade height lowering at the
local minimum of conduction energy band due to biased VDS of the device with LG ¼ 10 nm from the TCAD simulations. With
the similar TCAD simulations for distinct channel lengths, we imprecise the barricade alteration as a linear function for
elucidation.

DVBAR ¼ P1 $VDS (1)

where the dimensionless P1 is a fitting parameter defined as barricade-alteration coefficient that can be acquired from the
TCAD simulation data.

Fig. 10. Electron Current Density Contour plots of n-type nano-MOSFETs for various sub 45 nm technologies operating in cutoff domain with VDS ¼ 0.1 V and
VGS ¼ 0 V. X-axis along the channel length in nm. S, G, D denoting Soutce Gate Drain terminals respectively.
266 Y. Swami, S. Rai / Superlattices and Microstructures 102 (2017) 259e272

1E-4

Drain Current on log scale (A)

1E-5

VDS=0.1V
VDS=0.3V
1E-6
VDS=0.5V
VDS=0.7V
VDS=0.9V
1E-7
0.00 0.05 0.10 0.15 0.20 0.25 0.30
VGS (V)

Fig. 11. Sub-surface Leakage Current Transfer Characteristics in Sub-threshold Domain for various sub-45 nm technologies.

3.2. Channel length (LG) leverage

We consider the channel length-dependence of the sub-surface leakage current to be in exponential relationship
concluded from the analysis of Fig. 11, which displays that the slopes in a log scale for diverse VDS values are almost same in
sub-threshold domain. In addition, Fig. 12 illustrates that the drain current exponentially depends on VDS even in sub-
threshold domain, although the curves are marginally deviating from exponential conduct at high VDS due to nonlinear
barricade height lowering. The root-cause of this nonlinear outcome originates from the space-charge effect prejudiced by
the strong injection current, because the high velocity injected electrons can cross the electric field generated by the drain
terminal and hence discourages barricade height lowering. If the mobility is low enough to reduce the drift current across the
drain-to-body junction tunneling, the barricade height lowering will be much more linear, denoting that the injected elec-
trons actually are able to affect the electrostatics. Yet, the linear approximation is still espoused for simplification. Thus, the
sub-surface leakage current can be articulated as
0 1
B P1 VDS
C
ISUB ¼ P3 $eP2 LG @e VT
 1A$W (2)

where W is the channel width in units of m, VT is the thermal voltage (¼ kT/q), and P2 (m1) variable is called as inverse
characteristic length variable and P3 (A/m) variable is called as intrinsic leakage variable. It should be noted that (2) gua-
rantees that the leakage current must be zero when VDS ¼ 0. Furthermore, if LG is long enough to decouple the source and the
drain, the source current is much smaller than the drain current and, the drain current is almost independent of LG, meaning
that the junction tunneling leakage dominates the drain current for long channel devices. However, the source current was

0.00040 VGS=0.1V
0.00035 VGS=0.2V
VGS=0.3V
0.00030
Drain Current (A)

0.00025

0.00020

0.00015

0.00010

0.00005

0.00000

-0.00005
0.0 0.2 0.4 0.6 0.8 1.0
VDS (V)

Fig. 12. Sub-surface leakage current output characteristics in sub-threshold domain.

 Y. Swami, S. Rai / Superlattices and Microstructures 102 (2017) 259e272 267

just marginally lower than the drain current for all sub 45-nm model devices. Fig. 15 signifies the barricade height reduction
between source and drain due to the drain bias ensuing the upsurge of sub-surface leakage.

3.3. Source/drain junction depth (Xj) leverage

In long-channel MOSFETS, it is assumed the modifications of source/drain junction depth (Xj) are short enough partic-
ularly compared to the channel length (LG) to influence the device characteristics. The source/drain junction depths are
deeper than the MOSFET's gate depletion layer width. This supposition fails in short channel devices where Xj is shallower
than the gate depletion layer width. The influence of Xj on the sub-surface leakage current is explored in the sub-threshold
operating region of MOSFET in this section.
The 10 nm n-channel nano-MOSFET model device is considered for analysis. The source/drain junction depth of the model
device is varied from Xj ¼ 3 nm to Xj ¼ 15 nm, keeping all other physical parameters and limitations as constant. The sub-
surface leakage current is simulated in similar conditions for Xj at shallow junction limit (3 nm) to Xj at deep junction
limit (15 nm). We explored the sub-surface leakage current dependence on junction depth to be in exponential relationship
concluded from the analysis characterized Fig. 13. In addition, the influence of source/drain junction depth on sub-surface
leakage current is greater as Xj is greater than the gate depletion layer width. Hence sub-surface leakage is less in shallow
junction devices. We can express the relation as

ISUB f eP4 Xj (3)

1
where P4 (m ) variable is entitled as junction depth fitting variable. The value of P4 can be easily extracted from the output
characteristics of the device. Thus, the sub-surface leakage current can be further articulated as
0 1
 
B P1 VDS
C
ISUB ¼ P3 $ eP2 LG @e VT
 1A ep4 Xj $W (4)

It should be noted that (4) confirms that as the sub-surface leakage current exponentially increases with the junction
depth value. The slope of the logarithmic plot of the sub-surface leakage current characterized in Fig. 14 signifies the
statement. It should also be noted that the gradient of 10 nm technology node in the plot is excessive in comparison to other
sub 45 nm technologies. Hence we can conclude that the exponential increase of sub-surface leakage current is inversely
proportional to the technology node. In other words, the value of junction depth fitting variable P4 is smaller for larger
technology nodes.

3.4. Gate-to-source bias (VGS) leverage

As the gate bias sweeps from the cut-off domain to the transition point region (threshold voltage), the local minima of
conduction energy band declines further and moves toward the Si-SiO2 surface interface [16]. Figs. 11 and 12 demonstrates
that the leakage current is gate bias-dependent even in sub-threshold domain. Before the weak inversion layer is completely
formed, the gate field can pierce into the bulk, leading to VGS-dependent barricade height reduction. If the comprehensive
weak inversion layer is built, the gate electric field will be screened out by the previously accumulated holes, resulting in VGS-
independent behavior. Nevertheless, the VGS-dependent influence will no longer be noticeable when VGS is higher than the
threshold voltage (VTH). In other words, if the channel is inverted, the sub-surface leakage would mingle with the flow of

0.000025
Subsurface Leakage Current ISUB (A)

0.000020

0.000015

0.000010

0.000005

0.000000
Junction Depth Xj (nm)
2 4 6 8 10 12 14 16

Fig. 13. Sub-surface Leakage vs. Junction Depth (LG ¼ 10 nm, VGS ¼ 0 V and VDS ¼ 0.1 V).
268 Y. Swami, S. Rai / Superlattices and Microstructures 102 (2017) 259e272

1E-5 LG=10nm

LG=16nm
1E-6
LG=22nm
LG=32nm
1E-7 LG=45nm

ISUB on log scale (A)

1E-8

1E-9

1E-10

1E-11

0 5 10 15 20 25 30 35 40
Xj (nm)

Fig. 14. Sub-surface Leakage on log scale vs. Junction Depth for various sub-45 nm technologies (VGS ¼ 0 V, VDS ¼ 0.1 V).

normal transistor drain current and will become negligible, inconsequential and imperceptible [17]. Fig. 16 shows the
barricade height reduction due to gate bias (VGS). The barricade decline is expected to progressively saturate when VGS ap-
proaches or crosses the threshold voltage (VTH), where the band bending is for the formation of electron inversion layer. Gate
bias (VGS) influence is modeled on barricade height alteration (dj) as an exponential function inside the hyperbolic tangent
function.

dj ¼ P5 tanhðexpðP6 ðVGS  VTH ÞÞÞ (5)

where P5 and P6 in units of V and V1 are the VGS-associated fitting parameters. P5 and P6 fitting parameters can be extracted
from the TCAD data, as shown in Fig. 16 for diverse gate voltages below VTH. The threshold voltage (VTH) can be easily
calculated through the enhanced Constant Current Method (CCM) using transfer characteristics curve (Ref. Fig. 7). Therefore,
from (4), the sub-surface leakage current can be redrafted as
0 10 1
  dJ  
B CB P1 VDS
C
ISUB ¼ P3 eP2 LG @eVT A@e VT  1A ep4 Xj W (6)

3.5. Bulk doping leverage

As mentioned earlier, we consider uniform bulk doping NBULK for simplified TCAD simulation. It is apparent that in Fig. 17,
the sub-surface leakage current is inversely proportional to the bulk doping (NBULK). The conception can be justified as a
heavily doped bulk can diminish the depletion width of source-to-body and drain-to-body and, henceforth, coupling.

0.06 GATE
0.04

0.02
Barricade Potential (eV)

0.00

-0.02 SOURCE DRAIN

-0.04 for VDS=0V

-0.06

-0.08

-0.10

-0.12 for VDS=0.1V

-0.14 X-Axis along the Channel Length (um)
0.000 0.005 0.010 0.015 0.020 0.025 0.030

Fig. 15. Barricade Height Reduction due to Drain Bias (LG ¼ 10 nm).
 Y. Swami, S. Rai / Superlattices and Microstructures 102 (2017) 259e272 269

0.06

GATE
0.04

Barricade Potential (eV)

for VGS=0V

0.02

0.00 for VGS=0.1V

-0.02
SOURCE DRAIN
X-Axis along the Channel Length (um)
-0.04
0.000 0.005 0.010 0.015 0.020 0.025 0.030

Fig. 16. Barricade Height Reduction due to Gate Bias (LG ¼ 10 nm).

However, if NBULK is adequately high enough (for example, 1018 cm3), the GIDL current may overwhelm the sub-surface
leakage current in the drain current due to high electric field. Thus, we only plot the source currents in Fig. 17 in order to
get rid of the GIDL currents and get the factual characteristics of the sub-surface leakage current dependence on NBULK. On the
other hand, if the bulk doping (NBULK) is not fairly high (for example, 1016 cm3), based on Fig. 17, the leakage currents at
VGS ¼ 0 V are still linear but with diverse slopes in a log scale for altered NBULK values, which denotes that the doping effect can
be humbly modeled by letting the variables P2 and P3 be doping concentration-dependent with respect to 1023 (m3).
 E1
P2 ¼ P20 NBULK =
1023 (7)

  E1 
P3 ¼ P30 exp  NBULK =
1023 (8)

where NBULK is in units of m3, and P20, P30, and E1 are the fitting parameters. If the doping concentration between the source
and the drain is high enough to avoid coupling of the drain-to-body and source-to-body junction depletion regions, the sub-
surface leakage current can be obstructed by the barricade. Halo implantation and retrograde doping can restrain the leakage
current. It is worth noting that although the bulk doping profile in a real device is sophisticated so that the VDS dependence is
not significant, as shown in Fig. 11, the barricade alteration coefficient P1 can be set to a small value for matching the
experimental data [18].

3.6. Operating temperature leverage

In addition to bulk doping (NBULK), the model considers and appraise the operating temperature (Top) dependence in the
sub-surface leakage current. Due to larger number of energetic electrons at higher temperature surpassing the barricade, the
sub-surface leakage current would increase as the temperature escalates, as shown in Fig. 18. The illustration represents the
temperature effect on sub-surface leakage current for LG ¼ 10 nm model device at VGS ¼ 0 V for diverse operating temper-
atures. It can be perceived that the curves are linear functions but with diverse slopes in a log scale for varied temperatures
similar to bulk doping (NBULK) effect. Fitting parameter E2 is proposed to effectively model the operating temperature effect.
As a result, variables P2 and P3 can finally be expressed as
 E1  E2
P2 ¼ P20 NBULK =
1023 300
=Top (9)

  E1  E2 
P3 ¼ P30 $exp  NBULK =
1023 300
=Top (10)

where Top is in units of Kelvin. Hence From (4), we can represent the comprehensive form of sub-surface leakage current as
0 10 1
  dJ  
B CB P1$VDS=VT C
ISUB ¼ P3 ðNBULK ; TopÞ eP2 ðNBULK ;TopÞLG @eVT A@e  1A ep4 Xj W (11)
270 Y. Swami, S. Rai / Superlattices and Microstructures 102 (2017) 259e272

0.0000018
NBULK=1e16

Subsurface Leakage Current (A)

0.0000016
NBULK=5e16
0.0000014

0.0000012
NBULK=1e17

0.0000010
NBULK=5e17
0.0000008

0.0000006

0.0000004 NBULK=1e18
0.0000002
NBULK=5e18
0.0000000

-0.0000002
0.00 0.02 0.04 0.06 0.08 0.10

Drain Voltage VDS (V)

Fig. 17. Bulk Doping Effect on Sub-surface Leakage Current (LG ¼ 10 nm).

It is well elucidated in (11) that the sub-surface leakage current must be zero when VDS ¼ 0. However, with the escalation
in drain bias, the leakage exponentially upsurges. Furthermore, if the channel length (LG) is long enough to decouple the
source and drain domains, the leakage current exponentially declines. Threshold voltage value has contrary effect on the
leakage [19].

4. Sub-surface leakage current reduction techniques

Power dissipation has become the key consideration in the design of nano-scale CMOS circuits. Even for high performance
and device reliability, the reduction of leakage power is highly desirable especially for battery operated portable systems
which operate mostly in cutoff state for majority of their operating time. Various methodologies have been proposed for the
reduction of the sub-surface leakage current [3]. The predominant leakage current in off state at circuit level can be over-
whelmed by techniques like stacking of transistors, power gating, optimal body bias voltage generation etc. However, at
nano-level channel engineering, there are limited approaches to reduce the sub-surface leakage [12]. Few of the efficient
techniques are briefly explained.
Sub-surface leakage is vastly reliant on the drain bias in cutoff state. Keeping the source-drain bias at matching potential
while the device is in cutoff region will effectually diminish the sub-surface leakage current. As stated, sub-surface leakage
occurs even in sub-threshold domain at VGS ¼ 0 V (for n-type nano-MOSFET). However, reduction in the leakage is witnessed
as the gate terminal is negatively biased. This increases the control of the gate potential on the channel. Thus suppressing the
sub-surface leakage current. In other words, as the transistor is in sedentary state, we may push the transistor operate in
accumulation mode to reduce the sub-surface leakage [20].
Evidently known, sub-surface leakage is inversely proportional to the technology node. The leakage exponentially in-
creases with the decrement in the channel length. Hence if possible, operating at higher technology node will definitely
reduce the sub-surface leakage. In other words, increasing the channel length reduces the leakage. The leakage is nearly

T=400K
Subsurface Leakage Current (Log Scale)

1E-8
T=350K

1E-9
T=300K

1E-10

T=250K
1E-11

1E-12

T=200K
1E-13
Drain Voltage VDS (V)
0.00 0.02 0.04 0.06 0.08 0.10

Fig. 18. Temperature effect on Sub-surface Leakage Current (LG ¼ 10 nm).

 Y. Swami, S. Rai / Superlattices and Microstructures 102 (2017) 259e272 271

negligible above 70 nm technology node. Narrow channel width also diminishes the leakage as the channel width is directly
proportionate to leakage. Conjointly, we can accomplish that sub-surface leakage is inversely proportional to the device
aspect ratio. As depicted in the simulated statistics, the sub-surface leakage reduces as the bulk doping is elevated. The sub-
surface leakage current is inversely proportional to the bulk doping (NBULK). The conception can be justified as a heavily doped
bulk diminish the depletion width of source-to-body and drain-to-body and, henceforth, coupling between source to drain.
Biasing the bulk to lower voltage than ground (higher than VDD in PMOS) increases the threshold voltage. Hence subsequent
decrease of sub-surface leakage. The source and drain junction capacitances are also decreased to lower values. This method is
also called as reverse body bias (RBB) method. Reduction in the oxide thickness increases the gate control over the channel.
This will further result in the reduction of the sub-surface leakage. Source/Drain extensions (underlap) enhances the sub-
surface leakage as it lowers the barricade between the source and drain region. Hence lateral reduction in the source/
drain extension length will result in the suppression of sub-surface leakage. Super-steep Retrograde Wells, Halo Implanta-
tions and non-uniform channel doping profile in a lateral direction can also effectively reduce the sub-surface leakage. Multi-
gate FETs and Silicon-On-Insulator (SOI) FETs have also been developed to modulate the sub-surface current paths in an
effective manner [21].
Indubitably, all the above stated techniques would reduce the leakage but may also have severe effects on the output
characteristics and muddle the device properties.

5. Results and discussion

The sub-surface leakage current (11) model and associated parameters are assimilated in the updated latest PTM bulk
nano-MOSFET model. The comparison of the TCAD simulation data was performed with the SPICE simulation results for
different VDS values for n-channel nano-MOSFET with various channel length of sub-45 nm with the same set of fitting
parameters. The proposed model exhibits decent match with the TCAD simulation statistics. The VGS effect appears at around
flat-band voltage VFB and is effectively incorporated in respective model. Equation (11) efficiently models not only the
barricade lowering due to drain bias (VDS) but also the upsurge in the leakage current instigated by the escalating
temperature.
In the 10 nm model device, a sub-surface OFF-state leakage path was detected linking source and drain about 6 nm below
the Semiconductor/dielectric surface interface, whereas a clear sub-surface current path was visible at 8 nm below the gate
dielectric. Because this buried current path is relatively far from the gate, it cannot easily be curbed by the gate voltage. For
long channels, the source and drain are separated by an energy barricade of around 300e400 meV. Hence only few electrons
are able to overcome this energy barricade and consequently only a very small amount of current will flow from drain to
source i.e. IOFF would be low. Secondly, for long channel devices, the lowest energy path from source to drain is located at the
Semiconductor/dielectric surface interface. As a result, most of the IOFF current flows at this interface where it can be effi-
ciently curbed by the gate electrode. For small channel devices, the situation is different. Source and drain are no longer
separated by a large energy barricade. Instead a saddle point can be observed in the energy surface, several nm below the
Semiconductor/dielectric surface interface. As a result, more electrons will be able to overcome this smaller energy barricade,
resulting in a high current flow from drain to source i.e. IOFF would be rather larger. Secondly, the lowest energy path from
source to drain is located below the Semiconductor/dielectric surface interface, most of the current will follow this sub-
surface leakage path, where it cannot be efficiently curbed by the (more distant) gate electrode. Notably, the sub-surface
leakage path ultimately causes a sharp increase in Drain Induced Barrier Lowering (DIBL) and Subthreshold Slope (SS).
It is worth remarking that the impact of the source and drain junction depths (Xj) are also explicitly modeled in this paper.
As the junction depths are shallower in nano-MOSFET and shallow junction devices, the leakage pathway is considerable
nearer to the Semiconductor/dielectric surface interface. Hence, the leakage current is suppressed because of better gate
control. Sub-surface leakage current exponentially increases with the junction depth. Small gate oxide thickness enhances the
gate control thus resulting in suppression of leakage current. The junction depth effect can be extensively incorporated by
modifying the intrinsic leakage coefficient (P3) and barricade alteration coefficient (P1). Though, a shallow junction also
consequences in greater series resistance and therefore vitiate the device performance. Along with the junction depth (Xj), the
gate oxide thickness (Tox) also has an impact on the sub-surface leakage current. If the gate oxide is thicker, resulting in less
gate control, the sub-surface leakage current would be protuberant, since drain-to-body, source-to-body capacitance over-
whelms the gate capacitance. Similar to junction depth (Xj), the gate oxide effect can also be modeled accordingly by
regulating the barricade alteration coefficient (P1) and intrinsic leakage coefficient (P3) to appropriate values [10].

6. Conclusion

A sub-surface leakage current compact model is presented based on the analytical lucidities and TCAD simulation. The
sub-surface leakage current is normally caused by the barricade height decline between the source and the drain swayed by
the drain bias (VDS) at a distance from the Semiconductor/dielectric surface interface. The gate bias (VGS) also affects the
barricade height significantly near the flat band voltage (VFB). As the channel length is scaled down, the sub-surface leakage
current upsurges due to stronger drain-source coupling. The sub-surface leakage exponentially increases with the source/
drain junction depth (Xj). Hence, the leakage is less in shallow junction devices. Additionally, the bulk doping (NBULK) and
Operating Temperature (Top) are the vital factors affecting the sub-surface leakage current. As NBULK intensifies, the depletion
272 Y. Swami, S. Rai / Superlattices and Microstructures 102 (2017) 259e272

widths of junctions decrease and hence lower leakage current. As the Top escalates, more energetic electrons will surmount
the barricade, so the leakage current intensifies further. The above all consequences are effectively incorporated in the
proposed model. Finally, the presented model is instigated with the latest updated PTM bulk nano-MOSFET model. The
outcomes are in decent accord with the TCAD simulation results for diverse LG, VDS, NBULK, Xj and Top values.

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