Name: RITESH KUMAR SINHA

USN : 1KS21EC076
College Name: K S INSTITUTE OF TECHNOLOGY
Department: E&C
Date of Submission: 13/03/2025

Project: Design of an 8-bit Shift Register using verilog/system verilog/VHDL.

1. Introduction
This report presents the RTL design and functional verification of an 8-bit Shift Register using Verilog. The shifter is
capable of shifting an 8-bit input either to the left or right by a specified number of bits (N), based on control inputs.
The implementation was verified using EDA Playground and synthesized using FPGA/ASIC tools

Truth table of 8-Bit Shift Register

 2. Specifications
Inputs:
 clk: Clock Signal
 rst: Reset Signal (Active High)
 data_in (8-bit): Input Data
 shift_amount (3-bit): Shift Amount
 direction (1-bit): Shift Direction (0 for Left, 1 for Right)
Outputs:
 data_out (8-bit): Shifted Output
Control Signals:
 direction = 0: Shift Left
 direction = 1: Shift Right
Design Constraints:
 The design operates synchronously with the clock.
 The reset signal initializes the output to zero.

Block Diagram:
3. RTL Code
// Code your design here

module shifter_8bit(input clk,rst,

input[7:0] data_in,

input[2:0] shift_amount,

input direction,

output reg [7:0] data_out

);

always@(posedge clk)

begin

if(rst==1)

data_out <= 0;

else

if(direction==0)

data_out <= data_in << shift_amount;

else

data_out <= data_in >> shift_amount;

end

endmodule
4. Testbench Code

// Code your testbench here

// or browse Examples

module shift_tb;

reg clk,rst;

reg [7:0] data_in;

reg [2:0] shift_amount;

reg direction;

wire[7:0] data_out;

shifter_8bit uut (clk,rst,

data_in,

shift_amount,

direction,

data_out);

always #5 clk=~clk;

initial

begin

clk=1;

rst=1;

#10;

rst =0;

data_in = 8'b00110011;

shift_amount = 3'b010;

direction =0;//shift towards left

 #10;

$display("time=%0t: data_in=%b |shift_amount=%d |direction=%b ------- data_out=%b",$time,data_in,shift_amount,direction,data_out);

data_in= 8'b00110011;

shift_amount =3'b010;

direction =1;//shift towards right

#10;

$display("time=%0t: data_in=%b |shift_amount=%d |direction=%b ------- data_out=%b",$time,data_in,shift_amount,direction,data_out);

data_in= 8'b11010010;

shift_amount=3'b011;

direction = 0;//shift towards left

#10;

$display("time=%0t: data_in=%b |shift_amount=%d |direction=%b ------- data_out=%b",$time,data_in,shift_amount,direction,data_out);

data_in= 8'b11010010;

shift_amount=3'b011;

direction = 1;//shift towards right

#10;

$display("time=%0t: data_in=%b |shift_amount=%d |direction=%b ------- data_out=%b",$time,data_in,shift_amount,direction,data_out);

$finish;

end

initial
 begin

$dumpfile("dump.vcd");

$dumpvars;

end

endmodule
Simulation & Verification
Testbench Setup:
 Input values are provided for data_in, shift_amount, and direction.
 data_out is observed and compared with expected values.
 Multiple test cases are used to verify functionality.
Expected Output:
Input (data_in) Shift (shift_amount) Direction (direction) Output (data_out)
10101010 1 Left 01010100
10101010 2 Right 00101010
11001100 3 Left 01100000
11001100 4 Right 00001100

Simulated Input-Output Waveforms

The design was simulated in Aldec Riviera-PRO. The waveform confirmed correct sum
and carry-out values for different test cases.

5. Results and discussion

The 8-bit Shifter was successfully implemented and verified. The simulation results matched the expected behavior,
confirming the correctness of the design. The design was analyzed for power, area, and timing constraints, and it met
the required specifications.
Evaluation Criteria for Block-Level Verification in UVM

1. Testbench Architecture (50%)

● Proper use of UVM components

● Adherence to the UVM factory and configuration mechanism.
● Proper use of virtual sequences and sequence layering if applicable.

● Driver

class shifter_8bit_driver extends uvm_driver #(shifter_8bit_sequence_item);

`uvm_component_utils(shifter_8bit_driver)
virtual shifter_8bit_if vif;
shifter_8bit_sequence_item item;

function new(string name="shifter_8bit_driver",uvm_component parent);

super.new(name,parent);
`uvm_info("shifter_8bit_driver", "Inside constructor of shifter_8bit_driver", UVM_HIGH)

endfunction

function void build_phase(uvm_phase phase);

 super.build_phase(phase);
`uvm_info(get_name(), "Inside build phase", UVM_HIGH)

if(!(uvm_config_db #(virtual shifter_8bit_if)::get(this,"*","shifter_8bit_vif",vif)))

`uvm_error(get_name(), "Faild to get Virtual IF from database ........ ")

endfunction: build_phase

task run_phase(uvm_phase phase);

super.run_phase(phase);
`uvm_info(get_name(), "Inside run phase", UVM_HIGH)

/* repeat(2) begin
item=shifter_8bit_sequence_item::type_id::create("item");
seq_item_port.get_next_item(item);
init_drive(item);
//item.print();
seq_item_port.item_done();
end
*/
forever begin
// item=shifter_8bit_sequence_item::type_id::create("item");
this.item = uvm_object_registry#(shifter_8bit_sequence_item,
"shifter_8bit_sequence_item")::create("item", /* parent = null */, /* contxt = "\000" */);
//this.s_item = uvm_object_registry#(shifter_8bit_sequence_item,
"shifter_8bit_sequence_item")::create("s_item", /* parent = null */, /* contxt = "\000" */);

seq_item_port.get_next_item(item);
drive(item);
//item.print();
seq_item_port.item_done();
end

endtask

task drive(shifter_8bit_sequence_item item);

`uvm_info(get_name(),"Drive...",UVM_HIGH)
//vif.rst=item.rst;
@(posedge vif.clk);

// vif.A<=item.A;
// vif.B<=item.B;
vif.data_in = item.data_in;
vif.shift_amount = item.shift_amount;
 vif.shift_direction = item.shift_direction;

`uvm_info("DRIVER", $sformatf("Driving Data: %h, Shift: %h, Direction: %b", item.data_in,

item.shift_amount, item.shift_direction), UVM_MEDIUM)

// Allow combinational logic to settle

// seq_item_port.item_done();

// vif.valid=item.valid;
// vif.AgreaterthanB=item.AgreaterthanB;
// vif.AlessthanB=item.AlessthanB;
// vif.AequaltoB=item.AequaltoB;
endtask

/*
task init_drive(shifter_8bit_sequence_item item);
`uvm_info(get_name(),"Init Drive...",UVM_HIGH)
//vif.rst=item.rst;

@(posedge vif.clk);
vif.a<=item.a;
vif.b<=item.b;

endtask
*/
endclass: shifter_8bit_driver

● Monitor

class shifter_8bit_monitor extends uvm_monitor;

`uvm_component_utils(shifter_8bit_monitor)
virtual shifter_8bit_if vif;
shifter_8bit_sequence_item item;

uvm_analysis_port #(shifter_8bit_sequence_item) mon_port;

function new(string name="shifter_8bit_monitor",uvm_component parent);

super.new(name,parent);
`uvm_info("shifter_8bit_monitor", "Inside constructor of shifter_8bit_monitor", UVM_HIGH)
endfunction

function void build_phase(uvm_phase phase);

super.build_phase(phase);
 `uvm_info(get_name(), "Inside build phase", UVM_HIGH)

mon_port=new("mon_port",this);

if(!(uvm_config_db #(virtual shifter_8bit_if)::get(this,"*","shifter_8bit_vif",vif)))

`uvm_error(get_name(), "Faild to get Virtual IF from database...")

endfunction: build_phase

function void connect_phase(uvm_phase phase);

super.connect_phase(phase);
`uvm_info(get_name(), "Inside connect phase", UVM_HIGH)
endfunction

task run_phase(uvm_phase phase);

super.run_phase(phase);
`uvm_info(get_name(), "Inside run phase", UVM_HIGH)
forever begin
// item=shifter_8bit_sequence_item::type_id::create("item");
this.item = uvm_object_registry#(shifter_8bit_sequence_item,
"shifter_8bit_sequence_item")::create("item", /* parent = null */, /* contxt = "\000" */);
//this.s_item = uvm_object_registry#(shifter_8bit_sequence_item,
"shifter_8bit_sequence_item")::create("s_item", /* parent = null */, /* contxt = "\000" */);

sample(item);
`uvm_info(get_name(),"Item received!!",UVM_HIGH)
mon_port.write(item);
end
endtask

task sample(shifter_8bit_sequence_item item);

// item.rst=vif.rst;
// @(negedge vif.rdy);

@(posedge vif.clk);
// #1;
item.data_in = vif.data_in;
item.shift_amount = vif.shift_amount;
item.shift_direction = vif.shift_direction;
item.expected_data_out = (item.shift_direction == 0) ? (item.data_in << item.shift_amount) :
(item.data_in >> item.shift_amount);
item.data_out = vif.data_out;
// item.A = vif.A;
// item.B = vif.B;
// item.result = vif.result;
// item.exception = vif.exception;
// item.overflow = vif.overflow;
// item.underflow = vif.underflow;
// item.done = vif.done;
// @(posedge vif.clk);

endtask

endclass: shifter_8bit_monitor

● Agent

class shifter_8bit_agent extends uvm_agent;

`uvm_component_utils(shifter_8bit_agent)
shifter_8bit_driver drv;
shifter_8bit_monitor mon;
shifter_8bit_sequencer seqr;

function new(string name="shifter_8bit_agent",uvm_component parent);

super.new(name,parent);
`uvm_info("shifter_8bit_agent", "Inside constructor of shifter_8bit_agent", UVM_HIGH)
endfunction

function void build_phase(uvm_phase phase);

super.build_phase(phase);
`uvm_info(get_name(), "Inside build phase", UVM_HIGH)

drv=shifter_8bit_driver::type_id::create("drv",this);

mon=shifter_8bit_monitor::type_id::create("mon",this);
seqr=shifter_8bit_sequencer::type_id::create("seqr",this);

endfunction: build_phase

function void connect_phase(uvm_phase phase);

super.connect_phase(phase);
`uvm_info(get_name(), "Inside connect phase", UVM_HIGH)
drv.seq_item_port.connect(seqr.seq_item_export);
endfunction

task run_phase(uvm_phase phase);

 super.run_phase(phase);
`uvm_info(get_name(), "Inside run phase", UVM_HIGH)
endtask

endclass: shifter_8bit_agent

● Environment

class shifter_8bit_env extends uvm_env;

`uvm_component_utils(shifter_8bit_env)

shifter_8bit_agent agent;
shifter_8bit_scoreboard scb;
// shifter_8bit_coverage cov_subscriber; // Declare the coverage subscriber

function new(string name = "shifter_8bit_env", uvm_component parent = null);

super.new(name, parent);
`uvm_info("shifter_8bit_env", "Inside constructor of shifter_8bit_env", UVM_HIGH)
endfunction

function void build_phase(uvm_phase phase);

super.build_phase(phase);
`uvm_info(get_name(), "Inside build phase", UVM_HIGH)
agent = shifter_8bit_agent::type_id::create("agent", this);
scb = shifter_8bit_scoreboard::type_id::create("scb", this);
// cov_subscriber = shifter_8bit_coverage::type_id::create("cov_subscriber", this); // Instantiate the
coverage subscriber
endfunction : build_phase

function void connect_phase(uvm_phase phase);

super.connect_phase(phase);
`uvm_info(get_name(), "Inside connect phase", UVM_HIGH)
agent.mon.mon_port.connect(scb.scb_port);
// agent.mon.mon_port.connect(cov_subscriber.analysis_export); // Connect the monitor to the
coverage subscriber
endfunction : connect_phase
endclass : shifter_8bit_env

● Test
class shifter_8bit_test extends uvm_test;
`uvm_component_utils(shifter_8bit_test)

shifter_8bit_env env;
// shifter_8bit_main_seq main_seq;

function new(string name="shifter_8bit_test",uvm_component parent);

super.new(name,parent);
`uvm_info("shifter_8bit_test", "Inside constructor of shifter_8bit_test", UVM_HIGH)
endfunction

function void build_phase(uvm_phase phase);

super.build_phase(phase);
`uvm_info(get_name(), "Inside build phase", UVM_HIGH)
env=shifter_8bit_env::type_id::create("env",this);
endfunction: build_phase

function void connect_phase(uvm_phase phase);

super.connect_phase(phase);
`uvm_info(get_name(), "Inside connect phase", UVM_HIGH)
endfunction
/*
task run_phase(uvm_phase phase);
super.run_phase(phase);
`uvm_info(get_name(), "Inside run phase", UVM_HIGH)

phase.raise_objection(this);

// repeat(`TEST_COUNT) begin
// main_seq=shifter_8bit_main_seq::type_id::create("main_seq");class shifter_8bit_test extends
uvm_test;
`uvm_component_utils(shifter_8bit_test)

shifter_8bit_env env;
// shifter_8bit_main_seq main_seq;

function new(string name="shifter_8bit_test",uvm_component parent);

super.new(name,parent);
`uvm_info("shifter_8bit_test", "Inside constructor of shifter_8bit_test", UVM_HIGH)
endfunction

function void build_phase(uvm_phase phase);

super.build_phase(phase);
`uvm_info(get_name(), "Inside build phase", UVM_HIGH)
env=shifter_8bit_env::type_id::create("env",this);
endfunction: build_phase

function void connect_phase(uvm_phase phase);

super.connect_phase(phase);
`uvm_info(get_name(), "Inside connect phase", UVM_HIGH)
endfunction
 task run_phase(uvm_phase phase);
super.run_phase(phase);
`uvm_info(get_name(), "Inside run phase", UVM_HIGH)

phase.raise_objection(this);

// repeat(`TEST_COUNT) begin
// main_seq=shifter_8bit_main_seq::type_id::create("main_seq");
// main_seq.start(env.agent.seqr);
// end
wait(env.scb.test_cnt==`TEST_COUNT);

phase.drop_objection(this);

endtask
*/

endclass: shifter_8bit_test

class shifter_8bit_mul_test extends shifter_8bit_test;

`uvm_component_utils(shifter_8bit_mul_test)

// shifter_8bit_env env;
shifter_8bit_mul_seq mul_seq;

function new(string name="shifter_8bit_mul_test",uvm_component parent);

super.new(name,parent);
`uvm_info("shifter_8bit_mul_test", "Inside constructor of shifter_8bit_mul_test", UVM_HIGH)
endfunction

function void build_phase(uvm_phase phase);

super.build_phase(phase);
`uvm_info(get_name(), "Inside build phase", UVM_HIGH)
// env=shifter_8bit_env::type_id::create("env",this);
endfunction: build_phase

function void connect_phase(uvm_phase phase);

super.connect_phase(phase);
`uvm_info(get_name(), "Inside connect phase", UVM_HIGH)
endfunction

task run_phase(uvm_phase phase);

super.run_phase(phase);
`uvm_info(get_name(), "Inside run phase", UVM_HIGH)

phase.raise_objection(this);

repeat(`TEST_COUNT) begin
// forever begin
mul_seq=shifter_8bit_mul_seq::type_id::create("mul_seq");
mul_seq.start(env.agent.seqr);
end
wait(env.scb.test_cnt==`TEST_COUNT);

phase.drop_objection(this);
 endtask

endclass: shifter_8bit_mul_test

● Testbench

// Code your testbench here

// or browse Examples

// Code your testbench here

// or browse Examples
//`timescale 1ns/1ns
`include "uvm_macros.svh"
import uvm_pkg::*;

`define TEST_COUNT 200

`include "interface.sv"
`include "sequence_items.sv"
`include "sequencer.sv"
`include "sequence.sv"
`include "driver.sv"
`include "monitor.sv"
`include "scoreboard.sv"
`include "agent.sv"
`include "environment.sv"
`include "test.sv"

// Code your testbench here

// or browse Examples
`timescale 1ns/1ns
`include "uvm_macros.svh"
//`include "shifter_8bit_def.sv"
import uvm_pkg::*;

module top;

bit clk=0;
// bit rst;

shifter_8bit_if top_if(clk);

shifter_8bit dut(
.data_in (top_if.data_in),
.shift_amount (top_if.shift_amount),
.shift_direction (top_if.shift_direction),
.data_out (top_if.data_out )
);

//clock generation
initial forever #0.5 clk=~clk;
initial begin
// rst = 1;
// #2 rst =0;
end

initial begin
uvm_config_db #(virtual shifter_8bit_if) :: set(null,"*","shifter_8bit_vif",top_if);
`uvm_info("TOP","Configured database for interface...",UVM_LOW)
end

initial begin
run_test("shifter_8bit_test");
end

initial begin
$dumpfile("waveform.vcd");
$dumpvars;
end

endmodule
2. Stimulus Generation (15%)

● Development of constrained-random and directed test sequences.

● Use of UVM sequences and transaction-based stimulus generation.
● Ability to generate different corner cases and invalid scenarios.
● Parameterization and reuse of sequences.

● Sequence Item

class shifter_8bit_sequence_item extends uvm_sequence_item;

// rand logic rst;

// randc logic [31:0] A;

// randc logic [31:0] B;
// logic [31:0] result;
// logic exception;
// logic overflow;
// logic underflow;
// logic done;

randc logic [7:0] data_in; // 8-bit input data

randc logic [2:0] shift_amount; // Shift amount (0 to 7)
randc logic shift_direction; // Shift direction (0: left, 1: right)
logic [7:0] data_out ; // 8-bit shifted output
logic [7:0] expected_data_out ; // 8-bit shifted output
// `uvm_object_utils (shifter_8bit_sequence_item)

function new(string name="shifter_8bit_sequence_item");

super.new(name);
endfunction

/*module shifter_8bit (
input [7:0] data_in, // 8-bit input data
input [2:0] shift_amount, // Shift amount (0 to 7)
input shift_direction, // Shift direction (0: left, 1: right)
output [7:0] data_out // 8-bit shifted output
);
reg [7:0] shifted_data; // Temporary register to hold shifted data
*/
//`uvm_object_utils_begin(shifter_8bit_sequence_item)
// `uvm_field_int(A, UVM_ALL_ON)
// `uvm_field_int(B, UVM_ALL_ON)
// `uvm_field_int(result, UVM_ALL_ON)
// `uvm_object_utils_end

endclass
● Sequence
class shifter_8bit_base_sequence extends uvm_sequence;
`uvm_object_utils(shifter_8bit_base_sequence)
shifter_8bit_sequence_item shifter_8bit_item;

function new(string name="shifter_8bit_sequence");

super.new(name);
endfunction

endclass: shifter_8bit_base_sequence

class shifter_8bit_mul_seq extends shifter_8bit_base_sequence;

`uvm_object_utils(shifter_8bit_mul_seq)
shifter_8bit_sequence_item item;

function new(string name="shifter_8bit_mul_seq");

super.new(name);
endfunction

task body();
`uvm_info(get_name(),"Running main sequence...",UVM_HIGH);

// item=shifter_8bit_sequence_item::type_id::create("item");
this.item = uvm_object_registry#(shifter_8bit_sequence_item,
"shifter_8bit_sequence_item")::create("item", /* parent = null */, /* contxt = "\000" */);
//this.s_item = uvm_object_registry#(shifter_8bit_sequence_item,
"shifter_8bit_sequence_item")::create("s_item", /* parent = null */, /* contxt = "\000" */);

start_item(item);
item.randomize();
// rst == 1'b0; };

finish_item(item);
endtask

endclass
3. Scoreboarding and Checking (25%)

● Implementation of functional and self-checking scoreboard.

● Use of predictive models and golden reference comparison.
● Effective use of UVM phases for checking.

● Scoreboard

class shifter_8bit_scoreboard extends uvm_scoreboard;

`uvm_component_utils(shifter_8bit_scoreboard)

uvm_analysis_imp #(shifter_8bit_sequence_item, shifter_8bit_scoreboard) scb_port;

shifter_8bit_sequence_item item[$];
shifter_8bit_sequence_item s_item;
int test_cnt=0;
int test_valid=0;
int test_invalid=0;

function new(string name = "shifter_8bit_scoreboard", uvm_component parent);

super.new(name, parent);
`uvm_info("SCB_CLASS", "Inside Constructor!", UVM_HIGH)

endfunction: new

function void build_phase(uvm_phase phase);

super.build_phase(phase);
`uvm_info("SCB_CLASS", "Build Phase!", UVM_HIGH)
scb_port=new("scb_port",this);

endfunction: build_phase

function void connect_phase(uvm_phase phase);

super.connect_phase(phase);
`uvm_info("SCB_CLASS", "Connect Phase!", UVM_HIGH)

endfunction: connect_phase

function void write (shifter_8bit_sequence_item rx_item);

item.push_front(rx_item);
endfunction

task run_phase(uvm_phase phase);

super.run_phase(phase);
forever begin

this.s_item = uvm_object_registry#(shifter_8bit_sequence_item,
"shifter_8bit_sequence_item")::create("s_item", /* parent = null */, /* contxt = "\000" */);

wait((item.size() != 0));
s_item=item.pop_front();
// s_item.print();
compare(s_item);

test_cnt++;
end
endtask

function void compare(shifter_8bit_sequence_item item);

logic [31:0] ex_res;

if (item.expected_data_out == item.data_out) begin

`uvm_info(get_name,$sformatf("[%0d/%0d] Test
Passed",test_cnt,`TEST_COUNT),UVM_LOW);
test_analysis(item,ex_res,1);
test_valid++;
end
else begin
`uvm_error(get_name,$sformatf("[%0d/%0d] Test failed",test_cnt,`TEST_COUNT));
test_analysis(item,ex_res,1);
test_invalid++;
end
endfunction

function void test_analysis(shifter_8bit_sequence_item item, logic [31:0] ex_res,bit flag);

if(flag) begin
$display(" ");
$display(" data_in= %0h , shift_amount= %0h, shift_direction= %0h, \n data_out=%0h
,expected_data_out = %0h
,",item.data_in,item.shift_amount,item.shift_direction,item.data_out,item.expected_data_out);
end
endfunction
/*
randc logic [7:0] data_in; // 8-bit input data
randc logic [2:0] shift_amount; // Shift amount (0 to 7)
randc logic shift_direction; // Shift direction (0: left, 1: right)
logic [7:0] data_out ; // 8-bit shifted output
logic [7:0] expected_data_out ; // 8-bit shifted output
// `uvm_object_utils (shifter_8bit_sequence_item)
*/

function void report_phase(uvm_phase phase);

super.report_phase(phase);
`uvm_info(get_name(),$sformatf("Total tests: %0d",test_cnt),UVM_LOW)
`uvm_info(get_name(),$sformatf("Passed tests: %0d",test_valid),UVM_LOW)
`uvm_info(get_name(),$sformatf("Failed tests: %0d",(test_invalid/test_cnt)*100),UVM_LOW)

endfunction
endclass
4. Debugging and Logs (5%)

● Effective use of UVM messaging and verbosity levels.

● Debugging skills and ability to interpret waveforms and logs.
● Error detection.
● Documentation of issues and resolutions.

● interface

interface shifter_8bit_if(input logic clk);

logic [7:0] data_in;

logic [2:0] shift_amount;
logic shift_direction;
logic [7:0] data_out;

endinterface: shifter_8bit_if
● Waveform (In Testbench)

initial
begin
$dumpfile("dump.vcd");
$dumpvars();
end
5. Code Quality and Best Practices (5%)

● Consistency in naming conventions and coding style.

● Use of parameterized and reusable components.
● Proper comments and documentation within the code.
● Efficient and optimized coding practices.

EDA LInk: https://www.edaplayground.com/x/gjpf

 Generate GDS using OpenROAD tool

In this section, the layout of the RTL code has been generated using the OpenROAD software
tool.

Technology/Platform utilized: sky130hd

Instructions of the config.mk

export DESIGN_NICKNAME = project_2

export DESIGN_NAME = shifter_8bit
export PLATFORM = shy130hd

export VERILOG_FILES = $(sort $(wildcard

$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ shifter_8bit.v))
export SDC_FILE =
$(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc

#export PLACE_PINS_ARGS = -min_distance 4 -min_distance_in_tracks

export CORE_UTILIZATION = 0.5

#export CORE_ASPECT_RATIO = 1
#export CORE_MARGIN = 2

export PLACE_DENSITY = 0.1

export TNS_END_PERCENT = 100

#export EQUIVALENCE_CHECK ?= 0
#export REMOVE_CELLS_FOR_EQY = sky130_fd_sc_hd tapvpwrvgnd*

#export FASTROUTE_TCL =
$(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/fastroute.tcl

#export REMOVE_ABC_BUFFERS = 1
Instructions of the constraint.sdc

current_design shifter_8bit

set clk_name v_clk

#set clk_port_name clk
set clk_period 2.5
set clk_io_pct 0.2

#set clk_port [get_ports $clk_port_name]

create_clock -name $clk_name -period $clk_period

set non_clock_inputs [lsearch -inline -all -not [all_inputs]]

set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs

set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]

Layout of the Design

 Performance Analysis

Power Measurement:

Group Internal Switching Leakage Total

Power Power Power Power (Watts)

Sequential 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%

Combinational 1.15e-11 1.20e-12 1.13e-08 1.13e-08 7.3%
Clock 0.00e+00 0.00e+00 1.43e-07 1.43e-07 92.7%
Macro 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
Pad 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%

Total 1.15e-11 1.20e-12 1.55e-07 1.55e-07

Area Measurement:

Design area 0 u^2 29% utilization.

Timing Information:

Startpoint: shift_amount[2] (input port)

Endpoint: _057_/A (internal pin)

Path Group: unconstrained

Path Type: max

Delay Time Description

0.00 0.00 ^ input external delay

0.00 0.00 ^ shift_amount[2] (in)

 0.00 0.00 ^ _057_/A (sky130_fd_sc_hd clkbuf_2)

0.00 data arrival time

(Path is unconstrained)
Generated GDS
Conclusions
In this report, the RTL code of 8-bit shift register has been designed in verilog. The code is
successfully verified with the UVM with 100% test case pass. The design code is further processed
in the openROAD tool to generate its GDS using the gf180 platform. It has shown that the
generated layout consumes 155nW power which occupies 4662 sq. um area. There is no setup
and hold violations.