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mod 4-1

Stick diagrams are simplified representations of circuit layouts that convey layer information through color codes, showing relative placement of components without exact details. They follow specific rules for electrical contact and layout organization, particularly in CMOS designs. Design rules, such as micron and lambda rules, ensure proper fabrication tolerances and spacing between various components.

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8 views

mod 4-1

Stick diagrams are simplified representations of circuit layouts that convey layer information through color codes, showing relative placement of components without exact details. They follow specific rules for electrical contact and layout organization, particularly in CMOS designs. Design rules, such as micron and lambda rules, ensure proper fabrication tolerances and spacing between various components.

Uploaded by

aryaaandreams
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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STICK DIAGRAMS

•Stick diagrams are a means of capturing topography and


layer information using simple diagrams.

•Stick diagrams convey layer information through color codes

•Does show all components/vias


•It shows relative placement of components

•A stick diagram is a cartoon of a layout.


•Does not show
•–Exact placement of components
•–Transistor sizes
•–Wirelengths, wire widths, tub boundaries
•–Any other low level details such as parasitics
STICK DIAGRAM NOTATIONS
NMOS ENCODING
CMOS ENCODING
Rules in Stick Diagram
•Rule1:
When two or more ‘sticks’ of the same type cross or touch each other
that represents electrical contact

•Rule2:
When two or more “sticks” of different type cross or touch each other
there is no electrical contact.
•Rule3:
When a poly crosses diffusion it represents a transistor.(If a contact is
shown then it is nota transistor)

•Rule4:In CMOS a demarcation line is drawn to avoid touching of p-


diff with n-diff. All PMOS must lie on one side of the line and all
NMOS will have to be on the other side.
EXAMPLE
Design rules
•Design rules represents a tolerance which insures very
high probability of correct fabrication
•Two major approaches:
–“Micron” rules: stated at micron resolution.
– λ rules: simplified micron rules with limited scaling attributes.
MICRON RULE

•All minimum sizes and spacing specified in microns.

•Rules don't have to be multiples of λ.

•Can result in 50% reduction in area over λ based rules


LAMBDA RULE
•Lambda-based (scalable CMOS) design rules define scalable
rules based on λ (which is half of the minimum channel length)
•Stick diagram is a draft of real layout, it serves as an abstract
view between the schematic and layout.
•All widths, spacing, and distances are written in the form
λ=0.5 * minimum drawn transistor length
RULES
•Minimum feature size is defined as 2λ
•Minimum width of PolySi and diffusion line 2λ
•Minimum width of Metal line 3 λ as metal lines run over a
more uneven surface than other conducting layers to ensure
their continuity
•PolySi–PolyS ispace2 λ
•Metal-Metals pace2 λ
•Diffusion–Diffusion space3 λ To avoid the possibility of their
associated regions overlapping and conducting current
•Diffusion –PolySi space λTo prevent the lines overlapping to
form unwanted capacitor
•Metal lines can pass over both diffusion and polySi without
electrical effect. Where no separation is specified, metal lines can
overlap or cross
•Metal lines can pass over both diffusion and polySi without
electrical effect
•It is recommended practice to leave λ between a metal edge and
a polySi or diffusion line to which it is not electrically connected
Butting Contact
•The gate and source of a depletion device can be connected by
a method known as butting contact.
•Here metal makes contact to both the diffusion forming the source
of the depletion transistor and to the polySi forming this device’s
gate.
Buried Contact
•Here gate length is depend upon the alignment of the buried
contact mask relative to the polySi and there fore vary by ±λ.
Contact Cut
•Metal connects to polySi/diffusion by contact cut.
•Contact area:2λ* 2λ
•Metal and polySi or diffusion must overlap this contact area by “l”
so that the two desired conductors encompass the contact area
despite any misalignment between conducting layers and the
contact hole
Design Rules
•Wells must surround transistors by 6 λ
–Implies 12 λ between opposite transistor flavors
–Leaves room for one wire track
•A wiring track is the space required for a wire
•4λwidth,4 λ spacing from neighbour=8 λ pitch
•Transistors also consume one wiring track
Layout
•Layer Types
–p-substrate
–n-well
–n+
–p+
–Gate oxide
–Gate (polysilicon)
–Field Oxide
• Insulated glass
• Provide electrical isolation
Layouts

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