Design Techniques for Analog PLLs: Moving

Beyond Classical Topologies

CICC 2010

Michael Perrott
September 2010

Copyright © 2010 by Michael H. Perrott

All rights reserved.
What is a Phase-Locked Loop (PLL)?

ref(t) ref(t)
out(t) out(t)
e(t) v(t) e(t) v(t)

ref(t) e(t) Analog v(t) out(t)

Phase
Detect Loop Filter
VCO de Bellescize
Onde Electr, 1932

 VCO efficiently provides oscillating waveform with

variable frequency
 PLL synchronizes VCO frequency to input reference
frequency through feedback
- Key block is phase detector
 Realized as digital gates that create pulsed signals
2
Integer-N Frequency Synthesizers

ref(t)
div(t)
e(t) v(t)
Fout = N Fref
ref(t) e(t) Analog v(t) out(t)
Phase
Detect Loop Filter
VCO
div(t) Sepe and Johnston
Divider US Patent (1968)

N
 Use digital counter structure to divide VCO frequency
- Constraint: must divide by integer values
 Use PLL to synchronize reference and divider output
Output frequency is digitally controlled 3
Fractional-N Frequency Synthesizers
Kingsford-Smith
ref(t) US Patent (1974)
div(t) Wells
US Patent (1984)
e(t) v(t)
Fout = M.F Fref
ref(t) e(t) Analog v(t) out(t)
Phase
Detect Loop Filter
Riley
VCO US Patent (1989)
div(t) Divider JSSC ‘93

Nsd[k] Σ−Δ N[k] M.F

Modulator

 Dither divide value to achieve fractional divide values

- PLL loop filter smooths the resulting variations
Very high frequency resolution is achieved 4
The Issue of Quantization Noise

ref(t)
div(t)
e(t) v(t)
Fout = M.F Fref
ref(t) e(t) Analog v(t) out(t)
Phase
Detect Loop Filter
VCO
div(t) Divider

Nsd[k] Σ−Δ N[k] M.F

Modulator
Σ−Δ Quantization Noise
 Limits PLL bandwidth
 Increases linearity requirements of
phase detector f
5
Analog Phase Detection

1 D Q error(t) phase error

ref(t)
ref(t)
reset
1 D Q div(t)
div(t)
Reg
error(t)

ref(t) out(t)
Phase Analog
Detect Loop Filter
VCO
div(t) Divider

 Phase detector varies pulse width with phase error

 Loop filter smooths pulses to extract average value
6
 Issues with Analog Loop Filter

Charge
Vout
error(t) Pump
Icp

Cint

ref(t) out(t)
Phase Analog
Detect Loop Filter
VCO
Divider

 Charge pump: output resistance, mismatch, noise, leakage

- Analog design requires significant effort, hard to port
 RC Network: large area 7
 Should We Go All Digital ?

ref(t) out(t)
Phase Analog
Detect Loop Filter
VCO
Divider

ref(t) Time out(t)

Digital
-to- Loop Filter
Digital
DCO Staszewski et. al.,
Divider TCAS II, Nov 2003

 Digital loop filter: compact area, digital flow

 Issue: difficult to achieve low area and power in older
processes such as 0.18u CMOS
- May not be worth the effort unless advanced CMOS available 8
Can We Achieve an Analog PLL with Lower Design
Complexity and Adequate Performance?
Outline

 Background information on traditional analog PLL

implementations and analysis
 Moving away from the traditional approach
- XOR-based phase detection
- Switched resistor loop filter
- Switched capacitor frequency detection
 MEMS oscillator example

10
Key Characteristics of a Phase Detector

Phase Detector Signals Phase Detector

Characteristic

Average of
ref(t)

error(t)
out(t)

error(t)
phase error

ref(t) out(t)
Phase Analog
Detect Loop Filter
VCO

 Adequate phase detection range

- Fractional-N PLLs need more range than Integer-N PLLs
 Linearity across operating range of phase detector
- Fractional-N PLLs have issues with noise folding 11
XOR Phase Detector

 Creates pulse widths D Q

that vary according to Ref(t)
Q
Ref/2(t) e(t)
the phase difference
Div/2(t)
between reference and D Q
Div(t)
divider output signals Q

 Simple implementation
Divide-by-2
 Divide-by-2 is used to
eliminate impact of Ref(t)
falling edges
- Duty cycle of Ref(t) and Div(t)

Div(t) signals is no Ref/2(t)

longer of concern
Div/2(t)

e(t)

12
Modeling of XOR Phase Detector

 Average value of pulses is extracted by loop filter

- Look at detector output over one cycle:
W

1
e(t)
-1
T
 Equation:

Notice that the average error is a linear function

of the pulse width W regardless of mismatch
13
Overall XOR Phase Detector Characteristic
avg{e(t)}

Φref(t) - Φdiv(t)
0 2π 4π

Ref(t)

Div(t)

Ref/2(t)

Div/2(t)

e(t)

Gain flips in sign according to phase error

region of phase detector
14
Modeling of XOR Phase Detector
 Assume phase difference is confined to same slope region
- XOR PD model becomes a highly linear gain element
avg{e(t)}
gain = -1/π 1 gain = 1/π

Φref(t) - Φdiv(t)
-2π -π 0 π 2π
-1
phase detector
range = 2π

 Corresponding frequency-domain model

Ref(t) e(t)
PD Φref(t) e(t)
1
π

Φdiv(t) PD gain
Div(t)
15
Overall PLL Model with XOR Phase Detector
1
XOR PD: Kpd =
π Loop Filter VCO
Φref(t) e(t) v(t) Kv Φout(t)
Kpd H(f)
jf

Divider
Φdiv(t)
1
N

 Define A(f) as open loop response

- Where K pd is defined as PD gain (1/ for XOR PD)

 Define G(f) as a parameterizing closed loop function

16
Key Properties of G(f) Function
1
XOR PD: Kpd =
π Loop Filter VCO
Φref(t) e(t) v(t) Kv Φout(t)
Kpd H(f)
jf

Divider
Φdiv(t)
1
N

 G(f) always has a DC gain of 1

- True since A(f) goes to infinity as f goes to 0
 G(f) is lowpass in nature
- True since A(f) goes to 0 as f goes to infinity
 G(f) has bandwidth close to unity gain frequency of A(f)
17
Closed Loop Response From Ref to PLL Output
1
XOR PD: Kpd =
π Loop Filter VCO
Φref(t) e(t) v(t) Kv Φout(t)
Kpd H(f)
jf

Divider
Φdiv(t)
1
N

Lowpass with DC gain of N

18
Closed Loop Response From PD to PLL Output
1
XOR PD: Kpd =
π en(t) Loop Filter VCO
Φref(t) e(t) v(t) Kv Φout(t)
Kpd H(f)
jf

Divider
Φdiv(t)
1
N

Lowpass with DC gain of N/Kpd

19
Closed Loop Response From VCO to PLL Output
1
XOR PD: Kpd = Φvn(t)
π Loop Filter VCO
Φref(t) e(t) v(t) Kv Φout(t)
Kpd H(f)
jf

Divider
Φdiv(t)
1
N

Highpass with high frequency gain of 1

20
Consider A First Order Loop Filter
1
XOR PD: Kpd =
π Loop Filter VCO
Φref(t) e(t) v(t) Kv Φout(t)
Kpd H(f)
jf

Divider
Φdiv(t)
1
N

 First order loop filter

e(t) R1 v(t)

C1

21
Closed Loop Poles Versus Open Loop Gain
Evaluation of Closed Loop Pole
Phase Margin Locations of G(f)
Im{s}
Open loop 20log|A(f)| C
gain
increased
Dominant
pole pair B

0 dB f
fp
A
C
B
A Re{s}
angle(A(f)) 0
o
-90

A
PM = 59o for A
o
-120
PM = 45o for B
B
-150o PM = 33o for C

-180o
C

 Higher open loop gain leads to an increase in bandwidth

but decrease in phase margin
- Closed loop poles start exhibiting higher Q 22
Corresponding Closed Loop Response

Frequency Response of G(f) Step Response of G(f)

C
5 dB C 1.4
B
0 dB B
A
-5 dB A
1

0.6

f 0 t
fp

 Decrease in phase margin leads to

- Peaking in closed loop frequency response
- Ringing in closed loop step response
Design of PLL dynamics is similar to
opamps and other classical feedback systems 23
 The Problem with a First Order Loop Filter

Open loop 20log|A(f)|

gain
increased Unity Gain
Frequency

0 dB f
fp

o
angle(A(f))
-90
o
 Recall that bandwidth of G(f)
-120
is roughly the same as unity
-150o gain frequency of A(f)
-180o

 To achieve good phase margin, fp >> unity gain frequency

- Implies that H(f) ≈ 1 at unity gain frequency
- Bandwidth of G(f) purely set by K , K , and N pd v

Limited freedom to choose desired closed loop bandwidth

24
 Inclusion of a Charge Pump

 Charge pump current adds a new parameter that allows

more freedom in choosing the PLL bandwidth
 Lead/lag filter is a common loop filter with charge pump
- Current into a capacitor forms integrator
- Add extra pole/zero using resistor and additional capacitor
Icp
e(t) Up
i(t) v(t)  Where:
Down
R1
C1
Icp C2

Forms a Type II PLL

25
Type I versus Type II PLL Implementations
1
XOR PD: Kpd =
π Loop Filter VCO
Φref(t) e(t) v(t) Kv Φout(t)
Kpd H(f)
jf

Divider
Φdiv(t)
1
N

 Type I: one integrator in PLL open loop transfer

function A(f)
- VCO adds one integrator
- Loop filter, H(f), has no integrators
 Type II: two integrators in PLL open loop transfer
function A(f)
- Loop filter, H(f), has one integrator
26
VCO Input Range Issue for Type I PLL Implementations

 DC output range of gain block versus integrator

Gain Block Integrator
0 0
K
K s

 Issue: often need to provide attenuation through loop

filter to achieve a desired closed loop bandwidth
- Loop filter output fails to cover full input range of VCO
VDD
No Output Range
Integrator of Loop Filter
Gnd

ref(t) e(t) Loop v(t) out(t)

PFD Filter
VCO

Divider

N[k]
27
Options for Achieving Full Range Span of VCO
 Type I
- Add a D/A converter to provide coarse tuning
 Adds power and complexity
 Steady-state phase error inconsistently set
 Type II
- Integrator automatically provides DC level shifting
 Low power and simple implementation
 Steady-state phase error always set to zero
Type I Type II

Output Range Output Range

Course of Loop Filter of Loop Filter
Tune D/A
VDD VDD
No Contains
Integrator Integrator
Gnd Gnd

e(t) Loop v(t) e(t) v(t)

C.P. Loop
Filter C.P.
Filter
28
 Design of Type II, Charge Pump PLL
Evaluation of Closed Loop Pole
Phase Margin Locations of G(f)
Im{s}
Open loop 20log|A(f)|
gain C
increased

Dominant
B pole pair
0 dB f
fz fp A
Non-dominant
C pole
B
A Re{s}
angle(A(f)) A BC 0
o
120
PM = 54oo for B
PM = 53 for A
PM = 55o for C A
o
-140

o
B
-160

o
-180 C

 Place fz and fp based on phase margin, and open loop gain

based on desired PLL bandwidth
- Charge pump offers high flexibility in choosing PLL bandwidth 29
 Negative Issues For Type II PLL Implementations
Peaking caused by Step Responses for a Second Order
|G(f)| undesired pole/zero pair G(f) implemented as a Bessel Filter
1.4

Normalized Amplitude
Type II: fz/fo = 1/3
fcp fz Type II: fz/fo = 1/8

1 1
Type I

0.6

0 f 0
fz fo 1 2 3 4
Frequency (Hz) Normalized time: t*fo

 Parasitic pole/zero pair causes

- Peaking in the closed loop frequency response
 Increases PLL phase noise
- Extended settling time due to parasitic “tail” response
 Bad for applications demanding fast settling time
30
The Need for Frequency Detection
 Response of PLL to Divide Value Changes
XOR PD
Loop Filter VCO
Φref(t) e(t) v(t) Kv Φout(t)
1 H(f)
π jf

Divider
Φdiv(t)
1
N

N+1
N
t
 Change output frequency by changing the divide value
 Classical approach provides no direct model of impact of
divide value variations
- Treat divide value variation as a perturbation to a linear system
and use the PLL closed loop response
 More advanced PLL models include divide value variations
- M.H. Perrott, M.D. Trott, C.G. Sodini, "A modeling approach for Σ-∆
fractional-N frequency synthesizers allowing straightforward noise
analysis,“ JSSC, vol. 37, pp. 1028-1038, Aug. 2002.
32
 Response of an Actual PLL to Divide Value Change

 Example: Change divide value by one

Synthesizer Response To Divider Step

93
N (Divide Value)

92.8

92.6

92.4

92.2

92

91.8
40 60 80 100 120 140 160 180 200 220 240

1.87
Output Frequency (GHz)

1.86

1.85

1.84

1.83
40 60 80 100 120 140 160 180 200 220 240
Time (microseconds)

 PLL responds according to linear model of closed loop response!

33
What Happens with Large Divide Value Variations?
 PLL response does not fit linear model
Synthesizer Response To Divider Step
N (Divide Value) 96

95

94

93

92
40 60 80 100 120 140 160 180 200 220 240
Output Frequency (GHz)

1.92

1.9

1.88

1.86

1.84

40 60 80 100 120 140 160 180 200 220 240

Time (microseconds)

- What is happening here? 34

Recall Phase Detector Characteristic

avg{e(t)}
gain = -1/π 1 gain = 1/π

Φref(t) - Φdiv(t)
-2π -π 0 π 2π
-1
phase detector
range = 2π

 To simplify modeling, we assumed that we always

operated in a confined phase range (0 to 2)
- Led to a simple PD model
 Large perturbations knock us out of that confined
phase range
- PD behavior varies depending on the phase range it
happens to be in

35
Cycle Slipping
 Consider the case where there is a frequency offset
between divider output and reference
- We know that phase difference will accumulate
ref(t)

div(t)

 Resulting ramp in phase causes PD characteristic to

be swept across its different regions (cycle slipping)
avg{e(t)}
gain = -1/π 1 gain = 1/π

Φref(t) - Φdiv(t)
-2π -π 0 π 2π
-1

36
Impact of Cycle Slipping

 Loop filter averages out phase detector output

 Severe cycle slipping causes phase detector to
alternate between regions very quickly
- Average value of XOR characteristic can be close to
zero
- PLL frequency oscillates according to cycle slipping
- In severe cases, PLL will not re-lock
 PLL has finite frequency lock-in range!

XOR DC characteristic
cycle slipping
1

Φref - Φdiv
-2π 2π 4π n2π (n+1)2π
-1

37
Back to PLL Response Shown Previously
 PLL output frequency indeed oscillates
- Eventually locks when frequency difference is small enough
Synthesizer Response To Divider Step
96
N (Divide Value)

95

94

93

92
40 60 80 100 120 140 160 180 200 220 240
Output Frequency (GHz)

1.92

1.9

1.88

1.86

1.84

40 60 80 100 120 140 160 180 200 220 240

Time (microseconds)

- How do we extend the frequency lock-in range? 38

Phase Frequency Detectors (PFD)

 Example: Tristate PFD

up(t)
1 D Q
ref(t) Q
R
e(t)

R
1 D Q
down(t)
div(t) Q

Ref(t)

Div(t)

Up(t)

Down(t)

1
E(t)
0
-1
39
Tristate PFD Characteristic
 Calculate using similar approach as used for XOR
phase detector avg{e(t)}

1
gain = 1/(2π)

−2π
Φref - Φdiv
2π

−1

phase detector
range = 4π

 Note that phase error characteristic is asymmetric

about zero phase
- Key attribute for enabling frequency detection
40
PFD Enables PLL to Always Regain Frequency Lock

 Asymmetric phase error characteristic allows positive

frequency differences to be distinguished from
negative frequency differences
- Average value is now positive or negative according to
sign of frequency offset
- PLL will always relock for type II PLL
Tristate DC characteristic
cycle slipping

−2π
Φref - Φdiv
0 2π 4π 2nπ

lock
-1

41
The Issue of Noise
Reference Reference Charge Pump VCO Noise
Jitter Feedthrough Noise
-20 dB/dec

f f f f
1/T
T

ref(t) e(t) Charge v(t)

Loop
PFD
Pump Filter
VCO

div(t) Divider
Divider
Jitter
N
f
 Each PLL component contributes noise that impacts
overall PLL output phase noise
 Achievement of adequately low PLL phase noise is a
key issue when designing a PLL 42
Modeling the Impact of Noise on Output Phase of PLL
Divider/Reference Reference Charge Pump VCO Noise
Jitter Feedthrough Noise
S Φjit(f) S espur(f) S Icpn(f) S Φvn(f)

-20 dB/dec

f f f f
0 0 1/T 0 0
Φjit[k] espur(t) Icpn(t) Φvn(t)
Φref [k] e(t) v(t) KV Φout(t)
Kpd Icp Z(f)
jf
Charge Loop Filter
VCO
PFD Pump Impedance
Φdiv[k]
1
N
Divider

 Determine impact on output phase by deriving

transfer function from each noise source to PLL
output phase
- There are a lot of transfer functions to keep track of!
43
 Simplified Noise Model
PFD-referred VCO-referred
Noise Noise
S En(f) S Fvn(f)

-20 dB/dec

f f
0 1/T 0
Φjit[k] en(t) H(f) Φvn(t)
Φref [k] e(t) v(t) KV Φout(t)
Kpd Icp Z(f)
jf
Charge Loop Filter
VCO
PFD Pump Impedance
Φdiv[k]
1
N
Divider

 Refer all non-VCO PLL noise sources to the PFD output

- PFD-referred noise corresponds to the sum of these noise
sources referred to the PFD output
- Typically, charge pump noise dominates PFD-referred noise 44
Leverage Previous Transfer Function Analysis
PFD-referred VCO-referred
Noise Noise
S En(f) S Fvn(f)

-20 dB/dec

f f
0 1/T 0
Φjit[k] en(t) H(f) Φvn(t)
Φref [k] e(t) v(t) KV Φout(t)
Kpd Icp Z(f)
jf
Charge Loop Filter
VCO
PFD Pump Impedance
Φdiv[k]
1
N
Divider

 PFD-referred noise  VCO-referred noise

- Lowpass with DC gain of N/K pd - Highpass with gain of 1
45
Transfer Function View of PLL Phase Noise
PFD-referred VCO-referred
Noise Noise N 2
S (f)

Radians2/Hz
S en(f) S Φvn(f) Kcp e n

-20 dB/dec
S Φvn(f)
f f
0 1/T 0 f
en(t) Φvn(t) 0

S Φnpfd(f)

Radians2/Hz
N
G(f) 1-G(f)
fo Kcp fo
S Φnvco(f)
Φnpfd(t) Φnvco(t)
f
Φout(t) 0

 PFD-referred noise dominates at low frequencies

- Corresponds to close-in phase noise of synthesizer
 VCO-referred noise dominates at high frequencies
- Corresponds to far-away phase noise of synthesizer 46
 Spectral Density of PLL Phase Noise Components
PFD-referred VCO-referred
Noise Noise N 2
S (f)

Radians2/Hz
S en(f) S Φvn(f) Kcp e n

-20 dB/dec
S Φvn(f)
f f
0 1/T 0 f
en(t) Φvn(t) 0

S Φnpfd(f)

Radians2/Hz
N
G(f) 1-G(f)
fo Kcp fo
S Φnvco(f)
Φnpfd(t) Φnvco(t)
f
Φout(t) 0

 PFD-referred noise:  VCO-referred noise:

 Overall: 47
Take a Closer Look at Charge Pump Noise

Icp
Ibias
WP

id2bias id2 W
M1 M2 L
Cbig
current current
bias source

 Spectral density of charge pump noise is a function of

device noise and pulse width
- Short pulse widths reduce effective charge pump noise

Tristate PFD has an advantage of allowing short pulse

widths (i.e., lower noise) during steady-state operation
48
Impact of Transistor Current Magnitude on Noise

Icp
Ibias

id2bias id2 W
M1 M2 L
Cbig
current current
bias source
 Charge pump noise will be related to the current it
creates as

 Recall that gdo is the channel resistance at zero Vds

- At a fixed current density, we have

- Therefore, charge pump noise is proportional to I cp

49
Analysis of Charge Pump Noise Impact
Charge Pump VCO Noise
Noise
S Icpn(f) S Φvn(f)

-20 dB/dec
PFD-Referred
Noise f f
0 0
Φjit[k] en(t) Icpn(t) Φvn(t)
Φref [k] e(t) v(t) KV Φout(t)
Kpd Icp Z(f)
jf
Charge Loop Filter
VCO
PFD Pump Impedance
Φdiv[k]
1
N
Divider
 Transfer function from charge pump noise to PLL output
is found by referring noise to PFD output by factor 1/Icp

50
Increasing Icp Leads to Reduced Noise at PLL Output
Charge Pump VCO Noise
Noise
S Icpn(f) S Φvn(f)

-20 dB/dec
PFD-Referred
Noise f f
0 0
Φjit[k] en(t) Icpn(t) Φvn(t)
Φref [k] e(t) v(t) KV Φout(t)
Kpd Icp Z(f)
jf
Charge Loop Filter
VCO
PFD Pump Impedance
Φdiv[k]
1
N
Divider

 Output phase noise due to charge pump:

51
 Issue: Increasing Icp Leads to Larger Loop Filter
Charge Pump VCO Noise
Noise
S Icpn(f) S Φvn(f)

-20 dB/dec
PFD-Referred Zl(s)
Noise f f
0 0
s(C1+C2)
Φjit[k] en(t) Icpn(t) Φvn(t)
Φref [k] e(t) v(t) KV Φout(t)
Kpd Icp Z(f)
jf
Charge Loop Filter
VCO
PFD Pump Impedance
Φdiv[k]
1
N
Divider
 To keep PLL BW unchanged, assume Icp/(C1+C2) is held
constant (to maintain open loop gain)
Area gets larger since increasing Icp leads to
increased loop filter capacitance (C1+C2)
52
 Better Approach: Increase PD Gain to Lower Noise
Charge Pump VCO Noise
Noise
S Icpn(f) S Φvn(f)

-20 dB/dec
PFD-Referred
Noise f f
0 0
Φjit[k] en(t) Icpn(t) Φvn(t)
Φref [k] e(t) v(t) KV Φout(t)
Kpd Icp Z(f)
jf
Charge Loop Filter
VCO
PFD Pump Impedance
Φdiv[k]
1
N
Divider
 To keep PLL BW unchanged, assume IcpKpd held constant
- Loop filter can remain unchanged as K pd is increased

53
 Can We Increase PD Gain for a Charge Pump PLL?
Charge Pump VCO Noise
Noise
S Icpn(f) S Φvn(f)

-20 dB/dec
PFD-Referred
Noise f f
0 0
Φjit[k] en(t) Icpn(t) Φvn(t)
Φref [k] e(t) v(t) KV Φout(t)
Kpd Icp Z(f)
jf
Charge Loop Filter
VCO
PFD Pump Impedance
Φdiv[k]
1
N
Divider
 XOR-based PD provides factor of two higher gain than a
tristate PFD
- Key issue: carries an overall noise penalty since the charge
pump is never gated off (i.e., generates long pulses)
- XOR PD rarely used due to its noise penalty 54
 Key Issue of Tristate PFD: Charge Pump Mismatch

Up(t) Icp+ε
1 D Q
Ref(t)
RC
reset
Network
Down(t) Iin
1 D Q
Div(t)
Reg Icp

PD & Charge Pump Characteristic

2
avg{Iin(t)}
Ref(t) Icp+ε
Icp+ε Gain =
Div(t) 2
-2
error
Up(t) Icp 2
Gain =
2 -Icp
Down(t) Nonlinearity

 Mismatch of charge pump Up/Down currents leads to

nonlinearity in the PLL phase comparison path when
tristate PFD used 55
 Nonlinearity Causes Noise Folding with Frac-N PLLs
avg{IIN}
I-ε1

2π
Φref(t) - Φdiv(t)
-2π
Tristate PFD Nonlinearity
at origin
Up(t) -I
1 D Q VCO
Ref(t) Vtune(t) Out(t)
reset
IIN
1 D Q R1
Div(t) C1
Down(t)
Reg C2

Divider
Σ−Δ Quantization Noise

N[k] M.F
f
 Significant analog design effort is often required to avoid this issue 56
 Summary of Charge Pump PLL Issues

up(t)
1 D Q
ref(t) vtune(t)
reset
1 D Q R1
div(t) C1
down(t)
Reg C2

Divider

 Tristate PFD has issues with

- Low PD gain – leads to increased loop filter for given PLL noise
- Charge pump nonlinearity – causes quantization noise folding
 Charge Pump has issues with
- Nontrivial analog design effort for wide range, high output
impedance, low leakage, reasonable matching, low noise

Are there alternative analog PLL architectures?

57
 How Do We Achieve Higher PD Gain?

Up(t) Ipump
1 D Q
Ref(t)
RC
reset
Network
Down(t)
1 D Q
Div(t)
Reg Ipump

Phase Detector Characteristic

2
avg{Up(t)-Down(t)}
Ref(t)
1
Div(t)
-2
error
Up(t) 1 2
PD Gain =
2
Down(t) -1

 Use tristate PD as our starting point

- Range of detector spans 2 Reference periods (i.e., 4 radians)
- PD gain is 2/(PD range) = 2/(4) = 1/(2) 58
Sampled PD Achieves Much Higher PD Gain
Ref(t) Sampling PD

VCO
Vtune(t) Out(t)
Remaining
Loop Filter
C1 C2

-1 Gao, Klumperink, Bohsali, Nauta, JSSC, Dec 2009

PD Range = π/N
 Directly sample VCO signal at reference edges
- PD gain becomes 2/(/N) = 2N/assuming
 N = VCO Frequency)/(Ref Frequency)
 PD output voltage range assumed to be -1 to 1
Yields much lower in-band PLL noise, but constrained
to integer-N PLL structures 59
 Achieving Higher PD Gain for a Fractional-N PLL
2
avg{Vc1(t)}
Ref(t)
1
Div_4x(t)
-2 /8
error
Up(t) 8 2 /8
PD Gain =
2
Down(t) -1

1
Up(t)
Ref(t) High R1
Gain
PD Down(t)
C1 Vc1(t)
Div(t)
-1
 Develop a PD with reduced phase error range in which
Up/Down pulses vary in width in opposite directions
- Need an appropriate loop filter topology that properly leverages
the reduced PD range for higher PD gain
60
 Key Implementation Detail: Use Switched Resistor
2
avg{Vc1(t)}
Ref(t)
1
Div_4x(t)
-2 /8
error
Up(t) 8 2 /8
PD Gain =
2
Down(t) -1

1
Up(t)
Ref(t) High R1
See also:
Hedayati, Bakkaloglu Gain
PD Down(t)
RFIC 2009 C1 Vc1(t)
Div(t)
-1

 Switching to voltage Supply/Gnd causes Vc1(t) to reflect the

average of the Up/Down pulses within the reduced PD range
- PD gain is increased since full voltage range at V c1 achieved
across a reduced phase error range 61
 Implementation of High Gain Phase Detector
Delay Buffer For Non-Overlapping Up/Down Pulses

Down(t)

Up(t)

D Q D Q D Q D Q D Q
Ref(t) Q Q Q Q Q

Div_4x(t)
Phase Detector Characteristic
Ref(t)
avg{Up(t) - Down(t)}
Tref
Div_4x(t) 1

Up(t) error

-1
Down(t)
Tdiv
2
Tdiv Tref
 Use 4X higher divider frequency PD Gain =
1 Tref
2 =
8

- Simple digital implementation

2 Tdiv 2
62
Multi-Phase Pulse Generation (We’ll Use it Later…)
Mid(t)

Down(t)

Up(t)

Last(t)
D Q D Q D Q D Q D Q Short Pulse
Ref(t) Generator
Q Q Q Q Q

Div_4x(t)
Phase Detector Characteristic
Ref(t)
avg{Up(t) - Down(t)}
Tref
Div_4x(t) 1

Up(t) error

-1
Down(t)
Tdiv
2
Mid(t) Tdiv Tref
1 Tref 8
PD Gain = 2 =
Last(t) 2 Tdiv 2
63
 What If We Use A Charge Pump with the High Gain PD?

Up(t) Ipump
Ref(t) High
RC
Gain
PD Network
Down(t)
Div(t)
Ipump

2 Phase Detector Characteristic

Ref(t) avg{Up(t)-Down(t)}
1
Div_4x(t)
-2
error
Up(t) 2 2
PD Gain =
2
Down(t) -1

 PD Gain increased by 2 compared to tristate PFD

- Reduced phase error range and max/min current occurs
 High linearity despite charge pump current mismatch
- Similar to XOR PD, but noise is reduced 64
Increasing Feedforward Gain While Utilizing Charge Pump
Vdd PD Supply RC
Ref(t) Up(t) Vtune(t) Gain Gain Network
High ref(t) 8 Vdd 1
(Low Kv)
Gain 2 2 1+sR1_effC1
Div_4x(t) PD Down(t) R1
C1 PD Charge Integration
div(t)
Gnd Gain Pump Cap
2 Ipump 1
Ipump sC2
See also: Vtune(t) 2
Craninckx, (High Kv)
JSSC, Dec
1998 C2 H(w)
Ipump

 We can use the high gain PD in

a dual-path loop filter topology
- But we want a simple design! wz
w

Can we remove the charge pump to reduce

the analog design effort? 65
 Passive RC Network Offers a Simpler Implementation

Regulated Vdd
R3
Ref(t) Up(t) Vtune(t)
High
R1 R2
Gain
Div_4x(t) Phase Down(t)
Detector Cf
Vc1(t) C1 C2 C3
Gnd

Ref(t)
Div_4x(t) DC Gain = 1
Up(t) H(w)
Down(t) Cf
Cf +C3
 Capacitive feedforward path
provides stabilizing zero
 Design effort is simply choosing wz
w
switch sizes and RC values 66
 The Issue of Reference Spurs

Regulated Vdd
R3
Ref(t) Up(t) Vtune(t)
High
R1 R2
Gain
Div_4x(t) Phase Down(t)
Detector Cf
Vc1(t) C1 C2 C3
Gnd

Ref(t)
Div_4x(t)  Ripple from Up/Down
Up(t) pulses passes through
Down(t) to VCO tuning input
Vc1(t)

Is there an easy way to

reduce reference spurs?
Vtune(t)
67
 Leverage Multi-Phase Pulsing
Last(t)
Mid(t)
Regulated Vdd
R3/2 R3/2
Ref(t) Up(t) Vtune(t)
High
R1 R2/2 R2/2
Gain
Div_4x(t) Phase Down(t)
Detector Cf
Vc1(t) C1 C2 C3
Gnd

Ref(t)  Ripple from Up/Down pulses

Div_4x(t) blocked before reaching VCO
Up(t) - Reference spurs reduced!
Down(t) - Similar to sample-and-hold
Vc1(t) technique (such as Zhang et.
al., JSSC, 2003)
Mid(t)
Last(t) There is a nice side benefit
Vtune(t) to pulsing resistors…
68
Pulsing Resistor Multiplies Resistance!
Ton J. A. Kaehler, JSSC, Aug. 1969
and
P. Kurahashi, P. K. Hanumolu,
Tperiod G. C. Temes, and U.-K. Moon,
JSSC, Aug. 2007
Pulse_On(t)
Tperiod
R_eff = R
R/2 R/2 Ton

 Resistor only passes current when pulsed on

- Average current through resistance is reduced according
to ratio of On time, T , versus pulsing Period, T
- Effective resistance is actual resistance multiplied by ratio
on period

Tperiod/Ton

Resistor multiplication allows a large RC time constant

to be implemented with smaller area
69
Parasitic Capacitance Reduces Effective Resistance
Ton

Tperiod

Pulse_On(t)
Tperiod
R_eff < R
R/4 R/4 R/4 R/4 Ton

Cp Cp Cp Cp Cp Cp

 Parasitic capacitance stores charge during the pulse

“On” time
- Leads to non-zero current through resistor during pulse
Off time
- Effective resistance reduced
Spice simulation and measured results reveal that
>10X resistor multiplication can easily be achieved
70
 Multi-Modulus Divider Allows Short Pulse Generation
in(t)

out(t)
out(t) Latch Latch
out
D Q D Q

pulse_width_2x = 0 out(t) ck ck
clk
pulse_width_2x = 1 Latch Latch
Q D Q D modin
ck ck

con modout

pulse_width_2x
Divide-By-2/3 Stage Divide-By-2/3 Stage Divide-By-2/3 Stage
Vdd
in(t) clk out clk out clk out
modout modin modout modin modout modin
con con con

con0 con1 con2

 Creates well controlled pulse widths corresponding to

multiples of the period of its high speed input
- Standard circuit used in many fractional-N PLL structures
- Pulse width can be changed by tapping off different stages 71
 Utilize Short Pulses from Divider in the High Gain PD

Mid(t)

Down(t)

Up(t)

Last(t)
D Q D Q D Q D Q D Q Short Pulse
Ref(t) Generator
Q Q Q Q Q

Div_4x(t)

Ref(t)
 Short pulses from divider
Tref output are used to clock
Div_4x(t)
the PD registers
Up(t)  PD state is used to gate
Down(t) divider output every 4
Tdiv cycles to form Last pulse
Mid(t)

Last(t)
- Lower pulse frequencies
can also be implemented
72
 Switched Resistor Achieves PLL Zero with Low Area
Last(t)
Tperiod
Regulated Vdd Mid(t)
R3/2 R3/2
Up(t)
R1 R2/2 R2/2 Ton
Vtune(t)
Down(t)
Cf
Vc1(t) C1 C2 C3
Gnd

 For robust stability, PLL zero 1

wz =
1
should be set << PLL BW R3_eff Cf
- Example: PLL BW = 30kHz H(w)
Cf
- Assume desired w = 4 kHz Cf +C3
- Set C = 2.5pF (for low area)
z

- Required R = 16 MegaOhms
f

3_eff w
wz
 Large area
Example: Proper choice of Ton and Tperiod allows
R3_eff = 16 MegaOhms to be achieved with R3 = 500 kOhms!
73
 Overall Design of Loop Filter
R3_eff

Vlf(t) R1_eff R2_eff Vtune(t)

Cf
C1 C2 C3

PD Supply
Gain Gain H(s) VCO
Φref(t) α Vdd Vlf(t) Vtune(t) Φout(t)
1 + s/wz 2π Kv
2π 2 (1 + s/wp1)(1 + s/wp2)(1 + s/wp3) s

Φdiv(t)
1
Nnom
1
1 1
H(f) fz fp2
2πR3_effCf 2πβ1R1_effC1
Cf 1 1
Cf + C3 fp1 fp3
2πR3_eff(Cf +C3) 2πβ2R1_effC1
Overall PLL Unity Gain Examples: (assume C1 = C2)
Crossover Region
R2_eff = R1_eff β1=0.38, β2=2.62
f R2_eff = 2R1_eff β1=0.29, β2=1.7
fp1 fz fp2 fp3
 Apply standard transfer function analysis to achieve desired PLL
bandwidth and phase margin 74
Noise Analysis (Ignore Parasitic Capacitance of Resistors)

PD Supply 4kTR1_eff 4kTR2_eff 4kTR3_eff R3_eff

Gain Gain Vtune
Φref(t) 8 Vdd
R1_eff R2_eff
2π 2 Cf
C1 C2 C3
Voltage
Φdiv(t) Signal

 Assumption: switched resistor time constants are

much longer than “on time” of switches
- Single-sided voltage noise contributed by each resistor
is simply modeled as 4kTReff (same as for a resistor of
the equivalent value)
 Note: if switched resistor time constants are shorter
than “on time” of switches
- Resistors contribute kT/C noise instead of 4kTR
- We would not want to operate switched resistor filter in
eff

this domain since time constants would not be boosted

75
 Issue: Nonlinearity in Switched Resistor Loop Filter
Vdd
Ref(t) Up
Phase
R1 R2/2
Detector
& Down
Div_4x(t)
Pulse Gen Vc1 C1
Gnd

 Nonlinearity is caused by
- Exponential response of
Ref(t)

Div_4x(t)
RC filter to pulse width
Up modulation
Down
- Variation of Thold due to
Sigma-Delta dithering of
Ton Thold divide value
Tperiod  Note: to avoid additional
Vc1
Vc1[k-1] Vc1[k] Vc1[k+1] nonlinearity, design divide
value control logic to keep
Ton a constant value
76
 Nonlinearity Due to Pulse Width Modulation
Vdd
Ref(t) Up
Phase
R1 R2/2
Detector
& Down

Div_4x(t)
Pulse Gen Vc1 C1 Pulse width modulation
Gnd nonlinearity is reduced as
Ref(t) ratio T/(R1C1) is reduced
Div_4x(t) - If T/(R C ) is small:
1 1

Up

Down

Thold Ton
Ton/2+ΔT Ton/2-ΔT
- This implies nonlinearity
Vc1
is reduced with lower
Vc1[k-1] Vc1[k] PLL bandwidth

77
 Key Design Issue: Folded Noise versus Other Noise

Other PLL
Noise Sources

Folded Sigma-Delta
Quant Noise

Phase noise referred to

VCO carrier frequency

 Folded quantization noise due to nonlinearity is reasonably

below other noise sources for this example
- However, could be an issue for wide bandwidth PLLs
 Use (CppSim) behavioral simulation to evaluate this issue 78
 The Issue of Initial Frequency Acquisition

Regulated Vdd R3_eff = 16MegaOhms

Up(t)
R1 R2/2 R2/2
Vtune(t)
Down(t)
Cf
Vc1(t) C1 C2 C3 = 35pF
Gnd

 During initial frequency acquisition, Vtune(t) must be

charged to proper bias point
- Following through on previous example:
 Large 16 MegaOhm resistance of R3_eff prevents fast
settling of the voltage across C3

79
 Capacitive Divider Sets Instantaneous Voltage Range
Pulse_Last
Pulse_Mid
Vdd
Ref(t) R3/2 R3/2
Up Out
Phase
R1 R2/2 R2/2
Detector
& Down
Div_4x(t) Cf
Pulse Gen Vc1 C1 C2 C3
Gnd
Phase Detector and Supply Gain Characteristic
AC Gain
avg{Vc1(t)} α Vdd
gain = Cf
2π 2 =
Vdd C3+Cf Vdd
Instantaneous
Out range
Cf
= Vdd
C3+Cf
Gnd Φref-Φdiv Gnd

How do we quickly charge capacitor C3 to its correct

DC operating point during initial frequency acquisition?
80
 Utilize Switched Capacitor Charging Technique
Regulated Vdd
Up(t) R3/2 R3/2
Vtune(t)
R1 R2/2 R2/2 Vdd
Gnd
Down(t)
Cf
Vc1(t) C1 C2 C3 Cc
Gnd
Counter Count > 4 Charge Low
Count < 4 Charge High
Ref(t)
Div_4x(t) Connect

Ref(t)
Count
Charge Low(t)

Tdiv_4x Charge High(t)

Connect(t)
Tref
 Charge C3 high or low only when frequency error is detected
- No steady-state noise penalty, minimal power consumption 81
CppSim Behavioral Simulation of Frequency Locking
1

vtune
0.5

charge_high

charge_low

0
0 10 20 30 40 50 60 70 80 90 100
Time (microseconds)

Switched capacitor technique allows relatively

fast frequency locking 82
PLL Application: A MEMS-based Programmable Oscillator
Quartz Oscillators MEMS-based Oscillator

source: www.ecliptek.com

 A part for each frequency  Same part for all frequencies

and non-plastic packaging and plastic packaging
- Non-typical frequencies - Pick any frequency you want
require long lead times without extra lead time

We can achieve high volumes at low cost using IC fabrication

83
Architecture of MEMS-Based Programmable Oscillator

5 MHz 750-900 MHz 1 to 115 MHz

Oscillator Sustaining Programmable

Fractional-N
Circuit and Frequency
Synthesizer
Charge Pump Divider Continuously
Programmable
MEMS
Resonator
Digital
Frequency Setting
 MEMS device provides high Q resonance at 5 MHz
- CMOS circuits provide DC bias and sustaining amplifier
 Fractional-N synthesizer multiplies 5 MHz MEMS
reference to a programmable range of 750 to 900 MHz
 Programmable frequency divider enables 1 to 115 MHz
output 84
 Compensation of Temperature Variation
Freq Error (ppm) Freq Error (ppm)

Temp Temp
5 MHz 750-900 MHz

Oscillator Sustaining Programmable

Fractional-N
Circuit and Frequency
Synthesizer
Charge Pump Divider Continuously
Programmable
MEMS Freq Compensation (ppm) 1 to 115 MHz
Resonator
Temp
Temperature Digital
Sensor Logic

Digital
Frequency Setting
 High resolution control of fractional-N synthesizer allows
simple method of compensating for MEMS frequency
variation with temperature
- Simply add temperature sensor and digital compensation logic 85
 Why Use An Alternative Fractional-N PLL Structure?
Freq Error (ppm) Freq Error (ppm)

Temp Temp
5 MHz 750-900 MHz

Oscillator Sustaining Programmable

Fractional-N
Circuit and Frequency
Synthesizer
Charge Pump Divider Continuously
Programmable
MEMS Freq Compensation (ppm) 1 to 115 MHz
Resonator
Temp
Temperature Digital
Sensor Logic

Digital
Frequency Setting

Want to achieve low area, low power, and low design complexity
Switched resistor PLL provides a nice solution
for this application space
86
CMOS and MEMS Die Photos Show Low Area of PLL
 Active area:
- VCO & buffer & 2
bias: 0.25mm
- PLL (PFD, Loop
Filter, divider):
0.09 mm2
- Output divider:
0.02 mm2
 External supply
- 1.8/3.3V
 Current (20 MHz
output, no load)
- ALL: 3.2/3.7mA
- VCO: 1.3mA
- PLL & Output
Divider: 0.7mA 87
 Measured Phase Noise (100 MHz output)

Ref. Spur: -65 dBc

-90 dBc/Hz

-140 dBc/Hz
Integrated Phase Noise:
17 ps (rms) from 1 kHz to 40 MHz
100 Hz 30 kHz 40 MHz

 Suitable for most serial applications, embedded systems and

FPGAs, audio, USB 1.1 and 2.0, cameras, TVs, etc. 88
 Calculated Phase Noise Profile of Overall PLL
Calculated Phase Noise (100 MHz carrier)
-60
Integrated Phase Noise = 16.6 ps (rms) (1kHz to 40 MHz)
-70

-80

-90
Phase Noise (dBc/Hz)

MEMS
VCO
-100

-110 S-D

-120 Loop
Filter
-130

-140 Output
Buffer
-150

-160
100 1k 10k 100k 1M 10M 40M
Frequency Offset from Carrier (Hz)

 Note that loop filter noise is well below other PLL noise sources
89
Simulated Impact of Switched Resistor Nonlinearity
Simulated Phase Noise Impact of S-D Noise Folding (100 MHz carrier)

-90
Overall Phase Noise

-100
Phase Noise (dBc/Hz)

-110

-120
simulated
simulated

-130 ideal
ideal
3rd order S-D
-140 2nd order S-D

-150
1k 10k 100k 1M 3M
Frequency Offset from Carrier (Hz)
 Noise folding below other PLL noise sources
- More significant for third order Sigma-Delta 90
Frequency Variation After Single-Temperature Calibration
50

40
6600 Parts
Frequency V ariation (PPM)

30

20

10

-10

-20

-30

-40

-50
-50 0 50 100
Temperature (degC)

< +/-30 ppm across industrial temperature range

with single-temperature calibration 91
Conclusion

 We took a closer look at the classical charge pump PLL

- Very versatile structure
- Requires a fair amount of analog design effort
 Alternative PLL structures can provide low area, low
power, and reduced analog design effort
- High gain phase detector lowers impact of loop filter noise
- Switched resistor technique eliminates the charge pump
and reduces area through resistor multiplication
- Switched capacitor frequency detection enables reasonable
frequency acquisition time with no noise penalty

Application specific PLL structures can provide

worthwhile benefits over a classical analog PLL structure
92