M95320-125

Automotive 32-Kbit serial SPI bus EEPROM

with high-speed clock

Features
■ Compatible with the Serial Peripheral Interface
(SPI) bus
■ Memory array
s )
– 32 Kb (4 Kbytes) of EEPROM SO8 (MN)
c t(
■
– Page size: 32 bytes
Write
150 mil width

d u
– Byte Write within 5 ms
r o
– Page Write within 5 ms
e P
■ Write Protect: quarter, half or whole memory
array
le t
■

■
High-speed clock: 10 MHz
Single supply voltage: b so TSSOP8 (DW)
169 mil width

– 4.5 V to 5.5 V for M95320

- O
– 2.5 V to 5.5 V for M95320-W

( s )
ct
■ Operating temperature range: from -40°C up to
+125°C
■ Enhanced ESD protection
d u
■
r o
More than 1 million Write cycles
■
P
More than 40-year data retention

e
■ Packages

l e t
– RoHS compliant and halogen-free

s o
(ECOPACK®)

O b

January 2012 Doc ID 022583 Rev 1 1/38

www.st.com 1
M95320-125 Contents

Contents

1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1 Serial Data Output (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.2 Serial Data Input (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
s )
3.3
c t(
Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.4
d u
Chip Select (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.5
r o
Hold (HOLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.6 P
Write Protect (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
e
3.7
le t
VCC supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.8
o
VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
s
4 O b
Connecting to the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.1
) -
SPI modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

t ( s
5
u c
Operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.1
o d
Supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

P r 5.1.1 Operating supply voltage VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

e t e 5.1.2 Device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

o l 5.1.3 Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

bs
5.1.4 Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.2 Active Power and Standby Power modes . . . . . . . . . . . . . . . . . . . . . . . . . 14
O 5.3 Hold condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.4 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.5 Data protection and protocol control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

6 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.1 Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.2 Write Disable (WRDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.3 Read Status Register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.3.1 WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Doc ID 022583 Rev 1 2/38

 Contents M95320-125

6.3.2 WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

6.3.3 BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.3.4 SRWD bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.4 Write Status Register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.5 Read from Memory Array (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.6 Write to Memory Array (WRITE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

7 Power-up and delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

7.1 Power-up state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
s )
7.2
t(
Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
c
8
d u
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
r o
9 P
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
e
le t
10
o
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
s
11
O b
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

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12
s
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
t (
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 M95320-125 List of tables

List of tables

Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Table 2. Write-protected block size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 3. Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 4. Address range bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 5. Status Register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 6. Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 7. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 8. Operating conditions (M95320, device grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 9. Operating conditions (M95320-W, device grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

s )
t(
Table 10. AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 11. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 12.
u c
DC characteristics (M95320, device grade 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 13.
d
DC characteristics (M95320-W, device grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

o
Table 14.
Table 15.
Table 16.
r
AC characteristics (M95320, device grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

P
AC characteristics (M95320-W, device grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
SO8N – 8-lead plastic small outline, 150 mils body width, mechanical data . . . . . . . . . . . 34
Table 17.
t e
TSSOP8 – 8-lead thin shrink small outline, package mechanical data. . . . . . . . . . . . . . . . 35
Table 18.
Table 19.
o le
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

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 List of figures M95320-125

List of figures

Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 2. 8-pin package connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 4. Bus master and memory devices on the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 5. SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 6. Hold condition activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 7. Write Enable (WREN) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 8. Write Disable (WRDI) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 9. Read Status Register (RDSR) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

s )
t(
Figure 10. Write Status Register (WRSR) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 11. Read from Memory Array (READ) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 12.
u c
Byte Write (WRITE) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 13.
d
Page Write (WRITE) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

o
Figure 14.
Figure 15.
Figure 16.
r
AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

P
Serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 17.
t e
Serial output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 18.
Figure 19.
o le
SO8N – 8-lead plastic small outline, 150 mils body width, package outline . . . . . . . . . . . . 34
TSSOP8 – 8-lead thin shrink small outline, package outline . . . . . . . . . . . . . . . . . . . . . . . 35

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5/38 Doc ID 022583 Rev 1

 M95320-125 Description

1 Description

The M95320 devices are Electrically Erasable PROgrammable Memories (EEPROMs)

organized as 4096 x 8 bits, accessed through the SPI bus.
The M95320 devices can operate with a supply range from 2.5 V up to 5.5 V, and are
guaranteed over the -40 °C/+125 °C temperature range. They are compliant with the
Automotive standard AEC-Q100 Grade 1.

Figure 1. Logic diagram

VCC

s )
c t(
D Q
d u
C
r o
S M95xxx

e P
W
le t
HOLD
s o
O b
) - VSS

t ( s AI01789C

u c
The SPI bus signals are C, D and Q, as shown in Figure 1 and Table 1. The device is

d
selected when Chip Select (S) is driven low. Communications with the device can be
o
P
Table 1.
r
interrupted when the HOLD is driven low.

Signal names

e t e Signal name Function Direction

o l
b s C
D
Serial Clock
Serial Data Input
Input
Input

O Q
S
Serial Data Output
Chip Select
Output
Input
W Write Protect Input
HOLD Hold Input
VCC Supply voltage
VSS Ground

Doc ID 022583 Rev 1 6/38

 Description M95320-125

Figure 2. 8-pin package connections (top view)

M95xxx

S 1 8 VCC
Q 2 7 HOLD
W 3 6 C
VSS 4 5 D
AI01790D

1. See Section 10: Package mechanical data section for package dimensions, and how to identify pin 1.

s )
c t(
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e P
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O b
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7/38 Doc ID 022583 Rev 1

 M95320-125 Memory organization

2 Memory organization

The memory is organized as shown in the following figure.

Figure 3. Block diagram

HOLD
High voltage
W Control logic generator
S

s )
D
I/O shift register
ct(
Q

d u
r o
Address register
and counter
Data
register

e P
le t Status
Register

so
Size of the
read-only

O b EEPROM
area

) -
Y decoder

( s
u ct
o d
Pr
1 page

e t e
ol
X decoder

b s
O AI01272d

Doc ID 022583 Rev 1 8/38

 Signal description M95320-125

3 Signal description

During all operations, VCC must be held stable and within the specified valid range:
VCC(min) to VCC(max).
All of the input and output signals must be held high or low (according to voltages of VIH,
VOH, VIL or VOL, as specified in Section 9: DC and AC parameters). These signals are
described next.

3.1 Serial Data Output (Q)

s )
t(
This output signal is used to transfer data serially out of the device. Data is shifted out on the
falling edge of Serial Clock (C).

u c
o d
3.2 Serial Data Input (D)
P r
This input signal is used to transfer data serially into the device. It receives instructions,

t e
addresses, and the data to be written. Values are latched on the rising edge of Serial Clock
(C).

o le
3.3 Serial Clock (C) b s
- O
s )
This input signal provides the timing of the serial interface. Instructions, addresses, or data
present at Serial Data Input (D) are latched on the rising edge of Serial Clock (C). Data on
(
t
Serial Data Output (Q) change from the falling edge of Serial Clock (C).
c
d u
3.4
o
Chip Select (S)
r
P
When this input signal is high, the device is deselected and Serial Data Output (Q) is at high
e
l e t
impedance. The device is in the Standby Power mode, unless an internal Write cycle is in
progress. Driving Chip Select (S) low selects the device, placing it in the Active Power mode.

s o After power-up, a falling edge on Chip Select (S) is required prior to the start of any

O b instruction.

3.5 Hold (HOLD)

The Hold (HOLD) signal is used to pause any serial communications with the device without
deselecting the device.
During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data
Input (D) and Serial Clock (C) are Don’t Care.
To start the Hold condition, the device must be selected, with Chip Select (S) driven low.

9/38 Doc ID 022583 Rev 1

 M95320-125 Signal description

3.6 Write Protect (W)

The main purpose of this input signal is to freeze the size of the area of memory that is
protected against Write instructions (as specified by the values in the BP1 and BP0 bits of
the Status Register).
This pin must be driven either high or low, and must be stable during all Write instructions.

3.7 VCC supply voltage

VCC is the supply voltage.

s )
3.8 VSS ground
c t(
VSS is the reference for all signals, including the VCC supply voltage.
d u
r o
e P
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Doc ID 022583 Rev 1 10/38

 Connecting to the SPI bus M95320-125

4 Connecting to the SPI bus

All instructions, addresses and input data bytes are shifted in to the device, most significant
bit first. The Serial Data Input (D) is sampled on the first rising edge of the Serial Clock (C)
after Chip Select (S) goes low.
All output data bytes are shifted out of the device, most significant bit first. The Serial Data
Output (Q) is latched on the first falling edge of the Serial Clock (C) after the instruction
(such as the Read from Memory Array and Read Status Register instructions) have been
clocked into the device.

Figure 4. Bus master and memory devices on the SPI bus

s )
c t( VSS

d u VCC

r o
SPI Interface with
SDO
SDI
e P
(CPOL, CPHA) =
(0, 0) or (1, 1) SCK

le t
so
C Q D VCC C Q D VCC C Q D VCC

SPI Bus Master

O b VSS VSS VSS

) -
SPI Memory
Device
R SPI Memory
Device
R SPI Memory
Device
CS3 CS2 CS1

( s
u ct S W HOLD S W HOLD S W HOLD

o d
P r
e
AI12836b

l e t
1. The Write Protect (W) and Hold (HOLD) signals should be driven, high or low as appropriate.

s o Figure 4 shows an example of three memory devices connected to an SPI bus master. Only
one memory device is selected at a time, so only one memory device drives the Serial Data

O b Output (Q) line at a time. The other memory devices are high impedance.
The pull-up resistor R (represented in Figure 4) ensures that a device is not selected if the
Bus Master leaves the S line in the high impedance state.
In applications where the Bus Master may leave all SPI bus lines in high impedance at the
same time (for example, if the Bus Master is reset during the transmission of an instruction),
the clock line (C) must be connected to an external pull-down resistor so that, if all
inputs/outputs become high impedance, the C line is pulled low (while the S line is pulled
high): this ensures that S and C do not become high at the same time, and so, that the
tSHCH requirement is met. The typical value of R is 100 kΩ..

11/38 Doc ID 022583 Rev 1

 M95320-125 Connecting to the SPI bus

4.1 SPI modes

These devices can be driven by a microcontroller with its SPI peripheral running in either of
the following two modes:
● CPOL=0, CPHA=0
● CPOL=1, CPHA=1
For these two modes, input data is latched in on the rising edge of Serial Clock (C), and
output data is available from the falling edge of Serial Clock (C).
The difference between the two modes, as shown in Figure 5, is the clock polarity when the
bus master is in Stand-by mode and not transferring data:
● C remains at 0 for (CPOL=0, CPHA=0)

s )
t(
● C remains at 1 for (CPOL=1, CPHA=1)

Figure 5. SPI modes supported

u c
CPOL CPHA

o d
0 0 C
P r
t e
1 1 C
o le
b s
D MSB

- O
( s)
Q

c t MSB

d u AI01438B

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Doc ID 022583 Rev 1 12/38

 Operating features M95320-125

5 Operating features

5.1 Supply voltage (VCC)

5.1.1 Operating supply voltage VCC

Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage
within the specified [VCC(min), VCC(max)] range must be applied (see Operating conditions
in Section 9: DC and AC parameters). This voltage must remain stable and valid until the
end of the transmission of the instruction and, for a Write instruction, until the completion of
the internal write cycle (tW). In order to secure a stable DC supply voltage, it is

s )
t(
recommended to decouple the VCC line with a suitable capacitor (usually of the order of
10 nF to 100 nF) close to the VCC/VSS device pins.

u c
5.1.2 Device reset
o d
P r
In order to prevent erroneous instruction decoding and inadvertent Write operations during
power-up, a power-on-reset (POR) circuit is included. At power-up, the device does not

t e
respond to any instruction until VCC reaches the POR threshold voltage. This threshold is

and AC parameters).
o le
lower than the minimum VCC operating voltage (see Operating conditions in Section 9: DC

b s
At power-up, when VCC passes over the POR threshold, the device is reset and is in the
following state:
● in Standby Power mode,
- O
● deselected,
( s )
●
c t
Status Register values:
–
u
The Write Enable Latch (WEL) bit is reset to 0.
d
–
r o
The Write In Progress (WIP) bit is reset to 0.

e P
– The SRWD, BP1 and BP0 bits remain unchanged (non-volatile bits).
It is important to note that the device must not be accessed until VCC reaches a valid and

l e t
stable level within the specified [VCC(min), VCC(max)] range, as defined under Operating
conditions in Section 9: DC and AC parameters.

s o
O b
5.1.3 Power-up conditions
When the power supply is turned on, VCC rises continuously from VSS to VCC. During this
time, the Chip Select (S) line is not allowed to float but should follow the VCC voltage. It is
therefore recommended to connect the S line to VCC via a suitable pull-up resistor (see
Figure 4).
In addition, the Chip Select (S) input offers a built-in safety feature, as the S input is edge-
sensitive as well as level-sensitive: after power-up, the device does not become selected
until a falling edge has first been detected on Chip Select (S). This ensures that Chip Select
(S) must have been high, prior to going low to start the first operation.
The VCC voltage has to rise continuously from 0 V up to the minimum VCC operating voltage
defined under Operating conditions in Section 9: DC and AC parameters, and the rise time
must not vary faster than 1 V/µs.

13/38 Doc ID 022583 Rev 1

 M95320-125 Operating features

5.1.4 Power-down
During power-down (continuous decrease of the VCC supply voltage below the minimum
VCC operating voltage defined under Operating conditions in Section 9: DC and AC
parameters), the device must be:
● deselected (Chip Select S should be allowed to follow the voltage applied on VCC),
● in Standby Power mode (there should not be any internal write cycle in progress).

5.2 Active Power and Standby Power modes

When Chip Select (S) is low, the device is selected, and in the Active Power mode. The
device consumes ICC.
s )
When Chip Select (S) is high, the device is deselected. If a Write cycle is not currently in
c t(
progress, the device then goes into the Standby Power mode, and the device consumption
drops to ICC1, as specified in DC characteristics (see Section 9: DC and AC parameters).
d u
r o
5.3 Hold condition
e P
le t
The Hold (HOLD) signal is used to pause any serial communications with the device without
resetting the clocking sequence.
s o
O b
To enter the Hold condition, the device must be selected, with Chip Select (S) low.
During the Hold condition, the Serial Data Output (Q) is high impedance, and the Serial

) -
Data Input (D) and the Serial Clock (C) are Don’t Care.

( s
Normally, the device is kept selected for the whole duration of the Hold condition.
t
u c
Deselecting the device while it is in the Hold condition has the effect of resetting the state of
the device, and this mechanism can be used if required to reset any processes that had
d
been in progress.(a)(b)
o
P r
Figure 6. Hold condition activation

e t e
o l C

b s
O HOLD

Hold Hold
Condition Condition

AI02029D

The Hold condition starts when the Hold (HOLD) signal is driven low when Serial Clock (C)
is already low (as shown in Figure 6).

a. This resets the internal logic, except the WEL and WIP bits of the Status Register.
b. In the specific case where the device has shifted in a Write command (Inst + Address + data bytes, each data
byte being exactly 8 bits), deselecting the device also triggers the Write cycle of this decoded command.

Doc ID 022583 Rev 1 14/38

 Operating features M95320-125

The Hold condition ends when the Hold (HOLD) signal is driven high when Serial Clock (C)
is already low.
Figure 6 also shows what happens if the rising and falling edges are not timed to coincide
with Serial Clock (C) being low.

5.4 Status Register

The Status Register contains a number of status and control bits that can be read or set (as
appropriate) by specific instructions. See Section 6.3: Read Status Register (RDSR) for a
detailed description of the Status Register bits.

s )
5.5 Data protection and protocol control
c t(
The device features the following data protection mechanisms:
d u
●
o
Before accepting the execution of the Write and Write Status Register instructions, the
r
device checks whether the number of clock pulses comprised in the instructions is a
multiple of eight.
e P
●
t
All instructions that modify data must be preceded by a Write Enable (WREN)

le
instruction to set the Write Enable Latch (WEL) bit.
●
s o
The Block Protect (BP1, BP0) bits in the Status Register are used to configure part of

●
the memory as read-only.

O b
The Write Protect (W) signal is used to protect the Block Protect (BP1, BP0) bits in the
Status Register.
) -
( s
For any instruction to be accepted, and executed, Chip Select (S) must be driven high after
t
the rising edge of Serial Clock (C) for the last bit of the instruction, and before the next rising

u
edge of Serial Clock (C). c
o d
Two points should be noted in the previous sentence:
●
P r
The “last bit of the instruction” can be the eighth bit of the instruction code, or the eighth
bit of a data byte, depending on the instruction (except for Read Status Register

e t e (RDSR) and Read (READ) instructions).

o l ● The “next rising edge of Serial Clock (C)” might (or might not) be the next bus
transaction for some other device on the SPI bus.

b s
O Table 2. Write-protected block size
Status Register bits
Protected block Protected array addresses
BP1 BP0

0 0 none none
0 1 Upper quarter 0C00h - 0FFFh
1 0 Upper half 0800h - 0FFFh
1 1 Whole memory 0000h - 0FFFh

15/38 Doc ID 022583 Rev 1

 M95320-125 Instructions

6 Instructions

Each instruction starts with a single-byte code, as summarized in Table 3.

If an invalid instruction is sent (one not contained in Table 3), the device automatically
deselects itself.

Table 3. Instruction set

Instruction Description Instruction format

WREN Write Enable 0000 0110

WRDI Write Disable 0000 0100
s )
RDSR Read Status Register 0000 0101
c t(
WRSR Write Status Register
u
0000 0001

d
ro
READ Read from Memory Array 0000 0011

eP
WRITE Write to Memory Array 0000 0010

Table 4. Address range bits

l e t
Address significant bits
s o A11-A0(1)
1. Upper MSBs are Don’t Care.

O b
) -
(s
6.1 Write Enable (WREN)

c t
The Write Enable Latch (WEL) bit must be set prior to each WRITE and WRSR instruction.
u
The only way to do this is to send a Write Enable instruction to the device.
d
r o
As shown in Figure 7, to send this instruction to the device, Chip Select (S) is driven low,

P
and the bits of the instruction byte are shifted in, on Serial Data Input (D). The device then
enters a wait state. It waits for the device to be deselected, by Chip Select (S) being driven
e
l e thigh.

s o Figure 7. Write Enable (WREN) sequence

O b S

0 1 2 3 4 5 6 7

Instruction

High Impedance
Q
AI02281E

Doc ID 022583 Rev 1 16/38

 Instructions M95320-125

6.2 Write Disable (WRDI)

One way of resetting the Write Enable Latch (WEL) bit is to send a Write Disable instruction
to the device.
As shown in Figure 8, to send this instruction to the device, Chip Select (S) is driven low,
and the bits of the instruction byte are shifted in, on Serial Data Input (D).
The device then enters a wait state. It waits for a the device to be deselected, by Chip Select
(S) being driven high.
The Write Enable Latch (WEL) bit, in fact, becomes reset by any of the following events:
● Power-up
● WRDI instruction execution
s )
●
●
WRSR instruction completion
WRITE instruction completion.
ct(
d u
Figure 8. Write Disable (WRDI) sequence
r o
S

e P
0 1 2 3 4 5

le
6
t 7

s o
D
O b
Instruction

) -
Q
t ( s High Impedance

u c AI03750D

o d
P r
e t e
o l
b s
O

17/38 Doc ID 022583 Rev 1

M95320-125 Instructions

6.3 Read Status Register (RDSR)

The Read Status Register (RDSR) instruction is used to read the Status Register. The
Status Register may be read at any time, even while a Write or Write Status Register cycle
is in progress. When one of these cycles is in progress, it is recommended to check the
Write In Progress (WIP) bit before sending a new instruction to the device. It is also possible
to read the Status Register continuously, as shown in Figure 9.

Figure 9. Read Status Register (RDSR) sequence

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

s )
t(
C

Instruction

u c
D

o d
Q
High Impedance
Status Register Out

P r
Status Register Out

e
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7

MSB

le t MSB

so
AI02031E

b
The status and control bits of the Status Register are as follows:
O
6.3.1 WIP bit
) -
( s
ct
The Write In Progress (WIP) bit indicates whether the memory is busy with a Write or Write
Status Register cycle. When set to 1, such a cycle is in progress, when reset to 0, no such
u
cycle is in progress.
d
6.3.2 WEL bit r o
e P
The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.

l e t
When set to 1, the internal Write Enable Latch is set. When set to 0, the internal Write

o Enable Latch is reset, and no Write or Write Status Register instruction is accepted.

Obs The WEL bit is returned to its reset state by the following events:
● Power-up
● Write Disable (WRDI) instruction completion
● Write Status Register (WRSR) instruction completion
● Write (WRITE) instruction completion

6.3.3 BP1, BP0 bits

The Block Protect (BP1, BP0) bits are non volatile. They define the size of the area to be
software-protected against Write instructions. These bits are written with the Write Status
Register (WRSR) instruction. When one or both of the Block Protect (BP1, BP0) bits is set
to 1, the relevant memory area (as defined in Table 5) becomes protected against Write
(WRITE) instructions. The Block Protect (BP1, BP0) bits can be written provided that the
Hardware Protected mode has not been set.

Doc ID 022583 Rev 1 18/38

 Instructions M95320-125

6.3.4 SRWD bit

The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write
Protect (W) signal. The Status Register Write Disable (SRWD) bit and Write Protect (W)
signal enable the device to be put in the Hardware Protected mode (when the Status
Register Write Disable (SRWD) bit is set to 1, and Write Protect (W) is driven low). In this
mode, the non-volatile bits of the Status Register (SRWD, BP1, BP0) become read-only bits
and the Write Status Register (WRSR) instruction is no longer accepted for execution.

Table 5. Status Register format

b7 b0
SRWD 0 0 0 BP1 BP0 WEL WIP

s )
Status Register Write Protect
c t(
Block Protect bits
d u
r o
Write Enable Latch bit

e P Write In Progress bit

le t
s o
O b
) -
t ( s
u c
o d
P r
e t e
o l
b s
O

19/38 Doc ID 022583 Rev 1

M95320-125 Instructions

6.4 Write Status Register (WRSR)

The Write Status Register (WRSR) instruction is used to write new values to the Status
Register. Before it can be accepted, a Write Enable (WREN) instruction must have been
previously executed.
The Write Status Register (WRSR) instruction is entered by driving Chip Select (S) low,
followed by the instruction code, the data byte on Serial Data input (D) and Chip Select (S)
driven high. Chip Select (S) must be driven high after the rising edge of Serial Clock (C) that
latches in the eighth bit of the data byte, and before the next rising edge of Serial Clock (C).
Otherwise, the Write Status Register (WRSR) instruction is not executed.
The instruction sequence is shown in Figure 10.

s )
t(
Figure 10. Write Status Register (WRSR) sequence

S
u c
o d
C
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

P r
Instruction
t e Status

o le Register In

D
b s 7 6 5 4 3 2 1 0

-O
High Impedance MSB
Q

( s ) AI02282D

c t
Driving the Chip Select (S) signal high at a byte boundary of the input data triggers the self-

d u
timed Write cycle that takes tW to complete (as specified in AC tables under Section 9: DC

o
and AC parameters).
r
e P
While the Write Status Register cycle is in progress, the Status Register may still be read to
check the value of the Write in progress (WIP) bit: the WIP bit is 1 during the self-timed

e t Write cycle tW, and 0 when the Write cycle is complete. The WEL bit (Write Enable Latch) is

ol
also reset at the end of the Write cycle tW.

bs
The Write Status Register (WRSR) instruction enables the user to change the values of the
BP1, BP0 and SRWD bits:
O ● The Block Protect (BP1, BP0) bits define the size of the area that is to be treated as
read-only, as defined in Table 2.
● The SRWD (Status Register Write Disable) bit, in accordance with the signal read on
the Write Protect pin (W), enables the user to set or reset the Write protection mode of
the Status Register itself, as defined in Table 6. When in Write-protected mode, the
Write Status Register (WRSR) instruction is not executed.
The contents of the SRWD and BP1, BP0 bits are updated after the completion of the
WRSR instruction, including the tW Write cycle.
The Write Status Register (WRSR) instruction has no effect on the b6, b5, b4, b1, b0 bits in
the Status Register. Bits b6, b5, b4 are always read as 0.

Doc ID 022583 Rev 1 20/38

 Instructions M95320-125

Table 6. Protection modes

Memory content
W SRWD Write protection of the
Mode
signal bit Status Register
Protected area(1) Unprotected area(1)

1 0 Status Register is
writable (if the WREN
0 0
Software- instruction has set the
Ready to accept
protected WEL bit). Write-protected
Write instructions
(SPM) The values in the BP1
1 1
and BP0 bits can be
changed.
Status Register is

s )
t(
Hardware write-
Hardware-
protected. Ready to accept
0 1 protected
(HPM)
The values in the BP1
Write-protected

u c
Write instructions
and BP0 bits cannot be
changed.
o d
P r
1. As defined by the values in the Block Protect (BP1, BP0) bits of the Status Register. See Table 2.

t e
le
The protection features of the device are summarized in Table 6.

s o
When the Status Register Write Disable (SRWD) bit in the Status Register is 0 (its initial
delivery state), it is possible to write to the Status Register (provided that the WEL bit has

Write Protect (W) input pin. O b

previously been set by a WREN instruction), regardless of the logic level applied on the

) -
When the Status Register Write Disable (SRWD) bit in the Status Register is set to 1, two

t ( s
cases should be considered, depending on the state of the Write Protect (W) input pin:
●
c
If Write Protect (W) is driven high, it is possible to write to the Status Register (provided
u
that the WEL bit has previously been set by a WREN instruction).
●
o d
If Write Protect (W) is driven low, it is not possible to write to the Status Register even if

P r
the WEL bit has previously been set by a WREN instruction. (Attempts to write to the
Status Register are rejected, and are not accepted for execution). As a consequence,

e t e all the data bytes in the memory area, which are Software-protected (SPM) by the

o l Block Protect (BP1, BP0) bits in the Status Register, are also hardware-protected
against data modification.

b s Regardless of the order of the two events, the Hardware-protected mode (HPM) can be

O entered by:
● either setting the SRWD bit after driving the Write Protect (W) input pin low,
● or driving the Write Protect (W) input pin low after setting the SRWD bit.
Once the Hardware-protected mode (HPM) has been entered, the only way of exiting it is to
pull high the Write Protect (W) input pin.
If the Write Protect (W) input pin is permanently tied high, the Hardware-protected mode
(HPM) can never be activated, and only the Software-protected mode (SPM), using the
Block Protect (BP1, BP0) bits in the Status Register, can be used.

21/38 Doc ID 022583 Rev 1

 M95320-125 Instructions

6.5 Read from Memory Array (READ)

As shown in Figure 11, to send this instruction to the device, Chip Select (S) is first driven
low. The bits of the instruction byte and address bytes are then shifted in, on Serial Data
Input (D). The address is loaded into an internal address register, and the byte of data at
that address is shifted out, on Serial Data Output (Q).

Figure 11. Read from Memory Array (READ) sequence

0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30 31

C
s )
Instruction 16-Bit Address
c t(
d u
D 15 14 13 3 2 1 0

r o
High Impedance
MSB

e P
Data Out 1 Data Out 2

Q 7

le
MSB
t
6 5 4 3 2 1 0 7

s o AI01793D

O b
1. Depending on the memory size, as shown in Table 4, the most significant address bits are Don’t Care.

) -
If Chip Select (S) continues to be driven low, the internal address register is incremented
automatically, and the byte of data at the new address is shifted out.

t ( s
When the highest address is reached, the address counter rolls over to zero, allowing the

u c
Read cycle to be continued indefinitely. The whole memory can, therefore, be read with a

d
single READ instruction.

o
P r
The Read cycle is terminated by driving Chip Select (S) high. The rising edge of the Chip
Select (S) signal can occur at any time during the cycle.

e t e
The instruction is not accepted, and is not executed, if a Write cycle is currently in progress.

o l
6.6
b s Write to Memory Array (WRITE)
O As shown in Figure 12, to send this instruction to the device, Chip Select (S) is first driven
low. The bits of the instruction byte, address byte, and at least one data byte are then shifted
in, on Serial Data Input (D).
The instruction is terminated by driving Chip Select (S) high at a byte boundary of the input
data. The self-timed Write cycle, triggered by the Chip Select (S) rising edge, continues for a
period tW (as specified in AC characteristics in Section 9: DC and AC parameters), at the
end of which the Write in Progress (WIP) bit is reset to 0.

Doc ID 022583 Rev 1 22/38

 Instructions M95320-125

Figure 12. Byte Write (WRITE) sequence

0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30 31

Instruction 16-Bit Address Data Byte

D 15 14 13 3 2 1 0 7 6 5 4 3 2 1 0

Q
High Impedance

s )
c t(
d u AI01795D

r o
1. Depending on the memory size, as shown in Table 4, the most significant address bits are Don’t Care.
In the case of Figure 12, Chip Select (S) is driven high after the eighth bit of the data byte
P
has been latched in, indicating that the instruction is being used to write a single byte.
e
le t
However, if Chip Select (S) continues to be driven low, as shown in Figure 13, the next byte
of input data is shifted in, so that more than a single byte, starting from the given address

o
towards the end of the same page, can be written in a single internal Write cycle.
s
O b
Each time a new data byte is shifted in, the least significant bits of the internal address
counter are incremented. If the number of data bytes sent to the device exceeds the page

) -
boundary, the internal address counter rolls over to the beginning of the page, and the
previous data there are overwritten with the incoming data. (The page size of these devices
is 32 bytes).
t ( s
c
The instruction is not accepted, and is not executed, under the following conditions:
u
●
d
if the Write Enable Latch (WEL) bit has not been set to 1 (by executing a Write Enable
o
●
P r
instruction just before),
if a Write cycle is already in progress,
●

e t e
if the device has not been deselected, by driving high Chip Select (S), at a byte
boundary (after the eighth bit, b0, of the last data byte that has been latched in),

o l ● if the addressed page is in the region protected by the Block Protect (BP1 and BP0)

b s bits.

ONote: The self-timed write cycle tW is internally executed as a sequence of two consecutive
events: [Erase addressed byte(s)], followed by [Program addressed byte(s)]. An erased bit is
read as “0” and a programmed bit is read as “1”.

23/38 Doc ID 022583 Rev 1

 M95320-125 Instructions

Figure 13. Page Write (WRITE) sequence

0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30 31

Instruction 16-Bit Address Data Byte 1

D 15 14 13 3 2 1 0 7 6 5 4 3 2 1 0

s )
S
c t(
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
d u
C
r o
Data Byte 2 Data Byte 3

e P Data Byte N

le t
so
D 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 6 5 4 3 2 1 0

Ob
AI01796D

-
1. Depending on the memory size, as shown in Table 4, the most significant address bits are Don’t Care.

)
c t (s
d u
r o
e P
l e t
s o
O b

Doc ID 022583 Rev 1 24/38

 Power-up and delivery state M95320-125

7 Power-up and delivery state

7.1 Power-up state

After power-up, the device is in the following state:
● Standby power mode,
● deselected (after power-up, a falling edge is required on Chip Select (S) before any
instructions can be started),
● not in the Hold condition,
● the Write Enable Latch (WEL) is reset to 0,
● Write In Progress (WIP) is reset to 0.
s )
c
The SRWD, BP1 and BP0 bits of the Status Register are unchanged from the previous t(
power-down (they are non-volatile bits).
d u
r o
7.2 Initial delivery state
e P
le t
The device is delivered with the memory array set to all 1s (each byte = FFh). The Status
Register Write Disable (SRWD) and Block Protect (BP1 and BP0) bits are initialized to 0.

s o
O b
) -
t ( s
u c
o d
P r
e t e
o l
b s
O

25/38 Doc ID 022583 Rev 1

 M95320-125 Maximum rating

8 Maximum rating

Stressing the device outside the ratings listed in Table 7 may cause permanent damage to
the device. These are stress ratings only, and operation of the device at these, or any other
conditions outside those indicated in the operating sections of this specification, is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.

Table 7. Absolute maximum ratings

Symbol Parameter Min. Max. Unit

Ambient operating temperature –40 130

( s )°C
TSTG Storage temperature –65
c t
150 °C
TLEAD Lead temperature during soldering See
d u
note (1) °C
VO Output voltage
o
–0.50
r
VCC+0.6 V

eP
VI Input voltage –0.50 6.5 V

let
VCC Supply voltage –0.50 6.5 V
IOL DC output current (Q = 0) 5 mA
IOH DC output current (Q = 1)
s o 5 mA
VESD b
Electrostatic discharge voltage (human body
O
model)(2) 4000 V

) -
1. Compliant with JEDEC Std J-STD-020 (for small body, Sn-Pb or Pb assembly), with the ST ECOPACK®
7191395 specification, and with the European directive on Restrictions on Hazardous Substances (RoHS)
2002/95/EU.

t ( s
2. Positive and negative pulses applied on pin pairs, according to AEC-Q100-002 (compliant with JEDEC Std

c
JESD22-A114, C1=100 pF, R1=1500 Ω, R2=500 Ω).

u
o d
P r
e t e
o l
b s
O

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 DC and AC parameters M95320-125

9 DC and AC parameters

This section summarizes the operating conditions and the DC/AC characteristics of the
device.

Table 8. Operating conditions (M95320, device grade 3)

Symbol Parameter Min. Max. Unit

VCC Supply voltage 4.5 5.5 V

TA Ambient operating temperature –40 125 °C

s )
Table 9. Operating conditions (M95320-W, device grade 3)
c t(
Symbol Parameter Min.

d u Max. Unit

ro
VCC Supply voltage 2.5 5.5 V

eP
TA Ambient operating temperature –40 125 °C

Table 10. AC measurement conditions

l e t
o
bs
Symbol Parameter Min. Max. Unit

-O
CL Load capacitance 30 pF
Input rise and fall times 25 ns

( s )
Input pulse voltages 0.2 VCC to 0.8 VCC V

u ct
Input and output timing reference voltages 0.3 VCC to 0.7 VCC V

o d
P r
Figure 14. AC measurement I/O waveform
)NPUT VOLTAGE LEVELS )NPUT AND OUTPUT

e te TIMING REFERENCE LEVELS

o l  6##
 6##

b s  6##
O  6##

!)#

Table 11. Capacitance

Symbol Parameter Test condition(1) Min. Max. Unit

COUT Output capacitance (Q) VOUT = 0 V 8 pF

Input capacitance (D) VIN = 0 V 8 pF
CIN
Input capacitance (other pins) VIN = 0 V 6 pF
1. Sampled only, not 100% tested, at TA = 25 °C and a frequency of 5 MHz.

27/38 Doc ID 022583 Rev 1

 M95320-125 DC and AC parameters

Table 12. DC characteristics (M95320, device grade 3)

Symbol Parameter Test conditions Min. Max. Unit

Input leakage
ILI VIN = VSS or VCC ±2 µA
current
Output leakage
ILO S = VCC, VOUT = VSS or VCC ±2 µA
current
C = 0.1 VCC/0.9 VCC at 5 MHz,
4
VCC = 5 V, Q = open
ICC Supply current mA
C = 0.1 VCC/0.9 VCC at 10 MHz,
8
VCC = 5 V, Q = open
Supply current
s )
t(
ICC1 S = VCC, VCC = 5 V, VIN = VSS or VCC 5 µA
(Standby)
VIL Input low voltage –0.45
u c 0.3 VCC V
VIH Input high voltage
o d
0.7 VCC VCC+1 V
VOL (1) Output low voltage IOL = 2 mA, VCC = 5 V
P r 0.4 V
VOH(1) Output high voltage IOH = –2 mA, VCC = 5 V

e t e 0.8 VCC V

ol
Internal reset
VRES(2) 2.5 4.0 V
threshold voltage

b s
1. For all 5 V range devices, the device meets the output requirements for both TTL and CMOS standards.

O
2. Characterized only, not tested in production.

-
(s )
c t
d u
r o
e P
l e t
s o
O b

Doc ID 022583 Rev 1 28/38

 DC and AC parameters M95320-125

Table 13. DC characteristics (M95320-W, device grade 3)

Symbol Parameter Test conditions Min. Max. Unit

Input leakage
ILI VIN = VSS or VCC ±2 µA
current
Output leakage
ILO S = VCC, VOUT = VSS or VCC ±2 µA
current
fC = 5 MHz, VCC = 2.5 V,
3
Supply current C = 0.1 VCC/0.9 VCC, Q = open
ICC mA
(Read) fC = 10 MHz, VCC = 2.5 V,
6
C = 0.1 VCC/0.9 VCC, Q = open
Supply current During tW, S = VCC,
s )
t(
ICC0(1) 6 mA
(Write) 2.5 V < VCC < 5.5 V

ICC1
Supply current
S = VCC, VCC = 2.5 V, VIN = VSS or VCC
u c 2 µA
(Standby)

o d
VIH
VIL Input low voltage
Input high voltage P r –0.45 V
0.7 VCC
0.3 VCC
VCC+1
V
V

t e
le
VOL Output low voltage IOL = 1.5 mA, VCC = 2.5 V 0.4 V

so
VOH Output high voltage IOH = –0.4 mA, VCC = 2.5 V 0.8 VCC V

Ob
Internal reset
VRES(1) 1.0 1.65 V
threshold voltage

-
1. Characterized only, not tested in production.

)
c t (s
d u
r o
e P
l e t
s o
O b

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 M95320-125 DC and AC parameters

Table 14. AC characteristics (M95320, device grade 3)

Test conditions specified in Table 8 and Table 10

Symbol Alt. Parameter Min.(1) Max.(1) Min.(2) Max.(2) Unit

fC fSCK Clock frequency D.C. 5 D.C. 10 MHz

tSLCH tCSS1 S active setup time 90 30 ns
tSHCH tCSS2 S not active setup time 90 30 ns
tSHSL tCS S deselect time 100 40 ns
tCHSH tCSH S active hold time 90 30 ns
tCHSL S not active hold time 90 30
s )
ns
tCH(3) tCLH Clock high time 90 42

c t( ns
tCL(3)
(4)
tCLL Clock low time 90 40

d u ns
tCLCH
tCHCL (4)
tRC
tFC
Clock rise time
Clock fall time
1
1 r o 2
2
µs
µs
tDVCH tDSU Data in setup time 20
e P 10 ns

e t
ol
tCHDX tDH Data in hold time 30 10 ns
tHHCH Clock low hold time after HOLD not active 70 30 ns
tHLCH Clock low hold time after HOLD active
b s 40 30 ns
tCLHL
-
Clock low set-up time before HOLD active O 0 0 ns
tCLHH

(s )
Clock low set-up time before HOLD not active 0 0 ns

ct
tSHQZ(4) tDIS Output disable time 100 40 ns

du
tCLQV(5) tV Clock low to output valid 60 40 ns
tCLQX
(4)
tHO

r o
Output hold time 0 0 ns
tQLQH tRO
P
Output rise time 50 40 ns

ete
tQHQL(4) tFO Output fall time 50 40 ns

ol
tHHQV tLZ HOLD high to output valid 50 40 ns
(4)

b s
tHLQZ
tW
tHZ
tWC
HOLD low to output high-Z
Write time
100
5
40
5
ns
ms

O1. These timings are offered with grade 3 devices referenced with “/P” process letters only (see the last digits in Part
numbering).
2. These timings are offered with grade 3 devices referenced with “/PC” process letters only (see the last digits in Part
numbering).
3. tCH + tCL must never be lower than the shortest possible clock period, 1/fC(max).
4. Characterized only, not tested in production.
5. tCLQV must be compatible with tCL (clock low time): if the SPI bus master offers a Read setup time tSU = 0 ns, tCL can be
equal to (or greater than) tCLQV; in all other cases, tCL must be equal to (or greater than) tCLQV+tSU.

Doc ID 022583 Rev 1 30/38

DC and AC parameters M95320-125

Table 15. AC characteristics (M95320-W, device grade 3)

Test conditions specified in Table 9 and Table 10

Min. Max. Min. Max.

Symbol Alt. Parameter Unit
2.5 V to 5.5 V(1) 3.0 V to 5.5 V(2)

fC fSCK Clock frequency D.C. 5 D.C. 10 MHz

tSLCH tCSS1 S active setup time 90 30 ns
tSHCH tCSS2 S not active setup time 90 30 ns
tSHSL tCS S deselect time 100 40 ns
tCHSH tCSH S active hold time 90 30
s )
ns

t(
uc
tCHSL S not active hold time 90 30 ns
tCH (3) tCLH Clock high time 90 42 ns
tCL(3) tCLL Clock low time 90
o d
40 ns
r
eP
tCLCH(4) tRC Clock rise time 1 2 µs

let
tCHCL(4) tFC Clock fall time 1 2 µs
tDVCH tDSU Data in setup time 20 10 ns
tCHDX tDH Data in hold time
s o 30 10 ns
tHHCH Clock low hold time after HOLD not active
O b 70 30 ns
tHLCH

) -
Clock low hold time after HOLD active 40 30 ns

t(s
tCLHL Clock low set-up time before HOLD active 0 0 ns

uc
tCLHH Clock low set-up time before HOLD not active 0 0 ns
(4)
tSHQZ tDIS Output disable time 100 40 ns
tCLQV(5)
o d
tCLQX
tV
tHO
P r
Clock low to output valid
Output hold time 0
60
0
40 ns
ns

e
let
tQLQH(4) tRO Output rise time 50 40 ns
tQHQL(4) tFO Output fall time 50 40 ns

s o
tHHQV tLZ HOLD high to output valid 50 40 ns

Ob tHLQZ(4) tHZ HOLD low to output high-Z 100 40 ns

tW tWC Write time 5 5 ms
1. These timings are offered with grade 3 devices referenced with “/P” process letters only (see the last digits in Part
numbering).
2. These timings are offered with grade 3 devices referenced with “/PC” process letters only (see the last digits in Part
numbering).
3. tCH + tCL must never be lower than the shortest possible clock period, 1/fC(max).
4. Value guaranteed by characterization, not 100% tested in production.
5. tCLQV must be compatible with tCL (clock low time): if the SPI bus master offers a Read setup time tSU = 0 ns, tCL can be
equal to (or greater than) tCLQV; in all other cases, tCL must be equal to (or greater than) tCLQV+tSU.

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 M95320-125 DC and AC parameters

Figure 15. Serial input timing

tSHSL

tCHSL tSLCH tCH tCHSH tSHCH

tDVCH tCHCL tCL tCLCH

tCHDX

D MSB IN LSB IN

s )
Q
High impedance

c t(
d u AI01447d

r o
Figure 16. Hold timing

e P
le t
S

s o
b tHLCH

-O
tCLHL tHHCH

( s )
ct
tCLHH

tHLQZ tHHQV

Q
d u
r o
e P
HOLD

l e t AI01448c

s o
O b

Doc ID 022583 Rev 1 32/38

 DC and AC parameters M95320-125

Figure 17. Serial output timing

tCH tSHSL

tCLQV tCLCH tCHCL tCL tSHQZ

tCLQX

tQLQH
tQHQL

s )
ADDR
D LSB IN

c t(
d u AI01449f

r o
e P
le t
s o
O b
) -
t ( s
u c
o d
P r
e t e
o l
b s
O

33/38 Doc ID 022583 Rev 1

 M95320-125 Package mechanical data

10 Package mechanical data

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.

Figure 18. SO8N – 8-lead plastic small outline, 150 mils body width, package outline
h x 45˚

A2 A

ccc
c

s )
t(
b
e

0.25 mm
u c
D GAUGE PLANE

o d
8

P r k

1
E1 E

t e
L

le
A1
L1

s o
b
SO-A

1. Drawing is not to scale.

- O
Table 16.

( s )
SO8N – 8-lead plastic small outline, 150 mils body width, mechanical data
inches(1)
Symbol
c t millimeters

du
Typ Min Max Typ Min Max

ro
A 1.750 0.0689

e P
A1
A2
0.100
1.250
0.250 0.0039
0.0492
0.0098

l e t b 0.280 0.480 0.0110 0.0189

s o c 0.170 0.230 0.0067 0.0091

O b ccc
D 4.900 4.800
0.100
5.000 0.1929 0.1890
0.0039
0.1969
E 6.000 5.800 6.200 0.2362 0.2283 0.2441
E1 3.900 3.800 4.000 0.1535 0.1496 0.1575
e 1.270 - - 0.0500 - -
h 0.250 0.500 0.0098 0.0197
k 0° 8° 0° 8°
L 0.400 1.270 0.0157 0.0500
L1 1.040 0.0409
1. Values in inches are converted from mm and rounded to four decimal digits.

Doc ID 022583 Rev 1 34/38

Package mechanical data M95320-125

Figure 19. TSSOP8 – 8-lead thin shrink small outline, package outline
D

8 5
c

E1 E

1 4

s )
A A2
A1 L

c t(
CP L1

d u
b e

r o TSSOP8AM

1. Drawing is not to scale.

e P
Table 17.
le t
TSSOP8 – 8-lead thin shrink small outline, package mechanical data
millimeters
so inches(1)

Ob
Symbol
Typ Min Max Typ Min Max

)-
A 1.200 0.0472

t(s
A1 0.050 0.150 0.0020 0.0059

uc
A2 1.000 0.800 1.050 0.0394 0.0315 0.0413

od
b 0.190 0.300 0.0075 0.0118

Pr
c 0.090 0.200 0.0035 0.0079
CP 0.100 0.0039

e t e D 3.000 2.900 3.100 0.1181 0.1142 0.1220

l
so
e 0.650 - - 0.0256 - -

Ob
E 6.400 6.200 6.600 0.2520 0.2441 0.2598
E1 4.400 4.300 4.500 0.1732 0.1693 0.1772
L 0.600 0.450 0.750 0.0236 0.0177 0.0295
L1 1.000 0.0394
α 0° 8° 0° 8°
N 8 8
1. Values in inches are converted from mm and rounded to four decimal digits.

35/38 Doc ID 022583 Rev 1

 M95320-125 Part numbering

11 Part numbering

Table 18. Ordering information scheme

Example: M95320 – W MN 3 T P /P

Device type
M95 = SPI serial access EEPROM

Device function
320 = 32 Kbit (4096 x 8)

s )
Operating voltage
c t(
blank = VCC = 4.5 to 5.5 V
W = VCC = 2.5 to 5.5 V
d u
r o
Package
MN = SO8 (150 mil width)
e P
DW = TSSOP8 (169 mil width)

le t
Device grade
s o
O
Automotive temperature range (–40 to 125 °C) b
3 = Device tested with high reliability certified flow.

Option
) -
blank = Standard packing
t ( s
T = Tape and reel packing

u c
o d
Plating technology

r
P = RoHS compliant and halogen-free (ECOPACK®)

P
e t e
Process

o l /P or /PC = Manufacturing technology code

b s
O

Doc ID 022583 Rev 1 36/38

 Revision history M95320-125

12 Revision history

Table 19. Document revision history

Date Revision Changes

05-Jan-2012 1 Initial release.

s )
ct(
d u
r o
e P
le t
s o
O b
) -
t ( s
u c
o d
P r
e te
o l
b s
O

37/38 Doc ID 022583 Rev 1

 M95320-125

s )
Please Read Carefully:

c t(
d u
Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the

time, without notice.

r o
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All ST products are sold pursuant to ST’s terms and conditions of sale.

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le t
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s o
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O b
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) -
t ( s
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Doc ID 022583 Rev 1 38/38