CPE382

Cluster 1 | 2nd Semester A.Y. 2020-2021

Moodle: CPE382 Introduction to HDL
MS Teams: CPE382-H1-C1

Verilog Programming Elements

Module 1.1

ENGR. JUNDITH D. ALTERADO

Email Address: jundith.alterado@cit.edu
Facebook Account: (7) Jundith Alterado | Facebook
 Comfortable language elements that you use to
Keywords communicate with the compiler.

Reserved words in Verilog known as keywords. We can use them to

define language constructs. Always write keywords using lowercase
letters.
Identifiers Unique name which identifies an object.

Case-sensitive and made up of alphanumeric characters, underscore,

or a dollar sign.
Starts with alphanumeric or underscore.
Dollar sign is reserved for naming system tasks.
Also starting with numbers is not advisable.

Example:
Number Specifications
 Sized Numbers Format: <size>’<base format><number>

size – number of bits in the number; in decimal form only

Base format– base we use to represent our number.
(‘B or ‘b)Binary, (‘D or ‘d)Decimal, (‘O or ‘o)Octal, (‘H or ‘h)Hexadecimal
Number– consecutive digits from 1-f; only subsets of these digits is legal for each
base.

Example:

4'b1111 // 4-digit binary number

12'habc // 12-bit hexadecimal
number
16'd255 //16-bit decimal number
16'hDEF //16-bit haxadecimal
number.
 Numbers without <size> and/or
Unsized Numbers <base>

Default size value of 32-bits.

If no base is specified, it is decimal by default.

Reminder: Always thrive to use our memory allocation

efficiently to build efficient hardware.
X and Z values
representing ‘unknown’ and ‘high impedance’ Verilog uses x and z.
An x or z sets four bits in the hexadecimal base, three bits in the octal
base, and one bit in the binary base.

Comments
// - Single Line comments
/* … */ - Multiple Line comments
Data Types
 Informs the compiler whether to act as
Data Types transmission line or store data.

DATATYPE

DATATYPE
1 Net
2 Variable

- Responsible for the

- Connection between storage of values
hardware elements. - Used for the variables
- Don’t store values. whose values are assigned
- They have the value of the inside the always block.
drivers. - Input ports cannot be
- Usually used for TB (Test defined as a variable
Bench) module. datatype.
- Usually used for DUT
(Design Under Test)
module.
 Informs the compiler whether to act as
Data Types transmission line or store data.

DATATYPE

1 Net
- Connection between hardware
elements.
- Don’t store values.
- They have the value of the
drivers. For instance, in the figure, the
net out connected to the output
Net data type must be used when a
signal is: is driven by the driving output
1. Driven by the output of some value A&B.
devices
2. Declared as an input or inout.
3. In the left-hand side of
continuous assignment
statement.
Types of Nets
TYPE OF NET

1.1 Wire

- uses keyword wire

- exhibits same property as
an electrical wire used for
connections.
- most commonly used net
in modeling circuits.
- Default data type for
unspecified signal/ports.
Types of Nets
TYPE OF NET
supply0 and
1.2 supply1
- power supply and ground
- Power Supply
- supply1
- Ground
- supply0 Note: All nets connected to
Vcc are connected to the
power supply while all nets
connected to GND are
connected to ground.
Variable Data Type
DATATYPE

2 Register
reg reset; // declare a variable
reset that can hold it's value

- Variables that can hold initial

begin
values. reset = 1'b1; //initialize the
- Does not need a driver reset variable to 1 to reset the
- Doesn’t need a clock digital circuit
#10 reset = 1'b0; //After 10 time
- Declared using the units, reset is deasserted.
keyword reg end
Different Kind of Registers
TYPE OF REG

2.1 Integer

- uses the keyword integer

integer counter; //general purpose
- General purpose register variable used as a counter;
datatype used for initial
manipulating quantities. counter = -1; // A negative one is
stored in the counter.
- 32-bit default size.
- reg – unsigned
- integer – signed
Types of Registers
TYPE OF REG

2.2 Real real delta; // define a real

variable called delta

initial
begin
- uses the keyword real delta = 4e10; //assigned
scientific notation
- Store decimal/scientific delta = 2.13 //assigned a decimal
notations. value of 2.13
- 64-bit default size. end
- Cannot have a range
declaration.
- Default value is zero(0) Note: if a real value is
assigned to an integer value:
round-off to the nearest
integer. Ex: 2.3 → 2
Types of Registers
TYPE OF REG
Time
2.3 Registers
time save_sim_time; //Define a
time variable save_sim_time
initial
begin

- uses the keyword time save_sim_time = $time; // Save the

current simulation time.
- Record the simulation time end
- 64-bit default size.
- Invokes the $time function

Note: if a real value is

assigned to an integer value:
round-off to the nearest
integer. Ex: 2.3 → 2
Types of Registers
TYPE OF REG

2.4 Parameter module compr_genr(X,Y,xgty,

xlty,xeqy);
parameter N = 3;
input [N:0] X, Y;
output xgty, xlty, xeqy;
- Declared using the Wire [N:0] sum, Yb;
keyword parameter
- Represents a global
constant.
Note: to change the size of
the inputs x and y, nets sum,
and net Yb to 8 bits, the
value of N is changed to 7.
 Informs the compiler whether to act as
Data Types transmission line or store data.

DATATYPE
DATATYPE

1 Scalar
2 Vector

- multi-bit. Ex: wire [0:3] a; res [3:0] d0;

- Single bit
[<MSB bit number> : <LSB bit number>] or
- Example: wire n; reg d1; [<LSB bit number> : <MSB bit position>]
Module Declaration
Module Building block of a Verilog design

Starts with the keyword module and ends with the keyword
endmodule.
There are five components of within a module, not necessary that all
are found inside a single design.
Two Types of Verilog Modules / Design

MODULE
MODULE

1 DUT
2 Test Bench

- design under test (DUT), is a - A testbench is simply a Verilog

synthesizable module of the module.
functionality we want to test. - testbench module need not be
- It is the circuit design that we synthesizable.
would like to test. - needed to simulate it to check the
- Can be described using one functionality of our DUT.
of the three modeling styles
in Verilog – Gate-
level, Dataflow,
or Behavioral.
PORTS
Syntax – <port_direction> <port datatype> <port size> <port name>

EXAMPLE
EXAMPLE

1 D Flip-flop
1 Full Adder