The audioport is a digital intellectual property block that implements an

I2S audio output interface in a system-on-a-chip design. The audioport

Design Nameaudioport
module is the top-level design module that instantiates several
Description functional modules.
Clock domains
Clock Namesclk mclk
Active edge rising rising
Reset Namesrst_n mrst_n
Reset Kinds async_0 async_0
DESIGN PARAMETERS
Group Name Value HEX
Project CLK_PERIOD 18.5 12
Parameters MCLK_PERIOD 54.25347222 36
FILTER_TAPS 47 2F
AUDIO_BUFFER_SIZE 42 2A
CMD_WAIT_STATES 24 18
Register DSP_REGISTERS 188 BC
Counts ABUF_REGISTERS 168 A8
AUDIOPORT_REGISTERS 360 168
Register RINDEX_BITS 9 9
Indices CMD_REG_INDEX 0 0
STATUS_REG_INDEX 1 1
LEVEL_REG_INDEX 2 2
CFG_REG_INDEX 3 3
DSP_REGS_START_INDEX 4 4
DSP_REGS_END_INDEX 191 BF
ABUF0_START_INDEX 192 C0
ABUF0_END_INDEX 275 113
ABUF1_START_INDEX 276 114
ABUF1_END_INDEX 359 167
Register APB AUDIOPORT_START_ADDRESS 2348810240 8C000000
Addresses AUDIOPORT_END_ADDRESS 2348811676 8C00059C
CMD_REG_ADDRESS 2348810240 8C000000
STATUS_REG_ADDRESS 2348810244 8C000004
LEVEL_REG_ADDRESS 2348810248 8C000008
CFG_REG_ADDRESS 2348810252 8C00000C
DSP_REGS_START_ADDRESS 2348810256 8C000010
DSP_REGS_END_ADDRESS 2348811004 8C0002FC
ABUF0_START_ADDRESS 2348811008 8C000300
ABUF0_END_ADDRESS 2348811340 8C00044C
ABUF1_START_ADDRESS 2348811344 8C000450
ABUF1_END_ADDRESS 2348811676 8C00059C
Command CMD_NOP 0 0
Register CMD_CLR 1 1
Codes CMD_CFG 2 2
CMD_START 4 4
CMD_STOP 8 8
CMD_LEVEL 16 10
CMD_IRQACK 32 20
Status STATUS_PLAY 0 0
Register STATUS_CLR_ERR 1 1
Codes STATUS_CFG_ERR 2 2
STATUS_IRQ_ERR 3 3
STATUS_CMD_ERR 4 4
STATUS_CMD_ERR 4 4
Config Bit CFG_MONO 2 2
Indices CFG_FILTER 3 3
Config Bit RATE_48000 0 0
Values RATE_96000 1 1
RATE_192000 2 2
FILTER_ON 1 1
FILTER_OFF 1 1
MONO_ON 1 1
MONO_OFF 1 1
Clock Divisor CLK_DIV_192000 282 11A
Ratios for clk CLK_DIV_48000 1127 467
domain CLK_DIV_96000 564 234
Clock Divisor MCLK_DIV_192000 8 8
Ratios for mclk MCLK_DIV_48000 4 4
domain MCLK_DIV_96000 2 2
cdc_unit CDC_BITSYNC_INTERVAL 3 3
Verification CDC_BITSYNC_LATENCY 2 2
Settings CDC_DATASYNC_INTERVAL 24 18
CDC_DATASYNC_LATENCY 15 F
CDC_PULSESYNC_INTERVAL 1 1
CDC_PULSESYNC_LATENCY 5 5
dsp_unit Max DSP_UNIT_MAX_LATENCY 212 D4
Latency
Description
clk domain clock period in ns.
mclk domain clock period in ns.
Number of taps in each of the four FIR filters in module 'filter'.
Number of stereo samples in one of the two audio buffers regions.
Number of wait states inserted when a write to the command register CMD_REG is detected.
Number of registers reserved for filter tap coefficients. Equal to 4 * FILTER_TAPS.
Number of 24-bit registers in the ABUF register bank.
Last address of audioport in APB3 address space.
Number of bits in the register index value rindex.
Internal address of command register in cregs.
Number of registers in RBANK
Internal address of output level data register in cregs.
Internal address of configuration data register.
Internal address of first filter coefficient data register.
Internal address of last filter coefficient data register.
Internal address of first left channel sample in ABUF0 region
Internal address of last right channel sample in ABUF0 region
Internal address of first left channel sample in ABUF1 region
Internal address of if last right channel sample in ABUF1 region
Base address of audioport in APB3 address space.
Last address of audioport in APB3 address space.
APB bus address of CMD_REG
Number of registers in RBANK
APB bus address of LEVEL_REG
APB bus address of CFG_REG
Internal address of first left channel sample in ABUF0 region
Internal address of last right channel sample in ABUF1 region
Internal address of first left channel sample in ABUF0 region
Internal address of last right channel sample in ABUF0 region
Internal address of first left channel sample in ABUF1 region
Internal address of if last right channel sample in ABUF1 region
Code for "no operation" command.
Code for audio datapath clear command.
Code for load configuration data command..
Code for start playback command.
Code for stop playback command.
Code for load playback output level command.
Code for audio datapath clear command.
Status register bit index for play/standby mode bit.
Status register bit index for CMD_CLR error bit.
Status register bit index for CMD_CFG error bit.
Status register bit index for interrupt ack error bit.
Status register bit index for illegal command error bit.
Status register bit index for illegal command error bit.
Configuration register bit index for mono mode.
Configuration register bit index for filter enable.
Code for sample rate 48 kHz
Code for sample rate 96 kHz
Code for sample rate 192 kHz
Configuration register bit value for filter enable.
Configuration register bit value for filter disable.
Configuration register bit value for moni mode enable.
Configuration register bit value for mono mode disable.
Approximate clock divider ratio for 192 kHz sample rate in clk clock domain.
Approximate clock divider ratio for 48 kHz sample rate in clk clock domain.
Approximate clock divider ratio for 96 kHz sample rate in clk clock domain.
Clock divider ratio for 192 kHz sample rate in mclk clock domain.
Clock divider ratio for 48 kHz sample rate in mclk clock domain.
Clock divider ratio for 96 kHz sample rate in mclk clock domain.
Minimum interval between CDC 2FF bit sync events in TX clock domain cycles.
Latency of CDC handshake CDC 2FF bit sync events in RX clock comain cycles.
Minimum interval between CDC handshake sequences in TX clock domain cycles.
Latency of CDC handshake sequence in RX clock comain cycles.
Minimum interval between CDC pulse sync events in TX clock domain cycles.
Latency of CDC handshake CDC pulse sync events in RX clock comain cycles.
Maximum allowed latency for dsp_unit measured from tick_in to valid_out in clk clock cycles.
PORTS
Name Direction Kind Width Type
clk input clock (bits) 1 logic
rst_n input reset 1 logic
mclk input clock 1 logic
PSEL input data 1 logic
PENABLE input data 1 logic
PWRITE input data 1 logic
PADDR input data 32 logic [31:0]
PWDATA input data 32 logic [31:0]
PRDATA output data 32 logic [31:0]
PSLVERR output data 1 logic
PREADY output data 1 logic
irq_out output data 1 logic
sck_out output data 1 logic
ws_out output data 1 logic
sdo_out output data 1 logic
scan_en_in input data 1 logic
test_mode_in input data 1 logic
Description
Rising-edge sensitive clock signal input for main clock domain.
Active-low, asynchronous reset signal input for main clock domain.
Rising-edge sensitive clock signal input for I2S clock domain.
AMBA APB psel signal.
AMBA APB penable signal.
AMBA APB pwrite signal.
AMBA APB paddr bus.
AMBA APB pwdata bus.
AMBA APB prdata bus.
AMBA APB pslverr signal
AMBA APB pready signal.
Active-high interrupt request output
I2S serial clock output.
I2S word select output
I2S serial data output.
Active-high scan enable input.
Active-high test mode select input.
FEATURE FUNCTIONAL REQUIREMENT
apb_ports The APB ports shall function according to the APB3 protocol
scan_enable The scan path enable input scan_en shall be unconnected in the RTL design and
connected in test synthesis.
start_stop_interval The intervals between CMD_START and CMD_STOP commands should be larger than
one 48 kHz sample duration (1/48000 s)
control_unit The control unit submodule implements the APB bus interface, command
dsp_unit decoding,
The dsp_unit status register update,
implements audioprocessing
digital signal data streaming and interrupt
functions (filtering,functions.
mono
cdc_unit mode and level scaling).
The cdc_unit implements clock domain crossing functions.
i2s_unit The i2s_unit implements parallaer to serial conversion functions according to I2S
connections specifications.
The connections between the ports of the audioport and the ports of the
no_logic_on_top submodules
The top-levelare defined
module in not
shall the contain
audioport_rtl_2024
any functional block diagram. The
logic.
connections and connection names are part of the functional specification.
clk_domain Submodules control_unit and dsp_unit use the clock signal clk and reset signal
mclk_domain rst_n.
Submodule i2s_unit uses the clock signal mclk and the reset signal mrst_n.
synchronization Submodule cdc_unit receives the clock signals clk and mclk, and the reset signal
register_bank rst_n. It generatesshall
The control_unit the contain
reset signal mrst_n
a register by synchronizing
bank rst_n to clock mclk.
with AUDIOPORT_REGISTERS 32-
The
bit cdc_unit
registers contains
that can be synchronization
written and logic
read by that synchronizes
controlling the APB3all data signalsThe
interface.
cmd_wait_states When
that data
pass is written
between into register
modules CMD_REG,
that reside in the control_unit
different inserts
intowait states
names
into theand purpose
access by of the registers
keeping PREADY are for
low given in theclock
CMD_WAIT_STATES
domains
audioport clock
the clock
Specification
cycles and
pslverr Output
Design PSLVERR shall be permanently tied to '0.
Guide.
during
This the APB3 ACCESS
requirement phase
is verified with(when PSEL == '1 and PENABLE == '1). Write
the control_unit.
command_interface The command
accesses interface
to all other functions
registers, andarereaddecribed
accessesintodetail in control_unit
all registers are executed
status_interface specifications and verified with the control_unit.
The status register interface functions are described in detail in control_unit
specifications and verified with the control unit.

standby_mode Writing the command code CMD_STOP into the CMD_REG register puts the
play_mode audioport
Writing theinto standbycode
command mode. After entering
CMD_STOP standby
into the mode register
CMD_REG the audioport
puts thestops
generating
audioport I2S
into data
play within
mode. CLK_DIV_48000
After entering clock
play mode cycles
the audioport
data_rountrip A streaming data cycle begins when the i2s_unit generates a pulse begins to
mreq, and
generate I2S data a within CLK_DIV_48000 clock cycles.
dsp_unit_max_latency ends when the is2_unit receives a pulse mtick, provided that the audioport is in
playmode throughout this sequence. The roundtrip time of this shorter than one
irq_out irq_out
192kHz should
samplerise when AUDUIO_BUFFER_SIZE stereo samples have been
period.
sck_out serialized, and fall when
sck_out should show a valid the I2S
interrupt is acknowledged
SCK waveform by writing
for the selected the command
sample rate. This
code CMD_IRQ_ACK
requirement is covered or CMD_STOP
in detail in into
the the CMD_REG
i2s_unit register.
specifications and verified with
sdo_out sdo_out should contain the data written into the ABUF region of the
the i2s_unit.
control_unit's
ws_out sck_out shouldregister
show abank, andWS
valid I2S processed
waveform in the
for dsp_unit,
the selectedin serial
sampleformat
rate. This
specified in the I2S specification. This requirement is covered
requirement is covered in detail in the i2s_unit specifications and verified in detail in the
with
control_unit,
the i2s_unit. dsp_unit and i2s_unit specifications and verified with these
Err:508
TEST NAME DESCRIPTION
audioport_test Simple test program meant to perform a basic sanity-check. The
apb_test test initializes
A simple registers,example
UVM--based configures
of athe audioport,
read/write testand
forstarts and
the APB-
stops
based playback.
register interface with randomofstimulus dataunit.
generation
control_unit_uvm_test An UVM test that tests the function the control
and
The analysis
test uses components.
audioport_uvm_test A complex testtwo agents,
that the control_unit_agent
demonstrates that handles
the use of a scoreboard with a
the APB interface, and the irq_out_agent
reference mode and hierarchical sequences. that handles the
irq_out port.
TEST SEQUENCE
Notice: This test does not control the reset input rst_n.
1. Set scan_en_in,
Random test_mode_in
APB bus addresses are firstand APB inputs
written to andto zero,
then andfrom
read wait(apb_sequence).
until reset rst_n rises.
The results
1. Write and coverage
random are analyzed
configuration data to inallan analyzer
registers in component (apb_analyzer).
DSP_REGS region.
2. Write an increasing sequence of values starting from 1 into the ABUF region registers.
IMMEDIATE
ASSERTIONS

/
//
//
#
//
V
/A
L
FR BACKLINK NAME DESCRIPTION
0
0
0
0
0
0
0
0
0
0
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0
0
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PROPERTY CLOCK RESET DIRECTIVE COVER
CODE
NAME KIND TYPE
level_reg interconnect logic [31:0]
cfg_reg interconnect logic [31:0]
dsp_regs interconnect logic [DSP_REGISTERS*32-
1:0]
level interconnect logic
cfg interconnect logic
clr interconnect logic
req interconnect logic
audio0 interconnect logic [23:0]
audio1 interconnect logic [23:0]
tick interconnect logic
play interconnect logic
dsp0 interconnect logic [23:0]
dsp1 interconnect logic [23:0]
dsp_tick interconnect logic
mcfg_reg interconnect logic [31:0]
mcfg interconnect logic
mplay interconnect logic
mreq interconnect logic
mtick interconnect logic
mdsp0 interconnect logic [23:0]
mdsp1 interconnect logic [23:0]
mclk_mux interconnect logic
mrst_n interconnect logic
control_unit_1 instance control_unit
dsp_unit_1 instance dsp_unit

cdc_unit_1 instance cdc_unit

i2s_unit_1 instance i2s_unit

DESCRIPTION CLOCK RESET INITIAL
Output of LEVEL_REG register of control_unit. VALUE
Output of CFG_REG register of control_unit.
Outputs of all registers in the DSP_REGS region of the register bank in
control_unit cocatenated into one bitvector.
Active-high CMD_LEVEL command indicator pulse signal from control_unit.
Active-high CMD_CFG command indicator pulse signal from control_unit.
Active-high CMD_CLR command indicator pulse signal from control_unit.
Active-high next audio sample-request pulse signal in the clk clock domain.
Audio buffer output that contains the next left channel sample to be sent to
dsp_unit.
Audio buffer output that contains the next right channel sample to be sent to
dsp_unit.
Active-high audio data valid indicator pulse signal for audio0 and audio1.
Play mode indicator from control_unit.
Left channel audio output from dsp_unit.
Right channel audio output from dsp_unit.
dsp_unit audio output valid indicator for dso0 and dsp1.
cfg_reg signal in mclk clock domain,
cfg signal in mclk clock domain,
play signal in mclk clock domain.
Next audio sample request from i2s_unit.
dsp_tick signal in mclk clock domain.
dsp0 signal in mclk clock domain.
dsp1 signal in mclk clock domain.
mclk domain clock signal
Active-low, asynchronous reset signal for I2S clock domain from cdc_unit.
Instance of control_unit.
Instance of dsp_unit.

Instance of cdc_unit.

Instance of i2s_unit.
DESIGN INTENT SIGNAL DECLARATION
logic [31:0] level_reg;
logic [31:0] cfg_reg;
logic [DSP_REGISTERS*32-1:0] dsp_regs;

logic level;
logic cfg;

logic clr;
logic req;
logic [23:0] audio0;
logic [23:0] audio1;
logic tick;
logic play;
logic [23:0] dsp0;
logic [23:0] dsp1;
logic dsp_tick;
logic [31:0] mcfg_reg;
logic mcfg;
logic mplay;
logic mreq;
logic mtick;
logic [23:0] mdsp0;
logic [23:0] mdsp1;

logic mrst_n;
INPUTS:
clk clk
rst_n rst_n
PSEL PSEL
PENABLE PENABLE
PWRITE PWRITE
PADDR PADDR
PWDATA PWDATA
req_in req
OUTPUTS:
PRDATA PRDATA
PSLVERR PSLVERR
PREADY PREADY
irq_out irq_out
cfg_reg_out cfg_reg
level_reg_out level_reg
dsp_regs_out dsp_regs
cfg_out cfg
clr_out clr
level_out level
tick_out tick
audio0_out audio0
audio1_out audio1
play_out play
INPUTS:
clk clk
rst_n rst_n
audio0_in audio0
audio1_in audio1
tick_in tick
cfg_in cfg
cfg_reg_in cfg_reg
dsp_regs_in dsp_regs
level_in level
level_reg_in
INPUTS: level_reg
clk clk
rst_n rst_n
dsp0_in dsp0
dsp1_in dsp1
tick_in dsp_tick
cfg_in cfg
cfg_reg_in cfg_reg
play_in play
mclk_in mclk
INPUTS:
clk mclk_mux
rst_n mrst_n
play_in mplay
audio0_in mdsp0
audio1_in mdsp1
tick_in mtick
cfg_in mcfg
cfg_reg_in mcfg_reg
OUTPUTS:
req_out mreq
sck_out sck_out
ws_out ws_out
sdo_out sdo_out
CODE SVA MOD PORT xcheck
assign input logic [31:0] level_reg; `xcheck(level_reg);
assign input logic [31:0] cfg_reg; `xcheck(cfg_reg);
assign input logic [DSP_REGISTERS*32-1:0]`xcheck(dsp_regs);
assign input logic level; `xcheck(level);
assign input logic cfg; `xcheck(cfg);
assign input logic clr; `xcheck(clr);
assign input logic req; `xcheck(req);
assign input logic [23:0] audio0; `xcheck(audio0);
assign input logic [23:0] audio1; `xcheck(audio1);
assign input logic tick; `xcheck(tick);
assign input logic play; `xcheck(play);
assign input logic [23:0] dsp0; `xcheck(dsp0);
assign input logic [23:0] dsp1; `xcheck(dsp1);
assign input logic dsp_tick; `xcheck(dsp_tick);
assign input logic [31:0] mcfg_reg; `xcheck(mcfg_reg);
assign input logic mcfg; `xcheck(mcfg);
assign input logic mplay; `xcheck(mplay);
assign input logic mreq; `xcheck(mreq);
assign input logic mtick; `xcheck(mtick);
assign input logic [23:0] mdsp0; `xcheck(mdsp0);
assign input logic [23:0] mdsp1; `xcheck(mdsp1);

assign `xcheck(mrst_n);
control_unit control_unit_1 ;
dsp_unit dsp_unit_1 ;

cdc_unit cdc_unit_1 ;

i2s_unit i2s_unit_1 ;
connection : inport outport : connection

clk clk PRDATA PRDATA

rst_n rst_n PSLVERR PSLVERR
PSEL PSEL PREADY PREADY
PENABLE PENABLE irq_out irq_out
PWRITE PWRITE cfg_reg_out cfg_reg
PADDR PADDR level_reg_out level_reg
PWDATA PWDATA dsp_regs_out dsp_regs
req req_in cfg_out cfg
clr_out clr
level_out level
tick_out tick
audio0_out audio0
audio1_out audio1
play_out play
clk clk dsp0_out dsp0
rst_n rst_n dsp1_out dsp1
audio0 audio0_in valid_out dsp_tick
audio1 audio1_in
tick tick_in
cfg cfg_in
cfg_reg cfg_reg_in
dsp_regs dsp_regs_in
level level_in
level_reg level_reg_in
clr clr_in

clk clk mclk mclk_mux

rst_n rst_n mrst_n mrst_n
dsp0 dsp0_in dsp0_out mdsp0
dsp1 dsp1_in dsp1_out mdsp1
dsp_tick tick_in tick_out mtick
cfg cfg_in cfg_out mcfg
cfg_reg cfg_reg_in cfg_reg_out mcfg_reg
play play_in play_out mplay
mclk mclk_in req_out req
mreq req_in
test_mode_in test_mode_in

mclk_mux clk req_out mreq

mrst_n rst_n sck_out sck_out
mplay play_in ws_out ws_out
mdsp0 audio0_in sdo_out sdo_out
mdsp1 audio1_in
mtick tick_in
mcfg cfg_in
mcfg_reg cfg_reg_in
connect, clk, control_unit_1.clk
connect, rst_n, control_unit_1.rst_n
connect, PSEL, control_unit_1.PSEL
connect, PENABLE, control_unit_1.PENABLE
connect, PWRITE, control_unit_1.PWRITE
connect, PADDR, control_unit_1.PADDR
connect, PWDATA, control_unit_1.PWDATA
connect, req, control_unit_1.req_in
connect, control_unit_1.PRDATA, PRDATA
connect, control_unit_1.PSLVERR, PSLVERR
connect, control_unit_1.PREADY, PREADY
connect, control_unit_1.irq_out, irq_out
connect, control_unit_1.cfg_reg_out, cfg_reg
connect, control_unit_1.level_reg_out, level_reg
connect, control_unit_1.dsp_regs_out, dsp_regs
connect, control_unit_1.cfg_out, cfg
connect, control_unit_1.clr_out, clr
connect, control_unit_1.level_out, level
connect, control_unit_1.tick_out, tick
connect, control_unit_1.audio0_out, audio0
connect, control_unit_1.audio1_out, audio1
connect, control_unit_1.play_out, play
connect, clk, dsp_unit_1.clk
connect, rst_n, dsp_unit_1.rst_n
connect, audio0, dsp_unit_1.audio0_in
connect, audio1, dsp_unit_1.audio1_in
connect, tick, dsp_unit_1.tick_in
connect, cfg, dsp_unit_1.cfg_in
connect, cfg_reg, dsp_unit_1.cfg_reg_in
connect, dsp_regs, dsp_unit_1.dsp_regs_in
connect, level, dsp_unit_1.level_in
connect, level_reg, dsp_unit_1.level_reg_in
connect, clr, dsp_unit_1.clr_in
connect, dsp_unit_1.dsp0_out, dsp0
connect, dsp_unit_1.dsp1_out, dsp1
connect, clk, cdc_unit_1.clk
dsp_unit_1.valid_out, dsp_tick
connect, rst_n, cdc_unit_1.rst_n
connect, dsp0, cdc_unit_1.dsp0_in
connect, dsp1, cdc_unit_1.dsp1_in
connect, dsp_tick, cdc_unit_1.tick_in
connect, cfg, cdc_unit_1.cfg_in
connect, cfg_reg, cdc_unit_1.cfg_reg_in
connect, play, cdc_unit_1.play_in
connect, mclk, cdc_unit_1.mclk_in
connect, mreq, cdc_unit_1.req_in
connect, test_mode_in, cdc_unit_1.test_mode_in
connect, cdc_unit_1.mclk, mclk_mux
connect, mclk_mux,
connect, cdc_unit_1.mrst_n, mrst_n
i2s_unit_1.clk
connect,
connect, cdc_unit_1.dsp0_out,
mrst_n, i2s_unit_1.rst_nmdsp0
connect,
connect, cdc_unit_1.dsp1_out, mdsp1
mplay, i2s_unit_1.play_in
connect, mdsp0,
connect, cdc_unit_1.tick_out, mtick
i2s_unit_1.audio0_in
connect, mdsp1,
connect, cdc_unit_1.cfg_out, mcfg
i2s_unit_1.audio1_in
connect,
connect, cdc_unit_1.cfg_reg_out,
mtick, i2s_unit_1.tick_in mcfg_reg
connect,
connect, cdc_unit_1.play_out,
mcfg, i2s_unit_1.cfg_inmplay
connect,
connect, cdc_unit_1.req_out, req
mcfg_reg, i2s_unit_1.cfg_reg_in
connect, i2s_unit_1.req_out, mreq
connect, i2s_unit_1.sck_out, sck_out
connect, i2s_unit_1.ws_out, ws_out
connect, i2s_unit_1.sdo_out, sdo_out
req_in req Err:509
RTL # FR BACKLINK NAME DESCRIPTION
BACKLINK
PROPERTY CLOCK RESET DIRECTIVE COVER
CODE
TYPENAME INSTANCE DESCRIPTION
SAMPLING COVERPOINT NAME, EXPRESSION AND BINS
CROSS COVERAGE NAME AND EXSAMPLING COVERPOINT
BINS CROSS CODE
 #REF!

#NAME?
#NAME?
`xcheck(PRDATA);
`xcheck(PSLVERR);
`xcheck(PREADY);
`xcheck(irq_out);
`xcheck(sck_out);
`xcheck(ws_out);
`xcheck(sdo_out);
`xcheck(scan_en_in);
`xcheck(test_mode_in);
control_unit_svamod.sv
`xcheck(level_reg);
`xcheck(cfg_reg);
`xcheck(dsp_regs);
`xcheck(level);
`xcheck(cfg);
`xcheck(clr);
`xcheck(req);
`xcheck(audio0);
`xcheck(audio1);
`xcheck(tick);
`xcheck(play);
`xcheck(dsp0);
`xcheck(dsp1);
`xcheck(dsp_tick);
`xcheck(mcfg_reg);
`xcheck(mcfg);
`xcheck(mplay);
`xcheck(mreq);
`xcheck(mtick);
`xcheck(mdsp0);
`xcheck(mdsp1);
`xcheck(mrst_n);

/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// 2. Blackbox (functional) assumptions and assertions
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////

/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// 3. Whitebox (RTL) assertions
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////

/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// 4. Covergroups
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////

endmodule
control_unit_test_tasks.svh
#NAME?
Directions input output inout
Types logic unsigned signed tri bool sc_int
Port kinds data clock reset
Signal kinds register combinational interconnect instance
Process kinds combinational sequential assign guidance
Clock edges rising falling
Reset types async_0 async_1 sync_0 sync_1

Clock clk mclk 0 0 0 0

Clock edge posedge clk posedge mclk
Reset rst_n mrst_n 0 0 0
Reset edge negedge rst_nnegedge mrst
Process sensiti@(posedge clk@(posedge mcl @() @() @()
Reset conditio(rst_n == '0) (mrst_n == '0)

Test types BB WB
Assertions assume assert
CoverSpecs coverpoint cross

register combinational interconnect

Process suffix _reg _logic
ns process suff_logic
Variable suffix _r
Next-state suff_next

YesNo YES NO

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COMMENTS
// 1. X-checks
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/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// 2. Blackbox (functional) assumptions and assertions
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// 3. Whitebox (RTL) assertions
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// 4. Covergroups
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1
2
3 // 1 // 2 // 3
eka toka kolm #VALUE!
eka toka #NAME?
TRUE

#NAME?
sc_uint