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HDL 5

The document provides an overview of Hardware Description Languages (HDLs), focusing on their design flow, abstraction layers, and fundamental concepts. It details the Verilog language, including its syntax, control structures, data types, and number representations, as well as the importance of testbenches for verifying design behavior. The content is aimed at students in a 2-credit course on HDLs at the Indian Institute of Information Technology Raichur.

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Nidal Noushad
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6 views35 pages

HDL 5

The document provides an overview of Hardware Description Languages (HDLs), focusing on their design flow, abstraction layers, and fundamental concepts. It details the Verilog language, including its syntax, control structures, data types, and number representations, as well as the importance of testbenches for verifying design behavior. The content is aimed at students in a 2-credit course on HDLs at the Indian Institute of Information Technology Raichur.

Uploaded by

Nidal Noushad
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Hardware

Description Language
by

Dr. Dubacharla Gyaneshwar


Department of Computer Science and Engineering
Indian Institute of Information Technology Raichur (IIIT-R)

R slot – EE121 – 2 credit course


HDL – Design Flow

Dr. Dubacharla Gyaneshwar


Hardware Description Languages (HDLs)

Languages:

Dr. Dubacharla Gyaneshwar


HDL in Design

Dr. Dubacharla Gyaneshwar


Design Abstraction Layers
• Design abstraction layers refer
to the different levels of detail • Architecture Level • RTL Level
at which a hardware system
can be described. These layers
facilitate the design process by
allowing designers to focus on
specific aspects of the system
without getting bogged down
by lower-level details.

Dr. Dubacharla Gyaneshwar


Design Abstraction Layers
• Transistor Level • Physical Level
• Schematic Level

Dr. Dubacharla Gyaneshwar


RTL: abstraction used in digital design

Dr. Dubacharla Gyaneshwar


Fundamental Blocks in Digital Circuits

Dr. Dubacharla Gyaneshwar


Combinational circuits

Dr. Dubacharla Gyaneshwar


Combinational circuits

Dr. Dubacharla Gyaneshwar


Combinational circuits

Dr. Dubacharla Gyaneshwar


Fundamental concepts in HDL
• Signals and Variables: Represent data storage and transfer within a
digital system.
• Control Structures: Conditionals (if, case) and loops to direct data
flow and operations.
• Modules and Architectures: Define hierarchical structure and
organization of digital components.
• Libraries and Packages: Reusable collections of commonly used
functions and definitions.
• Syntax and Semantics: Specific rules and conventions for writing valid
HDL code.
• Simulation and Synthesis Tools: Software for verifying design
behavior and translating HDL to hardware.
Dr. Dubacharla Gyaneshwar
Recap

Dr. Dubacharla Gyaneshwar


Different levels

Dr. Dubacharla Gyaneshwar


Verilog cycle

Dr. Dubacharla Gyaneshwar


Verilog: Lexical Tokens

• Similar to the C language, Verilog has a set of Verilog lexical


tokens/standards that determine how language elements like
• keywords,
• identifiers,
• operators,
• integers,
• strings,
• white space, and
• comments are structured.
Dr. Dubacharla Gyaneshwar
Verilog

Dr. Dubacharla Gyaneshwar


Verilog example

Dr. Dubacharla Gyaneshwar


Verilog
• Keywords:
• Module-related: module, endmodule
• Data types: wire, reg, integer, real, logic
• Control flow: if, else, case, for, while, repeat, forever
• Concurrency: always, initial, assign
• Procedural blocks: begin, end, function, task
• Delays & Timing: #, @, posedge, negedge
• Miscellaneous: generate, parameter, localparam, define, include

Dr. Dubacharla Gyaneshwar


Verilog
• Control Flow Statements:
• Conditional: if, else, case
• Loops: for, while, repeat, forever
• Procedural: always, initial, begin … end
• Wait/Event: @(posedge clk), #10

Dr. Dubacharla Gyaneshwar


Verilog
• Variables and Data Types:
• Bit/Logic: wire, reg, logic, bit
• Integer: integer, real
• Arrays: reg [7:0] array [0:15]
• Constants: parameter, localparam
• String: Not directly supported

Dr. Dubacharla Gyaneshwar


Verilog: Number representation
❑ In HDL like Verilog, there are several ways to represent numbers, each specifying the bit-width and base.
Here is a comprehensive list:
Binary Representation
• Syntax: <bit-width>'b<binary_value>
• Example: 4'b1101 (Represents the 4-bit binary number 1101)
Octal Representation
• Syntax : <bit-width>'o<octal_value>
• Example: 8'o17 (Represents the 8-bit octal number 17, which is 001111 in binary)
Decimal Representation
• Syntax : <bit-width>'d<decimal_value>
• Example: 8'd45 (Represents the 8-bit decimal number 45, which is 00101101 in binary)
Hexadecimal Representation
• Syntax : <bit-width>'h<hexadecimal_value>
• Example: 16'h1A3F (Represents the 16-bit hexadecimal number 1A3F, which is 0001101000111111 in binary)
Dr. Dubacharla Gyaneshwar
Verilog: Number representation
Unsigned Numbers
• Format: <bit-width>'u<decimal_value> (Verilog doesn't use 'u, but SystemVerilog does)
• Example: 8'u200 (Represents the 8-bit unsigned decimal number 200)

Signed Numbers
• Format: <bit-width>'s<decimal_value> (Verilog doesn't use 's, but SystemVerilog does)
• Example: 8's-25 (Represents the 8-bit signed decimal number -25)

Time Units: Verilog also supports time units for simulation.


• Format: #<time_value> <time_unit>
• Example: #5 ns (Represents a delay of 5 nanoseconds)

Floating-Point Numbers: While traditional Verilog doesn't support floating-point numbers, SystemVerilog extends support for real numbers.
• Format: <real_value>
• Example: 3.14 (Represents the real number 3.14)

Custom Constants
• Format: parameter <name> = <value>;
• Example: parameter WIDTH = 8;
Dr. Dubacharla Gyaneshwar
Verilog

Dr. Dubacharla Gyaneshwar


Verilog: example

Dr. Dubacharla Gyaneshwar


Verilog

Dr. Dubacharla Gyaneshwar


Verilog: examples

Dr. Dubacharla Gyaneshwar


Verilog: Testbench

• The testbench is written to check the


functional correctness based on design
behavior.
• The connections between design and
testbench are established using a port
interface.
• A testbench generates and drives a stimulus
to the design to check its behavior. Since the
behavior of the design has to be tested, the
design module is known to be “Design
Under Test” (DUT) Dr. Dubacharla Gyaneshwar
Verilog: Testbench
• Instantiate top-level design and connect DUT port
interface with testbench variables or signals.

Dr. Dubacharla Gyaneshwar


Verilog: Example

Dr. Dubacharla Gyaneshwar


Verilog: Example

Dr. Dubacharla Gyaneshwar


Tool for experimenting with Verilog & VHDL

Dr. Dubacharla Gyaneshwar


Tool: Xilinx Vivado

Dr. Dubacharla Gyaneshwar


Q&A session

?
Dr. Dubacharla Gyaneshwar
Thank you!

Dr. Dubacharla Gyaneshwar

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