5th International Conference on Engineering Technology and its Applications 2022- (5thIICETA2022)

ANALYSIS and DESIGN of BJT DIFFERENTIAL

AMPLIFIER
2022 5th International Conference on Engineering Technology and its Applications (IICETA) | 978-1-6654-7215-9/22/$31.00 ©2022 IEEE | DOI: 10.1109/IICETA54559.2022.9888597

1st Muneer A. Hashem

Department of Electrical Engineering
Al- Mustansiriyah University
Baghdad, Iraq
muneer.aboud@uomustansiriyah.edu.iq

The differential amplifier is a fundamental circuit in analog

Abstract— A differential amplifier is a basic building block
integrated circuits; it is an input stage for the operational
for analog integrated circuit design; the operational amplifier
integrated circuit has wide applications in signal processing. In amplifiers and comparators. The circuit is multi-transistors
this paper, a bipolar junction transistor BJT differential circuit with different topologies, it uses bipolar junction
amplifier circuit is analyzed and designed to determine the transistor, BJT, or metal-oxide-semiconductor, MOS,
output resistance and the differential mode voltage gain. A transistor [4], in the former the emitters of the transistors are
cascode current mirror is used as a biasing circuit and the active coupled while in the later the sources are coupled.
load for the differential stage is a modified Widlar circuit. The
calculations and results are performed using MATLAB software
tool version 7.10.0 (R2010a) and the simulation is carried out
with NI Multisim version 14.0.0, 2016. With standard resistors
and transistors values the results showed that a decrease in the
biasing current cause an increase in the output resistance of both
the biasing circuit and active load stage, and a decrease in the
differential voltage gain. The output resistance of the differential
amplifier is also increased with increasing in the load resistance
but the differential voltage gain is increased in this case.

Keywords— BJT transistor, cascode current mirror, modified

Widlar circuit, differential amplifier, output resistance, differential (a)
voltage gain

I. INTRODUCTION
A quick progress in communication technology,
computing, and internet that leads to different applications
needs microelectronic circuit’s designs. Integrated circuits; IC
here play an important role.
In ICs, active devices like transistors are widely used.
Current mirrors are circuits with often has three terminals, two
terminals for supplying the input current for which these
terminals are connected to the power supply, and the third is for
output current. The output current is related to the input current
(b)
through the current gain factor. The circuit has high output
impedance and it is used for low power applications [1-2].
The most types of bipolar junction transistor, BJT, current
mirrors or current sources are depicted in “Fig. 1” where IREF
is the reference current [3].

The first two current sources; the two and three transistors
current sources circuits “Fig. 1, (a)-(b)” have output resistances
ro2 which is the output resistance for Q 2 transistor. The third is
the cascode current source “Fig. 1, (c)” has an output resistance
βro4 where β is the current gain of transistor Q 4 . The fourth,
“Fig. 1, (d)”, is Wilson current source has output resistance
βro3 ⁄2, and finally the fifth one, “Fig. 1, (e)”, is the Widlar
current source has an output resistance ro2 (1 + g m2 R′E ), R′E = (c)
R E ‖rπ2 where g m is the transconductance and rπ is the base-
emitter input resistance.

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5th International Conference on Engineering Technology and its Applications 2022- (5thIICETA2022)
which is same as the circuit depicted in “Fig. 1, (c)” and a
differential amplifier stage with modified Widlar circuit acting
V+ as an active load depicted in “Fig. 2”, so the complete circuit is
Ic3=Io
depicted in “Fig. 3”.
IREF As shown from “Fig. 3” a supply voltage ∓V, resistor R1
and four npn transistors; Q1 , Q 2 , Q 3 , and Q 4 for cascode biasing
Q3
circuit, a differential stage represented by two npn transistors;
Q 5 and Q 6 , an active load circuit represented by two pnp
transistors; Q 7 and Q 8 , and two resistors; R, and a supply
voltage V.
The analysis is started by evaluating the reference current
Q1 Q2 IREF and the current through the collector of Q 4 ; Ic4 which they
are given by [10];

Ic4 = nIREF ()

(d) Where
V+

IREF
β2
R1 n= ()
Ic2=Io β2 +4β+2

Vc2
and
Q1 Q2
V+−V− −0.7−0.7
VBE1
+ +
VBE2
IREF = ()
- - R1
RE
The selected value for β is 184.4 which is for 2N3414 npn
transistors, the chosen value of R1 = 8.25 kΩ and V + = V − =
−4 V are considered, so according to (1)-(3) and with the aid
V-
of MATLAB programming tool R2010a [11], n = 0.9787,
(e) IREF = 0.8 mA, and Ic4 = 0.783 mA.

Fig. 1. Types of BJT current mirrors. V+

II. LITERATURE SURVEY

In CMOS current mirror, the design of a novel very high
output impedance CMOS current mirror with improved output
voltage compliance and a 90 nm CMOS technology
transimpedance amplifier with current mirror is presented in R R
[5-6].
Active device current mirrors have become commonplace
in analog integrated circuits as both biasing and load devices
for amplifier stages [7-8]. Q7 Q8
Various useful structure can be achieved using CMOS
differential active load [9].

III. PROBLEM STATEMENT v1 Q5 Q6 v2

Analog circuit through analog signal processing can solve
difficulties in real world. Challenges, that analog designer face
arise when implementing low voltage circuits.
In this research, the focusing is based on the effect of
changing a biasing resistor in analog cascode circuit on the
output resistance and the differential mode voltage gain of the
V-
differential stage. Second the effect of changing the load in the
active load modified widlar circuit on the two mentioned Fig. 2. Differential amplifier stage.
parameters.

IV. CIRCUIT DESIGN

A BJT differential amplifier circuit to be designed consists
of two parts; the first is the cascode circuit used as a bias circuit

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 5th International Conference on Engineering Technology and its Applications 2022- (5thIICETA2022)
The modified Widlar current source is depicted in “Fig. 4” V+
[3] and the equivalent circuit to find the output resistance of Q 7 IREF
is depicted in “Fig. 5”. To account for this resistance, a test R2 Io
voltage and current; Vo7 and Io7 are applied, they are given by
Vc

Vbe7 Vbe7 Vo7 Qa Qb

Io7 = + βIb7 + + ()
rbe7 ro7 ro5

R R
Vbe7 Vbe7
V07 = Vbe7 + ( + βIb7 + )R ()
rbe7 ro7

where rbe , Vbe , and Ib are small signal resistance, base-emitter V-

voltage, and base current for Q 7 , respectively, where the second

subscript in the notation above refers to the transistor’s number. Fig. 4. Modified Widlar current source.
The output resistances for Q 5 and Q 7 are ro5 and ro7 ,
respectively. So
+ Io7
ro7 βIb7 rbe7 Vbe7
βVT
rbe7 = , -
+ V
Ic5 ro5
- o7
VAN
ro5 = ,
Ic5 R
VAp
ro7 = ,
Ic5
Vbe7
Ib7 = ,
rbe7 Fig. 5. Equivalent circuit to find R O7.

and Here, β = 185.8 for 2N4058 pnp transistors. The voltages

VAN = 74.03 V, and VAp = 45.7 V are the Early voltages for
Ic4 Q 5 and Q 7 transistors, respectively, the current Ic5 is the
Ic5 = . collector current for Q 5 . From (4) and (5), the output resistance
2
R o7 for Q 7 is given by
V+
(1+β) 1
1 Io7 1 +
rbe7 ro7
= = + 1+β 1
Ro7 Vo7 ro5 1+( + )R
rbe7 ro7
ro5 [ro7 rbe7 +{rbe7 +(1+β)ro7 }R]
R o7 = (r (6)
o7 +ro5 )rbe7 +(1+β)ro5 ro7 +{(1+β)ro7 +rbe7 }R
R R
Let R = 1 kΩ, and VT = 26 mV, the calculated value of
R o7 is 1.06 kΩ.
Q7 Q8 The equivalent circuit to calculate the output resistance for
Q 8 ; R o8 , is depicted in “Fig. 6”, from this circuit

Vo8 −Ve8
V+ Io8 = + βIb8 ()
v1 Q5 Q6 v2 ro8
IREF

R1 0−Ve8
(Ro7 +rbe8 )
= Ib8 ()

Q3 Q4 Ve8 = Io8 R′o8 ()

Where

R′o8 = R ‖(R o7 + rbe8 ) ()

Q1 Q2

From (7), (8), and (9),

Vo8 ro8 rbe8 +{rbe8 +(1+β)ro8 +Ro7 }R+ro8 Ro7
R o8 =
Io8
=
R+(rbe8 +Ro7 )
()
V-

Fig. 3. Differential amplifier with biasing circuit.

and the calculated value for it is 1.624 MΩ.

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5th International Conference on Engineering Technology and its Applications 2022- (5thIICETA2022)
The output resistance for the cascode stage can be i- For first value, the results are as follows; IREF =
determined from [12] as, 0.412 mA, Ic4 = 0.403 mA, R o7 = 1.124 kΩ, R o8 =
1.841 MΩ, R o4 = 33.1 MΩ, and AV = −2374.
R o4 = ro4 (1 + g m rbe4 ) () The simulation according to this value is performed with
NI Multisim [13]. The currents are depicted in “Fig. 8”,
where while input and output voltages are depicted in “Fig. 9”.
β
gm = , The voltage gain is about −2450 as seen from input and
rbe4
output waveforms depicted in “Fig. 10”.
Its value is 17.53 MΩ.
ii- For second value, the obtained results are IREF =
The open-circuit differential mode voltage gain, AV ,
assuming high output resistance as an approximation [3] for the 0.22 mA, Ic4 = 0.215 mA, R o7 = 1.237 kΩ, R o8 =
cascode stage, can be found using the small signal equivalent 2.1 MΩ, R o4 = 63.74 MΩ, and A V = −2145.
circuit depicted in “Fig. 7”, and can be determined as follows; B- Again in MATLAB, and for the second case; the value for
R1 = 8.25 kΩ is taken which is the same as before but now
Vo6 = −βIb6 (ro6 ‖R o8 ) () two values for R are considered, they are 2.32 kΩ and
5 kΩ.
since Vin6 = Vbe6 , so i- For first value the results obtained are; R o7 = 2.356 kΩ,
R o8 = 3.076 MΩ, and AV = −2682,
ii- For the second value the results are R o7 = 4.934 kΩ,
Vo6 β
AV = =− (r ‖R ) R o8 = 4.99 MΩ, and AV = −2743.
Vin6 rbe6 o6 o8
or Same results are obtained for R o4 as before in each one of
these two values. Also, the simulation that carried out for the
AV = −g m6 (ro6 ‖R o8 ) () second value, it is taken here as an illustration, is depicted in
“Fig. 11” and “Fig. 12”, respectively and the obtained AV is
The obtained value for AV is −2550. about −2790.
Ro7
VI. DISCUSSIONS
+ Io8
Vbe8 +
rbe8 βIb8 ro8
From the above results and for the first case, it can be seen
- -
+ V
from (1) and (3) that as R1 increased, IREF and Ic4 are
Ve8
- o8
decreased. This cause an increase in R o7 , R o8 , and R o4 as seen
from (6), (10), and (11), respectively due to the increase in ro5 ,
R
ro7 , ro8 , and ro4 . The open circuit differential voltage gain is
decreased because of the decreasing in g m6 as seen from (14).
For a fixed bias currents; the second case, the output
Fig 6. Equivalent circuit to find R o8. resistances R o7 and R o8 are also increased with increasing in R
as seen from (6) and (11), while the open circuit differential
voltage gain is now increasing in this case due to an increase in
R o8 .
+
V2
Vbe6 ro6
rbe6 βIb6 Ro8 Vo6
4V
R2 R3
- 1kΩ 1kΩ

Q7 Q8
V1 2N4058 2N4058
4V U3
Fig 7. Equivalent circuit to find AV . -
U1
+
+
0.199m
-
A
A 0.422m
DC 1e-009Ohm
DC 1e-009Ohm
V. SIMULATION AND RESULTS R1
16kΩ
Q5
2N3414
Q6
2N3414

For design, two cases are considered to evaluate the output

resistance of both the differential amplifier and the cascode
stage, and the open-circuit differential mode voltage gain of the Q3 Q4

differential amplifier. 2N3414 2N3414

U2
The first case is by changing the biasing current Ic4 while the +
0.409m
-
A

second is the change in the resistors values; R. DC 1e-009Ohm

Q1 Q2
2N3414 2N3414

A- With MATLAB and for the first case, let R = 1 kΩ, two V3

values are taken for R1 , 16 kΩ and 30 kΩ. 4V

Fig. 8. Reference and biasing currents for R1 = 16 kΩ and R = 1 kΩ.

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 5th International Conference on Engineering Technology and its Applications 2022- (5thIICETA2022)
V2
XSC1
V2
XSC1 4V Ext Trig
+
R2 R3 _
4V Ext Trig 5kΩ 5kΩ A B
+ + _ + _
R2 R3 _
A B
1kΩ 1kΩ + _ + _

XSC2
Q7 Q8
Ext Trig
XSC2 V1 2N4058 2N4058 +
Q7 Q8 4V _
XFG2 A B
V1 2N4058 2N4058 Ext Trig U1 + _ + _
4V +
- +
XFG2 _
A COM
U1 A B 0.814m
_ _
- + + +
A 0.422m COM DC 1e-009Ohm Q5 Q6 XFG1
R1
8.25kΩ 2N3414 2N3414
DC 1e-009Ohm Q5 Q6 XFG1 COM
R1
16kΩ 2N3414 2N3414
COM
U2
- +
A
U2 0.389m
- +
A 0.202m DC 1e-009Ohm
Q3 Q4
DC 1e-009Ohm
2N3414 2N3414
Q3 Q4
2N3414 2N3414 U3
+ -
U3 0.791m A
+ -
0.409m A DC 1e-009Ohm

DC 1e-009Ohm Q1 Q2
2N3414 2N3414
Q1 Q2
2N3414 2N3414 V3

V3
4V
4V

Fig. 9. Differential amplifier with R1 = 16 kΩ and R = 1 kΩ.

Fig11. Differential amplifier with R1 = 8.25 kΩ and R = 5 kΩ.

(a)
(a)

(b)
Fig12. Input voltage (a) and output voltage (b) for R1 = 8.25 kΩ and R =
(b) 5 kΩ.

Fig. 10. Input voltage (a) and output voltage (b) for R1 = 16 kΩ and R = VII. CONCLUSIONS
1 kΩ.
A BJT differential amplifier with active load is analyzed and
designed. The focusing is on the output resistances of both the
biasing and the active load circuits and the open circuit
differential mode voltage gain.
The output resistance of the biasing circuit and the active load
stage are increased with decreasing the biasing currents.
The open circuit differential mode voltage gain is decreased
because of the decrease in the transconductance parameter. The
output resistance is also increased with increasing the
resistance in the active load circuit but the voltage gain is
increased in this case.
The results obtained from simulation are in closed agreement
with that obtained from calculations.

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5th International Conference on Engineering Technology and its Applications 2022- (5thIICETA2022)
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