LTC2333-16

Buffered 8-Channel, 16-Bit, 800ksps

Differential ±10.24V ADC with
30VP-P Common Mode Range
Features Description
nn Eight Buffered Multiplexed Channels The LTC®2333-16 is a 16-bit, low noise 8-channel multi-
nn 800ksps Throughput plexed successive approximation register (SAR) ADC with
nn 500pA/12nA Maximum Input Leakage at 85°C/125°C buffered differential, wide common mode range picoamp
nn ±1LSB INL (Maximum ±10.24V Range) inputs. Operating from a 5V low voltage supply, flexible
nn Guaranteed 16-Bit, No Missing Codes high voltage supplies, and using the internal reference
nn Differential, Wide Common Mode Range Inputs and buffer, this SoftSpan™ ADC can be configured on a
nn 8-Channel Multiplexer with SoftSpan Input Ranges: conversion-by-conversion basis to accept ±10.24V, 0V to
±10.24V, 0V to 10.24V, ±5.12V, 0V to 5.12V 10.24V, ±5.12V, or 0V to 5.12V signals on any channel.
±12.5V, 0V to 12.5V, ±6.25V, 0V to 6.25V Alternately, the ADC may be programmed to cycle through
nn 94.2dB Single-Conversion SNR (Typical) a sequence of channels and ranges without further user
nn −110dB THD (Typical) at f = 2kHz intervention.
IN
nn 128dB CMRR, –125dB Active Crosstalk (Typical)
nn 420ns Step Response (Full-Scale, 0.005% Settling)
The integrated picoamp-input analog buffers, wide input
nn Rail-to-Rail Input Overdrive Tolerance
common mode range and 128dB CMRR of the LTC2333-
nn Programmable Sequencer with No-Latency Control
16 allow the ADC to directly digitize a variety of signals
nn Integrated Reference and Buffer (4.096V)
using minimal board space and power. This input signal
nn SPI CMOS (1.8V to 5V) and LVDS Serial I/O
flexibility, combined with ±1LSB INL, no missing codes
nn 268mW Power Dissipation (Typical)
at 16 bits, and 94.2dB SNR, makes the LTC2333-16 an
nn 48-Lead (7mm × 7mm) LQFP Package
ideal choice for many high voltage applications requiring
wide dynamic range.
Applications The LTC2333-16 supports pin-selectable SPI CMOS (1.8V
nn Direct Sensor Measurement to 5V) and LVDS serial interfaces.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
nn Programmable Logic Controllers SoftSpan is a trademark of Analog Devices, Inc. All other trademarks are the property of their
nn Industrial Process Control respective owners. Protected by U.S. Patents, including 7705765, 7961132, 8319673, 9197235.

nn Test and Measurement

Typical Application
15V 5V 1.8V TO 5V Integral Nonlinearity vs
0.1µF 0.1µF 2.2µF 0.1µF
Output Code and Channel
CMOS OR LVDS 1.00
I/O INTERFACE ±10.24V RANGE
0.75 TRUE BIPOLAR DRIVE (IN– = 0V)
FULLY BUFFERS VCC VDD VDDLBYP OVDD LVDS/CMOS ALL CHANNELS
ARBITRARY DIFFERENTIAL PD
+10V +5V 0.50
IN0+ LTC2333-16
INL ERROR (LSB)

0V 0V IN0– 0.25
SDO
–10V –5V SCKO 0
16-BIT SCKI
• • •

TRUE BIPOLAR UNIPOLAR MUX SAMPLING SDI –0.25

+10V +10V ADC CS
BUSY SAMPLE –0.50
0V 0V IN7+ CNV CLOCK
IN7– –0.75
–10V –10V
–1.00
DIFFERENTIAL INPUTS IN+/IN– WITH VEE REFBUF REFIN GND –32768 –16384 0 16384 32768
WIDE INPUT COMMON MODE RANGE
233316 TA01a OUTPUT CODE
EIGHT BUFFERED
47µF 0.1µF 233316 TA01b
CHANNELS 0.1µF

–15V

233316f

For more information www.linear.com/LTC2333-16 1

LTC2333-16
Absolute Maximum Ratings Pin Configuration
(Notes 1, 2)
TOP VIEW
Supply Voltage (VCC)......................–0.3V to (VEE + 40V)

VDDLBYP
Supply Voltage (VEE)................................. –17.4V to 0.3V

BUSY
IN7+
IN7–
GND

GND

GND
VDD
VDD

SDI
VEE
Supply Voltage Difference (VCC – VEE).......................40V

CS
48
47
46
45
44
43
42
41
40
39
38
37
Supply Voltage (VDD)...................................................6V
Supply Voltage (OVDD).................................................6V
Internal Regulated Supply Bypass (VDDLBYP).... (Note 3) IN6– 1 36 GND
IN6+ 2 35 SDO–
Analog Input Voltage IN5– 3 34 SDO+
IN5+ 4 33 SCKO–/SDO
IN0+ to IN7+, IN4– 5 32 SCKO+/SCKO
IN4+ 6
IN0– to IN7– (Note 4).......... (VEE – 0.3V) to (VCC + 0.3V) IN3– 7
31
30
OVDD
GND
REFIN..................................................... –0.3V to 2.8V IN3+ 8 29 SCKI–/SCKI
IN2– 9 28 SCKI+
REFBUF, CNV (Note 5).............. –0.3V to (VDD + 0.3V) IN2+ 10 27 SDI–
IN1– 11 26 SDI+
Digital Input Voltage (Note 5)...... –0.3V to (OVDD + 0.3V) IN1+ 12 25 GND
Digital Output Voltage (Note 5)... –0.3V to (OVDD + 0.3V)
Power Dissipation............................................... 500mW

IN0– 13
IN0+ 14
GND 15
VCC 16
VEE 17
GND 18
REFIN 19
GND 20
REFBUF 21
PD 22
LVDS/CMOS 23
CNV 24
Operating Temperature Range
LTC2333C................................................. 0°C to 70°C
LTC2333I..............................................–40°C to 85°C
LTC2333H........................................... –40°C to 125°C LX PACKAGE
48-LEAD (7mm × 7mm) PLASTIC LQFP
Storage Temperature Range................... –65°C to 150°C TJMAX = 150°C, θJA = 53°C/W

Order Information http://www.linear.com/product/LTC2333-16#orderinfo

TRAY PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE

LTC2333CLX-16#PBF LTC2333LX-16 48-Lead (7mm × 7mm) Plastic LQFP 0°C to 70°C
LTC2333ILX-16#PBF LTC2333LX-16 48-Lead (7mm × 7mm) Plastic LQFP –40°C to 85°C
LTC2333HLX-16#PBF LTC2333LX-16 48-Lead (7mm × 7mm) Plastic LQFP –40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through
designated sales channels with #TRMPBF suffix.

233316f

2 For more information www.linear.com/LTC2333-16

 LTC2333-16
Electrical Characteristics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 6)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VIN+ Absolute Input Range (Note 7) l VEE + 4 VCC – 4 V
(IN0+ to IN7+)
VIN– Absolute Input Range (Note 7) l VEE + 4 VCC – 4 V
(IN0– to IN7–)
VIN+ – VIN– Input Differential Voltage SoftSpan 7: ±2.5 • VREFBUF Range (Note 7) l –2.5 • VREFBUF 2.5 • VREFBUF V
Range SoftSpan 6: ±2.5 • VREFBUF/1.024 Range (Note 7) l –2.5 • VREFBUF/1.024 2.5 • VREFBUF/1.024 V
SoftSpan 5: 0V to 2.5 • VREFBUF Range (Note 7) l 0 2.5 • VREFBUF V
SoftSpan 4: 0V to 2.5 • VREFBUF/1.024 Range (Note 7) l 0 2.5 • VREFBUF/1.024 V
SoftSpan 3: ±1.25 • VREFBUF Range (Note 7) l –1.25 • VREFBUF 1.25 • VREFBUF V
SoftSpan 2: ±1.25 • VREFBUF/1.024 Range (Note 7) l –1.25 • VREFBUF/1.024 1.25 • VREFBUF/1.024 V
SoftSpan 1: 0V to 1.25 • VREFBUF Range (Note 7) l 0 1.25 • VREFBUF V
SoftSpan 0: 0V to 1.25 • VREFBUF/1.024 Range (Note 7) l 0 1.25 • VREFBUF/1.024 V
VCM Input Common Mode Voltage (Note 7) l VEE + 4 VCC – 4 V
Range
VIN+ – VIN– Input Differential Overdrive (Note 8) l −(VCC − VEE) (VCC − VEE) V
Tolerance
IOVERDRIVE Input Overdrive VIN+ > VCC, VIN− > VCC (Note 8) l 10 mA
Current Tolerance VIN+ < VEE, VIN− < VEE (Note 8) l 0 mA
IIN Analog Input Leakage Current 5 pA
C-Grade and I-Grade l 500 pA
H-Grade l 12 nA
RIN Analog Input Resistance For Each Pin >1000 GΩ
CIN Analog Input Capacitance 3 pF
CMRR Input Common Mode VIN+ = VIN− = 18VP-P 200Hz Sine l 105 128 dB
Rejection Ratio
VIHCNV CNV High Level Input Voltage l 1.3 V
VILCNV CNV Low Level Input Voltage l 0.5 V
IINCNV CNV Input Current VIN = 0V to VDD l –10 10 μA

Converter Characteristics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 9)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Resolution l 16 Bits
No Missing Codes l 16 Bits
Transition Noise SoftSpans 7 and 6: ±10.24V and ±10V Ranges 0.35 LSBRMS
SoftSpans 5 and 4: 0V to 10.24V and 0V to 10V Ranges 0.7 LSBRMS
SoftSpans 3 and 2: ±5.12V and ±5V Ranges 0.5 LSBRMS
SoftSpans 1 and 0: 0V to 5.12V and 0V to 5V Ranges 1.1 LSBRMS
INL Integral Linearity Error SoftSpans 7 and 6: ±10.24V and ±10V Ranges (Note 10) l –1 ±0.3 1 LSB
SoftSpans 5 and 4: 0V to 10.24V and 0V to 10V Ranges (Note 10) l –1.25 ±0.4 1.25 LSB
SoftSpans 3 and 2: ±5.12V and ±5V Ranges (Note 10) l –1 ±0.3 1 LSB
SoftSpans 1 and 0: 0V to 5.12V and 0V to 5V Ranges (Note 10) l –1.5 ±0.5 1.5 LSB
DNL Differential Linearity Error (Note 11) l −0.9 ±0.2 0.9 LSB
ZSE Zero-Scale Error (Note 12) l −700 ±160 700 μV
Zero-Scale Error Drift ±4 μV/°C
FSE Full-Scale Error VREFBUF = 4.096V (REFBUF Overdriven) (Note 12) l −0.1 ±0.025 0.1 %FS
Full-Scale Error Drift VREFBUF = 4.096V (REFBUF Overdriven) (Note 12) ±2.5 ppm/°C

233316f

For more information www.linear.com/LTC2333-16 3

LTC2333-16
Dynamic Accuracy The l denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Notes 9, 13)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
SINAD Signal-to-(Noise + SoftSpans 7 and 6: ±10.24V and ±10V Ranges, fIN = 2kHz l 91.6 94.1 dB
Distortion) Ratio SoftSpans 5 and 4: 0V to 10.24V and 0V to 10V Ranges, fIN = 2kHz l 86.7 89.6 dB
SoftSpans 3 and 2: ±5.12V and ±5V Ranges, fIN = 2kHz l 88.8 91.5 dB
SoftSpans 1 and 0: 0V to 5.12V and 0V to 5V Ranges, fIN = 2kHz l 83.4 86.3 dB
SNR Signal-to-Noise Ratio SoftSpans 7 and 6: ±10.24V and ±10V Ranges, fIN = 2kHz l 92.0 94.2 dB
SoftSpans 5 and 4: 0V to 10.24V and 0V to 10V Ranges, fIN = 2kHz l 86.9 89.7 dB
SoftSpans 3 and 2: ±5.12V and ±5V Ranges, fIN = 2kHz l 88.9 91.5 dB
SoftSpans 1 and 0: 0V to 5.12V and 0V to 5V Ranges, fIN = 2kHz l 83.5 86.3 dB
THD Total Harmonic Distortion SoftSpans 7 and 6: ±10.24V and ±10V Ranges, fIN = 2kHz l –110 –101 dB
SoftSpans 5 and 4: 0V to 10.24V and 0V to 10V Ranges, fIN = 2kHz l –110 –99 dB
SoftSpans 3 and 2: ±5.12V and ±5V Ranges, fIN = 2kHz l –114 –102 dB
SoftSpans 1 and 0: 0V to 5.12V and 0V to 5V Ranges, fIN = 2kHz l –115 –101 dB
SFDR Spurious Free Dynamic SoftSpans 7 and 6: ±10.24V and ±10V Ranges, fIN = 2kHz l 101 111 dB
Range SoftSpans 5 and 4: 0V to 10.24V and 0V to 10V Ranges, fIN = 2kHz l 100 111 dB
SoftSpans 3 and 2: ±5.12V and ±5V Ranges, fIN = 2kHz l 102 115 dB
SoftSpans 1 and 0: 0V to 5.12V and 0V to 5V Ranges, fIN = 2kHz l 104 115 dB
Channel-to-Channel Alternating Conversions with 18VP-P 200Hz Sine in ±10.24V –125 dB
Active Crosstalk Range, Crosstalk to Any Other Channel
–3dB Input Bandwidth 6 MHz
Aperture Delay 1 ns
Aperture Delay Matching 150 ps
Aperture Jitter 3 psRMS
Transient Response Full-Scale Step, 0.005% Settling 420 ns

Internal Reference Characteristics

The l denotes the specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C. (Note 9)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VREFIN Internal Reference Output Voltage 2.043 2.048 2.053 V
Internal Reference Temperature Coefficient (Note 14) l 5 20 ppm/°C
Internal Reference Line Regulation VDD = 4.75V to 5.25V 0.1 mV/V
Internal Reference Output Impedance 20 kΩ
VREFIN REFIN Voltage Range REFIN Overdriven (Note 7) 1.25 2.2 V

233316f

4 For more information www.linear.com/LTC2333-16

 LTC2333-16
Reference Buffer Characteristics
The l denotes the specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C. (Note 9)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VREFBUF Reference Buffer Output Voltage REFIN Overdriven, VREFIN = 2.048V l 4.091 4.096 4.101 V
REFBUF Voltage Range REFBUF Overdriven (Notes 7, 15) l 2.5 5 V
REFBUF Input Impedance VREFIN = 0V, Buffer Disabled 13 kΩ
IREFBUF REFBUF Load Current VREFBUF = 5V, (Notes 15, 16) l 0.93 1.2 mA
VREFBUF = 5V, Acquisition or Nap Mode (Note 15) 0.39 mA

Digital Inputs and Digital Outputs The l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. (Note 9)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
CMOS Digital Inputs and Outputs
VIH High Level Input Voltage l 0.8 • OVDD V
VIL Low Level Input Voltage l 0.2 • OVDD V
IIN Digital Input Current VIN = 0V to OVDD l –10 10 μA
CIN Digital Input Capacitance 5 pF
VOH High Level Output Voltage IOUT = –500μA l OVDD – 0.2 V
VOL Low Level Output Voltage IOUT = 500μA l 0.2 V
IOZ Hi-Z Output Leakage Current VOUT = 0V to OVDD l –10 10 μA
ISOURCE Output Source Current VOUT = 0V –50 mA
ISINK Output Sink Current VOUT = OVDD 50 mA
LVDS Digital Inputs and Outputs
VID Differential Input Voltage l 200 350 600 mV
RID On-Chip Input Termination CS = 0V, VICM = 1.2V l 90 106 125 Ω
Resistance CS = OVDD 10 MΩ
VICM Common-Mode Input Voltage l 0.3 1.2 2.2 V
IICM Common-Mode Input Current VIN+ = VIN– = 0V to OVDD l –10 10 μA
VOD Differential Output Voltage RL = 100Ω Differential Termination l 275 350 425 mV
VOCM Common-Mode Output Voltage RL = 100Ω Differential Termination l 1.1 1.2 1.3 V
IOZ Hi-Z Output Leakage Current VOUT = 0V to OVDD l –10 10 μA

233316f

For more information www.linear.com/LTC2333-16 5

LTC2333-16
Power Requirements The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 9)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VCC Supply Voltage l 7.5 38 V
VEE Supply Voltage l –16.5 0 V
VCC − VEE Supply Voltage Difference l 10 38 V
VDD Supply Voltage l 4.75 5.00 5.25 V
IVCC Supply Current 800ksps Sample Rate (Note 17) l 7.2 7.7 mA
Acquisition Mode (Note 17) l 8.4 9.1 mA
Nap Mode l 2.9 3.3 mA
Power Down Mode l 6 15 μA
IVEE Supply Current 800ksps Sample Rate (Note 17) l –7.6 –6.7 mA
Acquisition Mode (Note 17) l –9.2 –8.1 mA
Nap Mode l –3.5 –2.8 mA
Power Down Mode l –15 –4 μA
CMOS I/O Mode
OVDD Supply Voltage l 1.71 5.25 V
IVDD Supply Current 800ksps Sample Rate l 10.6 11.9 mA
800ksps Sample Rate, VREFBUF = 5V (Note 15) l 9.4 10.7 mA
Acquisition Mode l 2.1 2.7 mA
Nap Mode l 1.7 2.4 mA
Power Down Mode (C-Grade and I-Grade) l 106 275 μA
Power Down Mode (H-Grade) l 106 550 µA
IOVDD Supply Current 800ksps Sample Rate (CL = 25pF) l 2.4 2.9 mA
Acquisition or Nap Mode l 1 20 μA
Power Down Mode l 1 20 μA
PD Power Dissipation 800ksps Sample Rate (Note 17) l 268 296 mW
Acquisition Mode (Note 17) l 258 288 mW
Nap Mode l 94 114 mW
Power Down Mode (C-Grade and I-Grade) l 0.68 1.9 mW
Power Down Mode (H-Grade) l 0.68 3.3 mW
LVDS I/O Mode
OVDD Supply Voltage l 2.375 5.25 V
IVDD Supply Current 800ksps Sample Rate l 13.4 14.5 mA
800ksps Sample Rate, VREFBUF = 5V (Note 15) l 12.2 13.7 mA
Acquisition Mode l 3.7 4.5 mA
Nap Mode l 3.4 4.1 mA
Power Down Mode (C-Grade and I-Grade) l 106 275 μA
Power Down Mode (H-Grade) l 106 550 µA
IOVDD Supply Current 800ksps Sample Rate, (RL = 100Ω) l 7 8.8 mA
Acquisition or Nap Mode (RL = 100Ω) l 7 8.3 mA
Power Down Mode l 1 20 μA
PD Power Dissipation 800ksps Sample Rate (Note 17) l 293 324 mW
Acquisition Mode (Note 17) l 284 318 mW
Nap Mode l 120 143 mW
Power Down Mode (C-Grade and I-Grade) l 0.68 1.9 mW
Power Down Mode (H-Grade) l 0.68 3.3 mW

233316f

6 For more information www.linear.com/LTC2333-16

 LTC2333-16
ADC Timing Characteristics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 9)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fSMPL Maximum Sampling Frequency l 800 ksps
tCYC Time Between Conversions l 1.25 μs
tCONV Conversion Time l 450 500 550 ns
tACQ Acquisition Time (tACQ = tCYC – tCONV – tBUSYLH) l 670 730 ns
tCNVH CNV High Time l 40 ns
tCNVL CNV Low Time l 750 ns
tBUSYLH CNV↑ to BUSY Delay CL = 25pF l 30 ns
tQUIET Digital I/O Quiet Time from CNV↑ l 20 ns
tPDH PD High Time l 40 ns
tPDL PD Low Time l 40 ns
tWAKE REFBUF Wake-Up Time CREFBUF = 47μF, CREFIN = 0.1μF 200 ms
CMOS I/O Mode
tSCKI SCKI Period (Notes 18, 19) l 10 ns
tSCKIH SCKI High Time l 4 ns
tSCKIL SCKI Low Time l 4 ns
tSSDISCKI SDI Setup Time from SCKI↑ (Note 18) l 2 ns
tHSDISCKI SDI Hold Time from SCKI↑ (Note 18) l 1 ns
tDSDOSCKI SDO Data Valid Delay from SCKI↑ CL = 25pF (Note 18) l 7.5 ns
tHSDOSCKI SDO Remains Valid Delay from SCKI↑ CL = 25pF (Note 18) l 1.5 ns
tSKEW SDO to SCKO Skew (Note 18) l –1 0 1 ns
tDSDOBUSYL SDO Data Valid Delay from BUSY↓ CL = 25pF (Note 18) l 0 ns
tEN Bus Enable Time After CS↓ (Note 18) l 15 ns
tDIS Bus Relinquish Time After CS↑ (Note 18) l 15 ns
LVDS I/O Mode
tSCKI SCKI Period (Note 20) l 4 ns
tSCKIH SCKI High Time (Note 20) l 1.5 ns
tSCKIL SCKI Low Time (Note 20) l 1.5 ns
tSSDISCKI SDI Setup Time from SCKI (Notes 11, 20) l 1.2 ns
tHSDISCKI SDI Hold Time from SCKI (Notes 11, 20) l –0.2 ns
tDSDOSCKI SDO Data Valid Delay from SCKI (Notes 11, 20) l 6 ns
tHSDOSCKI SDO Remains Valid Delay from SCKI (Notes 11, 20) l 1 ns
tSKEW SDO to SCKO Skew (Note 11) l –0.4 0 0.4 ns
tDSDOBUSYL SDO Data Valid Delay from BUSY↓ (Note 11) l 0 ns
tEN Bus Enable Time After CS↓ l 50 ns
tDIS Bus Relinquish Time After CS↑ l 15 ns

233316f

For more information www.linear.com/LTC2333-16 7

LTC2333-16
ADC Timing Characteristics
Note 1: Stresses beyond those listed under Absolute Maximum Ratings Note 10: Integral nonlinearity is defined as the deviation of a code from a
may cause permanent damage to the device. Exposure to any Absolute straight line passing through the actual endpoints of the transfer curve.
Maximum Rating condition for extended periods may affect device The deviation is measured from the center of the quantization band.
reliability and lifetime. Note 11: Guaranteed by design, not subject to test.
Note 2: All voltage values are with respect to GND. Note 12: For bipolar SoftSpan ranges 7, 6, 3, and 2, zero-scale error is
Note 3: VDDLBYP is the output of an internal voltage regulator, and should the offset voltage measured from –0.5LSB when the output code flickers
only be connected to a 2.2μF ceramic capacitor to bypass the pin to GND, between 0000 0000 0000 0000 and 1111 1111 1111 1111. Full-scale
as described in the Pin Functions section. Do not connect this pin to any error for these SoftSpan ranges is the worst-case deviation of the first
external circuitry. and last code transitions from ideal and includes the effect of offset
Note 4: When these pin voltages are taken below VEE or above VCC, they error. For unipolar SoftSpan ranges 5, 4, 1, and 0, zero-scale error is
will be clamped by internal diodes. This product can handle input currents the offset voltage measured from 0.5LSB when the output code flickers
of up to 100mA below VEE or above VCC without latchup. between 0000 0000 0000 0000 and 0000 0000 0000 0001. Full-scale error
Note 5: When these pin voltages are taken below GND or above VDD or for these SoftSpan ranges is the worst-case deviation of the last code
OVDD, they will be clamped by internal diodes. This product can handle transition from ideal and includes the effect of offset error.
currents of up to 100mA below GND or above VDD or OVDD without Note 13: All specifications in dB are referred to a full-scale input in the
latchup. relevant SoftSpan input range, except for crosstalk, which is referred to
Note 6: –16.5V ≤ VEE ≤ 0V, 7.5V ≤ VCC ≤ 38V, 10V ≤ (VCC – VEE) ≤ 38V, the crosstalk injection signal amplitude.
VDD = 5V, unless otherwise specified. Note 14: Temperature coefficient is calculated by dividing the maximum
Note 7: Recommended operating conditions. change in output voltage by the specified temperature range.
Note 8: Exceeding these limits on any channel may corrupt conversion Note 15: When REFBUF is overdriven, the internal reference buffer must
results on other channels. Driving an analog input above VCC on any be disabled by setting REFIN = 0V.
channel up to 10mA will not affect conversion results on other channels. Note 16: IREFBUF varies proportionally with sample rate.
Driving an analog input below VEE may corrupt conversion results on other Note 17: Analog input buffer supply currents from IVCC and IVEE are
channels. Refer to Applications Information section for further details. reduced outside the acquisition period. Refer to nap mode in Applications
Refer to Absolute Maximum Ratings section for pin voltage limits related Information section.
to device reliability. Note 18: Parameter tested and guaranteed at OVDD = 1.71V, OVDD = 2.5V,
Note 9: VCC = 15V, VEE = –15V, VDD = 5V, OVDD = 2.5V, fSMPL = 800ksps, and OVDD = 5.25V.
internal reference and buffer, true bipolar input signal drive in bipolar Note 19: A tSCKI period of 10ns minimum allows a shift clock frequency of
SoftSpan ranges, unipolar signal drive in unipolar SoftSpan ranges, unless up to 100MHz for rising edge capture.
otherwise specified. Note 20: VICM = 1.2V, VID = 350mV for LVDS differential input pairs.

CMOS Timing

0.8 • OVDD
tWIDTH
0.2 • OVDD

tDELAY tDELAY 50% 50%

0.8 • OVDD 0.8 • OVDD 233316 F01a

0.2 • OVDD 0.2 • OVDD

LVDS Timing (Differential)

+200mV
tWIDTH
–200mV

tDELAY tDELAY 0V 0V

+200mV +200mV 233316 F01b

–200mV –200mV

Figure 1. Voltage Levels for Timing Specifications

233316f

8 For more information www.linear.com/LTC2333-16

 LTC2333-16
Typical Performance Characteristics
TA = 25°C, VCC = +15V, VEE = –15V, VDD = 5V,
OVDD = 2.5V, Internal Reference and Buffer (VREFBUF = 4.096V), fSMPL = 800ksps, unless otherwise noted.

Integral Nonlinearity Integral Nonlinearity Differential Nonlinearity

vs Output Code and Channel vs Output Code and Channel vs Output Code and Range
1.00 1.00 0.5
±10.24V RANGE ±10.24V RANGE ALL RANGES
0.75 TRUE BIPOLAR DRIVE (IN– = 0V) 0.75 FULLY DIFFERENTIAL DRIVE (IN– = –IN+) 0.4 ALL CHANNELS
ALL CHANNELS ALL CHANNELS
0.3
0.50 0.50
0.2

DNL ERROR (LSB)

INL ERROR (LSB)

INL ERROR (LSB)

0.25 0.25 0.1
0 0 0.0

–0.25 –0.25 –0.1

–0.2
–0.50 –0.50
–0.3
–0.75 –0.75 –0.4
–1.00 –1.00 –0.5
–32768 –16384 0 16384 32768 –32768 –16384 0 16384 32768 0 16384 32768 49152 65536
OUTPUT CODE OUTPUT CODE OUTPUT CODE
233316 G01 233316 G02 233316 G03

Integral Nonlinearity Integral Nonlinearity Integral Nonlinearity

vs Output Code and Range vs Output Code and Range vs Output Code and Range
1.00 1.00 1.00
TRUE BIPOLAR DRIVE (IN– = 0V) FULLY DIFFERENTIAL DRIVE (IN– = –IN+) UNIPOLAR DRIVE (IN– = 0V)
0.75 ONE CHANNEL 0.75 ONE CHANNEL 0.75 ONE CHANNEL

0.50 ±10.24V AND ±10V 0.50 0.50

RANGES
INL ERROR (LSB)

INL ERROR (LSB)

0.25 0.25 ±10.24V AND ±10V INL ERROR (LSB) 0.25 0V TO 5.12V RANGE
RANGES
0 0 0

–0.25 ±5.12V AND ±5V –0.25 –0.25

±5.12V AND ±5V
RANGES RANGES
–0.50 –0.50 –0.50 0V TO 10.24V AND
0V TO 10V RANGES
–0.75 –0.75 –0.75

–1.00 –1.00 –1.00

–32768 –16384 0 16384 32768 –32768 –16384 0 16384 32768 0 16384 32768 49152 65536
OUTPUT CODE OUTPUT CODE OUTPUT CODE
233316 G04 233316 G05 233316 G06

Integral Nonlinearity
vs Output Code DC Histogram (Zero-Scale) DC Histogram (Near Full-Scale)
1.00 200000 200000
±10.24V RANGE ±10.24V RANGE ±10.24V RANGE
0.75 180000 180000
160000 160000
0.50 TRUE BIPOLAR DRIVE (IN– = 0V)
140000 140000
INL ERROR (LSB)

0.25 120000 120000

COUNTS

COUNTS

0 100000 100000

–0.25 80000 80000

60000 60000
–0.50
ARBITRARY DRIVE 40000 40000
IN+/IN– COMMON MODE
–0.75 20000 20000
SWEPT –10.24V to 10.24V
–1.00 0 0
–32768 –16384 0 16384 32768 –4 –3 –2 –1 0 1 2 3 32759 32761 32763 32765 32767
OUTPUT CODE CODE CODE
233316 G07 233316 G08 233316 G09

233316f

For more information www.linear.com/LTC2333-16 9

LTC2333-16
Typical Performance Characteristics
TA = 25°C, VCC = +15V, VEE = –15V, VDD = 5V,
OVDD = 2.5V, Internal Reference and Buffer (VREFBUF = 4.096V), fSMPL = 800ksps, unless otherwise noted.
32k Point Arbitrary Two-Tone FFT
32k Point FFT fSMPL = 800ksps, 32k Point FFT fSMPL = 800ksps, fSMPL = 800ksps, IN+ = –7dBFS 2kHz
fIN = 2kHz fIN = 2kHz Sine, IN– = –7dBFS 3.1kHz Sine
0 0 0
±10.24V RANGE ±10.24V RANGE ±10.24V RANGE
–20 TRUE BIPOLAR DRIVE (IN– = 0V) –20 FULLY DIFFERENTIAL DRIVE (IN– = –IN+) –20 ARBITRARY DRIVE

–40 SNR = 94.3dB –40 SNR = 94.3dB –40 SFDR = 120dB

THD = –109dB THD = –116dB SNR = 94.3dB

AMPLITUDE (dBFS)
AMPLITUDE (dBFS)

AMPLITUDE (dBFS)
–60 SINAD = 94.2dB –60 SINAD = 94.3dB –60
SFDR = 112dB SFDR = 119dB
–80 –80 –80

–100 –100 –100

–120 –120 –120

–140 –140 –140

–160 –160 –160

–180 –180 –180

0 100 200 300 400 0 100 200 300 400 0 100 200 300 400
FREQUENCY (kHz) FREQUENCY (kHz) FREQUENCY (kHz)
233316 G10 233316 G11 233316 G12

32k Point FFT fSMPL = 800ksps, SNR, SINAD vs VREFBUF, THD, Harmonics vs VREFBUF,
fIN = 2kHz fIN = 2kHz fIN = 2kHz
0 96 –100
±5.12V RANGE ±2.5 • VREFBUF RANGE ±2.5 • VREFBUF RANGE
–20 TRUE BIPOLAR DRIVE (IN– = 0V) TRUE BIPOLAR DRIVE (IN– = 0V) TRUE BIPOLAR DRIVE (IN– = 0V)
–105
–40 SNR = 91.6dB 95

THD, HARMONICS (dBFS)

THD = –114dB SNR
AMPLITUDE (dBFS)

SNR, SINAD (dBFS)

–60 SINAD = 91.6dB –110 THD

SFDR = 117dB 94 SINAD
–80
–115
–100 2ND
93
–120 –120

–140 92
–125 3RD
–160

–180 91 –130
0 100 200 300 400 2.5 3 3.5 4 4.5 5 2.5 3 3.5 4 4.5 5
FREQUENCY (kHz) REFBUF VOLTAGE (V) REFBUF VOLTAGE (V)
233316 G13 233316 G14 233316 G15

SNR, SINAD THD, Harmonics THD, Harmonics vs Input

vs Input Frequency vs Input Frequency Common Mode, fIN = 2kHz
102 –60 0
±10.24V RANGE ±10.24V RANGE ±10.24V RANGE
TRUE BIPOLAR DRIVE (IN– = 0V) 2VP-P FULLY DIFFERENTIAL DRIVE
TRUE BIPOLAR DRIVE (IN– = 0V) –20
98 –70
–40
THD, HARMONICS (dBFS)

SNR
SNR, SINAD (dBFS)

94 –80
–60 COMMON MODE LIMITS
THD (dBFS)

10kΩ –11V ≤ VCM ≤ 11V

90 –90 SOURCE 1kΩ –80
SOURCE
SINAD
–100
86 –100
THD
–120
82 –110 50Ω
SOURCE –140
3RD 2ND
78 –120 –160
100 1k 10k 100k 10 100 1k 10k 100k –15 –10 –5 0 5 10 15
FREQUENCY (Hz) FREQUENCY (Hz) INPUT COMMON MODE (V)
233316 G16 233316 G17 233316 G18

233316f

10 For more information www.linear.com/LTC2333-16

 LTC2333-16
Typical Performance Characteristics
TA = 25°C, VCC = +15V, VEE = –15V, VDD = 5V,
OVDD = 2.5V, Internal Reference and Buffer (VREFBUF = 4.096V), fSMPL = 800ksps, unless otherwise noted.

SNR, SINAD vs Input Level, CMRR vs Input Frequency Crosstalk vs Input Frequency
fIN = 2kHz and Channel and Conversion Sequence
94.8 160 –80
±10.24V RANGE ±10.24V SOFTSPAN ±10.24V RANGE
TRUE BIPOLAR DRIVE (IN– = 0V) 150 IN+ = IN– = 18V IN0+ = 0V
P-P SINE –90
94.6 ALL CHANNELS IN0– = 18VP-P SINE
140 –100 IN1+, IN1–, IN2+, IN2– = 0V
SNR, SINAD (dBFS)

130

CROSSTALK (dB)
94.4 SNR –110 CH0, CH1, CH0, CH1...

CMRR (dB)
120
–120
110
94.2 –130
100 CH0, CH2, CH0, CH2...
SINAD –140
94.0 90

80 –150
CH1, CH1, CH1, CH1...
93.8 70 –160
–40 –30 –20 –10 0 10 100 1k 10k 100k 1M 10 100 1k 10k 100k 1M
INPUT LEVEL (dBFS) FREQUENCY (Hz) FREQUENCY (Hz)
233316 G19 233316 G20 233316 G21

SNR, SINAD vs Temperature, THD, Harmonics vs Temperature,

fIN = 2kHz fIN = 2kHz INL, DNL vs Temperature
96.0 –95 1.00
±10.24V RANGE ±10.24V RANGE ±10.24V RANGE
TRUE BIPOLAR DRIVE (IN– = 0V) TRUE BIPOLAR DRIVE (IN– = 0V) 0.75 TRUE BIPOLAR DRIVE (IN– = 0V)
95.5
–100
95.0 0.50
THD, HARMONICS (dBFS)

INL, DNL ERROR (LSB)

SNR, SINAD (dBFS)

–105 MAX INL

94.5 THD 0.25
SNR MAX DNL
94.0 –110 0
SINAD 2ND
93.5 –0.25 MIN INL
–115
93.0 3RD –0.50 MIN DNL
–120
92.5 –0.75

92.0 –125 –1.00

–55 –35 –15 5 25 45 65 85 105 125 –55 –35 –15 5 25 45 65 85 105 125 –55 –35 –15 5 25 45 65 85 105 125
TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C)
233316 G22 233316 G23 233316 G24

Analog Input Leakage Current vs Positive Full-Scale Error vs Negative Full-Scale Error vs
Temperature Temperature and Channel Temperature and Channel
10k 0.100 0.100
16 ANALOG INPUT PIN TRACES ±10.24V RANGE ±10.24V RANGE
ANALOG INPUT LEAKAGE CURRENT (pA)

FOR EACH INPUT VOLTAGE 0.075 REFBUF OVERDRIVEN 0.075 REFBUF OVERDRIVEN
1k VIN = 0V VREFBUF = 4.096V VREFBUF = 4.096V
VIN = 10V 0.050 ALL CHANNELS 0.050 ALL CHANNELS
FULL-SCALE ERROR (%)

FULL-SCALE ERROR (%)

VIN = –10V
100 0.025 0.025

0.000 0.000
10 –0.025 –0.025

–0.050 –0.050
1
–0.075 –0.075

0.1 –0.100 –0.100

–55 –35 –15 5 25 45 65 85 105 125 –55 –35 –15 5 25 45 65 85 105 125 –55 –35 –15 5 25 45 65 85 105 125
TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C)
233316 G25 233316 G26 233316 G27

233316f

For more information www.linear.com/LTC2333-16 11

LTC2333-16
Typical Performance Characteristics
TA = 25°C, VCC = +15V, VEE = –15V, VDD = 5V,
OVDD = 2.5V, Internal Reference and Buffer (VREFBUF = 4.096V), fSMPL = 800ksps, unless otherwise noted.

Zero-Scale Error vs Power-Down Current

Temperature and Channel Supply Current vs Temperature vs Temperature
3 14 1000
±10.24V RANGE IVDD
12
ALL CHANNELS IVDD
2 10
100

POWER-DOWN CURRENT (µA)

ZERO-SCALE ERROR (LSB)

SUPPLY CURRENT (mA)

1 6
IVCC
4 10 IVCC
0 2
0 IOVDD 1 –IVEE
–1 –2
–4
0.1 IOVDD
–2 –6
–8 IVEE
–3 –10 0.01
–55 –35 –15 5 25 45 65 85 105 125 –55 –35 –15 5 25 45 65 85 105 125 –55 –35 –15 5 25 45 65 85 105 125
TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C)
233316 G28 233316 G29 233316 G30

Offset Error Internal Reference Output

PSRR vs Frequency vs Input Common Mode vs Temperature
150 2.0 2.051
VCC IN+ = IN– = 0V ±10.24V RANGE
140 15 UNITS
1.5

INTERNAL REFERENCE OUTPUT (V)

2.050
130
OVDD 1.0
OFFSET ERROR (LSB)

120
2.049
110 0.5 VCC = 38V, VEE = 0V
PSRR (dB)

VCM = 4V to 34V
100 VEE 0 2.048
90 –0.5
2.047
80
–1.0 VCC = 21.5V, VEE = –16.5V
70
VCM = –12.5V to 17.5V 2.046
VDD –1.5
60
50 –2.0 2.045
10 100 1k 10k 100k –17 0 17 34 –55 –35 –15 5 25 45 65 85 105 125
FREQUENCY (Hz) INPUT COMMON MODE (V) TEMPERATURE (°C)
233316 G31 233316 G32 233316 G33

Step Response Step Response

Supply Current vs Sampling Rate (Large-Signal Settling) (Fine Settling)
14 32768 100
WITH NAP MODE ±10.24V RANGE
12 tCNVL = 750ns
24576 80 IN+ = 199.91156kHz
DEVIATION FROM FINAL VALUE (LSB)

10 SQUARE WAVE
60
16384 IN– = 0V
8 IVDD
SUPPLY CURRENT (mA)

40
OUTPUT CODE (LSB)

6 8192 20
4 IVCC ±10.24V RANGE
0 IN+ = 199.91156kHz SQUARE WAVE 0
2 IN– = 0V
–8192 –20
0 IOVDD
–40
–2 –16384
–4 –60
IVEE –24576 –80
–6
–8 –32768 –100
0 160 320 480 640 800 –100 0 100 200 300 400 500 600 700 800 900 –100 0 100 200 300 400 500 600 700 800 900
SAMPLING FREQUENCY (kHz) SETTLING TIME (ns) SETTLING TIME (ns)
233316 G34 233316 G35 233316 G36

233316f

12 For more information www.linear.com/LTC2333-16

 LTC2333-16
Pin Functions
Pins that are the Same for All Digital I/O Modes at REFIN. With the buffer disabled, overdrive REFBUF with
IN0+/IN0− to IN7+/IN7− (Pins 14/13, 12/11, 10/9, 8/7, 6/5, an external reference voltage in the range of 2.5V to 5V.
4/3, 2/1, and 48/47): Positive and Negative Analog Inputs, When using the internal reference buffer, limit the loading
Channels 0 to 7. The converter samples (VIN+ – VIN–) and of any external circuitry connected to REFBUF to less than
digitizes the selected channel. Wide input common mode 200µA. Using a high input impedance amplifier to buffer
range (VEE + 4V ≤ VCM ≤ VCC – 4V) and high common VREFBUF to any external circuits is recommended.
mode rejection allow the inputs to accept a wide variety PD (Pin 22): Power Down Input. When this pin is brought
of signal swings. Full-scale input range is determined by high, the LTC2333-16 is powered down and subsequent
the selected SoftSpan configuration. conversion requests are ignored. If this occurs during a
conversion, the device powers down once the conversion
GND (Pins 15, 18, 20, 25, 30, 36, 41, 44, 46): Ground.
completes. If this pin is brought high twice without an
Solder all GND pins to a solid ground plane.
intervening conversion, an internal global reset is initi-
VCC (Pin 16): Positive High Voltage Power Supply. The ated, equivalent to a power-on-reset event. Logic levels
range of VCC is 7.5V to 38V with respect to GND and 10V are determined by OVDD.
to 38V with respect to VEE. Bypass VCC to GND close to
LVDS/CMOS (Pin 23): I/O Mode Select. Tie this pin to OVDD
the pin with a 0.1μF ceramic capacitor.
to select LVDS I/O mode, or to ground to select CMOS I/O
VEE (Pins 17, 45): Negative High Voltage Power Supply. mode. Logic levels are determined by OVDD.
The range of VEE is 0V to –16.5V with respect to GND and
CNV (Pin 24): Conversion Start Input. A rising edge on
–10V to –38V with respect to VCC. Connect Pins 17 and 45
together and bypass the VEE network to GND close to Pin this pin puts the internal sample-and-holds into the hold
17 with a 0.1μF ceramic capacitor. In applications where mode and initiates a new conversion. CNV is not gated
VEE is shorted to GND, this capacitor may be omitted. by CS, allowing conversions to be initiated independent
of the state of the serial I/O bus.
REFIN (Pin 19): Bandgap Reference Output/Reference Buf-
fer Input. An internal bandgap reference nominally outputs BUSY (Pin 38): Busy Output. The BUSY signal indicates
2.048V on this pin. An internal reference buffer amplifies that a conversion is in progress. This pin transitions low-
VREFIN to create the converter master reference voltage to-high at the start of each conversion and stays high until
VREFBUF = 2 • VREFIN on the REFBUF pin. When using the the conversion is complete. Logic levels are determined
internal reference, bypass REFIN to GND (Pin 20) close to by OVDD.
the pin with a 0.1μF ceramic capacitor to filter the bandgap VDDLBYP (Pin 40): Internal 2.5V Regulator Bypass Pin. The
output noise. If more accuracy is desired, overdrive REFIN voltage on this pin is generated via an internal regulator
with an external reference in the range of 1.25V to 2.2V. operating off of VDD. This pin must be bypassed to GND
Do not load this pin when internal reference is used. close to the pin with a 2.2μF ceramic capacitor. Do not
connect this pin to any external circuitry.
REFBUF (Pin 21): Internal Reference Buffer Output. An
internal reference buffer amplifies VREFIN to create the VDD (Pins 42, 43): 5V Power Supply. The range of VDD
converter master reference voltage VREFBUF = 2 • VREFIN is 4.75V to 5.25V. Connect Pins 42 and 43 together and
on this pin, nominally 4.096V when using the internal bypass the VDD network to GND with a shared 0.1μF
bandgap reference. Bypass REFBUF to GND (Pin 20) close ceramic capacitor close to the pins.
to the pin with a 47μF ceramic capacitor. The internal
reference buffer may be disabled by grounding its input

233316f

For more information www.linear.com/LTC2333-16 13

LTC2333-16
Pin Functions
CMOS I/O Mode LVDS I/O Mode
SDI+/SDI–, SCKI–, SDO+/SDO– (Pins 26/27, 28, and SDI+/SDI– (Pins 26/27): LVDS Positive and Negative Serial
34/35): LVDS Inputs and Outputs. In CMOS I/O mode Data Input. Differentially drive SDI+/SDI– with the desired
these pins are Hi-Z. MUX control words (see Table 1a), latched on both the
rising and falling edges of SCKI+/SCKI–. The SDI+/SDI–
SCKI (Pin 29): CMOS Serial Clock Input. Drive SCKI with
input pair is internally terminated with a 100Ω differential
the serial I/O clock. SCKI rising edges latch serial data in
resistor when CS is low.
on SDI and clock serial data out on SDO. For standard
SPI bus operation, capture output data at the receiver on SCKI+/SCKI– (Pins 28/29): LVDS Positive and Negative
rising edges of SCKI. SCKI is allowed to idle either high Serial Clock Input. Differentially drive SCKI+/SCKI– with
or low. Logic levels are determined by OVDD. the serial I/O clock. SCKI+/SCKI– rising and falling edges
latch serial data in on SDI+/SDI– and clock serial data out
OVDD (Pin 31): I/O Interface Power Supply. In CMOS I/O
on SDO+/SDO–. Idle SCKI+/SCKI– low, including when
mode, the range of OVDD is 1.71V to 5.25V. Bypass OVDD
transitioning CS. The SCKI+/SCKI– input pair is internally
to GND (Pin 30) close to the pin with a 0.1μF ceramic
terminated with a 100Ω differential resistor when CS is low.
capacitor.
OVDD (Pin 31): I/O Interface Power Supply. In LVDS I/O
SCKO (Pin 32): CMOS Serial Clock Output. SCKI rising
mode, the range of OVDD is 2.375V to 5.25V. Bypass OVDD
edges trigger transitions on SCKO that are skew-matched to
to GND (Pin 30) close to the pin with a 0.1μF ceramic
the serial output data stream on SDO. The resulting SCKO
capacitor.
frequency is half that of SCKI. Rising and falling edges of
SCKO may be used to capture SDO data at the receiver SCKO+/SCKO– (Pins 32/33): LVDS Positive and Negative
(FPGA) in double data rate (DDR) fashion. For standard Serial Clock Output. SCKO+/SCKO– outputs a copy of the
SPI bus operation, SCKO is not used and should be left input serial I/O clock received on SCKI+/SCKI–, skew-
unconnected. SCKO is forced low at the falling edge of matched with the serial output data stream on SDO+/SDO–.
BUSY. Logic levels are determined by OVDD. Use the rising and falling edges of SCKO+/SCKO– to cap-
ture SDO+/SDO– data at the receiver (FPGA). The SCKO+/
SDO (Pin 33): CMOS Serial Data Output. The most recent
SCKO– output pair must be differentially terminated with
conversion result along with channel configuration informa-
tion is clocked out onto the SDO pin on each rising edge a 100Ω resistor at the receiver (FPGA).
of SCKI. Output data formatting is described in the Digital SDO+/SDO– (Pins 34/35): LVDS Positive and Negative Se-
Interface section. Logic levels are determined by OVDD. rial Data Output. The most recent conversion result along
SDI (Pin 37): CMOS Serial Data Input. Drive this pin with with channel configuration information is clocked out onto
the desired MUX control words (see Table 1a), latched SDO+/SDO– on both rising and falling edges of SCKI+/
SCKI–. The SDO+/SDO– output pair must be differentially
on the rising edges of SCKI. Hold SDI low while clock-
terminated with a 100Ω resistor at the receiver (FPGA).
ing SCKI to configure the next conversion according to
the previously programmed sequence. Logic levels are SDI (Pin 37): CMOS Serial Data Input. In LVDS I/O mode
determined by OVDD. this pin is Hi-Z.
CS (Pin 39): Chip Select Input. The serial data I/O bus is CS (Pin 39): Chip Select Input. The serial data I/O bus is
enabled when CS is low and is disabled and Hi-Z when enabled when CS is low, and is disabled and Hi-Z when
CS is high. CS also gates the external shift clock, SCKI. CS is high. CS also gates the external shift clock, SCKI+/
Logic levels are determined by OVDD. SCKI–. The internal 100Ω differential termination resistors
on the SCKI+/SCKI– and SDI+/SDI– input pairs are disabled
when CS is high. Logic levels are determined by OVDD.

233316f

14 For more information www.linear.com/LTC2333-16

 LTC2333-16
Configuration Tables
Table 1a. SoftSpan Configuration Table. Use This Table with Table 1b to Choose Binary SoftSpan Codes SS[2:0] Based on Desired
Analog Input Range. Combine MUX Word Header (10) with Binary Channel Number and SoftSpan Code to Form MUX Control Word
C[7:0]. Use Serial Interface to Program LTC2333-16 Sequencer as Shown in Figures 16 to 19
BINARY SoftSpan CODE BINARY FORMAT OF
ANALOG INPUT RANGE FULL SCALE RANGE
SS[2:0] CONVERSION RESULT
111 ±2.5 • VREFBUF 5 • VREFBUF Two’s Complement
110 ±2.5 • VREFBUF/1.024 5 • VREFBUF/1.024 Two’s Complement
101 0V to 2.5 • VREFBUF 2.5 • VREFBUF Straight Binary
100 0V to 2.5 • VREFBUF/1.024 2.5 • VREFBUF/1.024 Straight Binary
011 ±1.25 • VREFBUF 2.5 • VREFBUF Two’s Complement
010 ±1.25 • VREFBUF/1.024 2.5 • VREFBUF/1.024 Two’s Complement
001 0V to 1.25 • VREFBUF 1.25 • VREFBUF Straight Binary
000 0V to 1.25 • VREFBUF/1.024 1.25 • VREFBUF/1.024 Straight Binary

Table 1b. Reference Configuration Table. The LTC2333-16 Supports Three Reference Configurations. Analog Input Range Scales with
the Converter Master Reference Voltage, VREFBUF
BINARY SoftSpan CODE
REFERENCE CONFIGURATION VREFIN VREFBUF ANALOG INPUT RANGE
SS[2:0]
111 ±10.24V
110 ±10V
101 0V to 10.24V
Internal Reference with 100 0V to 10V
2.048V 4.096V
Internal Buffer 011 ±5.12V
010 ±5V
001 0V to 5.12V
000 0V to 5V
111 ±6.25V
110 ±6.104V
101 0V to 6.25V
1.25V 100 0V to 6.104V
2.5V
(Min Value) 011 ±3.125V
010 ±3.052V
001 0V to 3.125V
External Reference with
Internal Buffer 000 0V to 3.052V
(REFIN Pin Externally 111 ±11V
Overdriven) 110 ±10.742V
101 0V to 11V
2.2V 100 0V to 10.742V
4.4V
(Max Value) 011 ±5.5V
010 ±5.371V
001 0V to 5.5V
000 0V to 5.371V

233316f

For more information www.linear.com/LTC2333-16 15

LTC2333-16
Configuration Tables
Table 1b. Reference Configuration Table (Continued). The LTC2333-16 Supports Three Reference Configurations. Analog Input Range
Scales with the Converter Master Reference Voltage, VREFBUF
BINARY SoftSpan CODE
REFERENCE CONFIGURATION VREFIN VREFBUF ANALOG INPUT RANGE
SS[2:0]
111 ±6.25V
110 ±6.104V
101 0V to 6.25V
2.5V 100 0V to 6.104V
0V
(Min Value) 011 ±3.125V
010 ±3.052V
External Reference 001 0V to 3.125V
Unbuffered
000 0V to 3.052V
(REFBUF Pin
111 ±12.5V
Externally Overdriven,
REFIN Pin Grounded) 110 ±12.207V
101 0V to 12.5V
5V 100 0V to 12.207V
0V
(Max Value) 011 ±6.25V
010 ±6.104V
001 0V to 6.25V
000 0V to 6.104V

233316f

16 For more information www.linear.com/LTC2333-16

 LTC2333-16
Functional Block Diagram
CMOS I/O Mode

BUFFERS VCC VDD VDDLBYP LTC2333-16 OVDD

IN0+

IN0–
2.5V
IN1+ REGULATOR
SDO
IN1–

IN2+ SCKO
SEQUENCER
IN2– CMOS
SDI
8-CHANNEL MULTIPLEXER

SERIAL
IN3+ I/O
INTERFACE SCKI
IN3–
16-BIT
IN4+ 16 BITS CS
SAMPLING
IN4– ADC

IN5+

IN5–

IN6+
REFERENCE
IN6– BUFFER
2.048V 20k CONTROL BUSY
IN7+ 2×
REFERENCE LOGIC
IN7–

VEE GND REFIN REFBUF CNV PD LVDS/CMOS

233316 BD01

LVDS I/O Mode

BUFFERS VCC VDD VDDLBYP LTC2333-16 OVDD

IN0+
IN0–
2.5V SDO+
IN1+ REGULATOR
SDO–
IN1–
SCKO+
IN2+
SEQUENCER SCKO–
LVDS
IN2–
SERIAL SDI+
8-CHANNEL MULTIPLEXER

IN3+ I/O
INTERFACE SDI–
IN3–
SCKI+
16-BIT
IN4+
SAMPLING 16 BITS SCKI–
IN4– ADC
CS
IN5+

IN5–

IN6+
REFERENCE
IN6– BUFFER
2.048V 20k CONTROL BUSY
IN7+ 2×
REFERENCE LOGIC
IN7–

VEE GND REFIN REFBUF CNV PD LVDS/CMOS

233316 BD02

233316f

For more information www.linear.com/LTC2333-16 17

LTC2333-16
Timing Diagram
CMOS I/O Mode
CS = PD = 0

SAMPLE N SAMPLE N + 1
CNV

BUSY CONVERT ACQUIRE

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

SCKI

SDI DON’T CARE C7 C6 C5 C4 C3 C2 C1 C0 C7 C6 C5 C4 C3 C2 C1 C0

CONTROL WORD FOR CONTROL WORD FOR

CONVERSION N + 1 CONVERSION N + 2

SCKO

SDO DON’T CARE D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 CH2 CH1 CH0 SS2 SS1 SS0 D15

CONVERSION RESULT
CONVERSION RESULT CHANNEL ID SoftSpan
(REPETITION)
233316 TD01
CONVERSION N

LVDS I/O Mode

CS = PD = 0

SAMPLE N SAMPLE N + 1
CNV
(CMOS)

BUSY
CONVERT ACQUIRE
(CMOS)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
SCKI
(LVDS)

SDI
DON’T CARE C7 C6 C5 C4 C3 C2 C1 C0 C7 C6 C5 C4 C3 C2 C1 C0
(LVDS)

CONTROL WORD FOR CONTROL WORD FOR

CONVERSION N + 1 CONVERSION N + 2

SCKO
(LVDS)

SDO DON’T CARE D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 CH2 CH1 CH0 SS2 SS1 SS0 D15
(LVDS)
CONVERSION RESULT
CONVERSION RESULT CHANNEL ID SoftSpan (REPETITION)
233316 TD02
CONVERSION N

233316f

18 For more information www.linear.com/LTC2333-16

 LTC2333-16
Applications Information
Overview channel's sampling capacitors are connected to a 16-bit
The LTC2333-16 is a 16-bit, low noise 8-channel mul- charge redistribution capacitor D/A converter (CDAC). The
tiplexed successive approximation register (SAR) ADC CDAC is sequenced through a successive approximation
with buffered differential, wide common mode range algorithm, effectively comparing the sampled input voltage
picoamp inputs. The ADC operates from a 5V low volt- with binary-weighted fractions of the channel’s SoftSpan
age supply and flexible high voltage supplies, nominally full-scale range (e.g., VFSR/2, VFSR/4 … VFSR/65536) using
±15V. Using the integrated low-drift reference and buffer a differential comparator. At the end of this process, the
(VREFBUF = 4.096V nominal), this SoftSpan ADC can be CDAC output approximates the channel’s sampled analog
configured on a conversion-by-conversion basis to accept input. The ADC control logic then prepares the 16-bit digital
±10.24V, 0V to 10.24V, ±5.12V, or 0V to 5.12V signals on output code for serial transfer.
any channel. Alternately, the ADC may be programmed to
cycle through a sequence of channels and ranges without Transfer Function
further user intervention. The input signal range may be
The LTC2333-16 digitizes the full-scale voltage range into
expanded up to ±12.5V using an external 5V reference.
216 levels. In conjunction with the ADC master reference
The integrated picoamp-input analog buffers, wide input voltage, VREFBUF, the selected SoftSpan configuration
common mode range, and 128dB CMRR of the LTC2333- determines its input voltage range, full-scale range, LSB
16 allow the ADC to directly digitize a variety of signals size, and the binary format of its conversion result, as
using minimal board space and power. This input signal shown in Tables 1a and 1b. For example, employing the
flexibility, combined with ±1LSB INL, no missing codes internal reference and buffer (VREFBUF = 4.096V nominal),
at 16-bits, and 94.2dB SNR, makes the LTC2333-16 an SoftSpan 7 configures a channel to accept a ±10.24V bi-
ideal choice for many high voltage applications requiring polar analog input voltage range, which corresponds to a
wide dynamic range. 20.48V full-scale range with a 312.5μV LSB. Other SoftSpan
The absolute common mode input range (VEE + 4V to configurations and reference voltages may be employed to
VCC – 4V) is determined by the choice of high voltage convert both larger and smaller bipolar and unipolar input
supplies. These supplies may be biased asymmetrically ranges. Conversion results are output in two’s comple-
around ground and include the ability for VEE to be tied ment binary format for all bipolar SoftSpan ranges, and
directly to ground. in straight binary format for all unipolar SoftSpan ranges.
The ideal two’s complement transfer function is shown in
The LTC2333-16 supports pin-selectable SPI CMOS (1.8V Figure 2, while the ideal straight binary transfer function
to 5V) and LVDS serial interfaces, enabling it to communi- is shown in Figure 3.
cate equally well with legacy microcontrollers and modern
FPGAs. The LTC2333-16 typically dissipates 268mW when
converting at 800ksps throughput. Optional nap and power 011...111
OUTPUT CODE (TWO’S COMPLEMENT)

011...110 BIPOLAR
down modes may be employed to further reduce power ZERO
consumption during inactive periods. 000...001
000...000

Converter Operation 111...111

111...110
The LTC2333-16 operates in two phases. During the ac-
quisition phase, the sampling capacitors in each channel 100...001 FSR = +FS – –FS
connect to their respective analog input pins and track the 100...000 1LSB = FSR/65536

differential analog input voltage (VIN+ – VIN–). A rising edge –FSR/2 –1 0V 1 FSR/2 – 1LSB
on the CNV pin transitions the S/H circuits from track mode LSB LSB
INPUT VOLTAGE (V)
to hold mode, sampling the input signals and initiating a 233316 F02

conversion. During the conversion phase, the selected Figure 2. LTC2333-16 Two’s Complement Transfer Function
233316f

For more information www.linear.com/LTC2333-16 19

LTC2333-16
Applications Information
111...111
connect to the integrated buffers Buffer+/Buffer– through
the sampling switches. The sampled voltage is reset during
OUTPUT CODE (STRAIGHT BINARY)

111...110
the conversion process and is therefore re-acquired for
100...001 each new conversion.
100...000
011...111 UNIPOLAR VCC
ZERO BUFFER+ CSAMP
011...110 RSAMP 30pF
750Ω
IN+
000...001 FSR = +FS
000...000 1LSB = FSR/65536
VEE BIAS
VCC VOLTAGE
0V FSR – 1LSB BUFFER– CSAMP
INPUT VOLTAGE (V) RSAMP 30pF
233316 F03
750Ω
IN– 233316 F04
Figure 3. LTC2333-16 Straight Binary Transfer Function

VEE
Buffered Analog Inputs
Figure 4. Equivalent Circuit for Differential Analog Inputs,
The LTC2333-16 samples the voltage difference (VIN+ – Single Channel Shown
VIN–) between its analog input pins over a wide common
mode input range while attenuating unwanted signals The diodes between the inputs and the VCC and VEE sup-
common to both input pins by the common-mode re- plies provide input ESD protection. While within the supply
jection ratio (CMRR) of the ADC. Wide common mode voltages, the analog inputs of the LTC2333-16 draw only
input range coupled with high CMRR allows the IN+/ 5pA typical DC leakage current and the ESD protection
IN– analog inputs to swing with an arbitrary relation- diodes do not turn on. This offers a significant advantage
ship to each other, provided each pin remains between over external op amp buffers, which often have diode
(VCC – 4V) and (VEE + 4V). This feature of the LTC2333- protection that turns on during transients and corrupts
16 enables it to accept a wide variety of signal swings, the voltage on any filter capacitors at their inputs.
including traditional classes of analog input signals such
as pseudo-differential unipolar, pseudo-differential true Bipolar SoftSpan Input Ranges
bipolar, and fully differential, simplifying signal chain For conversions configured in SoftSpan ranges 7, 6, 3,
design. For conversion of signals extending to VEE, the or 2, the LTC2333-16 digitizes the differential analog
unbuffered LTC2335-16 ADC is recommended. input voltage (VIN+ – VIN–) over a bipolar span of
The wide operating range of the high voltage supplies ±2.5 • VREFBUF, ±2.5 • VREFBUF/1.024, ±1.25 • VREFBUF, or
offers further input common mode flexibility. As long as ±1.25 • VREFBUF/1.024, respectively, as shown in Table
the voltage difference limits of 10V ≤ (VCC – VEE) ≤ 38V 1a. These SoftSpan ranges are useful for digitizing input
are observed, VCC and VEE may be independently biased signals where IN+ and IN– swing above and below each
anywhere within their own individually allowed operating other. Traditional examples include fully differential input
ranges, including the ability for VEE to be tied directly to signals, where IN+ and IN– are driven 180 degrees out-of-
ground. This feature enables the common mode input phase with respect to each other centered around a common
range of the LTC2333-16 to be tailored to the specific mode voltage (VIN+ + VIN–)/2, and pseudo-differential
application’s requirements. true bipolar input signals, where IN+ swings above and
below a ground reference level, driven on IN–. Regardless
In all SoftSpan ranges, each channel’s analog inputs can
of the chosen SoftSpan range, the wide common mode
be modeled by the equivalent circuit shown in Figure 4. At
the start of acquisition, the sampling capacitors (CSAMP)

233316f

20 For more information www.linear.com/LTC2333-16

 LTC2333-16
Applications Information
input range and high CMRR of the IN+/IN– analog inputs The LTC2333-16 features proprietary circuitry to achieve
allow them to swing with an arbitrary relationship to each exceptional internal crosstalk isolation between channels
other, provided each pin remains between (VCC – 4V) and (–125dB typical). The PC board wiring to the analog inputs
(VEE + 4V). The output data format for all bipolar SoftSpan should be short and shielded to prevent external capacitive
ranges is two’s complement. crosstalk between channels. The capacitance between adja-
cent package pins is 0.16pF. Low source resistance and/or
Unipolar SoftSpan Input Ranges high source capacitance help reduce external capacitively
For conversions configured in SoftSpan ranges 5, 4, 1, coupled crosstalk. Single ended input drive also enjoys
or 0, the LTC2333-16 digitizes the differential analog additional external crosstalk isolation because every other
input voltage (VIN+ – VIN–) over a unipolar span of 0V input pin is grounded, or at a low impedance DC source,
to 2.5 • VREFBUF, 0V to 2.5 • VREFBUF/1.024, 0V to 1.25 • and serves as a shield between channels.
VREFBUF, or 0V to 1.25 • VREFBUF/1.024, respectively, as
Input Overdrive Tolerance
shown in Table 1a. These SoftSpan ranges are useful for
digitizing input signals where IN+ remains above IN–. A Driving an analog input above VCC on any channel up to
traditional example includes pseudo-differential unipolar 10mA will not affect conversion results on other channels.
input signals, where IN+ swings above a ground reference Approximately 70% of this overdrive current will flow out
level, driven on IN–. Regardless of the chosen SoftSpan of the VCC pin and the remaining 30% will flow out of VEE.
range, the wide common mode input range and high CMRR This current flowing out of VEE will produce heat across
of the IN+/IN– analog inputs allow them to swing with an the VCC-VEE voltage drop and must be taken into account
arbitrary relationship to each other, provided each pin re- for the total Absolute Maximum power dissipation of
mains between (VCC – 4V) and (VEE + 4V). The output data 500mW. Driving an analog input below VEE may corrupt
format for all unipolar SoftSpan ranges is straight binary. conversion results on other channels. This product can
handle input currents of up to 100mA below VEE or above
Input Drive Circuits VCC without latchup. Keep in mind that driving the inputs
above VCC or below VEE may reverse the normal current
The CMOS buffer input stage offers a very high degree of flow from the external power supplies driving these pins.
transient isolation from the sampling process. Most sen-
sors, signal conditioning amplifiers and filter networks with Input Filtering
less than 10kΩ of impedance can drive the passive 3pF
The true high impedance analog inputs can accommodate
analog input capacitance directly. For higher impedances
a very wide range of passive or active signal conditioning
and slow-settling circuits, add a 680pF capacitor at the
filters. The buffered ADC inputs have an analog bandwidth
pins to maintain the full DC accuracy of the LTC2333-16.
of 6MHz, and impose no particular bandwidth requirement
The very high input impedance of the unity gain buf- on external filters. The external input filters can therefore
fers in the LTC2333-16 greatly reduces the input be optimized independent of the ADC to reduce signal
drive requirements and makes it possible to include chain noise and interference. A common filter configura-
optional RC filters with kΩ impedance and arbitrarily tion is the simple anti-aliasing and noise reducing RC filter
slow time constants for anti-aliasing or other purposes. with its pole at half the sampling frequency. For example,
Micro-power op amps with limited drive capability are
also well suited to drive the high impedance analog inputs
directly.

233316f

For more information www.linear.com/LTC2333-16 21

LTC2333-16
Applications Information
15V
OPTIONAL
TRUE BIPOLAR LOWPASS FILTER
+10V 0.1µF
R = 590Ω
0V IN+
IN0+ VCC
–10V 680pF IN0–
UNIPOLAR
LTC2333-16
+10V

0V IN–
VEE REFBUF REFIN
–10V
47µF 0.1µF
0.1µF
–15V
ONLY CHANNEL 0 SHOWN FOR CLARITY 233316 F05

Figure 5. Filtering Single-Ended Input Signals

sampling one channel at 800ksps yields R = 590Ω and C The two-tone test shown in Figure 6b demonstrates the
= 680pF as shown in Figure 5. arbitrary input drive capability of the LTC2333-16. This test
simultaneously drives IN+ with a −7dBFS 2kHz single-ended
High quality capacitors and resistors should be used in
sine wave and IN− with a −7dBFS 3.1kHz single-ended sine
the RC filters since these components can add distortion.
wave. Together, these signals sweep the analog inputs
NPO/COG and silver mica type dielectric capacitors have
across a wide range of common mode and differential
excellent linearity. Carbon surface mount resistors can
mode voltage combinations, similar to the more general
generate distortion from self-heating and from damage
arbitrary input signal case. They also have a simple spec-
that may occur during soldering. Metal film surface mount
tral representation. An ideal differential converter with no
resistors are much less susceptible to both problems.
common-mode sensitivity will digitize this signal as two
Arbitrary and Fully Differential Analog Input Signals −7dBFS spectral tones, one at each sine wave frequency.
The FFT plot in Figure 6b demonstrates the LTC2333-16
The wide common mode input range and high CMRR of response, which approaches this ideal with 120dB of
the LTC2333-16 allow each channel’s IN+ and IN– pins to SFDR limited by the converter's second harmonic distor-
swing with an arbitrary relationship to each other, provided tion response to the 3.1kHz sine wave on IN–.
each pin remains between (VCC – 4V) and (VEE + 4V). This
feature of the LTC2333-16 enables it to accept a wide
variety of signal swings, simplifying signal chain design.

233316f

22 For more information www.linear.com/LTC2333-16

 LTC2333-16
Applications Information
15V
FULLY
ARBITRARY DIFFERENTIAL
+10V +5V 0.1µF

0V 0V IN+
IN0+ VCC
–10V –5V
IN0–
LTC2333-16
TRUE BIPOLAR UNIPOLAR
+10V +10V IN–
VEE REFBUF REFIN
0V 0V
47µF 0.1µF
–10V –10V 0.1µF

–15V
ONLY CHANNEL 0 SHOWN FOR CLARITY 233316 F06a

Figure 6a. Input Arbitrary, Fully Differential, True Bipolar, and Unipolar Signals

Arbitrary Drive Fully Differential Drive

0 0
±10.24V RANGE ±10.24V RANGE
–20 SFDR = 120dB –20 SNR = 94.2dB
SNR = 94.3dB THD = –115dB
–40 –40 SINAD = 94.2dB
SFDR = 119dB
AMPLITUDE (dBFS)

AMPLITUDE (dBFS)
–60 –60

–80 –80

–100 –100

–120 –120

–140 –140

–160 –160

–180 –180
0 100 200 300 400 0 100 200 300 400
FREQUENCY (kHz) FREQUENCY (kHz)
233316 F06b 233316 F06c

Figure 6b. Two-Tone Test. IN+ = –7dBFS 2kHz Sine, IN– = –7dBFS Figure 6c. IN+/IN– = –1dBFS 2kHz Fully Differential Sine, VCM = 0V,
3.1kHz Sine, 32k Point FFT, fSMPL = 800ksps. Circuit Shown in 32k Point FFT, fSMPL = 800ksps. Circuit Shown in Figure 6a
Figure 6a

True Bipolar Drive Unipolar Drive

0 0
±10.24V RANGE 0V to 10.24V RANGE
–20 SNR = 94.3dB –20 SNR = 89.9dB
THD = –109dB THD = –113dB
–40 SINAD = 94.2dB –40 SINAD = 89.9dB
SFDR = 112dB SFDR = 114dB
AMPLITUDE (dBFS)

AMPLITUDE (dBFS)

–60 –60

–80 –80

–100 –100

–120 –120

–140 –140

–160 –160

–180 –180
0 100 200 300 400 0 100 200 300 400
FREQUENCY (kHz) FREQUENCY (kHz)
233316 F06d 233316 F06e

Figure 6d. IN+ = –1dBFS 2kHz True Bipolar Sine, IN– = 0V, 32k Point Figure 6e. IN+ = –1dBFS 2kHz Unipolar Sine, IN– = 0V, 32k Point
FFT, fSMPL = 800ksps. Circuit Shown in Figure 6a FFT, fSMPL = 800ksps. Circuit Shown in Figure 6a
233316f

For more information www.linear.com/LTC2333-16 23

LTC2333-16
Applications Information
The ability of the LTC2333-16 to accept arbitrary signal In Figure 8, another application circuit is shown which uses
swings over a wide input common mode range with high two channels of the LTC2333-16 to sense the voltage on
CMRR can simplify application solutions. In practice, and bidirectional current through a sense resistor over a
many sensors produce a differential sensor voltage riding wide common mode range.
on top of a large common mode signal. Figure 7a depicts
one way of using the LTC2333-16 to digitize signals of ADC Reference
this type. The amplifier stage provides a differential gain
of approximately 10V/V to the desired sensor signal while As shown previously in Table 1b, the LTC2333-16 supports
the unwanted common mode signal is attenuated by the three reference configurations. The first uses both the in-
ADC CMRR. The circuit employs the ±5V SoftSpan range of ternal bandgap reference and reference buffer. The second
the ADC. Figure 7b shows measured CMRR performance externally overdrives the internal reference but retains the
of this solution, which is competitive with the best com- internal buffer, which isolates the external reference from
mercially available instrumentation amplifiers. Figure 7c ADC conversion transients. This configuration is ideal
shows measured AC performance of this solution. for sharing a single precision external reference across
multiple ADCs. The third disables the internal buffer and
overdrives the REFBUF pin externally.

31V
INTERNAL HIGH-Z BUFFERS
IN+ + LTC2057HV ALLOW OPTIONAL
ARBITRARY
kΩ PASSIVE FILTERS
– 31V
24V 3.65k

0.1µF
2.49k BUFFERED
ANALOG
INPUTS VCC
COMMON MODE IN0+
549Ω GAIN = 10 2.2nF
INPUT RANGE IN0–
2.49k
LTC2333-16
DIFFERENTIAL MODE
INPUT RANGE: ±500mV 3.65k
VEE REFBUF REFIN
0V –
47µF 0.1µF
IN–
+ LTC2057HV
BW = 10kHz 0.1µF

–7V –7V
233316 F07a
ONLY CHANNEL 0 SHOWN FOR CLARITY

Figure 7a. Amplify Differential Signals with Gain of 10 Over a Wide Common Mode Range with Buffered Analog Inputs

233316f

24 For more information www.linear.com/LTC2333-16

 LTC2333-16
Applications Information
160 Internal Reference with Internal Buffer
±5V RANGE
150
140
The LTC2333-16 has an on-chip, low noise, low drift
130 (20ppm/°C maximum), temperature compensated band-
120 gap reference that is factory trimmed to 2.048V. The
CMRR (dB)

110 reference output connects through a 20kΩ resistor to

100 IN+ = IN– = 1VP-P SINE the REFIN pin, which serves as the input to the on-chip
90 reference buffer, as shown in Figure 9a. When employing
80 the internal bandgap reference, the REFIN pin should be
70 bypassed to GND (Pin 20) close to the pin with a 0.1μF
60
10 100 1k 10k
ceramic capacitor to filter wideband noise. The reference
FREQUENCY (Hz)
233316 F07b
buffer amplifies VREFIN to create the converter master
reference voltage VREFBUF = 2 • VREFIN on the REFBUF pin,
Figure 7b. CMRR vs Input Frequency. Circuit Shown in Figure 7a nominally 4.096V when using the internal bandgap refer-
ence. Bypass REFBUF to GND (Pin 20) close to the pin with
0
±5V RANGE at least a 47μF ceramic capacitor (X7R, 10V, 1210 size or
–20 FULLY DIFFERENTIAL DRIVE (IN– = –IN+) X5R, 10V, 0805 size) to compensate the reference buffer,
–40 SNR = 90.6dB
THD = –118dB
absorb transient conversion currents, and minimize noise.
AMPLITUDE (dBFS)

–60 SINAD = 90.6dB

SFDR = 119dB
–80
LTC2333-16
–100
REFIN 20k BANDGAP
–120 REFERENCE
0.1µF
–140

–160 REFBUF REFERENCE

BUFFER
–180
0 80 160 240 320 400
FREQUENCY (kHz) 6.5k
233316 F07c
47µF

6.5k
Figure 7c. IN+/IN– = 450mV 2kHz Fully Differential Sine,
0V ≤ VCM ≤ 24V, 32k Point FFT, fSMPL = 800ksps. Circuit GND
Shown in Figure 7a
233316 F9a

15V

0.1µF
Figure 9a. Internal Reference with Internal Buffer Configuration

VCC
IN0+
VS1 IN0–
LTC2333-16
RSENSE ISENSE IN1+
IN1 –
VEE REFBUF REFIN
VS2 47µF 0.1µF
0.1µF
233316 F08
–15V

ONLY CHANNELS 0 AND 1 SHOWN FOR CLARITY

V – VS2 –10.24V ≤ VS1 ≤ 10.24V
ISENSE = S1
RSENSE –10.24V ≤ VS2 ≤ 10.24V

Figure 8. Sense Voltage (CH0) and Current (CH1) Over a

Wide Common Mode Range
233316f

For more information www.linear.com/LTC2333-16 25

LTC2333-16
Applications Information
External Reference with Internal Buffer external reference voltage between 2.5V and 5V, as shown
If more accuracy and/or lower drift is desired, REFIN can in Figure 9c. Maximum input signal swing and SNR are
be easily overdriven by an external reference since 20kΩ achieved by overdriving REFBUF using an external 5V
of resistance separates the internal bandgap reference reference. The buffer feedback resistors load the REFBUF
output from the REFIN pin, as shown in Figure 9b. The pin with 13kΩ even when the reference buffer is disabled.
valid range of external reference voltage overdrive on the The LTC6655-5 offers the same small size, accuracy, drift,
REFIN pin is 1.25V to 2.2V, resulting in converter mas- and extended temperature range as the LTC6655-2.048,
ter reference voltages VREFBUF between 2.5V and 4.4V, and achieves a typical SNR of 94.8dB when paired with
respectively. Linear Technology offers a portfolio of high the LTC2333-16. Bypass the LTC6655-5 to GND (Pin 20)
performance references designed to meet the needs of close to the REFBUF pin with at least a 47μF ceramic ca-
pacitor (X7R, 10V, 1210 size or X5R, 10V, 0805 size) to
many applications. With its small size, low power, and high
absorb transient conversion currents and minimize noise.
accuracy, the LTC6655-2.048 is well suited for use with the
LTC2333-16 when overdriving the internal reference. The
LTC6655-2.048 offers 0.025% (maximum) initial accuracy LTC2333-16
20k
REFIN
and 2ppm/°C (maximum) temperature coefficient for high BANDGAP
REFERENCE
2.7µF
precision applications. The LTC6655-2.048 is fully speci-
fied over the H-grade temperature range, complementing REFBUF REFERENCE
BUFFER
the extended temperature range of the LTC2333-16 up to
125°C. Bypassing the LTC6655-2.048 with a 2.7µF to 100µF LTC6655-2.048 47µF
6.5k

ceramic capacitor close to the REFIN pin is recommended. 6.5k

GND
External Reference with Disabled Internal Buffer 233316 F09b

The internal reference buffer supports VREFBUF = 4.4V

maximum. By grounding REFIN, the internal buffer may Figure 9b. External Reference with Internal Buffer Configuration
be disabled, allowing REFBUF to be overdriven with an

LTC2333-16
REFIN 20k BANDGAP
REFERENCE

REFBUF REFERENCE
BUFFER

6.5k
LTC6655-5 47µF

6.5k

GND
233316 F09c

Figure 9c. External Reference with Disabled Internal

Buffer Configuration

233316f

26 For more information www.linear.com/LTC2333-16

 LTC2333-16
Applications Information
The LTC2333-16 converter draws a charge (QCONV) from erence buffer and overdrives REFBUF with an external
the REFBUF pin during each conversion cycle. On short LTC6655-4.096. In both cases REFBUF is bypassed to
time scales most of this charge is supplied by the external GND with a 47µF ceramic capacitor.
REFBUF bypass capacitor, but on longer time scales all of
2.5
the charge is supplied by either the reference buffer, or ±10.24V RANGE
IN+ = 10V
when the internal reference buffer is disabled, the external

DEVIATION FROM FINAL VALUE (LSB)

2.0
IN– = 0V
reference. This charge draw corresponds to a DC current 1.5
equivalent of IREFBUF = QCONV • fSMPL, which is proportional
1.0
to sample rate. In applications where a burst of samples EXTERNAL REFERENCE ON REFBUF

is taken after idling for long periods of time, as shown in 0.5

Figure 10, IREFBUF quickly transitions from approximately 0

0.4mA to 0.9mA (VREFBUF = 5V, fSMPL = 800ksps). This INTERNAL REFERENCE BUFFER
–0.5
current step triggers a transient response in the external
reference that must be considered, since any deviation in –1.0
0 100 200 300 400 500
VREFBUF affects converter accuracy. If an external reference TIME (µs)
is used to overdrive REFBUF, the fast settling LTC6655
233316 F11

family of references is recommended. Figure 11. Burst Conversion Response of the

LTC2333-16, fSMPL = 800ksps
Internal Reference Buffer Transient Response
For optimum performance in applications employing burst Dynamic Performance
sampling, the external reference with internal reference
buffer configuration should be used. The internal reference Fast Fourier transform (FFT) techniques are used to test
buffer incorporates a proprietary design that minimizes the ADC’s frequency response, distortion, and noise at the
movements in VREFBUF when responding to a burst of rated throughput. By applying a low distortion sine wave
conversions following an idle period. Figure 11 compares and analyzing the digital output using an FFT algorithm,
the burst conversion response of the LTC2333-16 with an the ADC’s spectral content can be examined for frequen-
input near full scale for two reference configurations. The cies outside the fundamental. The LTC2333-16 provides
first configuration employs the internal reference buffer guaranteed tested limits for both AC distortion and noise
with REFIN externally overdriven by an LTC6655-2.048, measurements.
while the second configuration disables the internal ref-

CNV
233316 F10
IDLE IDLE
PERIOD PERIOD

Figure 10. CNV Waveform Showing Burst Sampling

233316f

For more information www.linear.com/LTC2333-16 27

LTC2333-16
Applications Information
Signal-to-Noise and Distortion Ratio (SINAD) between DC and half the sampling frequency (fSMPL/2).
THD is expressed as:
The signal-to-noise and distortion ratio (SINAD) is the
ratio between the RMS amplitude of the fundamental input
frequency and the RMS amplitude of all other frequency V22 + V32 + V42 ...VN2
THD = 20log
components at the A/D output. The output is band-limited V1
to frequencies below half the sampling frequency, exclud-
ing DC. Figure 12 shows that the LTC2333-16 achieves a where V1 is the RMS amplitude of the fundamental fre-
typical SINAD of 94.2dB in the ±10.24V range at a 800ksps quency and V2 through VN are the amplitudes of the second
sampling rate with a true bipolar 2kHz input signal. through Nth harmonics, respectively. Figure 12 shows
that the LTC2333-16 achieves a typical THD of –109dB
0 (N = 6) in the ±10.24V range at a 800ksps sampling rate
±10.24V RANGE
–20 TRUE BIPOLAR DRIVE (IN– = 0V) with a true bipolar 2kHz input signal.
–40 SNR = 94.3dB
THD = –109dB
Power Considerations
AMPLITUDE (dBFS)

–60 SINAD = 94.2dB

SFDR = 112dB
–80
The LTC2333-16 requires four power supplies: the posi-
–100
tive and negative high voltage power supplies (VCC and
–120
VEE), the 5V core power supply (VDD) and the digital input/
–140 output (I/O) interface power supply (OVDD). As long as
–160 the voltage difference limits of 10V ≤ VCC – VEE ≤ 38V
–180
0 100 200 300 400
are observed, VCC and VEE may be independently biased
FREQUENCY (kHz) anywhere within their own individual allowed operating
ranges, including the ability for VEE to be tied directly to
233316 F12

Figure 12. 32k Point FFT fSMPL = 800ksps, fIN = 2kHz ground. This feature enables the common mode input
range of the LTC2333-16 to be tailored to the specific
application’s requirements. The flexible OVDD supply al-
Signal-to-Noise Ratio (SNR) lows the LTC2333-16 to communicate with CMOS logic
The signal-to-noise ratio (SNR) is the ratio between the operating between 1.8V and 5V, including 2.5V and 3.3V
RMS amplitude of the fundamental input frequency and systems. When using LVDS I/O mode, the range of OVDD
the RMS amplitude of all other frequency components is 2.375V to 5.25V.
except the first five harmonics and DC. Figure 12 shows
Power Supply Sequencing
that the LTC2333-16 achieves a typical SNR of 94.3dB in
the ±10.24V range at a 800ksps sampling rate with a true The LTC2333-16 does not have any specific power supply
bipolar 2kHz input signal. sequencing requirements. Care should be taken to adhere
to the maximum voltage relationships described in the
Total Harmonic Distortion (THD) Absolute Maximum Ratings section. The LTC2333-16 has
Total harmonic distortion (THD) is the ratio of the RMS sum an internal power-on-reset (POR) circuit which resets the
of all harmonics of the input signal to the fundamental itself. converter on initial power-up and whenever VDD drops
The out-of-band harmonics alias into the frequency band below 2V. Once the supply voltage re-enters the nominal

233316f

28 For more information www.linear.com/LTC2333-16

 LTC2333-16
Applications Information
supply voltage range, the POR reinitializes the ADC. No Internal Conversion Clock
conversions should be initiated until at least 10ms after The LTC2333-16 has an internal clock that is trimmed
a POR event to ensure the initialization period has ended. to achieve a maximum conversion time of 550ns. With
When employing the internal reference buffer, allow 200ms a minimum acquisition time of 670ns, throughput per-
for the buffer to power up and recharge the REFBUF bypass formance of 800ksps is guaranteed without any external
capacitor. Any conversion initiated before these times will adjustments. The LTC2333-16 is a multiplexed ADC and
produce invalid results. converts one channel per CNV edge, taking a minimum of
1.25μs per conversion. Thus, while scanning N channels
Timing and Control (N = 1 to 8), a complete scan takes at least 1.25 • N μs and
the maximum per-channel throughput is 800/N ksps/ch.
CNV Timing
Nap Mode
The LTC2333-16 sampling and conversion is controlled
by CNV. A rising edge on CNV transitions the S/H circuits The LTC2333-16 can be placed into nap mode after a con-
from track mode to hold mode, sampling the input signals version has been completed to reduce power consumption
and initiating a conversion. Once a conversion has been between conversions. In this mode a portion of the device
started, it cannot be terminated early except by resetting circuitry is turned off, including circuits associated with
the ADC, as discussed in the Reset Timing section. For sampling the analog input signals. Nap mode is enabled
optimum performance, drive CNV with a clean, low jitter by keeping CNV high between conversions, as shown in
signal and avoid transitions on data I/O lines leading up Figure 13. To initiate a new conversion after entering nap
to the rising edge of CNV. Additionally, for best crosstalk mode, bring CNV low and hold for at least 750ns before
performance, avoid high slew rates on the analog inputs for bringing it high again. The converter acquisition time (tACQ)
100ns before and after the rising edge of CNV. Converter is set by the CNV low time (tCNVL) when using nap mode.
status is indicated by the BUSY output, which transitions
low-to-high at the start of each conversion and stays high Power Down Mode
until the conversion is complete. Once CNV is brought high
When PD is brought high, the LTC2333-16 is powered
to begin a conversion, it should be returned low between
down and subsequent conversion requests are ignored. If
40ns and 60ns later or after the falling edge of BUSY to
minimize external disturbances during the internal conver- this occurs during a conversion, the device powers down
sion process. The CNV timing required to take advantage once the conversion completes. In this mode, the device
of the reduced power nap mode of operation is described draws only a small regulator standby current resulting in a
in the Nap Mode section. typical power dissipation of 0.68mW. To exit power down

t CNVL
CNV
tCONV
BUSY
tACQ
NAP NAP MODE
233316 F13

Figure 13. Nap Mode Timing for the LTC2333-16

233316f

For more information www.linear.com/LTC2333-16 29

LTC2333-16
Applications Information
mode, bring the PD pin low and wait at least 10ms before Power Dissipation vs Sampling Frequency
initiating a conversion. When employing the internal refer- When nap mode is employed, the power dissipation of
ence buffer, allow 200ms for the buffer to power up and the LTC2333-16 decreases as the sampling frequency is
recharge the REFBUF bypass capacitor. Any conversion reduced, as shown in Figure 15. This decrease in aver-
initiated before these times will produce invalid results. age power dissipation occurs because a portion of the
LTC2333-16 circuitry is turned off during nap mode, and
Reset Timing
the fraction of the conversion cycle (tCYC) spent napping
A global reset of the LTC2333-16, equivalent to a power- increases as the sampling frequency (fSMPL) is decreased.
on-reset event, may be executed without needing to cycle
the supplies. This feature is useful when recovering from 14
system-level events that require the state of the entire sys- WITH NAP MODE
12 tCNVL = 750ns
tem to be reset to a known synchronized value. To initiate 10
a global reset, bring PD high twice without an intervening 8 IVDD

SUPPLY CURRENT (mA)

conversion, as shown in Figure 14. The reset event is trig- 6
IVCC
4
gered on the second rising edge of PD, and asynchronously
2
ends based on an internal timer. Reset clears all serial data 0 IOVDD
output registers and restores the internal sequencer default –2
state of converting channels 0 through 7 sequentially, all –4
IVEE
in SoftSpan 7. If reset is triggered during a conversion, the –6

conversion is immediately halted. The normal power down –8

0 160 320 480 640 800
behavior associated with PD going high is not affected by SAMPLING FREQUENCY (kHz)
233316 F15

reset. Once PD is brought low, wait at least 10ms before

initiating a conversion. When employing the internal refer- Figure 15. Power Dissipation of the LTC2333-16
ence buffer, allow 200ms for the buffer to power up and Decreases with Decreasing Sampling Frequency
recharge the REFBUF bypass capacitor. Any conversion
initiated before these times will produce invalid results.

tPDH
PD t WAKE

tCNVH tPDL
CNV
SECOND RISING EDGE OF
BUSY tCONV PD TRIGGERS RESET

RESET RESET TIME

SET INTERNALLY
233316 F14

Figure 14. Reset Timing for the LTC2333-16

233316f

30 For more information www.linear.com/LTC2333-16

 LTC2333-16
Applications Information
Digital Interface Within a window, the device accepts control words on SDI
The LTC2333-16 features CMOS and LVDS serial interfaces, to configure the SoftSpan range and channel for the next
selectable using the LVDS/CMOS pin. The flexible OVDD conversion and program the sequencer, and outputs 24-bit
supply allows the LTC2333-16 to communicate with any packets containing the conversion result and configuration
CMOS logic operating between 1.8V and 5V, including 2.5V information from the previous conversion on SDO.
and 3.3V systems, while the LVDS interface supports low New data transaction windows open 10ms after power-
noise digital designs. Together, these I/O interface options ing up or resetting the LTC2333-16, and at the end of
enable the LTC2333-16 to communicate equally well with each conversion on the falling edge of BUSY. The data
legacy microcontrollers and modern FPGAs. transaction should be completed with a minimum tQUIET
time of 20ns prior to the start of the next conversion, as
Serial CMOS I/O Mode shown in Figure 16. New control words are only accepted
As shown in Figure 16, in CMOS I/O mode the serial data within this recommended data transaction window, but
bus consists of a serial clock input, SCKI, serial data input, configuration changes take effect immediately with no ad-
SDI, serial clock output, SCKO, and serial data output, ditional analog input settling time required before starting
SDO. Communication with the LTC2333-16 across this the next conversion.
bus occurs during predefined data transaction windows.

CS = PD = 0
SAMPLE N SAMPLE N + 1
t CYC
tCNVH
CNV t CNVL

BUSY tCONV t ACQ

tBUSYLH RECOMMENDED DATA TRANSACTION WINDOW

t QUIET
t SSDISCKI t SCKI t SCKIH

SCKI 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
t HSDISCKI t SCKIL

SDI DON’T CARE C7 C6 C5 C4 C3 C2 C1 C0 DON’T CARE

CONTROL WORD FOR CONVERSION N + 1

t DSDOBUSYL t HSDOSCKI t SKEW

SCKO
t DSDOSCKI

SDO DON’T CARE D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 CH2 CH1 CH0 SS2 SS1 SS0 D15

CONVERSION RESULT CHANNEL ID SoftSpan CONVERSION RESULT

24-BIT PACKET CONVERSION N 24-BIT PACKET CONVERSION N

(REPETITION) 233316 F16

Figure 16. Serial CMOS I/O Mode, Direct Per-Conversion Configuration

233316f

For more information www.linear.com/LTC2333-16 31

LTC2333-16
Applications Information
Just prior to the falling edge of BUSY and the opening of Configuring the Multiplexer and SoftSpan Range in
a new data transaction window, SCKO is forced low and CMOS I/O Mode
SDO is updated with the latest conversion result from the
On power-up and after a reset, the LTC2333-16 defaults
just-completed conversion. Rising edges on SCKI serially to converting channels 0 through 7 sequentially, all in
clock the conversion result and analog input channel con- SoftSpan 7. If this configuration does not need to be
figuration information out on SDO and trigger transitions
changed, simply hold SDI low.
on SCKO that are skew-matched to the data on SDO. The
resulting SCKO frequency is half that of SCKI. The LTC2333-16 multiplexer and SoftSpan range may
be controlled in two ways, depending on the needs of
SCKI rising edges also latch control words provided on
the application. If the desired sequence of channels and
SDI, which are used to set the SoftSpan range and chan-
SoftSpan ranges are known ahead of time, the LTC2333-
nel for the next conversion, and program the sequencer.
16’s internal sequencer may be programmed with a se-
See the section Configuring the Multiplexer and SoftSpan quence of up to 16 configurations, and will cycle through
Range for further details. SCKI is allowed to idle either those configurations on subsequent conversions without
high or low in CMOS I/O mode. As shown in Figure 17,
further user intervention. Alternately, if ultimate flexibility
the CMOS bus is enabled when CS is low and is disabled is desired, the LTC2333-16 may be directly controlled by
and Hi-Z when CS is high, allowing the bus to be shared overwriting the sequencer each conversion with the chan-
across multiple devices. nel and SoftSpan range for the following conversion. This
The data on SDO are formatted as a 24-bit packet consisting reconfiguration has no latency and requires no additional
of a 16-bit conversion result followed by two zeros, 3-bit settling time or digital I/O overhead.
analog channel ID, and 3-bit SoftSpan code, all presented
MSB first. As suggested in Figures 16 and 17, if more than Using the Sequencer
24 SCKI clocks are applied, the 24-bit packet is repeated To use the internal sequencer of the LTC2333-16, first
indefinitely on SDO. program it as described below with the desired sequence
When interfacing the LTC2333-16 with a standard SPI of up to 16 configurations. Each of these configurations
bus, capture output data at the receiver on rising edges specifies the desired channel number and SoftSpan range
of SCKI. SCKO is not used in this case. In other applica- for one conversion. The LTC2333-16 will then apply the
tions, such as interfacing the LTC2333-16 with an FPGA first configuration to the first conversion, the second
or CPLD, rising and falling edges of SCKO may be used configuration to the second conversion, and so on until
to capture serial output data on SDO in double data rate the end of the programmed sequence is reached, at which
(DDR) fashion. Capturing data using SCKO adds robust- point the cycle will start again from the beginning.
ness to delay variations over temperature and supply. Each data transaction window is an opportunity to program
The LTC2333-16 guarantees a minimum data transfer win- the sequencer by clocking in a series of 8-bit control words
dow (tACQ – tQUIET) of 650ns while converting at 800ksps. on SDI, each specifying a channel number and SoftSpan
Thus, if an application needs to read the full 24-bit packet range, as shown in Figures 16 and 17. To program the
of conversion result plus channel ID and SoftSpan, the sequencer with a series of up to 16 conversion configu-
minimum usable SCKI frequency is 37MHz. Applications rations, write in the corresponding control words in the
needing to read only the conversion result may send only desired conversion order during a single data transaction.
16 SCKI pulses and thus have a minimum SCKI frequency Words beyond the 16th valid word will be ignored.
of 25MHz. The LTC2333-16 supports CMOS SCKI frequen-
cies up to 100MHz.

233316f

32 For more information www.linear.com/LTC2333-16

 PD = 0

BUSY

CS

SCKI DON’T CARE DON’T CARE

Applications Information

CONTROL WORD CONTROL WORD CONTROL WORD CONTROL WORD CONTROL WORD CONTROL WORD CONTROL WORD CONTROL WORD CONTROL WORD CONTROL WORD PARTIAL WORD
SDI DON’T CARE DON’T CARE
FOR CONV N + 1 FOR CONV N + 2 FOR CONV N + 3 FOR CONV N + 4 FOR CONV N + 5 FOR CONV N + 6 FOR CONV N + 7 FOR CONV N + 8 FOR CONV N + 9 FOR CONV N + 10 (IGNORED)

Hi-Z Hi-Z
SCKO

Hi-Z RESULT PACKET Hi-Z

SDO 24-BIT RESULT PACKET 24-BIT RESULT PACKET 24-BIT RESULT PACKET
(PARTIAL)

tEN t DIS
233316 F17

For more information www.linear.com/LTC2333-16

Figure 17. Programming the Sequencer for a 10-Conversion Sequence, Serial CMOS Bus Response to CS

33
233316f
LTC2333-16
LTC2333-16
Applications Information
The control word format is as follows: If the desired channel and SoftSpan range for conversion
N+1 are known before seeing the result of conversion N,
C[7] C[6] C[5] C[4] C[3] C[2] C[1] C[0] specify the configuration by clocking in the corresponding
V 0 CH[2] CH[1] CH[0] SS[2] SS[1] SS[0] control word on SDI while clocking out the first 8 bits,
then hold SDI low. This particular use case is illustrated in
The V bit (C[7]) controls whether the LTC2333-16 should Figure 16. If the desired configuration is not known until
consider this a valid word. Any words which have V = after the conversion data has been read, clock in 24 zeros
0 are considered invalid and are ignored (though valid on SDI while the 24 bits of data are being read out; since
words will still be accepted after an invalid word). Words the V bits of those words are then 0, they are ignored.
which have V = 1 will be added to the sequencer in the Once the configuration has been determined, clock in 8
order provided. The C[6] bit is reserved for future use and more bits on SDI which specify the desired configuration
should be set to 0. The CH[2:0] (C[5:3]) bits are a binary for conversion N+1.
value 0 to 7 controlling the channel to be converted. The
Serial LVDS I/O Mode
SS[2:0] (C[2:0]) bits specify the desired SoftSpan range
for the conversion, as described in Table 1. In LVDS I/O mode, information is transmitted using
positive and negative signal pairs (LVDS+/LVDS−) with bits
Sequencer programming is completed when the next
differentially encoded as (LVDS+ − LVDS−). These signals
conversion is started. At this time, any incomplete words
are typically routed using differential transmission lines
are considered invalid and discarded. If one or more
with 100Ω characteristic impedance. Logical 1s and 0s
valid words were provided, the sequencer is completely
are nominally represented by differential +350mV and
overwritten with the new sequence, and the just-initiated
−350mV, respectively. For clarity, all LVDS timing diagrams
conversion employs the first provided configuration.
and interface discussions adopt the logical rather than
If no valid words were provided during the data transac- physical convention.
tion window, the sequencer program is unchanged, and
As shown in Figure 18, in LVDS I/O mode the serial data
the pointer advances to the next entry in the previously
bus consists of a serial clock differential input, SCKI, serial
programmed cycle to configure the next conversion.
data differential input, SDI, serial clock differential output,
Thus, once the sequencer has been programmed, simply SCKO, and serial data differential output, SDO. Communi-
hold SDI low during subsequent data transactions to cation with the LTC2333-16 across this bus occurs during
cycle continually through the programmed sequence of predefined data transaction windows. Within a window,
configurations. the device accepts control words on SDI to configure the
SoftSpan range and channel for the next conversion and
Direct Per-Conversion Configuration program the sequencer, and outputs 24-bit packets con-
As a special case of the sequencer, the LTC2333-16 taining the conversion result and configuration information
multiplexer and SoftSpan range can be directly controlled from the previous conversion on SDO.
every conversion with no latency and no additional set- New data transaction windows open 10ms after power-
tling time or digital I/O overhead. To use the part in this ing up or resetting the LTC2333-16, and at the end of
direct fashion, simply supply one control word on SDI each conversion on the falling edge of BUSY. The data
during a data transaction to specify the desired channel transaction should be completed with a minimum tQUIET
number and SoftSpan range for the following conversion,
as shown in Figure 16.

233316f

34 For more information www.linear.com/LTC2333-16

 LTC2333-16
Applications Information
CS = PD = 0
SAMPLE N SAMPLE N + 1
t CYC
t CNVH
CNV t CNVL
(CMOS)

BUSY t CONV t ACQ

(CMOS)
t BUSYLH RECOMMENDED DATA TRANSACTION WINDOW
t QUIET
t SSDISCKI t SCKI t SCKIH

SCKI
(LVDS) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

t HSDISCKI t SCKIL
SDI
DON’T CARE C7 C6 C5 C4 C3 C2 C1 C0 DON’T CARE
(LVDS)

CONTROL WORD FOR CONVERSION N + 1

t DSDOBUSYL t HSDOSCKI t SKEW
SCKO
(LVDS)
t DSDOSCKI
SDO DON’T CARE D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 CH2 CH1 CH0 SS2 SS1 SS0 D15
(LVDS)

CONVERSION RESULT CHANNEL ID SoftSpan CONVERSION RESULT

24-BIT PACKET CONVERSION N 24-BIT PACKET CONVERSION N

(REPETITION) 233316 F18

Figure 18. Serial LVDS I/O Mode, Direct Per-Conversion Configuration

time of 20ns prior to the start of the next conversion, as SCKI rising and falling edges also latch control words
shown in Figure 18. New control words are only accepted provided on SDI, which are used to set the SoftSpan range
within this recommended data transaction window, but and channel for the next conversion, and program the
configuration changes take effect immediately with no ad- sequencer. See the section Configuring the Multiplexer
ditional analog input settling time required before starting and SoftSpan Range in LVDS I/O Mode for further details.
the next conversion. As shown in Figure 19, the LVDS bus is enabled when CS
Just prior to the falling edge of BUSY and the opening of is low and is disabled and Hi-Z when CS is high, allow-
ing the bus to be shared across multiple devices. Due to
a new data transaction window, SDO is updated with the
the high speeds often involved in LVDS signaling, LVDS
latest conversion result from the just-completed conver-
bus sharing must be carefully considered. Transmission
sion. Both rising and falling edges on SCKI serially clock the
conversion result and analog input channel configuration line limitations imposed by the shared bus may limit the
information out on SDO. SCKI is also echoed on SCKO, maximum achievable bus clock speed. LVDS inputs are
skew-matched to the data on SDO. Whenever possible, internally terminated with a 100Ω differential resistor when
it is recommend that rising and falling edges of SCKO be CS is low, while outputs must be differentially terminated
used to capture DDR serial output data on SDO, as this will with a 100Ω resistor at the receiver (FPGA). SCKI must
yield the best robustness to delay variations over supply idle in the low state in LVDS I/O mode, including when
and temperature. transitioning CS.

233316f

For more information www.linear.com/LTC2333-16 35

36
LTC2333-16

PD = 0

BUSY
(CMOS)

CS
(CMOS)

SCKI
DON’T CARE DON’T CARE
(LVDS)

SDI CONTROL WORD CONTROL WORD CONTROL WORD CONTROL WORD CONTROL WORD CONTROL WORD CONTROL WORD CONTROL WORD CONTROL WORD CONTROL WORD PARTIAL WORD
DON’T CARE DON’T CARE
Applications Information

(LVDS) FOR CONV N + 1 FOR CONV N + 2 FOR CONV N + 3 FOR CONV N + 4 FOR CONV N + 5 FOR CONV N + 6 FOR CONV N + 7 FOR CONV N + 8 FOR CONV N + 9 FOR CONV N + 10 (IGNORED)

SCKO Hi-Z Hi-Z

(LVDS)

SDO Hi-Z RESULT PACKET Hi-Z

24-BIT RESULT PACKET 24-BIT RESULT PACKET 24-BIT RESULT PACKET
(LVDS) (PARTIAL)

233316 F19
tEN t DIS

For more information www.linear.com/LTC2333-16

Figure 19. Programming the Sequencer with a 10-Conversion Sequence, Serial LVDS Bus Response to CS

233316f
 LTC2333-16
Applications Information
The data on SDO are formatted as a 24-bit packet consisting specifies the desired channel number and SoftSpan range
of a 16-bit conversion result followed by two zeros, 3-bit for one conversion. The LTC2333-16 will then apply the
analog channel ID, and 3-bit SoftSpan code, all presented first configuration to the first conversion, the second
MSB first. As suggested in Figures 18 and 19, if more than configuration to the second conversion, and so on until
24 SCKI clocks are applied, the 24-bit packet is repeated the end of the programmed sequence is reached, at which
indefinitely on SDO. point the cycle will start again from the beginning.
The LTC2333-16 guarantees a minimum data transfer win- Each data transaction window is an opportunity to program
dow (tACQ – tQUIET) of 650ns while converting at 800ksps. the sequencer by clocking in a series of 8-bit control words
Thus, if an application needs to read the full 24-bit packet on SDI, each specifying a channel number and SoftSpan
of conversion result plus channel ID and SoftSpan, the range, as shown in Figures 18 and 19. To program the
minimum usable SCKI frequency is 19MHz (38Mbps). Ap- sequencer with a series of up to 16 conversion configu-
plications needing to read only the conversion result may rations, write in the corresponding control words in the
send only 16 SCKI edges and thus have a minimum SCKI desired conversion order during a single data transaction.
frequency of 13MHz (26Mbps). The LTC2333-16 supports Words beyond the 16th valid word will be ignored.
LVDS SCKI frequencies up to 250MHz (500Mbps). The control word format is as follows:
Configuring the Multiplexer and SoftSpan Range in
C[7] C[6] C[5] C[4] C[3] C[2] C[1] C[0]
LVDS I/O Mode
V 0 CH[2] CH[1] CH[0] SS[2] SS[1] SS[0]
On power-up and after a reset, the LTC2333-16 defaults
to converting channels 0 through 7 sequentially, all in The V bit (C[7]) controls whether the LTC2333-16 should
SoftSpan 7. If this configuration does not need to be consider this a valid word. Any words which have V =
changed, simply hold SDI at an LVDS low level. 0 are considered invalid and are ignored (though valid
The LTC2333-16 multiplexer and SoftSpan range may be words will still be accepted after an invalid word). Words
controlled in two ways, depending on the needs of the ap- which have V = 1 will be added to the sequencer in the
plication. If the desired sequence of channels and SoftSpan order provided. The C[6] bit is reserved for future use and
ranges are known ahead of time, the LTC2333-16’s internal should be set to 0. The CH[2:0] (C[5:3]) bits are a binary
sequencer may be programmed with a sequence of up to value 0 to 7 controlling the channel to be converted. The
16 configurations, and will cycle through those configu- SS[2:0] (C[2:0]) bits specify the desired SoftSpan range
rations on subsequent conversions without further user for the conversion, as described in Table 1.
intervention. Alternately if ultimate flexibility is desired, the Sequencer programming is completed when the next
LTC2333-16 may be directly controlled by overwriting the conversion is started. At this time, any incomplete words
sequencer each conversion with the channel and SoftSpan are considered invalid and discarded. If one or more
range for the following conversion. This reconfiguration valid words were provided, the sequencer is completely
has no latency and requires no additional settling time or overwritten with the new sequence, and the just-initiated
digital I/O overhead. conversion employs the first provided configuration.
Using the Sequencer If no valid words were provided during the data transac-
tion window, the sequencer program is unchanged, and
To use the internal sequencer of the LTC2333-16, first
the pointer advances to the next entry in the previously
program it as described below with the desired sequence
programmed cycle to configure the next conversion.
of up to 16 configurations. Each of these configurations

233316f

For more information www.linear.com/LTC2333-16 37

LTC2333-16
Applications Information
Thus, once the sequencer has been programmed, simply If the desired channel and SoftSpan range for conversion
hold SDI at an LVDS low level during subsequent data N+1 are known before seeing the result of conversion N,
transactions to cycle continually through the programmed specify the configuration by clocking in the corresponding
sequence of configurations. control word on SDI while clocking out the first 8 bits,
then hold SDI at an LVDS low level. This particular use
Direct Per-Conversion Configuration case is illustrated in Figure 18. If the desired configura-
As a special case of the sequencer, the LTC2333-16 tion is not known until after the conversion data has been
multiplexer and SoftSpan range can be directly controlled read, clock in 24 zeros on SDI while the 24 bits of data
every conversion with no latency and no additional set- are being read out; since the V bits of those words are
tling time or digital I/O overhead. To use the part in this then 0, they are ignored. Once the configuration has been
direct fashion, simply supply one control word on SDI determined, clock in 8 more bits on SDI which specify the
during a data transaction to specify the desired channel desired configuration for conversion N+1.
number and SoftSpan range for the following conversion,
as shown in Figure 18.

Board Layout
To obtain the best performance from the LTC2333-16, a Supply bypass capacitors should be placed as close as
four-layer printed circuit board (PCB) is recommended. possible to the supply pins. Low impedance common re-
Layout for the PCB should ensure the digital and analog turns for these bypass capacitors are essential to the low
signal lines are separated as much as possible. In particu- noise operation of the ADC. A single solid ground plane
lar, care should be taken not to run any digital clocks or is recommended for this purpose. When possible, screen
signals alongside analog signals or underneath the ADC. the analog input traces using ground.
Also minimize the length of the REFBUF to GND (Pin 20)
bypass capacitor return loop, and avoid routing CNV near Reference Design
signals which could potentially disturb its rising edge. For a detailed look at the reference design for this con-
verter, including schematics and PCB layout, please refer
to DC2365, the evaluation kit for the LTC2333-16.

233316f

38 For more information www.linear.com/LTC2333-16

 LTC2333-16
Package Description
Please refer to http://www.linear.com/product/LTC2333-16#packaging for the most recent package drawings.

LX Package
48-Lead Plastic LQFP (7mm × 7mm)
(Reference LTC DWG # 05-08-1760 Rev A)

7.15 – 7.25 9.00 BSC

5.50 REF 7.00 BSC
48

48 SEE NOTE: 4
1 1
2 2
0.50 BSC

9.00 BSC
5.50 REF
7.00 BSC
7.15 – 7.25
0.20 – 0.30
A A

PACKAGE OUTLINE
C0.30 – 0.50

1.30 MIN
RECOMMENDED SOLDER PAD LAYOUT
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

1.60
11° – 13° 1.35 – 1.45 MAX
R0.08 – 0.20 GAUGE PLANE
0.25
0° – 7°

11° – 13°
0.50
0.09 – 0.20 0.17 – 0.27 0.05 – 0.15
1.00 REF BSC

0.45 – 0.75

SECTION A – A

NOTE: e3
XXYY

1. PACKAGE DIMENSIONS CONFORM TO JEDEC #MS-026 PACKAGE OUTLINE

Q_ _ _ _ _ _

2. DIMENSIONS ARE IN MILLIMETERS

LTCXXXX

3. DIMENSIONS OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH

LX-ES

SHALL NOT EXCEED 0.25mm ON ANY SIDE, IF PRESENT

COMPONENT
4. PIN-1 INDENTIFIER IS A MOLDED INDENTATION, 0.50mm DIAMETER PIN “A1”
5. DRAWING IS NOT TO SCALE

TRAY PIN 1 LX48 LQFP 0113 REV A

BEVEL
PACKAGE IN TRAY LOADING ORIENTATION

233316f

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
For more
tion that the interconnection of itsinformation www.linear.com/LTC2333-16
circuits as described herein will not infringe on existing patent rights. 39
LTC2333-16
Typical Application
Amplify Differential Signals with Gain of 10 Over a Wide Common Mode Range with Buffered Analog Inputs

31V
INTERNAL HIGH-Z BUFFERS
IN+ + LTC2057HV ALLOW OPTIONAL
ARBITRARY
kΩ PASSIVE FILTERS
– 31V
24V 3.65k
BUFFERED
ANALOG 0.1µF
2.49k
INPUTS

COMMON MODE IN0+ VCC

549Ω GAIN = 10 2.2nF
INPUT RANGE IN0–
2.49k
LTC2333-16
DIFFERENTIAL MODE
INPUT RANGE: ±500mV 3.65k
VEE REFBUF REFIN
0V –
47µF 0.1µF
IN–
+ LTC2057HV
BW = 10kHz 0.1µF

–7V –7V
233316 TA02
ONLY CHANNEL 0 SHOWN FOR CLARITY

Related Parts
PART NUMBER DESCRIPTION COMMENTS
ADCs
LTC2358-18/LTC2358-16 Buffered 18-/16-Bit, 200ksps/Ch, 8-Channel Buffered ±10.24V SoftSpan Inputs with Wide Common Mode Range,
Simultaneous Sampling, ±3.51LSB/±1LSB INL 96/94dB SNR, Serial CMOS and LVDS I/O, 7mm × 7mm LQFP-48 Package
LTC2335-18/LTC2335-16 18-/16-Bit, 1Msps, 8-Channel Multiplexed, ±10.24V SoftSpan Inputs with Wide Common Mode Range, 97dB/94dB
±3LSB/±1LSB INL, Serial ADC SNR, Serial CMOS and LVDS I/O, 7mm × 7mm LQFP-48 Package
LTC2348-18/LTC2348-16 18-/16-Bit, 200ksps/Ch, 8-Channel Simultaneous ±10.24V SoftSpan Inputs with Wide Common Mode Range, 97/94dB SNR,
Sampling, ±3/±1LSB INL, Serial ADC Serial CMOS and LVDS I/O, 7mm × 7mm LQFP-48 Package
LTC2345-18/LTC2345-16 18-/16-Bit, 200ksps/Ch, 8-Channel Simultaneous ±4.096V SoftSpan Inputs with Wide Common Mode Range, 92/91dB SNR,
Sampling, ±5/±1.25LSB INL, Serial ADC Serial CMOS and LVDS I/O, 7mm × 7mm QFN-48 Package
LTC2338-18/LTC2337-18/ 18-Bit, 1Msps/500ksps/250ksps, Serial, Low 5V Supply, ±10.24V Fully Differential Input, 100dB SNR, MSOP-16 Package
LTC2336-18 Power ADC
LTC2328-18/LTC2327-18/ 18-Bit, 1Msps/500ksps/250ksps, Serial, Low 5V Supply, ±10.24V Pseudo-Differential Input, 95dB SNR, MSOP-16
LTC2326-18 Power ADC Package
LTC2373-18/LTC2372-18 18-Bit, 1Msps/500ksps, 8-Channel, Serial ADC 5V Supply, 8-Channel Multiplexed, Configurable Input Range, 100dB SNR,
DGC, 5mm × 5mm QFN-32 Package
LTC1859/LTC1858/ 16-/14-/12-Bit, 8-Channel, 100ksps, Serial ADC ±10V, SoftSpan, Single-Ended or Differential Inputs, Single 5V Supply,
LTC1857 SSOP-28 Package
DACs
LTC2756/LTC2757 18-Bit, Serial/Parallel IOUT SoftSpan DAC ±1LSB INL/DNL, Software-Selectable Ranges, SSOP-28/7mm × 7mm
LQFP-48 Package
LTC2668 16-Channel 16-/12-Bit ±10V VOUT SoftSpan DACs ±4LSB INL, Precision Reference 10ppm/°C Max, 6mm × 6mm QFN-40 Package
References
LTC6655 Precision Low Drift Low Noise Buffered Reference 5V/2.5V/2.048V/1.25V, 2ppm/°C, 0.25ppm Peak-to-Peak Noise, MSOP-8
Package
LT6657 Precision Low Drift Low Noise Buffered Reference 5V/3V/2.5V, 1.5ppm/°C, 0.5ppm Peak-to-Peak Noise, MSOP-8 Package
Amplifiers
LTC2057/LTC2057HV High Voltage, Low Noise Zero-Drift Op Amp Maximum Input Offset: 4.5µV, Supply Voltage Range: 4.75V to 60V
LT6020 Dual, Micropower, 5Vµs, Rail-to-Rail Op Amp Maximum Input Offset: 30µV, Maximum Supply Current: 100µA/Amplifier
LT1354/LT1355/LT1356 Single/Dual/Quad 1mA, 12MHz, 400V/µs Op Amp Good DC Precision, Stable with All Capacitive Loads

233316f

40
LT 0517 • PRINTED IN USA
www.linear.com/LTC2333-16
For more information www.linear.com/LTC2333-16  LINEAR TECHNOLOGY CORPORATION 2017