VLSI

INTERVIEW
PREPARATION
PHYSICAL DESIGN
STEP 1 : FLOOR PLANNING

Your Complete Experience-Level Guide

By ProV Logic
 INTRODUCTION
Floorplanning is a critical phase in ASIC design, where the
layout and organization of various components — such as
I/O pads, macros, and power/ground structures — are
defined on the chip.
It sets the stage for subsequent design steps, including
placement, routing, and timing closure.
The floorplanning aims to create a layout that minimizes
wiring congestion, optimizes the placement of standard
cells and macros, and ensures efficient power distribution.
Achieving this requires careful consideration of the
design’s physical constraints and logical requirements.
 INTRODUCTION
Floorplanning is a critical phase in ASIC design, where the
layout and organization of various components — such as
I/O pads, macros, and power/ground structures — are
defined on the chip.
It sets the stage for subsequent design steps, including
placement, routing, and timing closure.
The floorplanning aims to create a layout that minimizes
wiring congestion, optimizes the placement of standard
cells and macros, and ensures efficient power distribution.
Achieving this requires careful consideration of the
design’s physical constraints and logical requirements.

KEY INPUTS FOR FLOORPLANNING

Netlist (.v): The netlist is a structural representation of the

circuit, outlining the logical connections between various
components.
Technology File (techlef): This file provides details about
the manufacturing process, including the metal layers,
spacing, and other technology-specific design rules.
Timing Library Files (.lib): These files define the timing
characteristics of the standard cells, crucial for meeting
performance and timing goals.
 Physical Library (.lef): This file contains information about
the physical dimensions, pin positions, and layout of
standard cells and macros.
Synopsys Design Constraints (.sdc): The SDC file defines
timing constraints such as clock definitions, input/output
delays, and multi-cycle paths.
Tlu+ Files: These are parasitic files that are essential for
performing accurate RC (resistance and capacitance)
extraction, which is key to analyzing signal delays and
optimizing timing.

STEPS IN FLOORPLANNING

Once the necessary inputs are in place, the process of

floorplanning begins. Below is a breakdown of the essential
steps involved in floorplanning:

1. Die Size Estimation: Core Width and Height

The first step in floorplanning is estimating the die size,
which involves determining the width and height of the
core area.
This estimation is based on the number of standard cells,
macros, and I/O cells that need to be placed.
A precise die size estimation ensures there is enough
space for cell placement and routing, without wasting
silicon real estate.
2. Creation of I/O Pad Sites
I/O pads are the interface between the chip and the
external world. In this step, pad sites are created to
determine the placement of input and output pads.
Proper placement of I/O pads ensures efficient signal flow
and minimizes delays caused by long wire routes.

3. Macro Placement
Macros are larger blocks such as memory (SRAM), PLLs, or
custom-designed IPs.
Their placement is critical because macros take up
significant space and affect the overall routing complexity.
Floorplanning ensures macros are strategically placed to
reduce congestion and meet timing requirements.

4. Standard Cell Rows Creation

Standard cells are placed in rows that are created within
the core area.
The layout of these rows, their orientation, and spacing are
essential for ensuring efficient utilization of the core area.
Standard cell placement must also account for routing
channels and power distribution.

5. Power Planning (Pre-routing)

Power planning is one of the most critical tasks during
floorplanning.
 A robust power network ensures reliable power delivery to
all the components on the chip.
Power rings, power grids, and power straps are planned to
ensure that IR drop and electromigration are minimized,
maintaining the integrity of the design.

6. Inserting Physical-Only Cells

In addition to standard cells, physical-only cells such as
decoupling capacitors, filler cells, and tap cells are inserted
into the layout.
These cells help maintain the structural integrity of the
design and improve power and signal integrity.

CORE CONTROL PARAMETERS IN FLOORPLANNING

1. Aspect Ratio
The aspect ratio is the ratio of the chip’s width to its height,
and it plays a crucial role in determining the chip’s size and
shape.
An aspect ratio of 1.0 signifies a square core, while a value
greater or lesser than 1.0 results in a rectangular core.
Choosing the correct aspect ratio is important for
balancing horizontal and vertical routing resources.
TYPES OF DESIGN

There are two types of design:

1. Core Limited Design
2. Pad Limited Design

1. Core Limited Design

The size of the die is restricted by the core’s area.
Possible lower number of I/O pads.

2. Core Limited Design

The size of the die is restricted by the Pad area.
Core area is dominated by the Pad area.
Sanity Checks
All imported input files should be clean, accurate and data
should match among them.
So, to check the quality of input files, sanity checks have to
be performed.
if everything is good with the input files then we need to
proceed to the next stage, otherwise we have to sort out
the issues with the files and fix those issues to move
forward to further stages.

Design Checks
This sanity check have to perform on netlist to check
whether the netlist is free of design issues or not.
Some of the design issues are listed below:
 Combinational Loops
Floating Inputs
Multi Driven Inputs
Un-intended latches
Tri-Stateable gates
Empty Modules in Netlist
Assign Statements

Library Checks
This sanity check have to perform to check the correlation
between Netlist and libraries.
The cells present in the netlist should be present in the
libraries(timing and standard cell libraries).

Timing Checks
This sanity check have to check the quality of SDC file,
which means each and every path in the design should be
constrained.
if any path is not constrained then those paths are
considered as unconstrained timing paths.
And also it checks the consistency among the constraints.
Routing Tracks
Entire metal layer can be divided into number of horizontal
and vertical lines, each line can be considered as one
routing track.
These tracks are virtual, created for routing
purpose(physically don’t exist in the design).
A net or route middle is exactly aligns automatically to the
routing track.
The distance between the tracks is called as pitch.
Standard Cell Rows
Standard cell rows are created in core area to place
standard cells.
During the placement stage all the standard cells in the
core area will have to align with in these rows.

Inverted Rows
Every standard cell row has VDD & VSS.
While coming to the second row its inverted i.e. VSS &
VDD.
Its because the first row cells and second row cells should
share the same VSS & VDD so that more area is saved.
If it doesn’t follow inverted row concept huge area will be
wasted.
Macro Guidelines
Macro is also like a standard cell but gigantic in size.
macros are like some other design is using as a part of
current design, it can be altered, logic fixed for the macros.
These are available in different shapes (rectangular,
square) and sizes, some of the macro shapes are
rectilinear (some of the macro shapes are like a nightmare
for many physical design engineers).

1. Macros should be place at periphery of the core boundary.

2. Macro pins should be face towards the center of the core
area.
3. Macros should not place at middle of the core area. If it
places middle of the core it will create round about routing
paths.
4. Avoid notches in the core area.
5. Avoid criss-cross.
6. Place talking Marcos near to each other.
7. Maintain proper halo around the macros.
TYPES OF PLACEMENT BLOCKAGES

There are 3 types of placement blockages, which are:

• Hard blockage
• Soft blockage
• Partial blockage

Hard blockage:
It will not allow to place any type of standard cells inside
the blockage area.
Soft blockage:
It will allow only buffers and inverters inside the blockage
area while optimization.
Partial blockage:
It will allow any type of standard cells inside the blockage
but there is a hard rule that it will allow only for some
percentage of area.
For instance, consider partial blockage of 30%, means tool
allows 30% percentage of blockage area to place
standard cells.

Halo:
There is another type of blockage which is “Halo”.
Halo is nothing but hard blockage, which is placed around
the macros.
Here, difference between the halo and hard blockage is
halo will move along with the macros.
But hard blockage will not move along with macros.

TYPES OF FLOORPLANS

There are three types of floorplan techniques:

• Abutted floorplan
• Non-Abutted floorplan
• Mixed floorplan
Abutted floorplan type:
For this technique, no spacing can be maintained between
the elements in the floorplan (Zero channel spacing
among the macros).

Non-Abutted floorplan type:

For this technique, some spacing can be maintained
among the elements in the floorplan.
Mixed floorplan type:
For this technique, name of type itself explaining that
combination of both Abutted and Non-Abutted type
floorplan techniques.
There will be some spacing for few elements and no
spacing for few elements.
 INTERVIEW QUESTIONS

1. What factors influence macro placement in floor planning?

Solution:
Macro placement is a critical aspect of floor planning in
ASIC/FPGA design. The key factors that influence macro
placement include:
1. Peripheral Placement:
Macros are usually placed near the periphery of the core
to ensure easy routing and to minimize congestion.
This prevents blocking the central routing channels and
avoids excessive wirelength.
2. Pin Orientation:
Macro pins should face the standard cell area to facilitate
easier connections.
3. Routing Congestion:
Placing macros in the middle of the core can create
routing congestion and increase wire delays.
To avoid congestion, channel spacing and blockages need
to be properly managed.
4. Clock and Power Distribution:
Macros need to be positioned to minimize IR drop and
power noise issues.
Proper power straps should be planned for macros.
 INTERVIEW QUESTIONS

2. How do you handle congestion during floor planning?

Solution:
Congestion is one of the biggest challenges in floor planning and
can impact timing, routing, and overall design closure. Here are
some techniques to handle congestion effectively:
1. Macro and Standard Cell Placement Strategy:
Place macros at the periphery to leave sufficient space in
the center for standard cells.
Align macro pins properly to reduce detours in routing.
2. Utilizing Blockages:
Apply hard blockages to prevent standard cells from being
placed in critical routing areas.
Use soft blockages to allow only buffers and inverters,
improving routability.
Partial blockages can be used to reduce cell density in
congested regions.
3. Proper Spacing Between Macros:
Increase the spacing between macros to improve routing
channels and reduce wire detours.
Maintain sufficient halo around macros to prevent cell
crowding.
 INTERVIEW QUESTIONS

3. How do you optimize floor planning for power distribution?

Solution:
A well-optimized floor plan ensures efficient power distribution to
prevent IR drop and electromigration issues. The following
strategies help optimize power distribution:
1. Uniform Power Grid Design:
Create a structured power grid using metal layers to
distribute power evenly.
Ensure power straps are sufficiently wide to handle
current demands.
2. Macro Power Planning:
Macros should have dedicated power straps to avoid
drawing excess current from the standard cell region.
Use multiple power rings around macros for better current
handling.
3. Decoupling Capacitors (Decaps):
Place decaps near macros and high-switching logic to
stabilize power delivery.
4. Minimizing IR Drop:
Avoid placing macros in locations that create high
resistance paths.
Use multiple power vias to improve connectivity between
power layers.
 INTERVIEW QUESTIONS

4. What is Aspect Ratio in Floor Planning? How does it impact

design?

Solution:
Aspect Ratio (AR) = Width / Height
1. Ideal Aspect Ratio:
The optimal AR is close to 1 (square shape) to ensure
balanced placement and routing.
2. Impact on Design:
High AR (e.g., 2:1 or more) → Leads to longer wire lengths,
timing issues, and congestion.
Low AR (e.g., 1:2) → Can impact power distribution and
require careful planning.
3. Considerations for Floor Planning:
A lower AR provides better routability, reducing
congestion.
A well-balanced AR helps in achieving uniform timing
distribution.
 INTERVIEW QUESTIONS

5. What are Notches in Floor Planning, and why should they be

avoided?

Solution:
Notches are narrow gaps or irregular indentations in a design's
floorplan that can lead to congestion and routing inefficiencies.
Why should notches be avoided?
1. Routing Congestion – Notches reduce the available routing
space, increasing congestion in that region.
2. Timing Issues – The longer routing paths caused by notches
can lead to higher delays and timing violations.
3. Manufacturing Complexity – Notches create non-uniform
metal density, causing yield and fabrication issues.
4. Clock Skew – Clock signals may experience skew due to
uneven wire lengths in a notched area.
How to Avoid Notches?
Optimize Macro Placement: Arrange macros with enough
spacing to eliminate unnecessary gaps.
Use Fillers: Place standard cells or routing resources to
smooth out the floorplan.
Adjust Aspect Ratio: Modify the core dimensions to prevent
excessive gaps in the layout.
Use Blockages Strategically: Define proper placement
blockages to prevent deep notches.
 INTERVIEW QUESTIONS

6. How do you handle thermal hotspots in Floor Planning?

Solution:
Thermal hotspots occur when certain regions have excessive
power dissipation.
Techniques to Reduce Hotspots:
1. Distribute High Power Blocks: Spread high-power macros
across the floorplan.
2. Use Thermal Vias: Improve heat dissipation by adding
thermal vias in power-hungry regions.
3. Optimize Metal Layers: Distribute power using wide metal
layers to avoid localized heating.
4. Apply Power Gating: Turn off unused blocks dynamically to
reduce heat generation.
5. Insert Decoupling Capacitors: Helps smooth out power
fluctuations that cause heat spikes.
 INTERVIEW QUESTIONS

7. How do you handle routing congestion in floor planning?

Solution:
Routing congestion occurs when there are too many
interconnections in a small region, leading to timing and
manufacturing issues.
Techniques to Reduce Congestion:
1. Adjust Core Utilization – Reduce standard cell density in
congested areas (keep utilization below 70%).
2. Optimize Macro Placement – Avoid clustering macros in one
region, which can block routing channels.
3. Use Proper Placement Blockages – Introduce soft blockages
in critical routing areas.
4. Increase Metal Layers – Utilize higher routing layers for global
interconnects.
5. Modify Aspect Ratio – Adjust the floorplan shape to distribute
routing demand evenly.
6. Improve Pin Density Management – Spread out I/O pins to
avoid localized congestion.
7. Enable Detailed Routing Analysis – Run congestion maps
early in the flow using tools like Innovus or ICC.
Example:
If congestion is observed near a memory macro, increasing
spacing and rerouting signal buses can improve congestion.
 INTERVIEW QUESTIONS

8. What is a Power Grid in Floor Planning, and how do you

optimize it?

Solution:
A power grid distributes power evenly across the chip to prevent
IR drop and electromigration.
Optimization Techniques:
1. Use Multiple Power Rings – Wide power rings around the
core and macros help distribute current.
2. Increase Power Straps – More metal layers reduce resistance
and voltage drop.
3. Use Decoupling Capacitors – Reduces noise and voltage
fluctuations.
4. Follow Electromigration Guidelines – Increase wire width to
handle high current density.
5. Run Power Analysis (IR Drop Checks) – Use tools like
RedHawk or Voltus to verify power integrity.
Example:
A high-performance SoC uses multi-layer metal stacks (M8-M11)
for robust power distribution.
 INTERVIEW QUESTIONS

9. What is a Dummy Metal Fill, and why is it used in Floor

Planning?

Solution:
Dummy metal fills are added during layout to balance the metal
density and improve manufacturing yield.
Purpose of Dummy Metal Fill:
1. Prevents Planarity Issues – Ensures uniform etching during
fabrication.
2. Reduces Stress Effects – Minimizes thermal and mechanical
stress variations.
3. Improves CMP Process – Helps in Chemical Mechanical
Polishing (CMP) for even surface finish.
Example:
In 45nm technology, fabs require at least 30% metal density to
avoid yield loss, requiring dummy fills.
 INTERVIEW QUESTIONS

10. What is the impact of Wire Load Models in Floor Planning?

Solution:
Wire load models estimate the interconnect capacitance and
resistance before actual routing.
Impacts on Design:
1. Timing Estimation – Longer wire lengths increase
propagation delays.
2. Power Estimation – High capacitance increases dynamic
power consumption.
3. Area Overhead – Incorrect estimation may lead to congestion
and timing failures.
How to Handle Wire Load Issues?
Use Early Global Routing to refine wirelength estimation.
Shift to Post-Route Extraction for accurate delays.
Example:
In 90nm and above technologies, wire load models are used. For
45nm and below, actual RC extraction is preferred.
 INTERVIEW QUESTIONS

11. How do you optimize Floor Planning for High-Speed

Designs?

Solution:
High-speed designs require special placement and routing
strategies to reduce delays.
Optimization Strategies:
1. Minimize Critical Path Lengths – Place high-speed blocks
closer.
2. Use Low-Skew Clock Trees – Ensure uniform clock
propagation.
3. Reduce Fanout on Critical Nets – Insert buffers on high-
speed signals.
4. Use Shielding for Noise Reduction – Ground shields reduce
crosstalk.
5. Enable Multi-Corner Multi-Mode (MCMM) Analysis – Ensure
timing closure across different process-voltage-temperature
(PVT) corners.
Example:
For high-speed SerDes designs, critical signals must be routed
with minimum detours and separate shielding layers.
 INTERVIEW QUESTIONS

12. What is a Flyline Analysis, and why is it important?

Solution:
A flyline analysis is a visualization of net connections before
routing to check for congestion and macro placement issues.
Benefits of Flyline Analysis:
1. Identifies Macro Placement Issues – Helps in better block
arrangement.
2. Reduces Wirelength – Ensures minimum interconnect delays.
3. Avoids Routing Congestion – Guides proper I/O placement.
Example:
If a DSP block has excessive flyline density, it should be moved
closer to the data bus.

13. What are the Best Practices for Macro Placement in Floor
Planning?

Solution:
1. Keep Large Macros at the Periphery – Reduces routing
congestion in the center.
2. Align Macros for Easy Routing – Straight-line placement
minimizes wirelength.
3. Avoid Notches and Corners – Uneven placement creates
routing blockages.
 INTERVIEW QUESTIONS

14. How does Metal Density Affect Floor Planning?

Solution:
Metal density variations impact manufacturing yield and
performance.
Issues Due to Uneven Metal Density:
1. Chemical-Mechanical Planarization (CMP) Issues – Uneven
surfaces cause defects.
2. IR Drop Variations – Leads to power integrity problems.
3. Increased Crosstalk – Uneven spacing affects signal integrity.
Solutions:
Dummy Metal Fill – Adds uniform metal density.
Density Rules Compliance – Ensures minimum/maximum
metal usage in different layers.
Example:
A 45nm processor design requires at least 30% metal density per
layer to avoid fabrication defects.
 INTERVIEW QUESTIONS

15. How does Floor Planning affect Power Integrity?

Solution:
Poor floor planning can lead to high IR drop, voltage fluctuations,
and electromigration issues.
Ways to Improve Power Integrity:
1. Multiple Power Domains – Reduces dynamic power
consumption.
2. Wide Metal Power Straps – Lowers resistance and IR drop.
3. Uniform Decoupling Capacitors (Decaps) – Reduces voltage
noise.
4. Electromigration-Aware Routing – Prevents excessive
current density in metal layers.
Example:
In high-speed AI chips, power-sensitive regions like compute
cores must have dedicated thick power rails.
 INTERVIEW QUESTIONS

16. What is Floor Planning Congestion Analysis, and how is it

performed?

Solution:
Congestion analysis identifies areas where excessive routing
demand exceeds available resources.
Steps to Perform Congestion Analysis:
1. Run Global Routing – Predicts wirelength and routing
demand.
2. Generate Congestion Maps – Identifies hot spots in tools like
ICC, Innovus.
3. Adjust Placement Constraints – Spread standard cells to
relieve congestion.
4. Apply Track Assignments – Pre-assign routing tracks for
better utilization.
Example:
In a DSP-heavy FPGA, congestion near MAC units can be reduced
by increasing routing channels.
 INTERVIEW QUESTIONS

17. What are Keep-Out Regions (KORs), and why are they used
in Floor Planning?

Solution:
KORs are restricted areas around macros and critical blocks to
avoid congestion and noise coupling.
Uses of Keep-Out Regions:
Avoids Signal Coupling – Reduces noise between adjacent
blocks.
Prevents Macro Overlaps – Ensures proper space for routing.
Enhances Thermal Dissipation – Provides space for heat
flow.
Example:
A PLL block has a KOR around it to prevent interference from
digital switching signals.
 INTERVIEW QUESTIONS

18. How does Floor Planning impact Design for Testability

(DFT)?

Solution:
Poor floor planning can increase test access time and scan chain
complexity.
DFT Considerations in Floor Planning:
Ensure Test Port Accessibility → Easy access to scan chains
and JTAG pins.
Avoid Long Scan Paths → Minimize scan chain wirelength to
improve test speed.
Enable Test Compression → Reduces test pattern size and
scan time.
Example:
For an automotive IC, DFT-aware floor planning ensures that
Built-In Self-Test (BIST) logic is placed efficiently.
 INTERVIEW QUESTIONS
19. How do you optimize Clock Distribution during Floor
Planning?

Solution:
A poorly planned clock tree causes high skew, latency, and power
issues.
Clock Optimization Techniques:
1. Distribute Flip-Flops Evenly – Reduces local clock skew.
2. Minimize Long Clock Paths – Avoid excessive wire delays.
3. Use Multiple Clock Buffers – Balances load distribution.
4. Shield Clock Wires – Prevents crosstalk-induced jitter.
Example:
For high-speed network processors, H-Tree or Grid-based
clocking provides uniform distribution.

20. How does Floor Planning impact Design for Testability

(DFT)?

Solution:
Poor floor planning can increase test access time and scan chain
complexity.
DFT Considerations in Floor Planning:
Ensure Test Port Accessibility → Easy access to scan chains
and JTAG pins.
Avoid Long Scan Paths → Minimize scan chain wirelength to
improve test speed.
 INTERVIEW GUIDE
If you are preparing for a Physical Design (PD) interview, here’s a
structured guide covering technical preparation, common
questions, tips, and strategies to perform well.

UNDERSTANDING THE INTERVIEW PROCESS

Most PD interviews have three main stages:

Technical Screening – Covers basics of PD flow, STA, timing,
and concepts.
Problem-Solving & Coding – Includes Verilog/SystemVerilog,
scripting (TCL, Perl, Python), and algorithms.
Project & Practical Questions – Discuss previous projects,
challenges faced, and optimizations done.

TECHNICAL TOPICS TO PREPARE

Physical Design Flow Timing Analysis (STA)

ASIC Flow: From RTL to Setup & Hold Violations
GDSII Clock Tree Synthesis
PD Steps: Floorplanning, Delay Calculations
Placement, CTS, Routing, (Elmore Delay)
DRC/LVS OCV, AOCV, POCV
Standard Cells: Libraries, Clock Skew, Jitter,
LEF/DEF files Latency
Graph Theory in PD Power, IR Drop & Thermal
Minimum Spanning Tree Analysis
Dijkstra’s Algorithm for Dynamic & Static Power
Shortest Path Power Grid Design
Steiner Tree Problem EM & IR Drop Issues
Graph Coloring for
Routing Congestion Scripting & Automation
Max Flow in Routing TCL/Python for
automation in PD tools
DFT & Sign-Off Checks Perl scripting for log file
Scan Chain Insertion parsing
DRC/LVS Basics Shell scripting for
Antenna Violations automation

TIPS TO CRACK A PD INTERVIEW

1. Master the Basics – Revise PD flow, STA, DRC/LVS rules, and

scripting.
2. Practice Graph Algorithms – MST, Dijkstra, Steiner Tree, Graph
Coloring.
3. Learn Tool-Specific Concepts – Synopsys ICC, Cadence
Innovus, etc.
4. Prepare Your Projects Well – Discuss your PD project in detail
with optimizations.
5. Work on Scripting – Automate PD tasks with TCL, Perl, or
Python.
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