Experiment-5

AIM:- Design the circuit of 4-bit binary incrementer and decrementer.

Theory:-
1. Introduction
A 4-bit binary incrementer and decrementer are digital circuits used to perform addition and
subtraction of one bit on a 4-bit binary number. These circuits are widely used in processors,
counters, and arithmetic logic units (ALUs).
2. 4-bit Binary Incrementer
A binary incrementer increases a given binary number by 1. The circuit is built using half
adders (HA) or full adders (FA), where the least significant bit (LSB) receives an initial
carry of 1.
Working Principle
• Each bit of the binary number is added with a carry.
• The carry propagates through each bit position until it is either absorbed or results in
an overflow.
Logic Circuit
A 4-bit incrementer can be implemented using 4 full adders, where:
• The input binary number is A = A3 A2 A1 A0.
• An initial carry-in C0 = 1 is used to add 1 to the LSB.
• The carry propagates through the full adders as:
Si=Ai⊕CiS_i = A_i \oplus C_i Ci+1=Ai⋅CiC_{i+1} = A_i \cdot C_i
• The final sum S3 S2 S1 S0 represents the incremented value.
Example
For an input A = 0110 (6 in decimal), the output after incrementing will be 0111 (7 in
decimal).
3. 4-bit Binary Decrementer
A binary decrementer decreases a given binary number by 1. It uses full subtractors (FS),
where the LSB gets an initial borrow of 1.
Working Principle
• Each bit of the binary number is subtracted with a borrow.
• The borrow propagates through each bit position until no further borrow is needed.
Logic Circuit
A 4-bit decrementer consists of 4 full subtractors, where:
• The input binary number is A = A3 A2 A1 A0.
• An initial borrow-in B0 = 1 is used to subtract 1 from the LSB.
• The borrow propagates as:
Di=Ai⊕BiD_i = A_i \oplus B_i Bi+1=Ai‾⋅BiB_{i+1} = \overline{A_i} \cdot B_i
• The final difference D3 D2 D1 D0 represents the decremented value.
Example
For an input A = 0110 (6 in decimal), the output after decrementing will be 0101 (5 in
decimal).
4. Applications
• Used in counters for counting operations.
• Essential for address generation in microprocessors.
• Utilized in arithmetic operations inside ALUs.
5. Conclusion
A 4-bit incrementer and decrementer are essential components in digital systems,
performing +1 and -1 operations efficiently. These circuits can be implemented using full
adders and full subtractors, making them simple yet crucial in computational devices.
Would you like a circuit diagram or Verilog implementation as well?

Truth Table:-

A3 A2 A1 A0 F3 F2 F1 F0 P F3 F2 F1 F0 P
0 0 0 0 0 0 0 1 0 1 1 1 1 1
0 0 0 1 0 0 1 0 0 0 0 0 1 0
0 0 1 0 0 0 1 1 0 0 0 0 1 0
0 0 1 1 0 1 0 0 0 0 0 0 0 0
0 1 0 0 0 1 0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 0 0 0 1 0 0 0
0 1 1 0 0 1 1 1 0 0 1 1 0 0
0 1 1 1 1 0 0 0 0 0 1 1 1 0
1 0 0 0 1 0 0 1 0 1 0 0 0 0
1 0 0 1 1 0 1 0 0 1 0 0 1 0
1 0 1 1 1 1 0 0 0 1 0 1 1 0
1 1 0 0 1 1 0 1 0 1 1 0 0 0
1 1 0 1 1 1 1 0 0 1 1 0 1 0
1 1 1 0 1 1 1 1 0 1 1 1 0 0
1 1 1 1 0 0 0 0 1 1 1 1 1 0

Circuit/Program Implementation
 Experiment-6

AIM:- Design 4-bit Arithmetic circuit.

Theory:-
4-Bit Arithmetic Circuit Theory
A 4-bit arithmetic circuit is a digital circuit capable of performing basic arithmetic
operations (such as addition, subtraction, and sometimes multiplication or division) on 4-bit
binary numbers. It typically consists of four interconnected 1-bit full adders and additional
control logic.
Components of a 4-Bit Arithmetic Circuit:
1. Full Adders (FA) – Four full adders are used to perform bit-wise addition with carry
propagation.
2. Multiplexers (MUX) – Used to select different arithmetic operations.
3. Control Inputs – Determines the operation performed by the circuit.
4. Binary Inputs (A & B) – Two 4-bit numbers to be processed.
5. Carry & Overflow Detection – Indicates carry generation or overflow in arithmetic
operations.
Operations Performed:
• Addition (A + B)
• Subtraction (A - B) (using 2’s complement)
• Increment (A + 1) / Decrement (A - 1)
• AND, OR, XOR (Logic operations in some cases)
This circuit is commonly used in ALUs (Arithmetic Logic Units) of microprocessors and
digital computing systems.

Truth Table:-

A (4-bit) B (4-bit) M (Mode) Operation Result (4-bit) Carry/Borrow

0000 0000 0 A+B 0000 0
0001 0001 0 A+B 0010 0
0010 0001 0 A+B 0011 0
0100 0010 0 A+B 0110 0
0111 0001 0 A+B 1000 0
1000 0001 1 A-B 0111 1(Borrow)
1010 0011 1 A-B 0111 0
1111 0001 1 A-B 1110 0
0110 0011 1 A-B 0011 0
Circuit/Program Implementation
 Experiment-7

AIM:- Design one stage of Logic circuit.

Theory:-
Logic Circuit: Combinational Logic Stage
A combinational logic circuit is a stage in digital logic where the output is determined
solely by the current inputs, without any memory or feedback. These circuits are built using
basic logic gates such as AND, OR, NOT, XOR, NAND, and NOR.
Key Characteristics:
1. No Memory: The output depends only on present inputs.
2. Instantaneous Response: The circuit processes inputs and generates outputs without
delay caused by feedback.
3. Boolean Algebra-Based Design: The logic follows Boolean equations to achieve the
desired output.
Examples of Combinational Circuits:
• Adders (Half Adder, Full Adder) – Used in arithmetic operations.
• Multiplexers (MUX) – Select one of many inputs.
• Encoders/Decoders – Convert data between different forms.
Combinational logic circuits are widely used in data processing, arithmetic operations, and
digital communication systems.

Truth Table:-

S1 S0 Output Opration
0 0 A*B AND
0 1 A+B OR
1 0 AB XOR
1 1 A NOT

Circuit/Program Implementation
 Experiment-8

AIM:- Design 4 bit combinational circuit shifter.

Theory:-
4-Bit Combinational Circuit Shifter
A 4-bit combinational circuit shifter is a digital logic circuit that shifts the position of bits
in a 4-bit binary number. It is a combinational circuit, meaning it does not store previous
states and directly determines the output based on the current inputs.
Types of Shifting Operations:
1. Logical Shift:
o Left Shift (LSL): Moves all bits to the left, inserting 0 at the least significant bit
(LSB).
o Right Shift (LSR): Moves all bits to the right, inserting 0 at the most significant
bit (MSB).
2. Arithmetic Shift:
o Left Arithmetic Shift (ASL): Same as logical left shift but used for signed
numbers.
o Right Arithmetic Shift (ASR): Retains the sign bit (MSB) to preserve the
number’s sign.
3. Circular Shift (Rotate):
o Left Rotate (ROL): Shifts bits left, moving the MSB to LSB.
o Right Rotate (ROR): Shifts bits right, moving the LSB to MSB.
Implementation:
A 4-bit shifter can be implemented using multiplexers, logic gates, or barrel shifters. It is
commonly used in processors, arithmetic operations, and data encoding applications.

Truth Table:-

Selector Output
S H0 H1 H2 H3
0 IR A0 A1 A2
1 A1 A2 A3 IL
Circuit/Program Implementation
 Experiment-9
AIM:- Design 4 bit Arithmetic Logic Shift Unit.
Theory:-
4-Bit Arithmetic Logic Shift Unit (ALSU)
A 4-bit Arithmetic Logic Shift Unit (ALSU) is a digital circuit that performs arithmetic,
logic, and shift operations on 4-bit binary data. It is a key component of processors and
ALUs, enabling fundamental computations required for digital processing.
Components & Operations
1. Arithmetic Operations
o Addition
o Subtraction (using two’s complement)
2. Logic Operations
o AND
o OR
o XOR
o NOT
3. Shift Operations
o Logical Shift Left (LSL) – shifts bits left, inserting 0 at LSB.
o Logical Shift Right (LSR) – shifts bits right, inserting 0 at MSB.
o Arithmetic Shift Right (ASR) – shifts bits right while preserving the sign bit
(MSB).
Working Principle
• The ALSU takes two 4-bit inputs and a control signal to determine the operation.
• A multiplexer selects between arithmetic, logic, and shift functions based on an
operation code (opcode).
• The output is a 4-bit result along with status flags (e.g., carry, zero, overflow).
This unit is fundamental in microprocessors and digital systems, enabling efficient binary
computations.

Truth Table:-
Operation Select
Cin Operation Function
S3 S2 S1 S0
0 0 0 0 0 F=A Transfer A
0 0 0 0 1 F=A+1 Increment 1
0 0 0 1 0 F=A+B Addition
0 0 0 1 1 F=A+B+1 Add with Carry
0 0 1 0 0 F=A+B’ Subtract with Borrow
0 0 1 0 1 F=A+B’+1 Subtraction
0 0 1 1 0 F=A-1 Decrement A
0 0 1 1 1 F=A Transfer A
0 1 0 0 X F=A^B And
0 1 0 1 X F=AvB Or
0 1 1 0 X F=A XOR B XOR
0 1 1 1 X F=A’ Complement A
1 0 X X X F= shr A Shift right A into F
1 1 X X X F= shl A Shift left A into F
Circuit/Program Implementation
 Experiment-10

AIM:- Develop Assembly language program to find out the 2’s complement of the
number.

ORG 0000H ; Set starting address of the program

LDA 2000H ; Load the number from memory (2000H) into Accumulator

CMA ; Take 1’s complement (invert all bits)

INC ; Increment A by 1 (Add 1 to get 2’s complement)

STA 3000H ; Store the result at memory location 3000H

HLT ; Halt the program

END ; End of the program

 Experiment-11

AIM:- Develop Assembly language program to find out the subtraction of two
numbers using indirect mode.
.

ORG 0000H ; Set the starting address of the program

LDA 2001H ; Load the subtrahend from memory location 2001H into the
Accumulator

CMA ; Take 1’s complement (invert all bits)

INC ; Increment AC

MOV B, AC ; Store the 2's complement of the subtrahend in register B

LDA 2000H ; Load the minuend from memory location 2000H into the
Accumulator

ADD B ; Add the 2's complement of the subtrahend (A = A + B)

STA 3000H ; Store the result at memory location 3000H

HLT ; Halt the program

 Experiment-12

AIM:- Develop Assembly language program for the following pseudo code
SUM=0
SUM=SUM+A+B
DIF=DIF-C
SUM=SUM+DIF

ORG 100 ; Main program

CLA ; Clear Accumulator
STA SUM ; SUM = 0
LDA A ; Load first operand
ADD SUM ; Accumulator  SUM + A
STA SUM ; Store result in SUM
LDA B ; Load second operand
ADD SUM ; Accumulator  SUM + B
STA SUM ; Store result in SUM
LDA DIF ; load the value in DIF
SUB C ; Accumulator  DIF – C
STA DIF ; Store result in DIF
ADD SUM ; Accumulator  SUM + DIF
STA SUM ; Store the result, i.e SUM = SUM + DIF
SUM, -
A, -
B, -
C, -
DIF, -
END ; End of symbolic program
 Experiment-13

AIM:- Develop Assembly language program to add 100 numbers.

ORG 100 ;Origin of program is HEX 100

LDA ADS ;Load first address of operands

STA PTR ;Store in pointer

LDA NBR ;Load minus 100

STA CTR ;Store in counter

CLA ;Clear accumulator

LOP, ADD PTR I ;Add an operand to AC

ISZ PTR ;Increment pointer

ISZ CTR ;Increment counter

BUN LOP ; Repeat loop again

STA SUM ;Store SUM

HLT ;Halt

ADS, HEX 150 ; First address of operands

PTR, HEX 0 ; !This location reserved for a pointer

NBR, DEC-100 ; Constant to initialized counter

CTR, HEX 0 ; this location reserved for a counter

SUM, HEX 0 ; Sum is stored here

ORG 150 ; Origin of operands is HEX 150

DEC 75 ; First operand

*
DEC 23 ;Last operand

END ; End of symbolic program

 Experiment-14

AIM:- Develop Assembly language program to logically OR two numbers.

ORG 100 ; Main program

LDA A ; Load first operand A

CMA ; Complement to get A’

STA TR ; Store in a temporary register

LDA B ; Load second operand B

CMA ; Complement to get B’

AND TR ; AND with a’ to get A’ /\ B’

CMA ; Complement again to get A \/ B

STA RES ; Store result in RES

HLT

A, -

B, -

RES, -

END
 Experiment-15

AIM:- Develop Assembly language program to multiply two numbers by

repeated addition method. (5*4=5+5+5+5)

ORG 100 ; Origin of program is HEX 100

LOP, LDA X ; Load multiplicand

ADD P ; Add to partial product

STA P ; Store partial product

ISZ CTR ; Increment counter

BUN LOP ; If counter is not zero, repeat

HLT ; If counter is zero; stop

CTR, DEC -4 ; This location serves as a counter (multiplier)

X, HEX 5 ; Multiplicand is stored here

P, HEX 0 ; Product is formed here

END
 Experiment-16

AIM:- Develop Assembly language program to multiply two positive numbers.

ORG 100 ; Set the starting address of the program to 100

LOP, CLE ; Clear the E (likely an accumulator or flag register)

LDA Y ; Load the value from memory location Y into the accumulator

CIR ; Circular shift right (moves the least significant bit to E and shifts
all bits to the right)

STA Y ; Store the shifted value back into memory location Y

SZE ; Skip if E is zero (check if the shifted bit was zero)

BUN ONE ; Branch to label ONE if E is not zero

BUN ZRO ; Branch to label ZRO if E is zero

ONE, LDA X ; Load the value from memory location X into the accumulator

ADD P ; Add the value from memory location P (partial product) to the
Accumulator

STA P ; Store the result back into memory location P

CLE ; Clear the E register

ZRO, LDA X ; Load the value from memory location X into the accumulator

CIL ; Circular shift left (moves E to the most significant bit and shifts
All bits to the left)

STA X ; Store the shifted value back into memory location X

ISZ CTR ; Increment and skip if zero (increments the counter at memory
location CTR and skips the next instruction if it becomes zero)

BUN LOP ; Branch back to label LOP if the counter is not zero

HLT ; Halt the program

CTR, DEC -8 ; Define CTR as a memory location initialized to -8 (counter)

X, HEX 000F ; Define X as a memory location initialized to 000F

(multiplicand)

Y, HEX 000B ; Define Y as a memory location initialized to 000B (multiplier)

P, HEX 0 ; Define P as a memory location initialized to 0 (product)

END ; End of the program