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IRJET Sobel Edge Detection On Zynq Based

This paper discusses the implementation of the Sobel edge detection algorithm on a Zynq-based architecture using Vivado for real-time video processing. It details the use of the Zybo board to create a video streaming architecture that detects edges in grayscale images and outputs the processed video. The findings demonstrate the efficiency and low resource utilization of the system, highlighting the advantages of high-level synthesis in hardware design.

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19 views3 pages

IRJET Sobel Edge Detection On Zynq Based

This paper discusses the implementation of the Sobel edge detection algorithm on a Zynq-based architecture using Vivado for real-time video processing. It details the use of the Zybo board to create a video streaming architecture that detects edges in grayscale images and outputs the processed video. The findings demonstrate the efficiency and low resource utilization of the system, highlighting the advantages of high-level synthesis in hardware design.

Uploaded by

Noah Okitoi
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395-0056

Volume: 06 Issue: 09 | Sep 2019 www.irjet.net p-ISSN: 2395-0072

Sobel Edge Detection on Zynq based Architecture with Vivado


Neol Solanki1, Neel tailor2
1Student-B.Tech, Electronics Department, Birla Vishvakarma Mahavidhyalaya, Anand, Gujarat-India
2Student-B.Tech, Electronics Department, Birla Vishvakarma Mahavidhyalaya, Anand, Gujarat-India
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Abstract - Edge detection is tool used in many image then,
processing application for withdrawing information from
image. Sobel edge detection is gradient based edge selection
method to find edge pixels in image. This paper proposes an Gx=( )*A , Gy=( )*A
implementation of sobel edge detection algorithm to find
edge pixels in gray scale image. We present a video
streaming architecture and IP implementation using high where A is the source image. The edge is measured by
level synthesis. A video with 720p resolution streamed from amplitude and direction given by
the HDMI source and edge detected video captured in VGA
monitor. For implementation zybo board (based on zynq
7000) is used, which has provided adequate peripherals for
G=√ ,  
implementation.
Where G represents the magnitude and represents the
Key Words: Sobel edge detection, Real time video direction.
processing, Video processing using Zybo, Video processing
using HLS ,Video processing using zynq based 1.2 HLS and IP Integrator Motivation
architecture, Video processing with FPGA.
HLS can do synthesis of digital system directly from
1. INTRODUCTION high level languages like C, C++ and also generate
The objective of this project is to detect the edge of the VHDL/Verilog from C/C++ source. The most arresting
feature of HLS is that hardware implementation and
image using FPGA. Edge detection is algorithm used to
designed functionality are isolated. The hardware is not
detect edge by finding the boundaries of objects within
implicitly fixed by the C-based description providing more
images. It works by detecting discontinues in the
flexibility. HLS extracts control and dataflow from source
brightness. Edge detection is used in object detection,
code and implementations are carried out based on the
machine vision, computer vision and image segmentation.
user applied directives. HLS provides more than one
Typical algorithms include Sobel, Canny, Prewitt, Roberts.
implementation for the same source and enables user to
To implement this project we have used the zybo explore the design and find the most optimal design.
(ZYnq BOard), which is the member of zynq-7000 family, Vivado accelerates the development of highly integrated,
the Z-7010. The Z-7010 has dual-core ARM cortex-A9 complex designs by providing the intelligent IP integration
processor with Xilinx 7-series field programmable gate with features like auto-correction of key IPs, one click IP
array logic based on SOC (System on chip). The opulent subsystem generation, real time DRCs, interface change
set of multimedia and connectivity peripherals on Zybo propagation with powerful debug capability. It supports
can be conductive to individual for creating whole system. all design domains, hierarchy and advanced design
We have created IP for Sobel edge detection with the help services.
of Vivado HLS and then implemented video pipelining
architecture on Vivado IP integrator.

1.1 Sobel Edge detection


Sobel edge detection was first proposed by the Irwin
sobel and Gary Feldman in 1968 at SAIL. Out of two types
of edge detection gradient and laplacian, Sobel is based on
former one. Gradient of intensity of each pixel is calculated
in Sobel. It uses 3x3 kernel one for vertical other for
horizontal for change in respective direction. Derivatives
are calculated by convolution of kernel with source image. Fig -1: HLS Design flow
If Gx and Gy are images containing horizontal and vertical
derivatives,

© 2019, IRJET | Impact Factor value: 7.34 | ISO 9001:2008 Certified Journal | Page 1068
International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395-0056

Volume: 06 Issue: 09 | Sep 2019 www.irjet.net p-ISSN: 2395-0072

2. IP Creation using HLS DVI to RGB converts the input from the HDMI source into
the RGB format sampled from 1280x720 resolution video.
We have used processing function that accepts an AXI- After that Video into AXI-4 stream converts the RGB
stream RGB video input and outputs the similarity format into AXI mapping, this is fed to the edge detection
formatted processed video data. The project requirements ip which detects the edge of the video into AXI form. Video
are 1280x720 resolution and a stable video feed. Sobel timing controller ensures the timing constrains between
edge detection algorithm takes RGB matrix and then its all the IPs. Edge detection ip propagates the edge detected
processes its value and generates the sobel edge detected image into AXI-4 to video stream, which further converts
output according to that image. First of all the data is in the the AXI mapping into video and finally fed to VGA source
AXI format which need to be converted into the matrix capable of supporting same resolution.
format and function used for the same is: AXIvideo2mat
(stream_in, img0). Function used for converting matrix into Final board resources utilization is given by:
gray scale is CvtColor<HLS_RGB2GRAY> (img0, img1).

After the conversion in gray scale we can do the sobel


edge detection. There is the function in HLS called sobel
which we have used. Sobel<1, 0, 3> (img1, img2).This 1
signifies the x order and y order is 0 so it first calculates the
x image derivative and 3 is the kernel size, which is 3x3
kernel.

Then to convert gray scale image into RGB format.


CvtColor<HLS GRAY2RGB> (img2, img3).After converting in
the RGB format we have to convert the matrix format back
to its original form i.e. in AXI format, using function
Mat2AXIvideo (img3, stream_out).
Fig -4: Board resources utilization
The utilization estimate for same in HLS in given by:
4. Test results

Fig -5
Fig -2: Resource utilization (HLS)

3. Implementing video pipelining in IPI

Fig -3: IPI block diagram

Fig -6

© 2019, IRJET | Impact Factor value: 7.34 | ISO 9001:2008 Certified Journal | Page 1069
International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395-0056

Volume: 06 Issue: 09 | Sep 2019 www.irjet.net p-ISSN: 2395-0072

Figure 5 and 6 shows the edge detected live video stream


in VGA monitor (left) from the HDMI source (right).

5. CONCLUSION
The paper has illustrated how efficiently Zybo board
is capable of implementing the entire video processing
system singularly with low power consumption, smaller
physical size and with minimal resources utilization
evidenced from the figure 4. Implication of implementing
entire system singularly is notion of SoC. Individual can
implement any complex design entirely using Zynq based
architecture. In our example we used HLS and saw how
good alternative it is to HDL language and can be time
saving. Vivado provides tightly integration of all IPs and
peripherals and also reusability. The video pipelining
architecture designed in our example can be used for any
video application is future.

6. REFERENCES
1. The zynq e-Book

2. Michrozed chronicles by Adam Taylor

3. Xilinx, Accelerating OpenCV Applications with Zynq-


7000 All Programmable SoC using Vivado HLS Video
Libraries, Stephen Neuendorffer, Thomas Li, and Devin
Wang

4. DIGILENT Zybo video workshop

© 2019, IRJET | Impact Factor value: 7.34 | ISO 9001:2008 Certified Journal | Page 1070

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