UNIT I MULTILEVEL TOPOLOGIES 6

Introduction – Generalized Topology with a Common DC bus

– Converters derived from the generalized topology –
symmetric topology without a common DC link –
Asymmetric topology.

Introduction:

Power electronic device which converts dc power into ac power at

desired output voltage and frequency is known as inverter. The inverter
producing an output voltage or current with two different levels of is
known as 2 level inverters. [+ & -]

This two-level conventional inverter operates at high

switching frequency, with high switching losses and rating
constraints for high power and voltage applications. It also faces
harmonic distortion, EMI and high stress. High level of total
harmonic distortion is another problem. Because of these problems, it is
difficult to interface power electronic switches directly to high
and medium voltage grid. [A two-level Inverter creates two different
voltages for the load i.e. suppose we are providing Vdc as an input to a
two level inverter then it will provide + Vdc/2 and – Vdc/2 on output. In
order to build an AC voltage, these two newly generated voltages are
usually switched]
Two level Inverter- Single phase

Two level Inverter waveform

Two level Inverter three phase

 Here comes the need for a different topology of multi level inverter.
The multilevel inverter topology concept has been introduced in the early
1975 with three level converters. It is possible to increase the power rating
with high number of voltage levels in the inverter. This reduces the device
rating in the inverter. A multilevel inverter generates a smooth sinusoidal
waveform from several d c voltage levels as its input.
Multilevel Topologies

Introduction

Voltage source multilevel converters (VSMCs) have been developed for

▪ high-power applications.

▪ their capability to work at medium-voltage levels

without power transformers.

▪ the blocking voltage of the power devices has limited the

supply voltage of transformer less power converters. But
this limit can be overcome if the number of voltage levels
of the converter is increased.

▪ Moreover, the increment of voltage levels contributes to

build a softer AC voltage with the consequent
reduction in harmonic distortion.

▪ Also, the voltage variation rate (dv/dt) is reduced,

diminishing the electromagnetic interference (EMI)
problems and other stresses on the power switches.

Multilevel Inverters are

Diode-clamped (DCMC)

Flying capacitor (FCMC)

Cascade H-bridge (CCMC)

The different combinations of ON and OFF states of

the power switches of the VSMC determine the “switching states” of the
converter. Different voltage levels may be obtained by the switching
states.

Depending on the topology, a given voltage level may be built with

different switching states. These states are known as the redundant
states of the converter.

In some topologies, like the DCMC, there exist some states for which
the voltage level is not determined by the converter, but depends on the
sign of the load current These states are defined as forbidden states and
should be avoided.

one voltage level for each state combination of power switches is

called as an ideal multilevel topology

Generalized Topology with a Common DC Bus:

one leg of a symmetric n-level VSMC with a common

DC bus is shown in Figure . This is built with a specific array of power
switching devices and capacitor.
It has a cellular structure in which the number of voltage levels
is increased by adding basic cells.

An n-level converter has n – 1 stages.

For example

2 level inverter: 1 stage

3 level Inverter : 2 stages

5 level inverter: 4 stages

7 level inverter : 6 stages

Two level inverter

Three level Inverters [DCML]
Five level Inverter [DCML]
Basic Cell :

The basic cell is the functional unit of

the generalized topology, and it is built with two complementary power
switches and one capacitor. power switches (Sj, S j), which can carry
bipolar current, together with a power source (battery, solar panel, etc.)
or a power storage element (capacitor).
The complementary power switches are controlled with a switching
function sj,

which has two possible states,

Converters derived from the generalized topology

Generalized topology (basic cell) permits to increase the number of

voltage levels by simply adding new basic cells.

For example, to increase the voltage levels from n to n + 1 it is necessary

to add a new stage with n cells. It is an easy way to increase the voltage
levels, but it requires a lot of devices. Then, the implementation is not
that much easy. (Complexity level increases)
Figure: Converter states of a three-level generalized topology
(a) state 00, (b) state 01, (c) state 11, and (d) state 10

The number of possible states increases more than the voltage levels, also
increasing the number of redundant states. So, the generalized topology
is useful to understand the operation of multilevel topologies.
Symmetric Topologies without a Common DC Link

One leg of an n-level multilevel topology with independent and isolated

power sources without common DC link is shown in figure . Each stage
has two basic cells connected in parallel and sharing a common DC source
or capacitor. The different stages are connected in series to obtain an n-
level voltage at the output. This topology is known as n-level cascaded cell
multilevel converter (CCMC) .

Figure N-level topologies with independent voltage sources.

 The voltage of each stage is calculated as the voltage
difference of each basic cell, as indicated . Then, each stage is controlled
with two independent switching functions and the stage voltage (vj) is
calculated as

Where s(2j–1) and s(2j) are the switching functions and VC is the
DC voltage source of the jth stage. Each stage offers three voltage levels, 0
and ±VC; a series connection of two stages gives five levels, 0, ±VC, and
±2VC, since the 0 levels of each stage do not sum a different level.
Continuing with this reasoning, (n – 1)/2 stages are required to obtain
an n-level leg voltage vio. Assuming that all stages have the same value of
DC voltage source VC, then vio is the sum of all the contributions of the
(n−1)/2 stages, resulting in

In this topology the leg voltage is the same as the load voltage

Asymmetric Topology

Due to a greater number of components, it is more complexity of

connections in symmetry topologies also cost rise. So, it is important to
look for a different alternative when more than four or five voltage levels
are required.

Hybrid Asymmetric Topologies

A topology with a cascade of different stages connected in series but with

different values of DC voltages known as the hybrid asymmetric
multilevel converter (HMC) shown in Figure . Each stage may be built
with a different topology, which in turn generates a different number of
voltage levels (n1,n2,...,nP).This fact, together with the different values of
the DC sources, generates asymmetric topologies in which there are no
equal stages The term hybrid is related to the modulation of each stage.
The asymmetry of the DC voltage sources also determines the power
handle by each stage. The stages with higher DC voltage manage higher
power than those with a lower DC voltage . Then it is possible to
implement the power switches of the different stages with different
devices.
UNIT II CASCADED H-BRIDGE MULTILEVEL INVERTERS 6

Introduction -H-Bridge Inverter, Bipolar Pulse Width Modulation, Unipolar Pulse Width
Modulation.
Multilevel Inverter Topologies, CHB Inverter with Equal DC Voltage, H-Bridges with
Unequal DC Voltages – PWM, Carrier-Based PWM Schemes, Phase-Shifted Multicarrier
Modulation, Level-Shifted Multicarrier Modulation, Comparison Between Phase- and
Level-Shifted PWM Schemes-Staircase Modulation

2.0.Introduction :

The symmetric cascaded H-bridge multilevel inverter (SCMI) and asymmetric cascaded H-
bridge multilevel inverter (ACMI) topologies are very similar in regards to the power topology.
They present the same amount of transistor and the same amount of dc sources. The only
difference between these topologies is the value of the dc sources. While the SCMI uses dc
sources with equal value in each H-bridge, the ACMI uses dc sources with different values in
each H-bridge. Each H-bridge used in SCMI or ACMI is called a module.

2.1.H Bridge Inverter

Full bridge inverter is a topology of H-bridge inverter used for converting DC power into AC
power. The circuit of a full bridge inverter consists of 4 diodes and 4 controlled switches as
shown below

Fig.2.1.Full Bridge Inverter

Positive input voltage will appear across the load by the operation of T1 and T2 for a half time
period. The polarity of voltage across load will be changed for the other half period by
operating T3 and T4.
 Fig.2.2.Full Bridge Inverter Gate Pulses

2.1.1.Operation of Full Bridge with R Load

The working operation of Full bridge for pure resistive load is simplest as compared to all
loads. As there is not any storage component in the load so, only control switches operate while
feedback diodes do not operate through the operation of the inverter. Only two modes are
enough for understanding the working operation of a full bridge inverter for R load.
Mode 1
Consider all the switches are initially off. By triggering T1 and T2, the input DC voltage (+Vdc)
will appear across the load. The current flow in clockwise direction from source to the series
connected load. The output current across the load will be
Io=Vdc/R
Where RL is the load resistance, While the output voltage across the load will be
Vo= Vdc
Mode 2
Thyristors T3 and T4 are triggered immediately after completely commutating T1 and T2. The
polarity of voltage immediately reverses after switching complementary switches T1 and
T2 with T3 and T4. The DC input voltage across the load appear with the negative voltage
which
Vo= -Vdc
While the output appearing current is
Io = – Vdc/RL
The current in anti-lock wise direction flows from source to load through T3 and T4 as shown
in the figure
These modes of operations are discussed by taking two assumptions.
 • All the switches are initially closed.
• There is initially zero energy stored in the load.
Mode 1 (t1<t<t2)
In this mode thyristor T1 and T2 will conduct from time interval t1 to t2. Thyristors T1 and
T2 will conduct current from source to load as soon as these thyristors are triggered. After
triggering the Whole input voltage will appear across the load with positive polarity while
current will gradually increase till it achieves maximum peak. The current does not rise to the
peak immediately as it rises in pure resistive load because the inductor resists the change.
The inductor will store energy in this mode. The reason behind it is that the polarity of voltage
and current is the same.
Mode 2 (t2<t<t3)
In this mode, feedback diodes D3 and D4 will conduct the stored energy in the load back to
the source. The feedback diodes will immediately start conduction by commutating thyristors
T1 and T2. These diodes also reduce the di/dt spike.
Negative voltage will appear across the load as soon as previously triggered thyristors are
commutated. The polarity of current remains the same, but it gradually decreases till the current
flowing through load becomes zero. As the current flows due to the stored energy therefore,
the current stops flowing when stored energy approaches to zero.
Mode 3 (t3<t<t4)
Thyristors T3 and T4 are triggered immediately after the complete discharge of inductive load.
By triggering T3 and T4, the current starts to flow in the opposite. The current gradually
increases till it achieves the negative peak.
During this interval, both current and voltage are negative. Therefore, inductive load charge
once again.
Mode 4 (t0<t<t1)
The feedback diodes D1 and D2 will conduct in this mode. These diodes will start conducting
immediately after commutating the previously triggered T3 and T4. The voltage polarity.
 Fig.2.3.Full Bridge with R & RL Load

Fig.2.4.Full Bridge Inverter wave forms for for all loads

2.2. Bipolar Pulse Width Modulation, Unipolar Pulse Width Modulation.

If we assume all devices are ideal, ie no losses, then the table shows the condition of each case

Table :Difference of Ideal and non- ideal switches .Switches may be SCR, Diode or IGBT.

And the switches also be unipolar or bipolar directions .

Fig.2.5.Unipolar Switch

2.2.1.Main Features a BPS Should Have

• A bidirectional switch device must be highly adaptable to enable easy and quick
power conduction from both sides, that is across A to B and B to A.
• When used in DC application, a BPS must exhibit minimum on state resistance
(Ron) for improved voltage regulation of the load.
• A BPS system must be equipped with proper protection circuitry to withstand
sudden in rush current during a polarity change, or at relatively high ambient
temperature conditions
2.2.2. Bipolar PWM

Fig.2.6.H Bridge Inverter

During first conduction period S1 and S2 will be connecting .and for the second conduction
period S3 and S4 are conducting (like pair of switches S1,S2 & S3,S4-diagonal switches are
connecting)

Stage 1: S1 and S2 are conducting the output voltage is V0=Vdc

Stage 2: S3 and S4 are conducting the output voltage is V0= - Vdc

PWM is a Comparative response of the a carrier and reference wave forms, Where the carrier
is triangular waveform and the reference wave form is DC .

switching frequency fs should be high value around 10 to 100kHZ.Period is Ts as shown in

wave form.
Output voltage with DC reference

𝑽𝑑𝑐∗𝒅 𝑻𝑠 +(−𝑽𝑑𝑐)(1−𝒅) 𝑻𝑠
̅̅̅̅ =
Average output voltage = Vo = 𝑉𝑜
𝑻𝑠

̅̅̅̅ = 𝑽𝑑𝑐 (2𝒅 − 1)

= 𝑉𝑜

̅̅̅̅̅
𝑽𝑜 1
d= +
2𝑽𝑑𝑐 2

For the sinusoidal reference

 ̅̅̅̅ = 𝑽𝑜
𝑉𝑜 ̂ 𝐬𝐢𝐧 𝝎𝟏 𝒕

̂
𝑽𝑜
Modulation Index = 𝒎𝑎
𝑽𝑑𝑐

Maximum modulation INDEX IS 1 ,Vo is Vdc

Idc component is DC ripple component and 2 nd harmonics also involved in this type of bipolar
PWM and is a disadvantage because the second harmonic is a much in lower frequency
harmonic, let us say suppose if you have 50Hz output and in the capacitor current there is
100Hz , Accordingly need to select the capacitor large enough to withstand the 100Hz
component in the dc bus.

For minimum DC bus voltage use maximum modulation index .

2..2.3.Unipolar PWM

Leg A and leg B has different reference waveforms,

All four switching combinations are used.

In this S1 and S3 are turned ON for the first stage and S2 and S4 are turned ON for the second
stage (not like bipolar ie, diagonal switched are turned ON)
S1 and S3 are conducting –
2.3.Cascaded h-bridge multilevel inverters :

The structure of the cascaded H-bridge (CHB) may consist of two or more H-bridge inverters.
The CHB inverter can be supplied by separated DC sources or a single DC source. The
structure of the CHB inverter with separated DC-sources is shown in Figure 1. This type of
inverter consists of two cells H bridge inverter hence employs 8 power electronic switches.
The modulation technique that applies to each cell of inverter may be the same or different. It
varies from fundamental switching frequency PWM, carrier based PWM or combination of the
two different PWM methods (known as mixed / hybrid PWM method).

2.3.1.Fundamental Switching Frequency (FSF)PWM :Fundamental Switching Frequency

PWM method controls the power electronic switches at fundamental frequency. The gating
signals are simply generated by examining the sinusoidal voltage reference (Vref). When Vref
has a positive (negative) value the upper (lower) switches are conducted (ON) otherwise the
switches are dis-conducted (OFF).The operation of the FSF PWM method (for the upper
switches) is governed using a simple logic as described in (1) and Figure 2.
Sx1 is the switching functions of the upper switches. The notation of switches refers to Figure
1. Since the switches operate in relatively slow switching, the output voltage contains high
value of fundamental component as well as the low-order harmonics.

2.3.2.Phase Shifted PWM (PS PWM) :Phase Shifted PWM applies several triangular carriers
that have the same frequency and same peak peak amplitude, but there is a phase shift between
any two adjacent carrier waves. For m voltage levels, (m-1) carrier signals are required and
they are phase shifted with an angle of θ = (360°/m-1). The gate signals are generated with
proper comparison of carriers and a modulating signal. The comparison of voltage reference
signal and triangular carriers and the respective gating signals for a five-level CHB inverter are
shown in Figure 3 and 4.

2.3.3.Level shifted PWM (LS PWM) :Level Shifted PWM also uses some carrier signals, but
they are arranged in different levels among the carriers. According to the disposition of carrier
waves, the LS PWM can be divided into three main types i.e (i) Phase disposition (PD), when
all the carrier signals are in phase, (ii) Phase opposition disposition (POD), when all the carrier
signals above zero reference are in phase but in opposition with those are below zero reference.
(iii) Alternate phase opposition disposition (APOD): when the modulating signal of each phase
is in opposition from each other. The gating signals are generated by comparing the carrier
waves and the modulating signal as shown in Figure 5 and 6.
2.3.4.Mixed Switching Frequency (MSF) PWM: Mixed multilevel inverters may need
different PWM strategies for the different stages composing them. For instance, a CHB inverter
composed by one GTOs stage and one IGBTs stage may require two different switching
frequencies, one for high-speed and one for low-speed devices. In this way, the output
waveform, being the sum of the single stage outputs, presents the two frequencies in its
harmonic content. The principle of a mixed switching frequency PWM of CHB inverter is
shown in Figure 7.

The modulation signal of the MSF PWM is obtained by subtracting the sinusoidal reference
signal and the output of the inverter that operates in FSF PWM. The gating signals for the
inverter switches are generated by comparing the modulation signal and the triangular carriers.
Figure 8 shows the modulation signal (bold line) along with the reference signal (dashed dot
line) and output voltage of inverter operates in the FSF PWM (dashed line)

2.3.5.Staircase modulation The staircase modulation is sometimes referred as nearest level

modulation.

A new reconfiguration module for asymmetrical multilevel inverters in which capacitors are
used as the dc links to create the levels for staircase waveforms. Fig. presents a single-phase
k-level ACMI with n modules. Each module has an isolated dc source. The module dc-link

Fig. Single-phase k-level asymmetrical cascaded multilevel inverter with n modules

Fig. Fundamental frequency diagram of the ACMI

voltages are commonly scaled in {1:2:6:…} or {1:3:9,…} ratios. Some applications have been
reported in the literature covering different ratios . The ACMI terminal voltage is called vta
while the module terminal voltages are called vta1, vta2, and vtan, respectively

The number of levels (kr) in the terminal voltage (vta) for the {1:2:6:…} ratio is given by

The number of levels in the terminal voltage (vta) for the {1:3:9:··· } ratio is given by

The terminal voltage is composed of the algebraic sum of each module terminal voltage. Fig.
3 presents the fundamental frequency diagram of the ACMI.

2.4.Features of Cascaded H-Bridge Multilevel Inverter

2.4.1.H-Bridge Cell

• Each H-Bridge Cell consists of four switches and four diodes as shown in the
picture.
• Like every H-Bridge, different combinations of switch positions determine
different voltages such as V+, V- and 0.
• Two switching combinations are present for 0 volts.
• S1 and S2 are connected to positive voltage and S3 and S4 are connected to negative
voltage.
2.4.1.Single Phase Multilevel Inverter

• The number of output levels from a multilevel inverter depends upon the number
of separate DC sources attached to it.
• The relation is m=2s+1
• All the outputs from H-Bridges should be quarter symmetric to generate a sin like
wave.
• No even harmonics are present.
2.4.2.Three-Phase Multilevel Inverter

• Three-phase Multilevel Inverter is simply like three single phase inverters

connected in wye configuration. Three H-Bridges are connected together.
• Delta configuration can also be used.
• Maximum number of line voltages is 2m+1 where m=no. of phase voltages.
• Triple harmonics are eliminated themselves.
2.4.3.Real Time Switching

In ideal cases the switching time is considered zero and the switching devices turn on and off
as soon as you command. But in real time application, switching time is an important
phenomenon. To avoid this Blanking time is introduced. The switch turns off just immediately,
but the other switch turns on after a certain delay.

2.4.4.Separate DC Source

One of the major issues with Cascaded H-Bridge Multilevel Inverters is that we need separate
DC sources with each leg. Well it might look that separate DC source will create a mess or
increase the components, but it is fairly necessary. Because same DC sources can give multiple
configurations that result in short circuit.

However this issue has also been resolved. Now lesser number of DC sources can be used and
SDC topology has also been proposed.

2.5.Advantages of Cascaded H-Bridge Multilevel Inverter

As the name suggests this multilevel inverter uses full H-Bridges connected is series to produce
inverted AC from separate DC sources. These DC sources can be any natural resource such as
sunlight or wind energy or anything.

• It does not need any capacitors or diodes for clamping.

• The wave is quite sinusoidal in nature even if you don’t filter it.
This was all about cascaded H-Bridge multi -level inverters. Due to their advantages they are
often used now-a-days. More of the inverters types are still there which are extensively used
and will be discussed in the upcoming tutorials. So keep visiting to know more about them and
their uses and advantages as well.
.

UNIT III DIODE CLAMPED MULTILEVEL CONVERTER 6

Introduction – Converter structure and Functional Description – Modulation of

Multilevel converters – Voltage balance Control – Effectiveness Boundary of voltage
balancing in DCMC converters –Performance results.

3.0. Introduction: Diode-Clamped Topology:

It is possible to eliminate C2 without altering the voltage levels at the output. Figure 3.1 shows the
converter without C2, which is called active neutral point clamping (ANPC) .A further reduction in
semiconductor devices may be obtained by eliminating the transistors from the switches S12 and S11
and leaving only the diodes (De and De ), as shown in Figure 3.1. In this case the voltages synthesized
by states 00 and 11 are the same as before. But the voltage generated in states 01 and 10 depends on
the sign of the current in node i.

Fig.3.1. ANPC topology

3.1. Converter structure and Functional Description
The structure of the diode-clamped multilevel converter was derived from the generalized topology.
By restructuring the original switching functions, it was possible to eliminate redundant capacitors and
also active power switches to finally come together with a common DC bus topology. Moreover, a
parts-count improvement could also be made towards a more compact and practical implementation
by considering different blocking voltages for the clamping diodes

Fig. 3.2. Basic configuration of Diode Clamped MLI

As a counterpart, this configuration has no redundant states for the synthesis of the leg voltages,
which is the result of the high number of forbidden states. Besides these proper- ties, an important
problem that affects the diode-clamped multilevel converter (DCMC) is the DC bus voltage balance,
which arises in the general case when a multi tapped DC voltage source is not available. In this sense,
the high number of forbidden states and the nonexistence of redundant states for leg voltage synthesis
prevent their use to address voltage balance. In addition, the dynamical switching behaviour of the
diode-clamped multilevel converter also imposes particular constraints in order to ensure safe
operation of the power devices.

3.2.1.Voltage Clamping

The practical implementation of the DCMC derived from the generalized topology, is depicted
in Figure 3.3. It shows one leg of the five-level converter, which is composed of the active switching
 Fig.3.3. Leg of the five-level DCMC, switching logic, and voltage clamping of

internal nodes

devices with their integrated freewheeling diodes, the clamping diodes, and the DC bus with its
intermediate nodes. The nodes between the active switches are labeled with the letters A to F in the
same figure 3.2. The capability of the DCMC topology to increase the output voltage beyond the
maximum blocking voltage of the individual switching devices lies on the voltage-limiting action that
the clamping diodes have on the internal nodes of the leg. Figure 3.1 shows this for clamping diodes
De2 and De3 and the corresponding nodes E and F. Considering that the switches S3 and S4 are in the
OFF state, it can be seen that the blocking voltage VCE4 cannot exceed the value VC since the anode
of De3 should have lower voltage than its cathode (voltage loop 1 in the figure). In this case the voltage
of node F and also VCE4 are directly clamped to the capacitor voltage, VC.In the same way, the voltage
of node E is clamped to 2VC due to the diode De2 (voltage loop 2). However, De2 does not ensure
VCE3 = VC unless VCE4 has been previously clamped to VC. This is true because voltage loop 2
states that 2VC – VCE3 – VCE4 = 0. This dependence of maximum blocking voltage over S3 is called
indirect clamping and applies to nodes B, C, D,and E, and generally to all inner active devices of an n-
level DCMC.
3.1.2.Switching Logic

Fig.3.3. shows the switching functions of a five-level DCMC .The forbidden and valid states are
respectively denoted as solid and hollow circles on each corner of the cubes, and the corresponding
leg voltages are specified. As it was mentioned, a great number of forbidden states are observed (11 in
total), while the allowed states are reduced to only five, which coincides with the number of converter
levels (this is general for the DCMC topology). Table 3.1 summarizes the leg output voltages as a
function of the gating signals where it can be seen that no redundancy exists, provided

that each output voltage level is synthesized by only one gating pattern. The black pin denotes that the
device is ON, while the gray pin indicates that the device is OFF.

Fig.3.4.Switching states

Table 3.1. Gating signal and corresponding leg voltages

3.2. Modulation of Multilevel Converter:

Switching converters needs continuous reference signal from a digital pulse train whose
average value coincides with the reference. It is achieved by a modulation of switching
converters. Several modulation techniques are available .These various techniques produce
different performances by the terms of losses, harmonic distortion, implementation
complexity, and flexibility for variable speed operation are achieved from various techniques
. Among the high-frequency switching strategies, the subharmonic modulation with shifted
carriers was the first extension to multilevel converters due to simplicity and ease of
implementation.

Fig.3.5.Multilevel modulators
It is classified as the level-shifted and the phase-shifted carrier modulations, which have found
application in different multilevel topologies.
3.2.1.level shifted carrier modulation
The level shifted carrier modulation was mainly applied to the DCMC converter is shown in
fig.3.6.

Fig.3.6. Implementation of a level-shifted carrier PWM scheme for a five-level

DCMC with comparators
It consists of the comparison of the modulating reference signal with a set of (n – 1) triangular
carriers associated with the n levels of the converter. The gating signals S1, S2, S3, and S4 are
the result of the comparison between the modulating signal Sref and the corresponding carriers,
which are shifted in level to span the complete range of Sref, as shown in Figure 3.10. Different
phase shifts can be introduced to the triangular carriers defining three basic switching patterns.
This is carried out by setting A1, A2, A3, and A4. One of them is called phase disposition pulse
width modulation (PD-PWM), and it is achieved by setting A1 = A2 = A3 = A4 =1. The
reference signal and its comparison with the carriers are shown in fig.3.7.

Fig.3..7.Multilevel subharmonic modulation. Triangular carriers and modulating signal for

PD-PWM,

This modulation technique has been extensively studied, and it is demonstrated through
spectral analysis that the variant PD-PWM has the best harmonic performance because it places
harmonic energy in a common mode first-carrier component, which is cancelled in the line-to-
line voltages
3.2.2. Multilevel Space Vector Modulation:
It is a familiar method of modulation with high flexibility and widely used for two level VSC.
It is more opt for a fast dynamic response or variable frequency operation is required, for
example, high-performance drives and power conditioning systems. Also, it basically has a
high DC bus voltage utilization factor and can also be naturally implemented on digital
hardware . Redundant states of the three-phase converter can be explicitly exploited, allowing
us to calculate the line voltages independently of leg voltages. However, the extension of two-
level SVM to multilevel converters is a challenging task, mainly due to the existence
of a high number of switching states.
A widely accepted representation of the space vector is defined in terms of the phase voltages
vao, vbo, and vco. Generally, these are transformed to the three space vector components vα,
vβ, and v0 through a coordinate transformation Tαβ0, according to

This representation allows us to describe the converter switching states with one vector in α-
β-0 coordinates. Figure 3.8 a shows the simplified model of a standard two-level voltage source
converter. In this case,the leg voltage can assume only two values, m = 1 and m = 0, and
therefore six active vectors can be synthesized on the α-β plane, as shown in Figure 3.8.b.

Fig.3.8.a. Voltage source converter

The space vector modulation is based on the approximation of the reference vector Vref
through the averaging of the nearest three vectors (NTV) within a sampling period TS,

where V1 and V2 are adjacent vectors that are directly identified from the phase of the
reference vector (θ), V3 is one zero vector, and d1, d2, and d3 are the corresponding duty cycles
for each vector. Figure 3.9 shows an averaging period, which is divided into the three activation
times corresponding to V1, V2, and V3.

Fig. 3.9 Averaging period

3.3.Voltage Balance Control:

This method of evaluation will be support to maintain DC bus constant from the switching
combinations. The following conditions apply:
• All capacitors have the same value (C1 = C2 = … = Cn–1 = C).
• The load is modeled as a three-wire current source.
3.3.1. Capacitor Voltage Calculation:
Figure 3.21 shows the three-phase DCMC functional model where it canbe seen that the
position of the single-pole multiple throw switches determines each leg voltage with respect
to the negative of the DC bus.In order to keep generality, this analysis takes into account the
existence or not of a DC bus voltage/power supply. This consideration lies in the fact that
there are applications in which active power transfer from the AC to DC side (or vice versa)
is inherent to the power processing system, for example, motor drives and active rectifiers.
On the other hand, applications such as reactive power compensation and harmonics filtering
do not need a power source on the DC bus. Both cases are explicitly represented through the
state of the switch F.
The calculation of voltage deviation in a given node of the DC bus is accomplished by
individually analyzing the effects of each phase current and then summing up their
contributions. This separate analysis requires a fictitious return path for the individual currents
for which the dummy impedance Z between the neutral and the negative of the DC bus is
included
The voltage variation in a given node of the DC bus is calculated by considering the equivalent
capacitance between the node and the negative terminal of the DC bus. When F = 1 the current
im flows to node m as shown in Figure 3.10. Also, im flows into an equivalent capacitance
Ceq_m given by

Fig.3.10. Functional model of the n-level three-phase DCMC converter

where Ceq_1 and Ceq_2 are the equivalent capacitances between node m and nodes 0 and (n
– 1), respectively. The voltage variation during the interval Td of node m with respect to the
negative of the DC bus is

When considering that the current is almost constant along the integration interval, the voltage
increment can be simplified to

The voltage deviation ΔVm is divided among all the capacitors of the DC bus, and the polarity
of the individual voltage deviation depends on the relative position of each capacitor with
respect to node m, that is, if it is above or below node m. Then, the capacitor Cj (j = 1, …, n –
1) will suffer a voltage variation ΔVCj, given by

A generalized expression for capacitor voltage variation that explicitly takes into account both
values of F can be summarized as
The total voltage deviation over each capacitor is calculated summing up the contributions of
the three line currents, that is, replacing ia, ib, and ic instead of im for the corresponding values
of ma, mb, and mc. The voltage variation on capacitor Cj due to the three phases results in

3.4.Voltage Balance Optimization:

At any sampling instant, say k, the present state of the DC bus can be represented by means of
a vector whose components are the voltages across the n – 1 capacitors

This equation indicates the necessity of selecting the most adequate switching combination in
order to minimize E[k + 1] and to steer the voltage vector toward the reference value VCref.
This selection can be achieved through the evaluation of a cost function that measures the
difference between VCref and VC. Such a function may be the norm of E[k + 1]:

From a sampling period to the next, this expression provides a way to evaluate the goodness
of any converter switching combination in order to force the capacitor voltages to their
reference values.

3.5. Effectiveness Boundary of Voltage Balancing in DCMC Converters

Redundant states are the key for capacitor voltage balancing control when additional hardware
is not considered. However, although it is possible to extend the operation of the converter to
active power processing, this approach still has limitations. In particular, n-level three-phase
converters with n > 3 cannot maintain a balancing condition when supplying current with a
high power factor at high modulation index, even when optimum selection of switching states
is carried out.
 Fig.3.11.Optimization Diagram

power factor (cos φ). Inside this domain, there is no modulation strategy that is able to
simultaneously synthesize a sinusoidal voltage waveform and preserve the voltage balance of
the DC bus capacitors.

The above demonstration of is supported on a balancing theorem introduced by Marchesoni

, which states the general conditions of any modulation algorithm to keep the voltage balance
of the DC bus.
 Fig.3.12.Figure for theorem proof

3.6.Performance results.
The control algorithms are tested by means of computer simulations. A five-level DCMC is
connected to a three-phase distribution grid through a coupling inductor as shown in Figure
3.13. The DC bus voltage is set to 20 kV, while the coupling inductor is 5 mH, Cbus = 4700
μF, and the averaging period TS is set to 0.4 ms. The power system is rated to a line voltage
of 14 kV.The reference vector Vref is synchronized to the main voltage, and the current flowing
through the coupling inductor is set by means of the amplitude of the reference voltage vector.
Figure 3.14 a shows one line voltage at the converter terminals. As it can be seen, it exhibits
single-step transitions over the complete trace featuring good harmonic performance. The
currents provided by the converter to the coupling inductor are shown in Figure 3.14b. The
three line currents that circulate through the coupling inductor have a large component
 Fig. 3.13 Five-level DCMC connected to the power grid through a coupling
inductor.
at the fundamental frequency with a small switching frequency ripple. Figure 3.15 shows the
capacitor voltages that remain balanced at their reference value of 5 kV, with an approximate
ripple of 200 V peak to peak.

Fig. 3.14 (a) Converter line voltage. (b) Converter line currents
In order to test the balancing algorithm, a voltage unbalance is forced externally to the DC bus
capacitors. With a modulation index of M = 0.85,the unbalance is set at t = 100 ms. The
capacitor voltages are shown in Figure 3.15. The unbalancing condition is mitigated and the
balance is restored in approximately 100 ms. Figure 3.16 shows single jumps on leg voltages,
even at the disturbance instant. Finally, the modulation index is modified to M = 0.96 and the
same disturbance on capacitor voltages is introduced. It is observed that the required time for
balancing restoration is slightly extended (Figure 3.30) compared with the previous case

Fig.3.15. DC Capacitor voltage

Fig.3.16. Leg voltages at unbalancing instant (M = 0.85)

UNIT IV FLYING CAPACITOR MULTILEVEL CONVERTER 6
Introduction – Flying Capacitor topology – Modulation scheme for the FCMC –
Dynamic voltage balance of FCMC

4.0.Introduction
The flying capacitor multilevel converter (FCMC) has been introduced by Meynard and
Foch. This topology was conceived to implement high-voltage converters without series
connection of the power switches. The FCMC has some advantages when compared to
the diode-clamped multilevel converter (DCMC). It is easy to increase the number of
voltage levels by simply adding basic cells in the load end of each leg. The main
disadvantage of this topology is that it requires a large number of capacitors since it
builds the voltage levels with flying capacitors in each leg of the converter. It is very
important that all the FCs reach a constant and stable voltage, so the net charge variation
on each of them should be null. There are two important reasons for this. The first is to
reduce the harmonic distortion on the output voltage. The second is to guarantee the
same blocking voltage of each power switch equals the same fraction of the total DC
bus voltage.

4.1. Flying Capacitor topology

The three-level generalized topology is shown in Figure 4.1.a, it was demonstrated that
the power switches S12 and S11 connect C2 in parallel with C11 or C12, fixing the
average voltage across C2 to VDC/2. It is possible to find a switching sequence between
the adjacent states shown in Figure 2.4b, in such a way to maintain the voltage across
C2 equal to VDC/2, without using S12 and S11 . When both switches are eliminated, C2
flies between both stages, as shown in Figure 4.1.b. This topology is known as capacitor-
clamped multilevel topology or flying capacitor multilevel converter .
 Fig.4.1.a Three-level generalized topology with switching states

Fig.4.1.b. Three-level generalized topology

The three-level FCMC comes from a two-stage generalized topology, so it has

two switching functions and four possible states, the same as were shown in Figure 2.4b.
The same as in the previous analysis, states 00 and 11 generate levels 0 V and V DC,
respectively. The connections for the intermediate states are shown in Figure 4.1, where
the switches that are open are indicated in light gray. Assuming that the voltage over C2
remains constant, the output voltage for both states equals VDC/2, while in state 01
switches S1 and S2 are closed and the voltage Vin is the voltage directly across from
C2. In state 10 the switches S1 and S2 connect C2 in series with the DC power supply
VDC; then Vin equals the difference between the voltages of the DC link and C2.
Moreover, the blocking voltage for each power switch is the voltage on each capacitor,
which is VDC/2. Unlike the NPC converter, there are no forbidden states and there are
two redundant states that generate the same voltage at the output.

4.1.1. Voltage on the Flying Capacitor

In the previous section it was assumed that the voltage across C2 is constant and equal
to VDC/2. In order to guarantee this constant value, it is necessary to have no net charge
on the capacitor along one switching cycle. This condition can be met using the
redundant states.

Each flying capacitor belongs to an intermediate basic cell of the generalized

topology, where all the inner switches were eliminated. The voltage across each
capacitor (VC) preserves the same value as in the generalized topology. For an n-level
converter

An n-level converter employs n –1 stages, where each stage is controlled with a

switching function (sj). The jth stage of a FCMC has a pair of complementary switches
plus (n – j) capacitors connected in series. The combined action of the switching
functions of each stage generates the leg voltage Vin, given by

An n-level FCMC requires (n – 1)(n – 2)/2 flying capacitors in each leg of the
converter plus (n – 1) capacitors on the DC bus. This number can be reduced if the flying
capacitors withstand different voltages. Then, the (n – j) capacitors of each stage may
be replaced by a single capacitor, and each leg has only (n – 2) capacitors. Now each
capacitor works with an average voltage equal to

where j = 1 corresponds to the stage beside the load. In this example, Figure 4.2 shows
one leg of a four-level converter, the average voltages over the flying capacitors are
2/3VDC and 1/3VDC for the second and third stages, respectively.

Fig 4.2 shows one leg of a four-level converter

4.2. Modulation Scheme for the FCMC

Modulation techniques , such as space vector modulation, predictive control , selective

harmonics elimination , or carrier-based pulse width modulation with several carriers.
Any of these modulations should satisfy in order to guarantee the charge balance of the
flying capacitors. Among them, the phase-shifted carrier pulse width modulation
(PSPWM) naturally provides the required charge and voltage balance of all the
capacitors of the FCMC. This modulation travels along the redundant states of the
FCMC providing self-charge balancing without additional controllers.

4.2.1. Phase-Shifted Carrier Pulse Width Modulation

The PSPWM of an n-level FCMC requires n – 1 carriers with a phase displacement as

shown in Figure 4.3. Each carrier is a triangular wave with an amplitude AP and a
frequency fS much higher than the modulating frequency. The phase shift among them
is equal to

A single modulating signal is compared with each carrier generating n – 1

switching functions. The modulation index (m) is defined as the ratio between the
amplitudes of the modulating signal and the carrier,

While m is lower than unity, there exists a linear relationship between the
amplitude of the fundamental component of the leg voltage (Vin) and VDC.

Fig.4.3. Carriers in PSPWM

The power devices of the FCMC switch at a frequency fS, while the leg voltage
(viN) commutates at a frequency equal to (n – 1).fS. Then, the harmonics spectrum of
the load voltage is shifted to higher frequencies, simplifying the design of the output
filter.
4.2.2. Charge Balance Using PSPWM

The PSPWM in an n-level FCMC naturally maintains the charge balance in all
the flying capacitors. This is done traveling along the redundant states in each
switching cycle. The same analysis procedure can be extended to an n-level converter.
The three-level FCMC converter requires two carriers with a phase shift equal to π .

Fig.4.4. PSPWM. Switching functions (s1i and s2i) for n = 3. (a) Switching
functions when the modulating signal is positive, (b) switching functions when the
modulating signal is negative, and (c) current and voltage on C2i.
The comparisons between the carrier waveforms and the modulating signal generate the
switching functions (s1i and s2i) that drive the power switches S1i and S2i, respectively.
Taking into account (4.2) for n = 3, when the modulating signal is positive, the output
voltage changes between VDC/2 and VDC. On the other hand, when the modulating signal
is negative, Vin changes between 0 and VDC/2.

4.2.3.Dynamic Voltage Balance:

For a three-level FCMC, that the PSPWM maintains the charge balance in steady state.
This is true assuming that the average voltage of C2i has already reached the value
VDC/2. But this is not the only stable condition. It may happen that the voltage vC2i has
a steady-state value different from the expected VDC/2. If this happens,the leg voltage
viN will have asymmetric voltage levels, leading to a loss in waveform symmetry. This
causes several drawbacks: voltage jumps of different amplitude, asymmetric voltage
waveform, increased harmonics spectrum, and increased blocking voltage for the power
switches of the converter. Then, it is very important to find a strategy in order to
guarantee that every flying capacitor reaches the desired voltage. The dynamic behavior
of the voltage in the flying capacitors has been treated in the literature through the
harmonics components [8,9]. It has been demonstrated that the voltage unbalances on
the flying capacitors of an n-level FCMC can be corrected introducing harmonic
currents at frequencies equal to k.fS (where k is an integer but not a multiple of

the number of levels n) There exist two mechanisms through which these harmonics can
appear on the flying capacitors. In this way, the time of convergence to the steady state
depends on the load. The other method consists in generating the balancing harmonics
with passive networks tuned at the switching frequency. This network not only allows
the dynamic balance of flying capacitors,it can also fix the convergence time to the
steady state, through a proper design of the passive network. Dynamic Model It is better
to use a time domain model to analyze the dynamic behavior of the currents through the
flying capacitors The circuit presented in Figure is used, assuming that the switching
frequency is much higher than the modulating frequency; in this case, it is valid to
assume that the duty cycles of both switches are equal, since the current is almost
constant along one commutation period. The increment of the averaged voltage on
capacitor C2i is much slower than the voltage ripple generated by the switching
frequency These averaged voltage variations are denoted with the symbol ∼. A variation
of the averaged voltage across the capacitor implies that there is an average current
through it. Both are related by

is easy to see in fig that, for a given load current, the voltage vC i2 is controlled with the
duty cycles d1i and d2i. This requires a voltage control loop for the flying capacitor.
When using a PSPWM, both duty cycles are equal; so regardless of load current ii, the
voltage vC i2 will remain in its steady-state value.
Assuming that the voltage ripple is much smaller than its average value, the output leg
voltage viN equals the sum of the voltages across the switches S i1 and S i2 . Then,

During start-up, the flying capacitor is initially discharged. So it is necessary to

introduce a difference in the duty cycles in order to reach the steady-state value. In this
case the phase-shifted carrier modulation is not capable of generating the charge of the
flying capacitor. So it is convenient to find a different way to charge the capacitor so
that vC i2 reaches its steady-state value independently of the duty cycles of the power
switches and the load current.
UNIT V MULTILEVEL CONVERTER WITH REDUCED SWITCH COUNT

Multilevel inverter with reduced switch count-structures, working principles and pulse
generation methods.
5.1. Introduction:
The dc-ac converter, also known as the inverter, converts dc power to ac power at desired
output voltage and frequency Multilevel inverters are cascaded H-bridges converter
with separate dc sources. Recently, multilevel inverters (MLI) have attracted more
attention in research and industry, as they are changing into a viable technology for
several applications. The concept of MLI was introduced for high power and
high/medium voltage applications as they can provide an effective interface with
renewable energy sources. which uses less number of switching components for
specified number of voltage output levels as compared to that of conventional multilevel
inverter topology. Developing reduced switch MLI topology has been a rapid research
topic since the past decade. These configurations are not only generating higher voltage
levels to improve the power quality but also to reduce the passive filter requirements.

5.2. Multilevel inverter with reduced switch count-structures and Working :

Another aspect of MLI has been the selection of magnitude of dc voltage sources used
in the topology. Based on this, MLIs have been classified as symmetrical and
asymmetrical. Symmetrical MLIs uses identical dc voltage sources whereas
asymmetrical MLIs employs dc voltage sources having unequal magnitude.
Symmetrical MLIs have more redundant states i.e. more number of switching
combination are available to get same voltage level. This improves the performance of
MLI in terms of balancing the voltage across capacitors and fault tolerant capabilities.
However, at the same time symmetrical configured MLIs requires more number of
switches, gate driver circuits, and dc voltage links. This increases the inverter size, cost
and control complexity for a higher number of levels. Asymmetrical configuration
increases the number of levels generated at the output compares to the symmetrical
configuration using the same number of components and dc voltage sources. A higher
number of switches are required to generate a staircase multilevel waveform. Moreover,
even low rating switches require separate driver circuit along with necessary protective
circuitry which adds to the complexity of the system. The results presented show that
the number of IGBT required to realize a similar voltage level is lesser. Moreover, the
standing voltages are also lesser on the bidirectional switch. The topology of has also
been experimentally verified with a suitable design example.

The topology proposed in utilized novel multilevel inverters which contain five-level
sub-module architecture. The proposed topology has been realized in both the
asymmetrical and symmetrical mode of operation. The result shows the structure has
advantages in levels of voltage generated for a given number of switches. The normal
topology proposed in existing requires 12 switches to produce 5 level output. But the
same voltage level can be achieved by converter proposed later in with the lesser
standing voltage on the switching devices. The proposed application of topology
presented in includes D-STATCOM, hybrid electric vehicle, and PV system. This
system requires lesser installation space and cost because of the reduced number of
switching devices, switching and conduction losses and total standing voltage.

Fig.5.1.Reduced switch topology

Pulse Generation Methods:

From the fig.5.1.the Input of DC supply ,the load resistor R is receiving the Alternating
voltage with the multi level topology.as per the MLI topology the number odf stages
frequired for 5 level inverter will be 4 and the number switches also around 8 .cause the
switching losses and economic issues also .In this reduced switching topology as seen
the required switches are only 5 for five level inverters .

The functional operation is having five mode of operation

Mode 1: where the s2 and s5 are conducting [Vo=Vdc/2]

Fig.5.1. Reduced switch module

Switching Switches in Switches in off Diodes in Output

state conduction FB voltage
Mode 1 S2 & S4 All other - 0
switches
Mode 2 S2 & S5 All other D1 & D4 Vdc/2
switches
Mode 3 S1 & S2 All other - Vdc
switches
Mode 4 S2 & S5 All other D1 & D4 Vdc/2
switches
Mode 5 S2 & S4 All other - 0
switches
Mode 6 S3 & S5 All other D2 & D3 -Vdc/2
switches
 Mode 7 S3 & S4 All other - -Vdc
switches
Mode 8 S3 & S5 All other D2 & D3 -Vdc/2
switches
Mode 9 S2 & S4 All other - 0
switches

Mode 1 for V0 = 0V

Mode 2 for Vo = Vdc/2

:
2. Draw and explain any Multilevel Inverter Topology With Reduce Switch Count

THREE SOURCE 15 LEVEL (3S-15L) TOPOLOGY

The proposed topology is depicted in Fig. 1. It consists of eight unidirectional switches from
S1 - S8 along with one bidirectional switch S9. The switches S3 - S6 along with S9 forms the
inner part of the topology with two dc voltage sources with a magnitude of V2. The remaining
four switches i.e., S1 – S2 and S7 – S8 and one dc voltage source with magnitude of V1 forms
the outer portion of the proposed topology. The switches (S1–S2), (S3–S4), (S5–S6), and (S7–
S8) need to operate in a complementary fashion to avoid short circuiting of dc voltage sources.
The number of levels depends upon the magnitude of the dc voltage source, i.e., V1 and V2 the
selection can be done in two ways as:
1) SYMMETRICAL CONFIGURATION In this configuration, each dc voltage source has the
same magnitude, i.e., V1 = V2 = Vdc. With such configuration, seven levels at the output are
achieved.
2) ASYMMETRICAL CONFIGURATION In the asymmetrical configuration, the magnitude
of dc voltage sources have different magnitude, i.e., V1 and V2 have a different magnitude.
For the proposed topology with asymmetrical configuration, the magnitude of dc voltage
sources are chosen in tertiary mode, i.e., V1 = Vdc, and V2 = 3Vdc (3S-15L Topology). With
the tertiary configuration, the proposed topology generates 15 output voltage levels, i.e., zero,
±Vdc, ±2Vdc, ±3Vdc, ±4Vdc, ±5Vdc, ±6Vdc, and ±7Vdc. The switching table for the proposed
topology with the tertiary mode is given in Table 1. Furthermore, the different switching states
for the proposed topology with tertiary mode are shown in Figs. 2 (a)-(h).
With tertiary mode, the maximum output voltage (Vo,max) of the proposed topology is:

The total standing voltage (TSV) is an important factor for the selection of switches. TSV is
the addition of the maximum blocking voltage across each semiconductor device. The
voltage stress across each pair of the complementary switch will be the same. Therefore,