PLC - 2
PLC - 2
EEE 4209
Graphical languages
▪ Ladder diagrams
▪ Function block diagram
▪ Sequential function chart
Text-based languages
▪ Instruction list
▪ Structured text
2
PLC Operation Cycle
1. Input Scan
Scans the state of the inputs
2. Program Scan
Executes the user-written program logic
3. Output Scan
Energizes or de-energizes the outputs
4. Housekeeping
Communication with programming terminals and internal diagnostics
3
PLC I/O Symbols
4
Ladder Programming Rules
▪ The vertical lines of the diagram represent the power rails between which circuits are
connected.
▪ Each rung on the ladder defines one operation in the control process.
▪ A ladder diagram is read from left to right and from top to bottom.
▪ This procedure of going through all the rungs of the program is termed a cycle.
▪ Each rung must start with an input or inputs and must end with at least one output,
input devices being represented by two short parallel lines to represent switching
contacts and output devices being represented by circles.
▪ The term input is used for a control action, such as closing the contacts of a switch,
used as an input to the PLC.
▪ The term output is used for a device connected to the output of a PLC, e.g. a motor.
5
Ladder Programming Rules (contd.)
Execution sequence
6
Ladder Programming Symbols (Inputs)
Logic 0 Logic 0
Logic 1 Logic 1
7
Ladder Programming Symbols for (Output Coil)
Logic 0 Logic 0
Logic 1
Logic 1
8
Example
I4 Q2
END
OR GATE 0V 0V
COM COM
+24 V
I1 Q0
I2 Q1
I2 Q3
I3
C Q2
I4 P Q3
I3
I5 U Q4
I6 +24 V
Q5
END I7 Q6
I8 Q7
Truth Table Ladder Diagram
Hardware Diagram
10
Implementations of Digital Logic Functions (contd.)
AND GATE 0V 0V
COM COM
+24 V
I1 Q0
I2 Q1
I3 Q3 I3
C Q2
I2
I4 P Q3
I5 U Q4
I6 +24 V
Q5
END I7 Q6
I8 Q7
11
Implementations of Digital Logic Functions (contd.)
NOT GATE 0V 0V
COM COM
+24 V
I1 Q0
I2 Q1
I3
C Q2
I2 Q3
I4 P Q3
I5 U Q4
I6 +24 V
Q5
END I7 Q6
I8 Q7
Truth Table Ladder Diagram
Hardware Diagram
12
Implementations of Digital Logic Functions (contd.)
H.W.
Design the ladder diagram and hardware diagram for NOR, NAND, XOR and
XNOR gates.
13