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27 04 2020 - Micro

The Intel 8257 is a 4-channel DMA controller that facilitates direct memory access for data transfer between I/O devices and memory without CPU intervention. It features a 40-pin DIP package, operates at a maximum clock frequency of 3 MHz, and supports simultaneous requests from four I/O devices, allowing for data transfer modes such as burst and cycle steal. The internal architecture includes functional blocks for data bus buffering, control logic, read/write operations, priority resolution, and dedicated DMA channels, enabling efficient management of data transfers.

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7 views4 pages

27 04 2020 - Micro

The Intel 8257 is a 4-channel DMA controller that facilitates direct memory access for data transfer between I/O devices and memory without CPU intervention. It features a 40-pin DIP package, operates at a maximum clock frequency of 3 MHz, and supports simultaneous requests from four I/O devices, allowing for data transfer modes such as burst and cycle steal. The internal architecture includes functional blocks for data bus buffering, control logic, read/write operations, priority resolution, and dedicated DMA channels, enabling efficient management of data transfers.

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tejas.dhangar17636
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INTRODUCTION TO 8257 (DMA CONTROLLER)

The bulk data transfer between memory and I/O devices through the CPU is
a time consuming process. For such cases, DMA (Direct Memory Access)
technique is preferred. DMA can be defined as a technique of transferring data
from I/O to memory and from memory to I/O without the intervention of the
CPU. Direct Memory Access needs a special hardware called DMA controller
that manages the data transfers.
Intel 8257 is a 4-channel DMA controller that manages the data transfers
for their Intel family of microprocessors. The I/O devices request to 8257 for
Direct Memory Access (DMA). 8257 temporarily borrows the address bus, data
bus, and control bus from the microprocessor and transfers the data bytes
directly between an I/O port and a series of memory locations.
FEATURES
 It is 40 pin DIP (Dual in line package).
 It requires +5V dc power supply for its operation.
 The maximum clock frequency is 3 MHz.
 It is 4-channel programmable DMA controller, hence four I/O devices can
request for DMA process simultaneously.
 Each channel has 16-bit address register & 14-bit counter. Therefore
each channel can support data transfer of 214=16KB during DMA
process.
 It can enables/disables control of individual DMA requests.
 It can execute three DMA cycles:
a) DMA read (Data transfer from memory to I/O device)
b) DMA write (Data transfer from I/O device to memory)
c) DMA verify (Prevent data transfer)
 It has internal priority resolver to determine the priority of the four DMA
channels in fixed or rotating priority mode.
 It provides on chip channel inhibit logic.
 It provides memory block initialization.
 It provides data transfer in two modes: (a) burst mode (b) cycle steal
(single byte transfer mode).
 It uses the control signal TC (Terminal Count) to indicate the completion
of DMA transfer.
 It uses the control signal MARK (Modulo 128 Mark) to indicate the
completion of 128 bytes of DMA transfer.
 It can be operated in auto load mode.
INTERNAL ARCHITECTURE OF 8257
The internal block diagram of 8257 DMA Controller is as shown in Fig 8.1.
It manages the data transfer between the memory and I/O device. The DMA
controller can issue commands to the memory that behave exactly like the
commands issued by the microprocessor. The DMA controller in a sense is a
second processor in the system but is dedicated to an I/O function. It consists
of five functional blocks:
a) Data bus buffer
b) Control logic
c) Read/write logic
d) Priority Resolver
e) DMA channels
Fig. 8.1 Internal Architecture of 8257

 DMA Channels
8257 has 4 independent DMA channels (CH0 to CH3), hence four I/O
devices can request for DMA simultaneously. Each channel consists of two
16-bit registers (i) Address register (ii) Count Register. Address register holds
the starting address of the memory block to be accessed by I/O device. Count
register holds the number of bytes to be transferred during DMA action. The low
order 14-bits of count register specify the number of bytes; therefore each
channel can support data transfer of 214=16KB during DMA process. The high
order 2-bits of count register specify the mode of operation (read, write or verify)
 Data Bus Buffer
This 8-bit Bidirectional buffer is used to interface the 8257 to the system
Data Bus. It allows the transfer of data and information between 8257 and
microprocessor. In master mode, it is used to output the higher order (A8-A15)
of memory address. In slave mode, it is used to transfer the data between 8257
and microprocessor.
 Read/Write Control Logic
8257 operates in two basic modes, master mode and slave mode. In the
slave mode, read/write logic accepts the or signal. In the master
mode, read/write logic generates and for DMA write cycle or
and for DMA read cycle.
 Priority Resolver
This logic block determines the priorities of the channels when more than
one I/O device request for DMA. By default the priority resolver work in fixed
priority mode. In this mode the CH0 has the highest priority while the CH3 has
lowest. In rotating priority, the priority of the channels has a circular sequence.
The channel which has being just serviced move to the lowest priority and
channel next to it move to the highest priority, hence each channel achieves the
highest priority in rotation.
 Control Logic
In the master mode, Control logic controls the sequence of operation during
DMA cycles (DMA read, DMA write & DMA verify). It also generates required
control signals and memory address to be accessed. It increments 16-bit
address register and decrement count register of corresponding channel during
DMA action. It is disabled in slave mode.

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