energies

Article
Article
DesignConsiderations
Design Considerationsof
ofSeries-Connected
Series-ConnectedDevices
Devices
BasedLLC
Based LLCConverter
Converter
DongkwanYoon,
Dongkwan Yoon, Sungmin
Sungmin Lee
Lee and
and Younghoon
Younghoon Cho
Cho * *
Department
Department ofof Electrical
Electrical Engineering,
Engineering, Konkuk
Konkuk University,
University, Seoul
Seoul 05029,
05029, Korea;
Korea; asdf0462@konkuk.ac.kr
asdf0462@konkuk.ac.kr (D.Y.);
(D.Y.);
lsm2429@konkuk.ac.kr (S.L.)
lsm2429@konkuk.ac.kr (S.L.)
* *Correspondence:
Correspondence: yhcho98@konkuk.ac.kr;
yhcho98@konkuk.ac.kr; +82-10-6207-0431
Tel.:
Tel.: +82-10-6207-0431

Received: 30 November 2019; Accepted: 02 January 2020; Published: date



Received: 30 November 2019; Accepted: 2 January 2020; Published: 5 January 2020


Abstract: This paper describes the design of a Series-Connected Device based on a fixed–frequency
Abstract: This paper
LLC resonant describes
converter the design
(SCDLLC). of a Series-Connected
Isolation Device based
of the dc-dc converter on LLC
like the a fixed–frequency LLC
resonant converter
resonant converter (SCDLLC). Isolation of the dc-dc converter like the LLC resonant converter
is used for the stability of the high voltage system such as a solid-state-transformer (SST). The series- is used
for the stability
connected of thedriving
devices high voltage
methodsystem
is onesuch as amethods
of the solid-state-transformer
applicable to a(SST). The series-connected
high voltage system. When
devices
drivingdriving method is one
series-connected of the methods
devices, an auxiliaryapplicable
circuittofor
a high voltage
voltage system. between
balancing When driving
series-
series-connected
connected devices devices, an auxiliary
is required, which circuit
can beforsimply
voltageimplemented
balancing between
using series-connected
a passive element. devices
In this
ispaper,
required,
LLCwhich can be
converter simply
design implemented
with using aconfigured
balancing circuits passive element. In this
in parallel paper,
with LLCisconverter
a device provided,
design with balancing circuits configured in parallel
and both the simulations and experiments were performed. with a device is provided, and both the simulations
and experiments were performed.
Keywords: solid-state-transformer (SST); isolation dc-dc converter; LLC resonant converter; Series-
Keywords: solid-state-transformer (SST); isolation dc-dc converter; LLC resonant converter;
connected devices
series-connected devices

1.1.Introduction
Introduction
Recently,
Recently, with
with new
new technologies
technologies such
such asas smart
smart grid
grid and
and DCDC distribution,
distribution, SST
SST have
have emerged.SST
emerged. SST
connects directly to the grid instead of the traditional transformers to perform a variety
connects directly to the grid instead of the traditional transformers to perform a variety of roles suchof roles such
asaspower
powerfactor
factorcorrection
correctionandandDC
DCdistribution.
distribution.Therefore,
Therefore,SSTSSTshould
shouldbebeable
abletotocope
copewith
withthe
thehigh
high
voltage of the grid, so that the various studies can be conducted [1–8]. To cope with high voltage, a a
voltage of the grid, so that the various studies can be conducted [1–8]. To cope with high voltage,
multi-moduleconverter
multi-module converter(MMC)
(MMC)orora aseries-connected
series-connectedswitching
switchingdevices
devicesmethod
methodhas hasbeen
beenstudied.
studied.
Figure1 1shows
Figure showsthethedifference
difference between
between MMC
MMC and
and the
the series-connected
series-connected device
device method.
method.

(a) (b)

Figure 1. 1.Comparison
Figure Comparisonstructure
structurebetween
betweenMMC
MMCandandthe
theseries-connected
series-connecteddevices-based
devices-basedconverter.
converter.(a)(a)
MMC;
MMC; (b)(b)
series-connected
series-connecteddevices-based
devices-basedconverter.
converter.
Energies 2020, 13, x; doi: FOR PEER REVIEW www.mdpi.com/journal/energies
Energies 2020, 13, 264; doi:10.3390/en13010264 www.mdpi.com/journal/energies
Energies 2020, 13, 264 2 of 14

MMC is a structure that increases the front of the circuit by stacking the circuit in series, which
is relatively easy to expand, and has the advantage of reducing filter size by increasing the Power
Conversion System (PCS) voltage level. But, since there is a separated DC link voltage, it is necessary
to control and balance the separated DC link voltage. In addition, all individual devices should be
controlled as the number of modules increases, which requires a digital computing device with many
Pulse Width Modulation (PWM) channels. On the other hand, the series-connected devices behave like
a single device, so even if many devices are connected in series, no digital computing device with many
PWM channels is required. Furthermore, due to the series-connected devices, PCS does not have the
separated DC link voltage. No additional control method is needed for DC link voltage balancing. On
the other hand, because the output voltage level of series-connected devices based on PCS decreases,
the filter size is larger than the MMC method. In addition, there is an issue with a switch voltage
imbalance between the series-connected switches.
According to References [9–16], there are various reasons for causing a voltage imbalance. The
first reason is the error of the gate driver. The gate driver is composed of various passive components
and semiconductor devices like Negative, Positive, Negative (NPN) and Positive, Negative, Positive
(PNP) transistors. Errors in devices of the gate driver cause an unbalance in the gate signal, which
causes an imbalance in the voltage across the series-connected devices. The second reason is the error
of parasitic components of the device itself. The error of the output capacitor of devices affects the
switching speed and causes a voltage imbalance. The third reason is the parasitic capacitor from gate
to ground of each device.
To solve voltage imbalance, various studies have been conducted [9–16]. In Reference [9], Active
Gate Driver using Field Programmable Gate Array (FPGA) with RCD (Resistor, Capacitor and Diode)
snubbers across each device method for balancing was proposed and tested. In the documents, the
three-phase half-bridge inverter was built in 12-series connected Insulated Gage Bipolar Transistor
(IGBT) and verified at a rated current within ±10 kV DC-link. In Reference [12], an active gate driver
using a current mirror with a steady-state balancing resistor was proposed and performed. The
steady-state voltage imbalance is reduced by the balancing resistor, and the transient imbalance was
solved by the analog gate controller used a current mirror. In Reference [14], the voltage balancing
method with only passive components using a single gate driver unit was proposed. In the documents,
experimental verifications were applied to the DC circuit breaker with a 1.2 kV bus voltage. It was
confirmed that it is possible to cope with the high voltage system by using a series connection element
applied to various methods.
In a high voltage system, like SST, isolated converters are needed to increase the stability of the
system and grid. Isolated converters are one of the necessary converters for SST regardless of MMC
or series-connected devices. There are many types of isolated converters such as Dual-Active-Bridge
(DAB), Quad-Active-Bridge (QAB), and LLC Converter. A fixed-frequency resonant converter conducts
zero voltage switching (ZVS) over a wide frequency range and provides the advantages of high efficiency
and high-power density.
In this paper, fixed-frequency LLC resonant converter-based series-connected devices is proposed.
In order to cope with a high voltage, a series-connected device based on PCS was applied and an R-C
snubber was applied to solve the voltage imbalance between series-connected devices. In conclusion,
this paper examined the effect of R-C snubber applied to the LLC converter to solve the voltage
imbalance. The proposed converter consists of a full-bridge inverter. Unlike the usual full-bridge
converter, the proposed converter consists of eight devices, as shown in Figure 1b. The operation of
the SCDLLC converter with a balancing circuit is described. This paper is structured as follows. In
Section 2, imbalance factors of series-connected devices are described and a balancing method using
passive elements is expressed. In Section 3, a configuration method of the LLC converter considering
series-connected devices is explained. In Sections 4 and 5, a 3-kW prototype model is manufactured
to verify the usefulness of the proposed system and the simulations and experiments are performed.
Lastly, in Section 6, we discuss experimental results and conclude the paper.
Energies 2020, 13, x FOR PEER REVIEW 3 of 15
Energies 2020, 13, x FOR PEER REVIEW 3 of 15
Energies 2020, 13, 264 3 of 14
2. Design
2. Design ofof Series-Connected
Series-Connected Devices
Devices Balancing
Balancing Circuit
Circuit
Figureof22 Series-Connected
2. Design
Figure depicts the
depicts the series-connected
series-connected device with
Devices Balancing
device with various factors
Circuit
various factors that
that cause
cause aa voltage
voltage imbalance.
imbalance.
Gate signal
Gate Figure mismatch
signal 2mismatch can occur due to
canseries-connected an error
occur due to andevice of
error of the device’s
thevarious parasitic
device’sfactors
parasitic capacitor, unbalance of the
the
depicts the with thatcapacitor, unbalance
cause a voltage of
imbalance.
gate
gate signal due to a gate pattern, and an error of the parasitic capacitor from gate to ground, which
Gate signal due to a gate
signal mismatch can pattern,
occur dueand an error
to an error of
ofthe
thedevice’s
parasiticparasitic
capacitor from gate
capacitor, to ground,
unbalance which
of the gate
causes an
causes an unbalance
unbalance of of voltage
voltage across
across the
the device.
device. Furthermore,
Furthermore, thethe voltage
voltage imbalance
imbalance of of devices
devices
signal due to a gate pattern, and an error of the parasitic capacitor from gate to ground, which causes
increases the
increases the stress
stress and
and can
can cause
cause damage
damage toto the
the device.
device. In
In this
this section,
section, in
in order
order to
to prevent
prevent damage
damage
an unbalance of voltage across the device. Furthermore, the voltage imbalance of devices increases the
to the
to the device,
device, the
the voltage
voltage balancing
balancing method
method of of the series-connected
series-connected devices
devices was
was analyzed
analyzed using
using
stress and can cause damage to the device. In thisthe
section, in order to prevent damage to the device,
passive
passive components.
components.
the voltage balancing method of the series-connected devices was analyzed using passive components.

Figure 2. Voltage imbalance factors in series-connected devices.

Voltage imbalance
Figure 2. Voltage factors in series-connected devices.

Passive snubbers
snubbersimplemented
implemented by by
passive devices
passive (C, RC,
devices (C,RCD,
RC, etc.)
RCD, areetc.)
usedare
for used
voltage
forbalancing
voltage
Passive snubbers implemented by passive devices (C, RC, RCD, etc.) are used for voltage
circuits. Voltage
balancing circuits. imbalance
circuits. Voltage of devices
Voltage imbalance
imbalance of is somewhat
of devices
devices is limited
is somewhat by
somewhat limited placing
limited by the passive
by placing
placing the snubber
the passive circuit
passive snubber
snubber
balancing
between drain todrain
circuit between
between source. The useThe
to source.
source. of passive
use of snubbersnubber
of passive
passive circuits circuits
reducesreduces
the switching speed ofspeed
the switching
switching devices
of
circuit drain to The use snubber circuits reduces the speed of
and the and
devices voltagethe imbalance
voltage due to adue
imbalance gatetosignal
a gateimbalance.
signal Figure 3Figure
imbalance. shows 3series-connected
shows devices
series-connected
devices and the voltage imbalance due to a gate signal imbalance. Figure 3 shows series-connected
with passive
devices withbalancing circuits. The
passive balancing
balancing snubber
circuits. Thecircuit
snubbercomposed
circuit of a steady-state
composed of aa balancing resistor
steady-state (Rbal )
balancing
devices with passive circuits. The snubber circuit composed of steady-state balancing
and a transient
resistor (Rbal statetransient
bal) and balancing capacitor (Csnub , Rdamp ).(Csnub, Rdamp).
resistor (R ) and aa transient state
state balancing
balancing capacitor
capacitor (Csnub, Rdamp).

Cdg
Gate Cdg Rdamp
Gate Cds Rbal Rdamp
Driver Cds Rbal
Driver Cgs Csnub
Cgs Csnub

Gate
Gate
Driver
Driver

Figure 3.
Figure Structure of
3. Structure of voltage
voltage balancing
balancing circuits
circuits in
in series-connected
series-connected devices.
devices.
Figure 3. Structure of voltage balancing circuits in series-connected devices.
The
The steady-state
steady-statebalancing
balancingresistors
resistorsoperate
operate when
whenthetheswitch
switchis fully turned-off.
is fully
fully turned-off.If the
If steady-state
the steady-
steady-
The
balancing steady-state
resistors balancing
are small, theresistors
devices operate
are when
well the switch
balanced. is
However, turned-off.
the power If the
dissipation of
state
state balancing
balancing resistors
resistors are small,
are small, the devices
the requires are
devices are well
well balanced.
balanced. However,
However, the power
the power dissipation
dissipation of
of
balancing
balancing resistors
resistors increased,
increased, which
which requires the
the use
use of
of higher-rated
higher-rated resistors.
resistors. Conversely,
Conversely, If
If the
the
balancing
balancing resistors are
resistors increased, which dissipation
requires theofuse of higher-rated resistors. However,
Conversely, If is
the
balancing resistors
balancing are big,
resistors are big,
the
big, the power
the power
power dissipation
dissipation of balancing
of balancing resistors decrease.
balancing resistors
resistors decrease. However,
decrease. However, there there is aaa
there is
high
high probability
probability that
that voltage
voltage balancing
balancing between
between series-connected
series-connected devicesdevices will
will fail. Therefore,
Therefore, when
fail. Therefore, when
high probability
designing the that
balancingvoltage balancing
resistor, the between
leakage series-connected
current of the device devices
should bewill fail.
considered. when
Steady-state
designing the
designing the balancing
balancing resistor,
resistor, the
the leakage
leakage current
current ofof the
the device
device should
should bebe considered.
considered. Steady-state
Steady-state
resistance
resistance are
are calculated
calculated below.
below.
resistance are calculated below.
𝑣 vds
𝑣 𝑣 vds
𝑣
< Rbal <
𝑅 (1)
(1)
10 10
𝑖 × ileakage_max
_
𝑅 10 10 ×𝑖 ileakage_min
_ (1)
10 𝑖 _ 10 𝑖 _
Energies 2020, 13, x FOR PEER REVIEW 4 of 15

Energies 2020, 13, 264 4 of 14

The transient state balancing circuit (Csnub, Rdamp) operates when the switch is a turn-on state and
a turn-off state. Csnub is selected considering the parasitic capacitor of the device. To avoid imbalance
by parasitic capacitor
The transient errors of the
state balancing devices,
circuit (Csnub ,attach
Rdamp ) aoperates
balancing
when capacitor
the switch with
is anegligible
turn-on state parasitic
and a
capacitors
turn-off of aCsnub
state. device. If snubber
is selected capacitance
considering is big, voltage
the parasitic unbalance
capacitor during
of the device. Tothe transient
avoid will by
imbalance be
stabilized,
parasitic but switching
capacitor speed
errors of the will attach
devices, decrease and switching
a balancing capacitorlosswithwill increase.
negligible If thecapacitors
parasitic snubber
capacitance
of a device. Ifissnubber
small, capacitance
the snubberis capacitors
big, voltagecannot
unbalanceperform
during proper balancing.
the transient Rsnub
will be works as
stabilized, buta
damping resistor.
switching speed will The inrush current
decrease of the snubber
and switching loss willcapacitor
increase. at
If the
the switching state is limited
snubber capacitance by Rthe
is small, snub.

Therefore,
snubber Rsnub is selected
capacitors cannotby the current
perform proper rating of the snubber
balancing. capacitor.
Rsnub works In addition,
as a damping when The
resistor. calculating
inrush
the Rsnubofvalue,
current the snubber capacitor(𝜏at=the
a time constant 𝑅𝐶) and switching
switching state isfrequency
limited by(fR ) should
swsnub be considered.
. Therefore, A large
Rsnub is selected
time
by theconstant
currentreduces
rating of the switching
the snubberspeed, increases
capacitor. switching
In addition, whenlosses, and alsothe
calculating hinders
Rsnub soft
value,switching
a time
of the LLC
constant converter.
(τ = RC) and switching frequency (fsw ) should be considered. A large time constant reduces
the switching speed, increases switching losses, and also hinders soft switching of the LLC converter.
3. Design of LLC Converter
3. Design of LLC Converter
Figure 4 depicts the series-connected SiC MOSFETs LLC Converter with voltage balancing
Figure 4 depictsthe
circuits. Generally, theoutput
series-connected
capacitanceSiC of MOSFETs
the switchingLLCdevice
Convertershould withbevoltage balancing
considered in thecircuits.
design
Generally, the output capacitance of the switching device should be considered
process. However, in this case, Snubber capacitors are added in parallel with the series-connected in the design process.
However,
devices for in voltage
this case,balancing.
Snubber capacitors
The output arecapacitor
added inshould
parallelbe with the series-connected
discharged during deadtime devicesforfora
voltage balancing. The output capacitor should be discharged during deadtime
sufficient Zero Voltage Switching (ZVS) effect. Therefore, the snubber capacitor should be considered for a sufficient Zero
Voltage Switching an
when designing (ZVS)LLC effect. Therefore,
converter. the snubber
Except for the capacitor
snubber should
capacitor, be considered
the otherswhen processdesigning
of the
an LLC converter.
designed Except for
LLC converter are the snubber
followed bycapacitor,
the generalthe others process ofdesign
LLC converter the designed
processLLC converter
in References
are followed by the general LLC converter design process in References [17,18].
[17,18].

Q1 Q2
+
+
Lr_pri Np : Ns Lr_sec

+ +
Vin iLr_pri iLr_sec
vpri Lm vsec
Vo
- -

Cr
-
-
Q3 Q4

Figure 4. Series-connected
Figure 4. Series-connected devices-based
devices-based LLC
LLC Converter
Converter with
with aa voltage
voltage balancing
balancing circuit.
circuit.

Figure
Figure 55 shows
shows theoretical
theoretical waveforms
waveforms ofof the
the conventional
conventional LLC
LLC converter.
converter. For
For simplifying
simplifying it
it to
to
analyze, some assumptions are made as follows.
analyze, some assumptions are made as follows.
•• There is
There is no
no error
errorofofparasitic
parasiticelements
elementsof ofaaswitching
switchingdevice;
device;
•• Gate drivers are all ideal, and there is no time delay between series-connected devices
Gate drivers are all ideal, and there is no time delay between series-connected devices due
due to
to the
the
gate driver.
gate driver.

The gate signals of devices are off during the deadtime (tdead ) interval. The magnetizing current
and resonant current become the same during the deadtime. During the deadtime, inductor current
flows through the antiparallel diode of the switch and discharges the parasitic output capacitor of the
switch. Then, the switch turns on after zero voltage is formed by the discharged output capacitor so
that soft switching is possible. The equation of minimum deadtime and magnetizing inductance for
soft switching is calculated below.
tdead ≥ 16Coss fsw Lm (2)
Energies 2020, 13, 264 5 of 14

Equation (2) represents that the ZVS is related to the magnetizing inductance of the high
frequency transformer (HF transformer) and the output capacitance of the switch. As mentioned in the
previous section, Snubber capacitors are required for voltage balance between series-connected devices.
Therefore, when manufacturing the LLC converter with balancing circuits that are connected in parallel
to each device, balancing circuits should be considered. This is not a parasitic component of the switch.
After that,
Energies 2020,the
13, rest
x FORprocess design of an LLC converter follows the conventional design process.5 of 15
PEER REVIEW

Figure 5. Switching state and resonant (iLr_pri ), magnetizing current (iLm ) of the transformer.
Figure 5. Switching state and resonant (iLr_pri), magnetizing current (iLm) of the transformer.

Figure 6 shows the equivalent circuit of an LLC converter. To design LLC, the converter is
The gate signals of devices are off during the deadtime (tdead) interval. The magnetizing current
described as follows [3–9].
and resonant current become the same during the N deadtime.
p
During the deadtime, inductor current
n =
flows through the antiparallel diode of the switch and (3)
Ns discharges the parasitic output capacitor of the
switch. Then, the switch turns on after zero voltage is formed by the discharged output capacitor so
Lr +Lm
that soft switching is possible. The equationmof=minimum deadtime and magnetizing inductance (4) for
Lr
soft switching is calculated below.
1
fr = √ (5)
𝑡 16𝐶
2π 𝑓Lr C𝐿r (2)
fsw
Equation (2) represents that the ZVS Fisx related = to the magnetizing inductance of the high (6)
fr
frequency transformer (HF transformer) and the output capacitance of the switch. As mentioned in
2
the previous section, Snubber capacitors are required 8 N for
p voltage balance between series-connected
devices. Therefore, when manufacturing ac, R themin =
LLC converter · ·Ro (7)
π2 Ns2 with balancing circuits that are connected
in parallel to each device, balancing circuits should√be considered. This is not a parasitic component
of the switch. After that, the rest process design Lr /Cr
Qmax =of an LLC converter follows the conventional design (8)
process. R ac,min

whereFigure
Np and 6Nshows
s meansthethe
equivalent
turn ratiocircuit of an LLC converter.
of the transformer and Ro is theTo load
design LLC, theFurthermore,
resistance. converter is
fdescribed
sw is the as follows
switching [3–9].
frequency, fr is the resonant frequency, and the R ac is the reflected load resistance.
Therefore, the voltage gain of the resonant tank isNdefined below.
p
n= (3)
Vo_ac (s)
N s F2x (m − 1)
K= = q (9)
Vinac (s) 2L +L
2
2

2
2 2 2
m·F= x − 1 + Fx Fx − 1 (m − 1) Q
r m
m (4)
Lr
where Vo_ac (s), Vin_ac (s), Q, m, and Fx are the vin_ac , vo_ac , the quality factor, the ratio of the total primary
inductance to resonant inductance, and the 1
fr =normalized switching frequency, respectively. Figure(5) 7
2π
shows voltage gain according to different m and Q factors. L C
r r In the figure, as the m factor decreases, the
voltage conversion ratio is extended. However, according to Equation (4), a low m factor requires low
𝑓
magnetizing inductance Lm . Thus, magnetizing 𝐹 = current increases. It means that the conduction loss (6) of
𝑓
magnetic components is increased. In terms of the Q factor, the Q factor is related to the load. The high
8 𝑁
𝑅 , = ∙ ∙ Ro (7)
π 𝑁

𝐿 /𝐶
𝑄 = (8)
where Vo_ac (s), Vin_ac (s), Q, m, and Fx are the vin_ac, vo_ac, the quality factor, the ratio of the total primary
where Vo_acto
inductance (s),resonant
Vin_ac (s), inductance,
Q, m, and Fxand are the
the vnormalized
in_ac, vo_ac, the quality factor, the ratio of the total primary
switching frequency, respectively. Figure 7
inductance to resonant inductance,
shows voltage gain according to different m and and the normalized
Q factors.switching frequency,
In the figure, as the mrespectively. Figure
factor decreases, the7
shows conversion
voltage voltage gainratio according to different
is extended. m and
However, Q factors.
according toIn the figure,
Equation (4),as the m
a low m factor
factor decreases,
requires lowthe
voltage
magnetizingconversion ratio is extended. However, according to Equation (4), a low
inductance Lm. Thus, magnetizing current increases. It means that the conduction 6loss m factor requires low
Energies 2020, 13, 264 of 14
ofmagnetizing inductanceisLmincreased.
magnetic components . Thus, magnetizing
In terms of current increases.
the Q factor, the QItfactor
means is that
relatedthetoconduction loss
the load. The
of magnetic
high Q valuecomponents
means heavy is increased. In termsand
load conditions of thetheQlow
factor,
Q the Q factor
value meansis light
related to the
load load. The
conditions.
high Q
Therefore, value
Q value means means
heavy load
it is important heavy load
toconditions conditions
and the
set the Q value and
lowrated
at the the
Q value low Q
load.means value
Thus,light means light
load conditions.
a voltage load
gain of an LLC conditions.
Therefore, it is
converter
Therefore,
important it
to is
setimportant
the
is related to m and Q factors.Q value to set
at the
the Q value
rated at
load. the
Thus, rated
a load.
voltage Thus,
gain a
ofvoltage
an LLC gain of
converteran LLC
is converter
related to m
is related to
and Q factors. m and Q factors.

Figure 6. Equivalent circuit of the LLC resonant tank.

Figure
Figure 6. Equivalent circuit
6. Equivalent circuit of
of the
the LLC
LLC resonant
resonant tank.
tank.
2.5 2.5 2.5
M=3 M=6 M=9
2.5 2.5 2.5
2.0 M = 3 2.0 M = 6 2.0 M=9
2.0 2.0 2.0
1.5 1.5 1.5
Q = 0.4
1.5 1.5 1.5
1.0 1.0 1.0 QQ= =0.6
0.4
QQ= =0.8
0.6
1.0 1.0 1.0
0.5 0.5 0.5 QQ= =1.0
0.8
0.5 0.5 0.5 QQ= =2.0
1.0
0.0 0.0 0.0 QQ= =10.0
2.0
0.0 1 0.0 1 0.0 1
Fx1 Fx1 Fx1 Q = 10.0
Fx Fx Fx
Voltagegain
Figure7.7.Voltage
Figure gainaccording differentmmand
accordingtotodifferent andQQfactors.
factors.
Figure 7. Voltage gain according to different m and Q factors.
4. Simulations and Simulation Results
4. Simulations and Simulation Results
4. Simulations
In order to and Simulation
verify Results devices-based LLC converter, simulation was conducted by
the series-connected
In order to verify the series-connected devices-based LLC converter, simulation was conducted
Power InSim (PSIM)
order andthe
to verify Linear Technology spice
series-connected (LTspice). LLC converter, simulation was conducted
by Power Sim (PSIM) and Linear Technologydevices-based
spice (LTspice).
by Power Sim (PSIM) and Linear Technology spice (LTspice).
4.1. Voltage Balancing Simulation
4.1. Voltage Balancing Simulation
4.1. Voltage
Figure Balancing
8 shows the Simulation
simulation circuit of voltage balancing. Table 1 shows the parasitic value
Figure 8 shows
of components the simulation
of experiment circuit
setup of voltage
and Table balancing.
2 shows Table 1value
the parasitic shows of the parasitic
device itself.value of
Voltage
Figure
components 8 shows the
of experiment simulation circuit
setup andby Tableof voltage
2 shows balancing. Table
the parasitic 1 shows the parasitic Voltageof
value
balancing simulation was performed LTspice. Parasitic values ofvalue
devicesof were
device itself.arbitrarily,
added
components
balancing of experiment
simulation setup and Table 2 shows the parasitic value of device itself. Voltage
and voltage balancingwas performed
simulation wasby LTspice. depending
performed Parasitic values of devices
on whether were added
the snubber arbitrarily,
circuit was used.
balancing simulation was performed by LTspice. Parasitic values of devices
and voltage balancing simulation was performed depending on whether the snubber circuit was were added arbitrarily,
and voltage balancing simulation was performed depending on whether the snubber circuit was
used. Table 1. Parameters of the voltage balance test circuit.
used.
Parameters Values
Input voltage (VIN ) 1000 V
Gate driver parasitic inductance (Lg1 ) 1 pH
Gate driver parasitic inductance (Lg2 ) 1.2 pH
Parasitic output capacitance (Coss_1 ) 170 pF
Parasitic output capacitance (Coss_2 ) 100 pF
Inductor (L) 3 mH
Voltage balancing resistor (Rbal ) 1 MΩ
Damping resistor (Rsnub ) 5Ω
Voltage balancing circuits capacitor (Csnub ) 1 nF

Table 2. Parameter of the selected device (C2M0040120D).

Parameters Minimum Type Maximum

Leakage current x 1 µA 100 µA
Output capacitance 150 pF
Energies 2020, 13, 264 7 of 14
Energies 2020, 13, x FOR PEER REVIEW 7 of 15

+ iL

VIN

- Lg1 Gate +
vsw_1 Coss_1
Driver
-
MCU
Lg2 Gate +
Driver vsw_2 Coss_2
-

Figure 8. Multi-pulse
Figure 8. Multi-pulsetest
testcircuit
circuit for voltagebalancing
for voltage balancing simulation.
simulation.

Figure 9 shows the simulation results with

Table 1. Parameters and
of the without
voltage balancing
balance test circuit. circuits. Without balancing
circuits, simulation results show that the voltage balancing between series devices did not converge,
Parameters Values
and the voltage imbalance increased as the inductor current increased. On the other hand, with
Input voltage (VIN) 1000 V
balancing circuits, voltage imbalance is somewhat reduced, and the imbalance range is maintained
Energies 2020, 13, x FOR PEER REVIEW
Gate driver parasitic inductance (Lg1) 1 pH 8 of 15
even with the increased inductor current.
Gate driver parasitic inductance (Lg2) 1.2 pH
720 V 26 A
Parasitic output
vsw_2 capacitance (Coss_1) 170 pFiL
vsw_1
600 V Parasitic output capacitance (Coss_2) 100 pF 22 A

480 V Inductor (L) 3 mH 18 A

360 V Voltage balancing resistor (Rbal) 1 MΩ 14 A

240 V
Damping resistor (Rsnub) 5Ω
10 A
Voltage balancing circuits capacitor (Csnub) 1 nF
120 V 6A

0 Table 2. Parameter of the selected device (C2M0040120D). 2A

Parameters Minimum
(a) Type Maximum
Leakage current x 1 µA 100 µA
720 V 26 A
iL
Output capacitance
vsw_2 150 pF
vsw_1
600 V 22 A

Figure 9 480
shows
V the simulation results with and without balancing circuits. Without
18 A balancing
circuits, simulation results show that the voltage balancing between series devices did not converge,
360 V 14 A
and the voltage imbalance increased as the inductor current increased. On the other hand, with
balancing circuits,
240 V voltage imbalance is somewhat reduced, and the imbalance range 10 A is maintained
even with the increased inductor current.
120 V 6A

0 2A

(b)

Figure
Figure 9. Multi-pulse
9. Multi-pulse testtest simulation
simulation result:(a)(a)
result: withoutbalancing
without balancingcircuits
circuitsand
and(b)
(b)with
withbalancing
balancingcircuits.
circuits.
4.2. LLC Converter Simulation
4.2. LLC Converter Simulation
The LLC converter simulation was conducted on the assumption that voltage imbalance did
TheThe
not occur. LLCsimulation
converter simulation
model iswas conducted
shown on the
in Figure 10.assumption that voltage
Table 3 gives imbalanceof
the parameters didthe
notsystem.
occur. The simulation model is shown in Figure 10. Table 3 gives the parameters of the system. An
An isolated HF transformer can be described as an ideal transformer, magnetizing inductance, and
isolated HF transformer can be described as an ideal transformer, magnetizing inductance, and
leakage inductance in simulation. In Figure 10, the model of the HF transformer of the LLC converter
leakage inductance in simulation. In Figure 10, the model of the HF transformer of the LLC converter
consists of of
consists magnetizing
magnetizingleakage inductanceand
leakage inductance and
anan ideal
ideal transformer,
transformer, whichwhich
has ahas
10:4atransfer
10:4 transfer
ratio. ratio.
Lm means
Lm means thethe
magnetizing
magnetizinginductance ofthe
inductance of thefabricated
fabricated HFHF Lr_secLmeans
transformer.
transformer. r_sec means the secondary
the secondary
side leakage inductance of the HF transformer. Lr_pri means the primary side leakage inductance of
the HF transformer, which is the sum of the leakage inductance of the HF transformer itself and the
added inductance on the outside. In addition, Cr means the resonant capacitor. Resonant capacitors
work as a resonant tank with Lr_pri. Therefore, the resonant frequency of the LLC converter is
determined by the resonant capacitor and the primary leakage inductance of the transformer. Figure
 4.2. LLC Converter Simulation
The LLC converter simulation was conducted on the assumption that voltage imbalance did not
occur. The simulation model is shown in Figure 10. Table 3 gives the parameters of the system. An
isolated HF transformer can be described as an ideal transformer, magnetizing inductance, and
Energiesleakage
2020, 13,inductance
264 in simulation. In Figure 10, the model of the HF transformer of the LLC converter8 of 14
consists of magnetizing leakage inductance and an ideal transformer, which has a 10:4 transfer ratio.
Lm means the magnetizing inductance of the fabricated HF transformer. Lr_sec means the secondary
side leakage inductance
side leakage of the
inductance of HF
the transformer.
HF transformer. Lr_pri means
Lr_pri meansthe
theprimary
primaryside
side leakage
leakage inductance
inductance of of the
HF transformer, which is the sum of the leakage inductance of the HF transformer
the HF transformer, which is the sum of the leakage inductance of the HF transformer itself and the itself and the added
inductance
addedon the outside.
inductance on the In outside.
addition, In Caddition,
r means C the resonant
r means capacitor.
the resonant Resonant
capacitor. capacitors
Resonant work as a
capacitors
resonantwork as with
tank a resonant
Lr_pri . tank with Lthe
Therefore, r_pri. resonant
Therefore,frequency
the resonant frequency
of the of the LLC
LLC converter converter by
is determined is the
resonantdetermined
capacitor byand
the resonant
the primary capacitor
leakage andinductance
the primaryof leakage inductance of
the transformer. the transformer.
Figure 11 shows theFigure
voltage
11 shows
gain curve the voltage
according to thegain curve
load of according
the proposed to theconverter.
load of the proposed converter.

Figure 10. Simulation circuit of series-connected devices based on the LLC converter with a voltage
balancing circuit.

Table 3. Parameters of simulation.

Parameters Values
Input voltage (Vi ) 1000 V
Output voltage (Vo ) 400 V
Power 3000 W
Resonant frequency (fr ) 100 kHz
Switching frequency (fsw ) 100 kHz
HF transformer turn ratio (primary: secondary) 10:4
Primary leakage inductance (Lr_pri ) 129 µH
Primary resonant capacitor (Cr ) 20 nF
Magnetizing inductance (Lm ) 302 µH
Secondary leakage inductance (Lr_sec ) 2.598 µH
Primary resistance (Rpri ) 0.135 Ω
Secondary resistance (Rsec ) 0.110 Ω
Deadtime 500 ns

Figures 12 and 13 show the simulation results of the LLC converter. Figure 12 shows the switching
voltage and channel current of the MOSFETs. In the figure, vds_Q1 , vds_Q2 , vds_Q3 , and vds_Q4 represents
Energies 2020, 13, x FOR PEER REVIEW 9 of 15
the drain to source voltages and iQ1 , iQ2 , iQ3 , and iQ4 represents the current of devices. In the figure,
the channel currents
Figure increasecircuit
10. Simulation after of
the devices are fully
series-connected turned
devices based on. It LLC
on the means ZVS iswith
converter achieved.
a voltageFigure 13
shows thebalancing
input/outputcircuit. voltage and the current of the HF transformer.

K(Q, m, Fx)
16
500 W
14 1.0 kW
1.5 kW
12 2.0 kW
2.5 kW
10 3.0 kW

K 8

0
100
Fx

Figure Voltage
11. 11.
Figure gain
Voltage graph
gain graphofofthe
theLLC
LLC converter according
converter according toto a different
a different load.
load.

Table 3. Parameters of simulation.

Parameters Values
Input voltage (Vi) 1000 V
 Energies 2020, 13, x FOR PEER REVIEW 10 of 15
Energies 2020, 13, 264 9 of 14
Energies 2020, 13, x FOR PEER REVIEW 10 of 15
600 V 30 A
400 V vds_Q1 20 A
600VV
200
iQ1 30AA
10
ZVS ZVS
400 0V vds_Q1 020 A
200 V
iQ1 10 A
ZVS ZVS
0 0
600 V 30 A
400 V vds_Q4 20 A
600VV iQ4 30AA
200 10
ZVS ZVS
400 V
0 vds_Q4 020 A
iQ4
200 V 10 A
ZVS ZVS
0 0
600 V 30 A
400 V vds_Q2 20 A
600VV
200
iQ2 30AA
10
400 V ZVS vds_Q2 ZVS
0 020 A
200 V
iQ2
10 A
ZVS ZVS
0 0
600 V 30 A

400 V vds_Q3 20 A
600VV iQ3 30 A
10 A
200
ZVS ZVS
400 0V vds_Q3 020 A
iQ3 10 A
200 V
ZVS ZVS
0 0

Figure 12. Switching waveform of the drain-source voltage and MOSFET current of the LLC
converter.
Figure
Figure 12. Switching
12. Switching waveform
waveform of drain-source
of the the drain-source voltage
voltage and MOSFET
and MOSFET current
current of the
of the LLC LLC
converter.
converter.
1000 V vpri vpri
500 V
0 vpri vsec vpri vsec
-500 VV
1000
500 V
-1000 V0
vsec vsec
-500 V
15 A
-1000 V iLr_pri ZVS iLr_pri ZVS
7.5 A
15 0A iLr_sec iLr_sec
iLr_pri ZVS iLr_pri ZVS
7.5AA
-7.5
iLr_secZVS iLr_sec ZVS
-15 A0
-7.5 A
ZVS ZVS
-15 A
(a) (b)

1000 V vpri (a) vpri (b)

500 V
1000 0V vpri vsec vpri vsec
-500 V
500 V
-1000 V0 vsec vsec
-500
15 AV
-1000 V iLr_pri ZVS iLr_pri ZVS
7.5 A
15 0A iLr_sec iLr_sec
iLr_pri ZVS iLr_pri ZVS
7.5AA
-7.5
iLr_sec
ZVS iLr_sec ZVS
-15 A0
-7.5 A
ZVS ZVS
-15 A
(c) (d)

1000 V vpri (c) vpri (d)

500 V
1000V 0V vpri vsec vpri vsec
-500
500 V
-1000 V0
vsec vsec
-500 V
15 A
-1000 V iLr_pri ZVS iLr_pri ZVS
7.5 A iLr_sec iLr_sec
15 0A
iLr_pri ZVS iLr_pri ZVS
7.5AA
-7.5 iLr_sec ZVS iLr_sec
ZVS
-15 A0
-7.5 A
ZVS ZVS
-15 A
(e) (f)
Figure
13.13. (e) ofofthe
Simulationresults
results theinput
input voltage
voltage vvpri and output voltage vsec of(f) the transformer and
Figure Simulation pri and output voltage vsec of the transformer and
resonant
resonant current of the primary side i Lr_pri and secondary side iLr_sec: (a) simulation at 500 W, (b)
iLr_privoltage iLr_sec : (a)
Figurecurrent of the primary
13. Simulation results of side
the input and secondary side voltage
vpri and output simulation
vsec of at 500and
the transformer W, (b)
simulation
resonant current of the primary side iLr_pri and secondary side iLr_sec: (a) simulation at 500 W, (b)and
at 1000 W, (c) simulation at 1500 W, (d) simulation at 2000 W, (e) simulation at 2500 W,
(f) simulation at 3000 W.
 Energies
Energies 2020,
2020, 13,13, x FOR
x FOR PEER
PEER REVIEW
REVIEW 11 11
of of
15 15

simulation
simulation at at 1000
1000 W,W,(c)(c) simulation
simulation at at 1500
1500 W,W,
(d)(d) simulation
simulation at at 2000
2000 W,W,
(e)(e) simulation
simulation at at 2500
2500 W,W,
and (f) simulation at 3000
and (f) simulation at 3000 W. W.
Energies 2020, 13, 264 10 of 14

5. 5. Experiments
Experiments andand Experimental
Experimental Results
Results
5. Experiments
TheThe andcircuit
proposed
proposed Experimental
circuit verified
verified Results
byby simulation
simulation was
was tested
tested through
through experiments.
experiments. Figure
Figure 1414 shows
shows
thetheexperimental
Theexperimental configuration
proposed configuration
circuit verified ofbyofsimulation
thetheproposed
proposed
was LLCLLCconverter
tested converter
through usinga a1200-V
using
experiments. 1200-V
FigureSiCSiC
14 MOSFET
MOSFET
shows the
(C2M0040120D,
(C2M0040120D, Cree)
Cree) and
experimental configuration and 1200-V
1200-V
of the proposed SiC
SiCLLC Schottky
Schottky Diode
converterDiode (C4D20120D,
using a(C4D20120D, Cree). Experimental
Cree). (C2M0040120D,
1200-V SiC MOSFET Experimental
specifications
specifications
Cree) areare
and 1200-V SiCshown
shown in in
Schottky Table
Table 3. 3.
Diode Before
Before thethe
(C4D20120D, verification
verification of of series-connected
series-connected
Cree). Experimental devices
devices
specifications based
based
are onon
shown inan
an
LLCLLC
Table 3.converter,
converter,
Before thea verification
multi-pulse
a multi-pulse test
test
of is is conducted
conducted
series-connected to to verify
verify voltage
voltage
devices balancing
basedbalancing
on an LLC between
between series-connected
series-connected
converter, a multi-pulse
devices.
devices.
test is conducted to verify voltage balancing between series-connected devices.

Full Full Bridge

Bridge Rectifier
Rectifier

Series
Series connected
connected
Full Full Bridge
Bridge Converter
Converter

Resonant
Resonant capacitor
capacitor

HF Transformer
Leakage
Leakage inductor HF Transformer
inductor

Figure
Figure 14. Hardware
14.14.
Figure Hardware configuration
Hardware forfor
configuration
configuration for aa series-connected
series-connected LLC
a series-connected converter.
LLC
LLC converter.
converter.

5.1. Voltage Balancing Experiment

5.1.
5.1. Voltage
Voltage Balancing
Balancing Experiment
Experiment
Voltage imbalance was tested through a multi-pulse test. The experimental setup is shown in
Voltage
Voltage imbalance
imbalance was
was tested
tested through
through a multi-pulse
a multi-pulse test.
test. TheThe experimental
experimental setup
setup is is shown
shown in in
Figure 8. The experiment parameters are represented in Table 1.
Figure
Figure 8. 8.
TheThe experiment
experiment parameters
parameters areare represented
represented in in Table
Table 1. 1.
Figure 15 shows the experimental results without balancing circuits and with balancing circuits.
Figure
Figure 1515 shows
shows thethe experimental
experimental results
results without
without balancing
balancing circuits
circuits and
and with
with balancing
balancing circuits.
circuits.
Compared with the simulation results, the trend tends to be different. In the simulation, the factor
Compared
Compared with
with thethe simulation
simulation results,
results, thethe trend
trend tends
tends to to
bebe different.
different. InIn
thethe simulation,
simulation, thethe factor
factor of of
of voltage imbalance reflects the unbalance of the device’s parasitic and the delay of the gate signal.
voltage imbalance reflects the unbalance of the device’s parasitic and the
voltage imbalance reflects the unbalance of the device’s parasitic and the delay of the gate signal. delay of the gate signal.
However, according to Reference [12], the parasitic capacitor from gate to ground one of the important
However,according
However, accordingto toReference
Reference[12], [12],thetheparasitic
parasiticcapacitor
capacitorfrom fromgategateto toground
groundone oneofofthethe
factors contribute to a voltage imbalance. In addition, this factor was not reflected in the simulation.
important
important factors
factors contribute
contribute to to a voltage
a voltage imbalance.
imbalance. InIn addition,
addition, this
this factor
factor waswasnotnot reflected
reflected in in
thethe
Although practical experiments, with the parasitic capacitors considered from gate to ground, the
simulation. Although practical experiments, with the parasitic capacitors considered from gate to to
simulation. Although practical experiments, with the parasitic capacitors considered from gate
voltage imbalance converges to a steady state through snubber circuits selected by simulation. It
ground,thethevoltage
ground, voltageimbalance
imbalanceconverges
convergesto toa asteady
steadystatestatethrough
throughsnubber
snubbercircuits
circuitsselected
selectedbyby
means that, if the unbalance voltage does not exceed the rated voltage of the switch, the switch can be
simulation.
simulation. It It means
means that,
that, if if
thethe unbalance
unbalance voltage
voltage does
does notnot exceed
exceed thethe rated
rated voltage
voltage ofofthethe switch,
switch,
regarded as a stable operation with selected balancing circuits by simulation.
the switch can be regarded as a stable operation with selected balancing
the switch can be regarded as a stable operation with selected balancing circuits by simulation. circuits by simulation.
vsw_1
vsw_1 vsw_1
vsw_1

vsw_2
vsw_2 vsw_2
vsw_2

iL iL iL iL

200V/div
200V/div 200V/div
200V/div
10A/div 10A/div
10A/div 100100 us/div
10A/div 100100 us/div
us/div us/div

(a)(a) (b)(b)
Figure
Figure
Figure 15.15.
15. Experimental
Experimental
Experimental results
results
results ofof
of thethe voltage
voltage imbalance
imbalance
imbalance test:
test:
test: (a)(a)
(a) without
without
without balancing
balancing
balancing circuits
circuits
circuits and
and
and (b)(b)
(b)
with balancing
with balancingcircuits.
circuits.
with balancing circuits.

5.2. Double
5.2. Pulse
Double Test
Pulse Test
5.2. Double Pulse Test
As mentioned in the previous section, an added snubber circuit for voltage balancing slows down
switching speed and increases switching loss. In this section, a Double Pulse Test (DPT) was conducted
Energies 2020, 13, x FOR PEER REVIEW 12 of 15

As mentioned in the previous section, an added snubber circuit for voltage balancing slows
Energies 2020, 13, 264 speed
down switching and increases switching loss. In this section, a Double Pulse Test (DPT)11 of
was14

conducted to analyze switching losses with and without snubber circuits. The experimental setup is
shown
to in Figure
analyze 16 and
switching parameters
losses with andare shownsnubber
without in Tablecircuits.
4. Balancing snubber parameters
The experimental setup isare shown
shown in
in Table 1.
Figure 16 and parameters are shown in Table 4. Balancing snubber parameters are shown in Table 1.

Energies 2020, 13, x FOR PEER REVIEW 12 of 15

As mentioned in the previous section, an added snubber circuit for voltage balancing slows
down switching speed and increases switching loss. In this section, a Double Pulse Test (DPT) was
conducted to analyze switching losses with and without snubber circuits. The experimental setup is
shown in Figure 16 and parameters are shown in Table 4. Balancing snubber parameters are shown
in Table 1.

(a) (b)
Figure 16. Double pulse test circuits: (a) without balancing circuits and (b) with balancing circuits.

Table 4. Parameters of the double pulse test.

Parameters Values
Input voltage (VIN ) 500 V
Inductor (L) 1.5 mH

DPT was conducted (a) when the DC-link is 500 V. Figure 17 shows DPT (b) results. According to
Figure 17, both turn-on and turn-off losses increased with snubber circuits. However, the proposed
Figure 16. Double pulse test circuits: (a) without balancing circuits and (b) with balancing circuits.
LLC converter operates ZVS turn-on at all loads. The turn-on loss can be negligible.

(a) (b)
Figure 17. Switching loss comparison according to the switch current: (a) without balancing circuits
and (b) with balancing circuits.

Table 4. Parameters of the double pulse test.

Parameters Values
Input voltage (VIN) 500 V
Inductor (L) 1.5 mH
(a) (b)
DPT was
Figure
Figure 17. conducted
Switching
17. Switching losswhen
loss the DC-link
comparison
comparison is 500
according
according to V.switch
to the
the Figure
switch 17 shows
current:
current: DPT results.
(a) without
(a) without According
balancing
balancing circuits to
circuits
Figure
and17,
and (b)both
(b) withturn-on
with balancingand
balancing turn-off losses increased with snubber circuits. However, the proposed
circuits.
circuits.
LLC converter operates ZVS turn-on at all loads. The turn-on loss can be negligible.
5.3. LLC Converter Experiment Table 4. Parameters of the double pulse test.
5.3. LLC Converter
Based Experimentcircuit’s value selected through simulations and a multi-pulse test, the
on the balancing
Parameters Values
series-connected
Based on thedevices based
balancing on thevalue
circuit’s LLC selected
converter experiment was conducted. Figure 18test,
shows
Input voltage (VIN) 500 simulations
through V and a multi-pulse the
the main waveforms of the proposed LLC converter according to the load. In the
series-connected devices based on the LLC converter experiment was conducted. Figure 18 showsfigure, vpri and vsec
represent input/output voltage of the Inductor
HF (L) iLr_pri
transformer, 1.5 and
mHiLr_sec represent input/output current
the main waveforms of the proposed LLC converter according to the load. In the figure, vpri and vsec
of the HF transformer,
represent input/outputaccording
voltage oftothe
theHF
load. As showniLr_pri
transformer, in the previous
and section, input/output
iLr_sec represent experimentalcurrent
results
DPT was conducted when the DC-link
were well matched with simulation results. is 500 V. Figure 17 shows DPT results. According to
Figure 17, both turn-on and turn-off losses increased with snubber circuits. However, the proposed
LLC converter operates ZVS turn-on at all loads. The turn-on loss can be negligible.

5.3. LLC Converter Experiment

Based on the balancing circuit’s value selected through simulations and a multi-pulse test, the
series-connected devices based on the LLC converter experiment was conducted. Figure 18 shows
Energies 2020, 13, x FOR PEER REVIEW 13 of 15

of the HF transformer, according to the load. As shown in the previous section, experimental results
Energies 2020, 13, 264 12 of 14
were well matched with simulation results.

(a) (b)

(c) (d)

(e) (f)

Figure 18.
Figure 18. Experimental
Experimental results
results of
of the
the input
inputvoltage
voltagevvpri and output
pri and output voltage
voltage vvsec transformer and
sec of transformer and
resonant current
resonant current of
of the
theprimary
primarysidesideiLr_pri secondary side
iLr_pri and the secondary side iiLr_sec
Lr_sec. . (a)
(a)Simulation
Simulationat at 500
500 W,
W, (b)
simulation at
simulation at1000
1000W,
W,(c)(c)simulation
simulationatat 1500
1500 W,W,
(d)(d) simulation
simulation at 2000
at 2000 W, simulation
W, (e) (e) simulation at 2500
at 2500 W,
W, and
and
(f) (f) simulation
simulation at 3000
at 3000 W. W.

Figure 19 shows vvqs_1

Figure qs_1 vqs_2
, ,vqs_2 , and
, and vgs vat at the
gs the rated
rated power. vqs_1, vvqs_1
power. vqs_2 represent
qs_2 ,represent the to
the drain drain to
source
source
voltagevoltage
of eachofdevice
each device
connected connected
in series in at
series at the power.
the rated rated power.
VoltageVoltage balancing
balancing between between
series-
series-connected
connected devicesdevices
did notdid not diverge,
diverge, and both and both switches
switches connectedconnected
in series had in series had ZVS
achieved achieved ZVS
operation.
operation. Figure 20 shows the efficiency of series-connected devices-based
Figure 20 shows the efficiency of series-connected devices-based LLC converter. The maximum LLC converter. The
maximum efficiency
efficiency was was at
measured measured
the ratedatload.
the rated load.
Energies 2020,
Energies 2020, 13,
13, 264
x FOR PEER REVIEW 14
13 of 14
15
Energies 2020, 13, x FOR PEER REVIEW 14 of 15

vq3_1
vq3_1
vgs
vgs
vq3_2
vq3_2

iLr_pri
iLr_pri

200V/div
10A/div 2 us/div
200V/div
10A/div 2 us/div

Figure 19. Experimental results of series-connected devices voltage vq3_1, vq3_2, and vgs at the rated load.
Figure 19. Experimental results of series-connected devices voltage vq3_1 , vq3_2 , and vgs at the rated load.
Figure 19. Experimental results of series-connected devices voltage vq3_1, vq3_2, and vgs at the rated load.
96 94.85 95.12
96 94.26 95.12
94 93.1 94.85
94.26
94 93.1
92 91.18
(%)(%)

92 91.18
90
Efficiency

90
88
Efficiency

88
86 85.11
86 85.11
84
84
82
82
80
500 1000 1500 2000 2500 3000
80
500 1000 1500 power
Output 2000
(W) 2500 3000
Output power (W)
Figure
Figure 20. Efficiency of
20. Efficiency of series-connected
series-connected devices-based
devices-based LLC
LLC converter.
converter.
Figure 20. Efficiency of series-connected devices-based LLC converter.
6. Conclusions
6. Conclusions
6. Conclusions
This paper describes the design consideration of the fixed frequency LLC converter considered
This paper describes the design consideration of the fixed frequency LLC converter considered
balancing circuitdescribes
This paper of series-connected
the design devices circuit. In thefixed
consideration introduction, the reason for theconsidered
imbalance
balancing circuit of series-connected devices circuit.ofInthe frequency
the introduction, theLLC converter
reason for the imbalance
voltage across
balancing theofseries-connected
circuit devices was described theand discussed the the need of an LLC converter.
voltage across the series-connected
series-connecteddevices
devicescircuit.
was In introduction,
described and discussed reason
the for
needtheofimbalance
an LLC
The proposed
voltage converter consists of a series-connected devices-based LLC converter.
converter. The proposed converter consists of a series-connected devices-based LLC converter. LLC
across the series-connected devices was described and discussed the need of an
In order
converter. Theto verify the
proposed proposed
converter converter,
consists a series-connected
of a series-connected devices-based
devices-based LLCvoltage balancing
converter.
In order to verify the proposed converter, a series-connected devices-based voltage balancing
experiment
In orderand the series-connected
to verify devices-based
the proposed converter, LLC converter
a series-connected was performed.
devices-based Thebalancing
voltage snubber
experiment and the series-connected devices-based LLC converter was performed. The snubber
circuit, which
experiment is
and the simplest
thesimplest method
series-connected among the
devices-basedvarious LLC methods for
converter voltage balancing,
was performed. was applied
circuit, which is the method among the various methods for voltage balancing,The wassnubber
applied
and thewhich
circuit, switching
is theloss comparison
simplest methodand voltage
among the balancing
various test wasfor
methods performed accordingwas
voltage balancing, to snubber
applied
and the switching loss comparison and voltage balancing test was performed according to snubber
circuits.
and Furthermore,
the switching based on the snubber
loss comparison voltagecircuits-designed simulation and experiments, 3 kW
circuits. Furthermore, based on theand snubber balancing test was
circuits-designed performed
simulation according
and to snubber
experiments, 3 kW
series-connected
circuits. devices-based
Furthermore, LLC
based onLLC converter
the converter was fabricated
snubber circuits-designed and verified. Through the experiments,
series-connected devices-based was fabricated andsimulation and experiments,
verified. Through 3 kW
the experiments,
the voltage balancing
series-connected between series-connected
devices-based LLC converter was devices and soft
fabricated andswitching operationthe
verified. Through of the proposed
the voltage balancing between series-connected devices and soft switching operation of experiments,
the proposed
converter
the voltage are verified.
balancing The
betweenefficiency of a
series-connectedfabricated
devices converter
and soft was measured
switching 95.12%
operation of at 3proposed
the kW load.
converter are verified. The efficiency of a fabricated converter was measured 95.12% at 3 kW load.
When the
converter series-connected based LLC converter is fabricated with balancing snubber circuits, it is
When theare verified. The efficiency
series-connected based LLC ofconverter
a fabricated converter with
is fabricated was measured
balancing 95.12%
snubberatcircuits,
3 kW load.it is
confirmed
When that the LLC converter
the series-connected based LLCdesign is necessary
converter considering
is fabricated the balancing
with balancing snubber,
snubber and itthe
circuits, is
confirmed that the LLC converter design is necessary considering the balancing snubber, and the
experimental
confirmed results
that the confirm
LLC that the
converter consideration
design is necessaryis valid.
considering the balancing snubber, and the
experimental results confirm that the consideration is valid.
experimental results confirm that the consideration is valid.
Author Contributions: D.Y. implemented the system and conducted the experiments. Y.C. managed the paper.
Author
S.L. Contributions:
assisted D.Y. implemented
the idea simulation thewriting.
and the paper system and conducted
All authors havethe
readexperiments.
and agreedY.C.
to themanaged theversion
published paper.
Author
of the
S.L. Contributions:
manuscript.
assisted D.Y. implemented
the idea simulation the system
and the paper and conducted the experiments. Y.C. managed the paper.
writing.
S.L. assisted the idea simulation and the paper writing.
Funding: The
Funding: The Human
Human Resources Program in
Resources Program in Energy
Energy Technology
Technology ofof the
the Korea
Korea Institute
Institute of
of Energy
Energy Technology
Technology
Evaluation
Funding:
EvaluationTheand Planning
andHuman
Planning (KETEP)
Resources supported
(KETEP)Program
supported in this work,
Energy
this which
which granted
Technology
work, of theaa financial
granted Korea resource
Institute
financial resourceof from the
Energy
from Ministry
Ministry of
theTechnology of
Trade, Industry & Energy, Republic of Korea. (NO. 20194030202370) and the Human Resources Program in Energy
Evaluation and Planning
Trade, Industry (KETEP)
& Energy, supported
Republic of Korea. this(NO.
work, which granted aand
20194030202370) financial resource
the Human from the Program
Resources Ministry ofin
Trade,
EnergyIndustry & Energy,
Technology Republic
of the Korea of Korea.
Institute (NO. 20194030202370)
of Energy and the and
Technology Evaluation Human Resources
Planning Program
(KETEP) in
granted
Energy Technology of the Korea Institute of Energy Technology Evaluation and Planning (KETEP) granted
Energies 2020, 13, 264 14 of 14

Technology of the Korea Institute of Energy Technology Evaluation and Planning (KETEP) granted financial
resource from the Ministry of Trade, Industry & Energy, Republic of Korea. (Grant No. 20174010201540).
Conflicts of Interest: The authors declare no conflict of interest.

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