MANIPAL UNIVERSITY JAIPUR

SCHOOL OF AUTOMOBILE, MECHANICAL &

MECHATRONICS ENGINEERING

DEPARTMENT OF MECHATRONICS ENGINEERING

INTEGRATED ELECTRONICS LAB

MCE2231

LAB MANUAL
Department of Mechatronics Engineering MCE2231 Integrated Electronics Lab
Department of Mechatronics Engineering MCE2231 Integrated Electronics Lab
 Department of Mechatronics Engineering
Lab Evaluation Report
Name of Laboratory : Integrated Electronics Lab Lab Code:
MCE2231
Student Name : Reg. No. Batch :
Exp. Exp. Name Page Date of Date of Attendance Record Performance Viva Total Remarks
No. No. allotment performance (01) (02) (03) (04) (10)

01
02
03
04
05
06
07
08
09
10
11
12
13
14

Total Marks: Marks Obtained : Normalized Marks (out of 60 Marks):

 Integrated Electronics Lab Manual – MCE2231

List of Experiments

Experiment name
S. No.

Design and Implement an Inverting and Non-inverting amplifier using Op Amp 741
1
a) Implement a voltage follower circuit using Op Amp 741
2 b) Design and Implement a summing amplifier using Op Amp 741

a) Design and Implement a difference amplifier circuit using Op Amp 741

3 b) Design and Implement a comparator using Op Amp 741

Design and Implement a Butterworth Low Pass and High Pass Filter using Op-Amp for the given
4 cut-off frequency and obtain its frequency response

Design a Schmitt Trigger using Op Amp 741 and verify its output
5

6 Design and Implement Astable Multivibrator using Timer IC 555 for the given time period

7 Study of Implementation of Logic Gates.

8 Study of Implementation of Arithmetic Circuits.

9 Code Converter Circuits

10 Multiplexers and De-multiplexers

11 Encoder and Decoder

12 Study of Flip Flops

13 Counters

14 Digital to Analog converter

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The Breadboard
The breadboard consists of two terminal strips and two bus strips (often broken in the centre). Each
bus strip has two rows of contacts. Each of the two rows of contacts are a node. That is, each contact
along a row on a bus strip is connected together (inside the breadboard). Bus strips are used primarily
for power supply connections, but are also used for any node requiring a large number of
connections. Each terminal strip has 60 rows and 5 columns of contacts on each side of the centre
gap. Each row of 5 contacts is a node. You will build your circuits on the terminal strips by inserting
the leads of circuit components into the contact receptacles and making connections with 22-26
gauge wire. There are wire cutter/strippers and a spool of wire in the lab. It is a good practice to wire
+5V and 0V power supply connections to separate bus strips.

Fig. 1 : The breadboard-The lines indicate connected holes

The 5V supply MUST NOT BE EXCEEDED since this will damage the ICs (Integrated circuits)
used during the experiments. Incorrect connection of power to the ICs could result in them exploding
or becoming very hot - with the possible serious injury occurring to the people working on the
experiment! Ensure that the power supply polarity and all components and connections are correct
before switching on power.

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Building the Circuit:

Throughout these experiments we will use TTL chips to build circuits. The steps for wiring a circuit
should be completed in the order described below:

1. Turn the power (Trainer Kit) off before you build anything!
2. Make sure the power is off before you build anything!
3. Connect the +5V and ground (GND) leads of the power supply to the power and ground bus
strips on your breadboard.
4. Plug the chips you will be using into the breadboard. Point all the chips in the same direction
with pin 1 at the upper-left corner. (Pin 1 is often identified by a dot or a notch next to it on
the chip package)
5. Connect +5V and GND pins of each chip to the power and ground bus strips on the
breadboard.
6. Select a connection on your schematic and place a piece of hook-up wire between
corresponding pins of the chips on your breadboard. It is better to make the short connections
before the longer ones. Mark each connection on your schematic as you go, so as not to try to
make the same connection again at a later stage.
7. Get one of your group members to check the connections, before you turn the power on.
8. If an error is made and is not spotted before you turn the power on. Turn the power off
immediately before you begin to rewire the circuit.
9. At the end of the laboratory session, collect you hook-up wires, chips and all equipment and
return them to the demonstrator.
10. Tidy the area that you were working in and leave it in the same condition as it was before you
started.

Common Causes of Problems:

1. Not connecting the ground and/or power pins for all chips.
2. Not turning on the power supply before checking the operation of the circuit.
3. Leaving out wires.
4. Plugging wires into the wrong holes.
5. Driving a single gate input with the outputs of two or more gates
6. Modifying the circuit with the power on.

In all experiments, you will be expected to obtain all instruments, leads, components at the
start of the experiment and return them to their proper place after you have finished the
experiment. Please inform the demonstrator or technician if you locate faulty equipment. If you
damage a chip, inform a demonstrator, don't put it back in the box of chips for somebody else to
use.

Example Implementation of a Logic Circuit:

Build a circuit to implement the Boolean function F = (A’.B’)’, please note that the
notation A’ refers to . You should use that notation during the write-up of your
laboratory experiments.

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Fig. 2: Quad 2 Input 7400 Fig. 3: Hex 7404 Inverter

Fig 4. The complete designed and connected circuit

Sometimes the chip manufacturer may denote the first pin by a small indented circle above the
first pin of the chip. Place your chips in the same direction, to save confusion at a later stage.
Remember that you must connect power to the chips to get them to work.

Discussion of Gate parameters

Analog signal is defined as one whose amplitude is proportional to the quantity it represents. As
this signal is continuous in time it has an infinite set of possible values.

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A digital signal is one that represents between two discrete levels of voltage. These changes
are abrupt. The most positive fixed voltage represents 1 state and the most negative fixed
voltage represents 0 state.
Logic gates are the most basic type of digital circuit which consists of two or more inputs and
one output. A gate can be used alone to perform a logic function. It can also be connected to
several other gates to form a logic network.
Each type of basic logic gate is assigned with a symbol that has a distinct shape so that it can be
distinguished from others and symbolically represent a logic gate.
A truth table is a formal specification that describes the exact circuit output behavior for every
possible set of inputs. Truth tables are also called function tables.
In most situations logic signals applied to the inputs of logic gates are not stationary levels.
Instead they are voltages that change continually between two states. To illustrate how logic
gates, respond to input logic signals in relation to time, timing diagrams are used. It is a plot
of signal values/ amplitude Vs time.
An IC (integrated circuit) is a miniature chip of silicon or germanium on which an entire
electronic circuit consisting of resistors, capacitors, diodes and transistors are built. When
combined, these components are capable of performing many functions which include logic
gate operations.
Several types of IC packages are available. A very popular package is DIP which stands for
dual in – line package. “Dual in – line” means that the pins are positioned in a line on both
sides of the IC package. The most common IC‟s have 8, 14, 16, 24 or 40 pins, which are
numbered in a counter clockwise direction when viewed from the top. Pin number 1 is located
next to an indentation or dot placed on the body of the IC package

To operate properly power must be supplied to the pin labeled VCC and ground must be
connected to the pin labeled GND. Most of the pins are used as input and output connections
for the circuitry.
The available digital IC‟s may be classified as – TTL (transistor – transistor logic) family,
CMOS (complementary metal oxide semiconductor) family and ECL (emitter coupled logic)
family. As most widely used gates have their equivalent CMOS gates sometimes it may
suffice to conduct experiments only on TTL gate.
VIHmin(VILmin) is the minimum input voltage used to represent a logic high (logic low).
VIHmax (VILmax) is the maximum input voltage used to represent a logic high (logic low).
VOHmin(VOLmin) is the minimum output voltage used to represent a logic high (logic low).
VOHmax (VOLmax) is the maximum input voltage used to represent a logic high (logic low).
Determination of VOL, VOH, VIL & VIH of an inverter:
Consider a inverter. If VIN = 0V dc then VOUT = +5V dc and if VIN = +5V dc then VOUT =
0V dc. A typical TTL inverter is composed of a number of transistors, resistors and diodes
and as a result the inverter output voltage levels depart somewhat from ideal values of +5 and
0 V dc. To establish acceptable operating limits, the manufacturer will list on data sheets the
maximum, minimum and typical values for the output levels (Fig 5).

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When the inverter output is at logic level 1, the manufacturer guarantees the output voltage in
this high state will be somewhere in the band labeled VOH. The maximum voltage VOHmax
is +5V dc and the minimum voltage is given as VOHmin in the data sheet. Most inverter
circuits have a logic 1 output level VOHtypical , near the middle of the high level band. If the
measured VOH is not within the limits specified VOHmin and VOHmax the IC must be
replaced as it is considered as defective. When the inverter output is at logic level 0, the
manufacturer guarantees the output voltage in this low state will be somewhere in the band
labeled VOL. The minimum voltage VOLmin is 0V dc and the maximum voltage is given as
VOLmax in the data sheet. Most inverter circuits have a logic 0 output level VOLtypical ,
near the middle of the ow level band. If the measured VOL is notwithin the limits specified
VOLmin and VOLmax the IC must be replaced as it is considered as defective.
Except when switching from one state to the other, the inverter output voltage level must be
either in the high band or in the low band. The transition region is therefore a forbidden
output voltage region except for the short time required for the inverter output to switch from
one voltage level to the other. Since the output of an inverter may be used as the input to
another inverter or for any other TTL logic circuits, limits must be placed on the input voltage
levels to ensure that all TTL logic circuits are compatible with one another.
For an inverter input to be at logic level 0, it must be somewhere in the band labeled VIL. The
minimum voltage VILmin is 0V dc and the maximum voltage is given as VILmax in the data
sheet. If the applied VIL is within the limits specified VILmin and VILmax then the output
will go to High state (Fig 6). For an inverter input to be at logic level 1, it must be somewhere
in the band labeled VIH. The maximum voltage VIHmax is +5V dc and the minimum voltage
is given as VIHmin in the data sheet. If the applied VIH is within the limits specified VIHmin
and VIHmax then the output will go to Low state (Fig 6).

Fig 5: TTL output levels

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Fig 6:TTL input levels

The unwanted spurious signals generated in the connecting wires due to stray electric and
magnetic fields is known as noise. This voltage obviously appears at the input of a gate. If the
input spurious signal has a large magnitude, it may change the output of a gate falsely thereby
causing error. The ability of the circuit to tolerate (maximum noise voltage that can appear at the
input without producing a change in the output state) noise voltages on its input is known as noise
immunity and measure of it is known as noise margin. Usually IC manufacturers give dc values of
noise margins giving both low and high values. High state noise margin is V NH = VOHmin – VIHmin
and Low state noise margin is VNL = VILmax – VOLmax.

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Determination of Noise margin for a NAND gate: Consider the following circuit shown in Fig7.
Tabulate the various voltages and calculate noise margin using the below formula.

When output is high VNH = VOHmin – VIHmin and when output is low VNL = VILmax – VOLmax.

Fig 7:Circuit to determine noise margin of TTL NAND gate.

IOH – HIGH LEVEL OUTPUT CURRENT – the current that flows from an output in a logic 1
state under specified load conditions.
IOHmax – It is the maximum current that the driver gate can source when it is in a 1 state
IOL – LOW LEVEL OUTPUT CURRENT – the current that flows from an output in a logic 0 state
under specified load conditions.
IOLmax –It is the maximum current that the driver gate can sink when its output is a logic 0. I IL
– LOW LEVEL INPUT CURRENT – the current that flows into an input when a specified
Low level voltage is applied to that input.
IIH – HIGH LEVEL INPUT CURRENT – the current that flows into an input when a specified
High level voltage is applied to that input.
The number of inputs a logic gate is designed to handle is termed as FAN IN. FAN OUT is the
ability of a logic gate to drive number of inputs of other logic gates of the same type. HIGH state
FAN OUT = IOHmax / IIH. & LOW state FAN OUT = IOLmax / IIL
Determination of FAN OUT for a NAND gate:

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Fig 8 & 9: FAN OUT for a NAND gate Circuit to determine fan out of TTL NAND gate
Consider the circuit shown in Fig 8 and 9. Keeping the driving gate output at low, keep connecting gates
to the output of this gate as shown in Fig 8 and measure maximum value of IOL by an ammeter.
Connecting additional gates may be stopped when the output of the driving gates changes its logical level.
As such the FAN OUT may be evaluated. Similarly keep the driving gate output high as shown in Fig 4b
and measure the maximum value of IOH. Calculate FAN OUT using the formula -
HIGH state FAN OUT = IOHmax / IIH & LOW state FAN OUT = IOLmax / IIL
NOTE: In few cases FAN OUT for HIGH state and LOW state may be same. If they are not same
then lower of the two values is taken as FAN OUT.
When an input signal is applied to a logic gate certain amount of time elapses before the signal
shows up at the output. The time elapsed is known as propagation delay.

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Determination of propagation delay: Consider an inverter. Apply a square wave input of known
amplitude and frequency (say amplitude of 5V and frequency of 10kHz). Observe the waveform
at the output terminal using a CRO and measure the propagation delay.
Manufacturers specify two delays namely tPLH (propagation delay when the output voltage
switches from low to high) and tPHL (propagation delay when the output voltage switches from
high to low).
The delays defined are between the 50% amplitude points on the input and output pulse
waveform.

Fig 10: Determination of propagation delay

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Useful IC numbers and descriptions:

IC Number Description
7400 Quad 2-NAND Gate
7402 Quad 2-NOR Gate
7404 Hex Inverter
7406 Hex Inverter, buffer
7408 Quad 2-AND gate
7410 3 input NAND gate
7411 Triple 3-AND gate
7413 Dual 4-NAND Schmitt
Trigger
7414 Hex Schmitt Trigger Inverter
7420 4 input NAND gate
7427 Triple 3-NOR gate
7432 Quad 2-OR Gate
7447 BCD-Segment Decoder
7473 Dual JK negative edge
triggered flip-flop
7474 Dual D F/F
7476 Dual J-K F/F
7483 4-bit Full adder
7485 4-Bit Magnitude Comparator
7486 Quad 2-X-OR Gate
7490 Decade Counter
7491 8-Bit Shift Register
7492 Divide by 12 Counter
7493 4-bit Binary Ripple Counter
7495 4-Bit Shift Register
74112 Dual J-K F/F with preset and
clear
74121 Mono-stable Multi-vibrator
74123 Dual Mono-stable Multi-
vibrator
74125 Quad 3-state buffer
74138 Decoder
74139 Dual 1:4 De-MUX/Decoder
74147 10:4 Priority Encoder
74148 Priority encoder, Octal to
Binary
74151 8:1 MUX
74153 Dual 4:1 MUX

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74154 1:16 DMUX

74157 Quad 2:1 MUX
74164 8 bit shift register
74180 8 bit parity generator
74192 Resettable Counter
74193 4 bit binary counter
74194 Shift Register
74283 4 bit binary adder
74365 Buffer/ Driver
DAC 0808 Digital to Analog Converter
ADC0804/09 Analog to Digital Converter
CD 4040 12 stage binary counter
CD4017 5 stage Jonson Counter
CD 4011 Quad 2 NAND gate
CD 4027 Dual JK flip-flop
7410 Triple 3-input NAND Gate
74138 Negative edge triggered dual
J-K F/F
74180 Parity Generator
7473 Dual J-K negative edge
triggered Flip Flop
74157 Quad 2:1 MUX

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Experiment 1
Aims & Objectives:
(a) Design and implement an inverting amplifier using Op Amp 741 for the given gain.
(b) Design and implement a non-inverting amplifier using Op Amp 741 for the given gain.
Equipment & Accessories Required:
CRO, Function Generator, Power Supply, Multimeter, Bread Board, and CRO probes.
Components Required: Resistors, Op Amp IC 741.
Inverting Amplifier:
The inverter is the basic building block of any circuit. This is perhaps the most widely used of all the
Op Amp circuits. The circuit of inverting amplifier is shown in Fig.1.1. The output voltage 𝑣𝑜 is
feedback to the inverting input terminal through the resistor 𝑅𝐹 and 𝑅1 network. Input signal 𝑣𝑖 (ac) is
applied to the inverting input terminal through R1 and non-inverting input terminal of Op Amp is
grounded. For simplicity let us assume an ideal Op Amp. As 𝑣𝑑 = 0, node ‘a’ is at virtual ground
potential. Writing nodal equation at point ‘a’ yields;
𝑣 𝑣
𝑖𝑖 + 𝑖𝑓 = 0, 𝑅𝑖 + 𝑅𝑜 = 0
1 𝐹
𝑅𝐹
𝑣𝑜 = − 𝑅 𝑣𝑖 RF (1)
1
𝑖𝑓
R1 2 +VCC=15V
a - 7
𝑖1 𝑖𝑖 = 0 6
Vi A VO
+ 4
3
-VEE= -15V
Fig. 1.1 Inverting Amplifier

Vi

VO
𝑡

Fig.1.2 Input & Output waveforms

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Non-inverting Amplifier:

If a signal (ac) is applied to the non-inverting input terminal and feedback is given as shown in
Fig.1.3, the circuit amplifies the input signal without inverting it. Such a circuit is called non-inverting
amplifier. It may be noted that it is also a negative feedback system as output is being fed back to the
inverting input terminal.

As the differential input voltage 𝑣𝑑 at the input terminal of Op Amp is zero, the voltage at node ‘a’ in
Fig.1.3 is 𝑣𝑖 , same as the input voltage applied to non-inverting input terminal. Now 𝑅𝐹 and 𝑅1 forms
a potential divider. Writing nodal equation at point a yields;
𝑣 𝑣 −𝑣 𝑣 𝑣 𝑣
𝑖1 = 𝑖𝑓 , 𝑅𝑖 = 𝑜𝑅 𝑖, 𝑅𝑖 + 𝑅 𝑖 = 𝑅𝑜
1 𝐹 1 𝐹 𝐹
𝑅𝐹
𝑣𝑜 = {1 + 𝑅 } 𝑣𝑖 (1)
1

RF
𝑖𝑓
R1 a 2 +VCC=15V
- 7
𝑖1 𝑖𝑖 = 0
A 6
VO
+ 4
3
Vi -VEE= -15V

Fig. 1.3 Non-inverting Amplifier

Vi
t

VO
t

Fig.1.4 input & output Waveforms

Procedure:
1. Rig up the circuit on the breadboard.
2. Apply the given inputs and observe the corresponding output voltages on CRO, keeping the
Frequency of the input signal fixed.
3. Draw the input and output waveforms on tracing paper.
4. Change the practical values of resistors R1 & RF for variable the gain and observe the output.
5. Calculate the gain for various values of R1 & RF.
6. Plot the outputs waveform for various values of RF on the graph paper for a fixed value of R1.

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Observations:
Inverting Amplifier:
S No. Resistors Input Output Gain Comment
R1 RF Voltage Frequency Voltage
1. 1k 1k 10mV 1kHz
2. 1k 2.2k 20mV 1kHz
3. 1k 3.0k 30mV 1kHz
4. 1k 5.1k 40mV 1kHz
5. 1k 6.2k 50mV 1kHz
6. 1k 8.2k 60mV 1kHz
7. 1k 10k 70mV 1kHz

Non-inverting Amplifier
S No. Resistors Input Output Gain Comments
R1 RF Voltage Voltage
1. 1k 1k 10mV
2. 1k 2.2k 20mV
3. 1k 3.0k 30mV
4. 1k 5.1k 40mV
5. 1k 6.2k 50mV
6. 1k 8.2k 60mV
7. 1k 10k 70mV
Calculations:

Gain Calculation: Inverting Amplifier:

Non Inverting Amplifier

Comments and Discussions:

QUESTIONS:
1. What do you mean by an Operational Amplifier?
2. How do you differentiate between an ideal Op Amp from a Practical Op Amp?
3. Why the pin no.1 & 5 N.C. for 741 IC?
4. How the circuit behaves if RF = R1 in a non-inverting configuration?

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Experiment 2
Aims & Objectives:
(a) Implement a voltage follower circuit using Op Amp 741 and calculate its voltage gain.
(b) Design and implement a summing amplifier (adder circuit) for at least three inputs using
Op Amp 741 for the given gain.
Equipment & Accessories Required:
CRO, Function Generator, Power Supply, Multimeter, Bread Board, and CRO probes.
Components Required:
Resistors, Op Amp IC 741.

(a) Voltage follower:

A voltage follower is a circuit which uses Op Amp in non-inverting configuration with gain equal to
unity. The circuit is as shown in Fig. 2.1.
𝑣
𝑣𝑖 − 𝑣𝑜 = 𝐴0 ≅ 0 as A→∞
𝑣𝑜 = 𝑣𝑖 (1)

2 +VCC=15V
− 7
A 6
3 VO
+ 4
-VEE=-15V
Vi

Fig.2.1 Voltage follower

This circuit turns out to be a very useful service, because the input impedance of the op amp is very
high, giving effective isolation of the output from the signal source. We draw very little power from
the signal source, avoiding "loading" effects. The voltage follower is often used for the construction
of buffers for logic circuits.

Vi
t

VO
VO=Vi
t

Fig. 2.2 Input & Output waveforms for voltage follower

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(b) Summing Amplifier:

Op Amp may be used to design a circuit whose output is the sum of several input signals. Such a
circuit is called a Summing Amplifier.
Inverting Summing Amplifier:
A typical summing amplifier with three input voltages 𝑣1 , 𝑣2 and 𝑣3 , three input resistors 𝑅1 , 𝑅2 , 𝑅3
and a feedback resistor 𝑅𝐹 is shown in Fig.2.3 The following analysis is carried out assuming that the
Op Amp is an ideal one, that is, AOL = ∞ and 𝑅𝑖 = ∞. Since the input bias current is assumed to be
zero, there is no voltage drop across the resistor Rcomp and hence the non-inverting input terminal is
at ground potential. Writing nodal equation at the summing point ‘S’ yields;
𝑣1 𝑣 𝑣 𝑣
+ 𝑅2 + 𝑅3 + 𝑅𝑜 = 0
1𝑅 2 3 𝐹
𝑅𝐹 𝑅 𝑅
𝑣𝑜 = − {𝑅 𝑣1 + 𝑅𝐹 𝑣2 + 𝑅𝐹 𝑣3 } = −{𝑣1 + 𝑣2 + 𝑣3 }, For RF = R1 = R2 = R3. (1)
1 2 3

RF
S
R1 R2 R3
𝑖1 𝑖3 +VCC=+15V
𝑖2 𝑖𝑓
2 − 7 6
V1 V2 V3 𝑣𝑂
A
3
+ 4
V1
R4 -VEE=-15V

Fig.2.3 Summing Amplifier

Vi
t
10mV
20mV
30mV
60mV
VO 60mV

-60mV
Fig. 2.4 Input and Output waveforms
Procedure:
For Summing Amplifier:
1. Rig up the circuit as shown in the Fig.2.3 on the breadboard.
2. Apply the given inputs and observe the output on CRO.
3. Calculate the amplitude & frequency of the output and draw it using graph paper.
4. Vary the values of inputs to vary the gain and observe the output.
5. Calculate the gain for various values of inputs.
6. Draw inputs and output waveforms for various inputs on the tracing paper as in Fig.2.4.
For Slew Rate:

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1. Rig up the circuit as shown in the Fig.2.3 on the breadboard.

2. Apply the sine input and increase the frequency.
3. Trace the output and input voltage to indicate different rate in the output voltage.
3. Calculate the gain.
4. Vary the inputs (square & triangular wave) and observe the frequency & amplitude.

Observation Table:
For Summing Amplifier: R1 = R2 = R3 = RF and fixed frequency of 1kHz.

S No. Input Voltage Frequency Output Voltage Gain

1.
2.
3.
4.
:

For Voltage Follower:

S No. Resistors Input Output

R1 RF Voltage Frequency Voltage Frequency

1.
2.
3.
Gain Calculation:
Inverting Summing Amplifier:
Gain = - RF (V1/R1+V2/R2+V3/R3) = - (V1+V2+V3) for RF = R1 = R2 = R3.
For Voltage follower
Gain= Output voltage/input voltage = 1.

Comments and Discussions:

Questions:
1. What is slew rate? What will be the value of slew rate for ideal Op Amp?
2. What do you mean by CMRR & PSRR?
3. What is the operating temperature of 741 IC for Military & Industrial Applications?
4. What are the different applications of summing amplifier?
5. What is the practical value of Slew Rate for 741 IC?

Advance Experiment: Design and implement a non-inverting summing amplifier (adder circuit) for
five inputs using Op Amp 741 for the given gain.

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Experiment 3
Aims & Objectives:
(a) Design and implement a difference amplifier (Subtractor) circuit using Op Amp 741 for the
given gain.
(b) Design and implement a comparator using Op Amp 741 and verify the output.
Equipment & Accessories Required:
CRO, Function Generator, Power Supply, Bread Board, Multimeter, and CRO probes
Components Required: Resistors, Op Amp IC 74.
Difference Amplifier:
A difference amplifier or subtractor circuit is shown in Fig.4.1. Here, input signals can be scaled to
the desired values by selecting appropriate values for the resistors. When this is done, the circuit is
referred to as scaling amplifier. However, in this circuit all external resistors are of equal value. So
the gain of amplifier is equal to one. The output voltage 𝑣𝑜 is equal to the voltage applied to the non-
inverting terminal minus the voltage applied to the inverting terminal; hence the circuit is called a
subtractor.
𝑅3 𝑣2
𝑣+ = 𝑅 𝑣2 = for R2 = R3.
2 +𝑅3 2
Writing node equation at the inverting input terminal yields;
𝑣1 −𝑣− 𝑣𝑜 −𝑣− 𝑣2
+ = 0, 2𝑣− = 𝑣 0 + 𝑣1 , 𝑣0 + 𝑣1 = 2𝑣 + = 2 = 𝑣2 for R1 = RF.
𝑅1 𝑅 𝐹 2
𝑣0 = 𝑣2 − 𝑣1 (1)
RF

R1 +VCC=+15V
𝑣1 − 7 𝑖𝑓
𝑖1 2
𝐴 𝑣𝑂
R2 6
𝑣2 3 + 4
𝑖2 -VEE=-15V
R3

Fig. 4.1 Difference amplifier

Comparator:
A comparator finds its importance in circuits where two voltage signals are to be compared and to be
distinguished on which is stronger and in the design of non-sinusoidal waveform generators as
relaxation oscillators. In an Op Amp with an open loop configuration having a differential or single
input signal greater than 0V, the high gain which goes to infinity drives the output of the Op Amp into
saturation. Thus, an Op Amp operating in open loop configuration will have an output that goes to
positive saturation or negative saturation level or switch between positive and negative saturation
levels and thus clips the output above these levels. This principle is used in a comparator circuit with
two inputs and an output. The 2 inputs, out of which one is a reference voltage (Vref) is compared
with each other.
A non-inverting 741 IC Op Amp comparator circuit is shown in the figure below with the input and
output waveforms.

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Protection Diodes +VCC

+
R1 A Vout

- RL
Vi
R -VEE
Vref = 1V

Fig. 4.2 Comparator Circuit

Vin
Vin +Vp
+Vp
VREF 1V t
t 0
0 -VREF -1V
-Vp
-Vp Vin>VREF
Vin>VREF +VAST
+VAST
VOUT 0 t
VOUT 0 t
-VAST -VAST
Vin<VREF Vin<VREF
Fig. 4.3 Input and output Waveform

Procedure:
1. Connect the circuit as per the diagram.
2. Apply the supply voltages of +15V to pin7 and -15V to pin4 of IC741 respectively.
3 Apply the inputs V1 and V2.
4. Apply two different signals to the inputs.
5. Vary the input voltages and note output at pin 6 of the IC 741 subtractor circuit.
6. Notice that the output is equal to the difference of the two inputs.

Calculations:
Comments and Discussions:
Questions:
1. Reduce a comparator to zero crossing detector.
2. What is the expected output wave shape if the input is a triangular wave?

Advance Experiment: Design and implement an instrumentation amplifier using op-amp.

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Experiment 4
Aims & Objectives:
(a) Design and implement a Butterworth Low Pass Filter using Op Amp 741 for the given cut-
off frequency and obtain its frequency response.
(b) Design and implement a Butterworth High Pass Filter using Op Amp 741 for the given
cut-off frequency and obtain its frequency response.
Equipment & Accessories Required:
CRO, Function Generator, Power Supply, Bread Board, Multimeter, Connecting wires, and
CRO probes.
Components Required:
Resistors, Capacitors, Op Amp IC 741.
Theory:
A filter segregates between two types of matters. Similarly, electric filter segregates the voltage
between different ranges of frequencies. A low-pass filter allows low-frequency signal components
(including direct current) to be transmitted, while high-frequency components up to definite range
(including infinite ones) are blocked. The range of low frequencies, which are passed, is called
the pass band or the bandwidth of the filter. The sharpness of the transition from stop band to pass
band can be controlled to some degree during the design.
The ideal low-pass filter response can be approximated by a rational function approximation scheme
such as the Butterworth response. The Butterworth filter is also called maximally flat or flat-flat filter.

Active Filters employ transistors, more appropriately Op – Amps in addition to that of resistors and
capacitors. Active filters have the following advantages over passive filters: (1) Flexible gain and
frequency adjustment, (2) No loading problem (because of high input impedance and low output
impedance), and (3) More economical than passive filters. A Second Order Low Pass Butterworth
filter uses RC networks for filtering. Note that the Op Amp is used in the non-inverting configuration;
hence it does not load down the RC network. Resistors RF and R1 determine the gain of the filter. Fig.
7.1 shows a second order LPF with a roll off of -40dB/decade.

dB
𝑣𝑜 ሺ𝑠ሻ
3dB
𝑣𝑖 ሺ𝑠ሻ
40dB/decade

1=0dB 
0.1c c

Fig. 7.1 10dB/decade and 20 dB/decade Roll off of LPF

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C4
𝑣𝑖 +
𝑣1 K 𝑣𝑜
R1 R2 C3
−

R RF RL

Fig. 7.2 second order Butterworth LPF

The gain magnitude equation of the Low Pass filter can be obtained by converting equation into its
equivalent polar form, as follows.
2
𝐾𝜔𝑝
𝑣𝑜
= 𝑠2 +𝑠ሺ3−𝐾ሻ𝜔 2
𝑣𝑖 𝑝 +𝜔𝑝
1 1 𝜔𝑝 1 𝑅𝐹
𝜔𝑝 = 𝜔𝐻 = 𝑅𝐶 = 𝑅 , 𝑄𝑝 = ሺ3−𝐾ሻ𝜔 = ሺ3−𝐾ሻ, 𝐾 = 1 +
1 𝑅2 𝐶3 𝐶4 𝑝 𝑅
𝑣𝑜 𝐴𝑜 2
= 𝑠2 +𝜔 2 for k = 3, and 𝐾𝜔𝑝 = 𝐴𝑜
𝑣𝑖 𝐻
The operation of the low – pass filter can be verified from the gain magnitude equation.
𝑣
At very low frequencies, that is f < fH, | 𝑣𝑜 | = 𝐴𝑜
𝑖

𝑣𝑜 𝐴𝑜
At f = fH, | 𝑣 | = = 0.707𝐴𝑜
𝑖 √2
𝑣
At f > fH, | 𝑣𝑜 | < 𝐴𝑜
𝑖

Thus the Low Pass filter has a constant gain 𝐴𝑜 from 0 Hz to the almost high cut-off frequency,
fH, it has the gain 0.707𝐴𝑜 at exactly fH, and after fH, it decreases at a constant rate with an
increase in frequency. The gain decreases 40 dB (= 20𝑙𝑜𝑔102 ) each time the frequency is increased
by 10. Hence, the rate at which the gain rolls off after fH is 40 dB/decade. The frequency f = fH is
called the cut-off frequency because the gain of the filter at this frequency is down by 3 dB (=20log
0.707) from 0 Hz. Other equivalent terms for cut-off frequency are -3dB frequency, break frequency,
or corner frequency.

C1 C2 R4
𝑣𝑖 𝑣1 +
K 𝑣𝑜
R3
−

R RF RL

Fig. 7.3 second order Butterworth HPF

Second Order High Pass Filter consists of RC networks for filtering. Second Order High Pass filter
can be constructed from a Second Order Low Pass filter simply by interchanging frequency

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determining components R & C. The operation of the high–pass filter can be verified from the gain
magnitude equation.
𝑣
1. At very low frequencies, that is f < fL, | 𝑣𝑜 | < 𝐴𝑜
𝑖
𝑣𝑜 𝐴𝑜
2. At f = fL, | 𝑣 | = = 0.707𝐴𝑜
𝑖 √2
𝑣
3. At f > fL, | 𝑣𝑜 | = 𝐴𝑜
𝑖

Procedure:
1. Connect the components/equipment as shown in the circuit diagram.
2. Set Vi = 1V & fi =50Hz using function generator.
3. Vary the input frequency in regular intervals, note down the output voltage.
4. Calculate the gain (Vo/Vin) and Gain in dB = 20 log (Vo/Vin) at every frequency.
5. Plot the frequency response curve (taking frequency on X-axis & Gain in dB on Y-axis) using
Semi log Graph.
6. Find out the high cut-off frequency, fH (at Gain= Constant Gain, Ao – 3 dB) from the
frequency response plotted.
7. Repeat steps 1 to 5 for high pass filter and find out the high cut-off frequency, fH (at Gain=
Constant Gain, Af – 3 dB) from the frequency response plotted.

S. Frequency Input Output Voltage gain Gain in dB

No. (Hz) Voltage (Vi) voltage (Vo) Av=Vo/Vi = 20 log (Av)
1 1.0V
2 1.0V
3 1.0V
4 1.0V
5 1.0V

High Pass Filter:

S. Frequency Input Output Voltage gain Gain in dB

No. (Hz) Voltage (Vi) voltage (Vo) Av=Vo/Vi = 20 log (Av)
1 1.0V
2 1.0V
3 1.0V
4 1.0V
5 1.0V

Calculations:
Let C2 = C3 = C as 0.1f, thus calculate R2=R3=R.
Gain, {1+(RF/R1)} = 1.586 to get Butterworth response. Hence choose a value of R1  100k and
calculate the value of RF.

Error in cut-off frequency = (theoretical cutoff- practical cutoff)/ theoretical cutoff

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Comments and Discussions:

Questions:
1. How filters are classified? Give one example for each classification.
2. What is an active filter and why it is called so?
3. How an active filter differs from a passive filter?
4. What are the advantages of active filters over passive filters?

Advance Experiment: Design and implement a first order low pass filter so that it has a cutoff
frequency of 2 kHz and a pass band gain of 1.

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Experiment 5
Aims & Objectives: Design a Schmitt Trigger using Op Amp 741 and verify its output.
Equipment & Accessories Required:
CRO, Function Generator, Power Supply, Bread Board, Multimeter, Connecting wires and
CRO probes.
Components Required: Resistors, Capacitors, Op Amp IC 741.
Schmitt Trigger:
Theoretically, if the loop gain - βAOL is adjusted to unity, then the gain with feedback, 𝐴𝑣𝑓 becomes
infinite. In practical circuits, however, it may not be possible to maintain loop-gain exactly equal to
unity for a long time because of supply voltage and temperature variations. So a value greater than
unity is chosen. This also gives an output waveform virtually discontinuous at the comparison
voltage. This circuit, however, now exhibits a phenomenon called hysteresis or backlash. Fig 9.1
shows a regenerative comparator. The circuit is also known as Schmitt trigger. The input voltage is
applied to the (-) input terminal and the feedback to the (+) input terminal. The input voltage Vi
triggers the output Vo every time it exceeds certain voltage levels. These voltage levels are called
upper threshold voltage (VUT) and lower threshold voltage (VLT). The hysteresis voltage (Vhy) is the
difference between these two threshold voltages i.e. VUT - VLT. These threshold voltages are calculated
as follows.
Upper threshold voltage, VUT = {R1 / (R1 + RF)} (+Vsat)
Lower threshold voltage, VLT = {R1 / (R1 + RF)}(-Vsat)
Hysteresis voltage, Vhy = VUT - VLT = {R1 / (R1 + RF)}(+Vsat-(-Vsat)

Fig.9.1 Schmitt Trigger

VO VO
VOH Vi VOH
VTH

0 t VI
VIL VIH
VTL
VOL
VOL
Fig.9.2 Input & Output waveforms

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PROCEDURE:
1. Rig up the circuit as shown in the Fig.9.1 on the breadboard.
2. Apply the input & observe the output on CRO.
3. Calculate the amplitude & frequency of the output.
4. Plot the outputs waveforms on the graph paper.

Observation Table
S. No. Input voltage R1 R2 Output voltage
VLT VUT
1.
2.

Calculation:
Calculate the values of R1 and R2 using the relationships as follows:
VUT = {R1 / (R1 + RF)} (+ Vsat)
VLT = {R1 / (R1 + RF)} (- Vsat)

Calculate the hysteresis voltage using

Vhy = VUT - VLT = {R1 / (R1 + RF)}( (+Vsat -(-Vsat))

Comments and Discussions:

Questions:
1 What is the other name of Schmitt trigger?
2 Schmitt trigger is which type of comparator?
3 What is the maximum output voltage values?
4 What do you mean by hysteresis loop?

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Experiment 6
Aims & Objectives:
Design and implement Astable Multivibrator using Timer IC 555 for the given time period.
Equipment & Accessories Required:
CRO, Function Generator, Power Supply, Bread Board, Digital Multimeter, Connecting wires
and CRO probes.
Components Required: Resistors, Op Amp IC 741,
Theory:
For the circuit shown in Fig. 11.1, if the diode is not connected, the discharging time period for the
capacitor is given as;
T1 = 0.693 R2C
And the charging time period of the capacitor is
T2 = 0.693 (R1+R2)C
Thus the total time period of the output wave is T = T1 + T2.

+5V
0.1K 8 4
R1 Reset
VCC
0.1K 7
Discharge 3
Output
R2 6 Threshold
0.1K
555
Trigger
2
C Ground Control
1 5 0.01F

Fig. 11.1 Astable Multivibrator Circuit

VC

(2/3)VCC

(1/3)VCC
t

VO
VCC

th tL
t
T
Fig. 11.2 output waveforms

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To reduce the output to a square wave with T1 =T2, the diode is connected with R1 = R2. The diode
remainsshort resulting in the charging time of T2 = 0.693 R1C.
Thus for different duty cycles, the following relationships between the resistances R1 and R2 should
be achieved:
T1 < T2 if R1 < R2
T1 > T2 if R1 > R2
T1 = T2 if R1 = R2
Procedure:
1. Connect the circuit as shown in the Fig.11.1 on the breadboard.
2. Observe and sketch the voltage waveform at pin-3 and that across the capacitor.
3. Measure the frequency and duty cycle of the output waveform.
4. Plot the output on the graph/trace paper.

Observation Table:

tON tOFF
Theoretical
Observed

Calculations:
For the given duty cycle calculate the value of R1 & R2 using the formula,
Toff = 0.69 R2C
Ton = 0.69 R1C
T =Ton+ Toff = 0.69 (R1+R2).C
And duty cycle, D = R1/R1+R2

Comments and Discussions:

Reference:
Questions:
1. Explain the function of reset in 555 timer IC.
2. What are the other modes of operation of timer?
3. Discuss some applications of timer in Astable mode.
4. Define duty cycle.
5. How is an Astable multivibrator connected into a pulse position modulator?

Advance Experiment: Design and implement an astable multivibrator having an output frequency of
10 kHz with a duty cycle of 25 %.

Advance Experiment: Design and implement Monostable Multivibrator using Timer IC 555 for the
given pulse width.

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Experiment 7
Study of Implementation of Logic Gates and Arithmetic Circuits

1. Design and study of Logic Gates and Boolean expressions

Aim:

• To get familiarization with IC trainer kit.

• To verify the characteristics of logic gates.

• To realize basic logic functions using universal gates.

• To construct and test simple combinational circuits.

Equipments and components required:

• Ics – 7400, 7402, 7408, 7432, 7486.

• IC trainer kit and pat

Study of Universality of NAND and NOR gates

• Basic Logic functions using NAND gate:

a) NOT Gate using NAND gate:

Fig. No. 1.1

b) AND gate using NAND gate:

Fig. No. 1.2

c) OR gate using NAND gate:

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Fig. No. 1.3

Basic Logic function using NOR gate:

a) NOT Gate using NOR gate:

Fig. No. 1.4

b) AND Gate using NOR gate

Fig. No. 1.5

c) OR gate using NOR gate

Fig. No. 1.6

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Experiment 8
Study of Implementation of Arithmetic Circuits.

Aim:To design, implement and test

i) Half adder
ii) Half subtractor
iii) Full adder
iv) Full Subtractor.
v) To study 4-bit
parallel adder -
IC 7483
Equipments & Components Required:

• ICs 7408, 7432, 7404, 7400, 7486, 7410, 7483 • IC trainer kit, Connecting wires

i) Half adder: A half adder circuit adds two bits to give the sum and carry outputs.

Table 2.1: Truth Table of Half Adder Fig. 2.1 Half Adder

ii) Half Subtractor

Table 2.2: Truth Table of Half Subtractor

Fig. 2.2: Half Subtractor Circuit

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iii) Full adder: Full adder adds two bits and also another bit called carry-in that is
propagated from the previous stage. In effect, a full adder adds three bits to give out two
outputs – sum and carry out. A, B and Cin are the three inputs, out of which Cin is to be
considered as carry propagated from the previous stage. S and Cout are the three outputs.

Table 2.3: Truth Table of Full Adder

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Fig. 2.3: Full Adder Circuit

iv) Full Subtractor

Table 2.4: Truth Table of Full

Subtractor

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Fig. 2.4 : Full Subtractor

Circuit
v) 4 –bit Binary full adder (IC 7483): The 7483 adds two 4-bit binary words plus the
incoming carry .This contains 4 inter connected full adder and a look ahead carry
adder circuit. Sum outputs are S3 to S0, the out-going carry is Cout.

Fig. 2.5: Pin Diagram of IC 7485 (4-Bit binary full adder)

Procedure:
• Connect Vcc and Ground to the respective pins.

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• Connect A3-A0 and B3–B0 to logic input switches.

• Connect Cout, S3-S0 to logic output LEDs.
• Give the inputs and note down the outputs.

4 Bit adder / 2’s complement Subtractor

Fig. 2.6: Pin diagram / circuit for 4-bit 2’complement adder Method:

• When control input is 0, input B = b3 b2 b1 b0 is added to input A = a3 a2 a1 a0.

• When control input is 1, 2’s complement of B is added to input A. (i.e., A – B) Difference is
available at S3 S2 S1 S0, borrow output at Cout.

• BCD adder:

When two 4 bit BCD numbers are added, if the sum exceeds 9 or if there is a carry ,then 6 is
added to the sum and a carry is generated to the next decimal digit. Carry from the addition of 6
(if any) is neglected.

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Fig. 2.7: BCD adder Circuit

Exercises:

1. Implement half adder circuit using only NOR gates.

2. Implement half Subtractor using only NAND gates.
3. Implement full adder using two half adder circuits and one OR gate.
4. Implement full Subtractor using two half Subtractors and any additional gate.
5. Implement BCD Subtractor using 7483 IC with result in 10‟s complement notation.
6. Design a 4bit XS-3 ADDER using 7483IC.

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EXPERIMENT 9

CODE CONVERTERS CIRCUITS

Aim:To design and implement the following code converters:

A. 4-bit Binary to Gray code

B. BCD to Excess-3 code
C. BCD to 7-segment code

Equipments & Components Required:

• ICs 7408, 7411, 7432, 7404, 7400, 7486, 7447, 7730

• IC trainer kit, Connecting wires

A. 4-bit Binary to Gray code:

Table 4.1: Truth table for 4-bit binary to grey code converter grey code converter

Fig. 4.1: 4-bit Binary to Gray code

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Implement above circuit and verify the truth table

B. BCD to Excess-3 converter:

Excess-3 code is obtained by adding 3 to BCD number
First draw the truth table and then using K-map, get expression for each of Excess-3 bits.

Table 4.2: Truth tale of BCD to grey code converter

Implement the above expressions and verify the truth table. C.

BCD to 7-segment code conversion:

A seven segment indicator is used for displaying decimal digits 0 through 9.

IC 7447 is BCD to seven segment decoder/ driver

IC 7730 is seven segment displays

Refer data sheet for LED type (Common cathode or anode)

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Fig. 4.2: Seven Segment Display (IC 7730)

Fig. 4.3: BCD to Seven Segment Display decoder circuit diagram Exercises:

Design the following converters:

1. 4-bit Gray code to binary

2. 2421 BCD to 8421 BCD

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EXPERIMENT 10
Multiplexers and De-multiplexers
MULTIPLEXERS – A multiplexer or data selector is a logic circuit that accepts several data
inputs and allows only one of them at a time to get through the output. The routing of the desired
data input to the output is controlled by SELECT inputs. The multiplexer acts like a digitally
controlled multi position switch. The digital code applied to the SELECT inputs determines which
data input to be switched to the output.
DEMULTIPLEXER – A de-multiplexer or data distributor is a circuit that receives information
on a single line and transmits this information on one of the 2n possible output lines. The selection
of a specific output line is controlled by n selection lines. A decoder can function as de-
multiplexer if enable line is taken as data input.

Aim:

• To design and implement various multiplexer circuits and to generate logic

functions using multiplexers.
• To design and implement De-multiplexers.

Components and Equipment Required:

ICs 74151, 74153
• Basic gates, universal gates IC trainer kit, connecting wires

i) 4:1 Multiplexer using only NAND gates

Logic Symbol

Fig. 6.1 - Logic Symbol

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Fig. 6.2- Logic Diagram

Truth Table Table 6.1- Truth Table of MUX

S1 S0 Y
0 0 D0
0 1 D1
1 0 D2
1 1 D3

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74153 – Dual 4:1 Mux 74151 – 8:1 Mux 74157 – Quad 2:1 Mux

Note:
• Pin no.16 = Vcc, pin no.8 = GND for all the three ICs.
• For pin-details of the ICs, refer data manual.
• Test all the three ICs by giving appropriate inputs and observing the corresponding
outputs. Thus verify the functional tables of these ICs.

ii) Implement f = ∑m (0, 3, 5, 7, 8, 10, 14) using i) 8:1 MUX ii) 4:1 MUX and
additional gates

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Table 6.2

Fig. 6.3 Fig. 6.4

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iii) Design a 1 to 4 De-multiplexer using basic gates

Fig. 6.5- Logic Diagram Table 6.3

Exercises:
1. Implement full adder using 4:1 MUX and 8:1 MUX
2. Implement F = ∑ m ( 0,5,7,11,15,16,18,25,29 ) using two 8:1 and one 2:1 MUX

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EXPERIMENT 11

ENCODERS AND DECODERS

ENCODER – An encoder has 2n(or less)input lines and n output lines. The output lines generate
the binary code for 2n inputs.

DECODER – It is a logic circuit that converts an N-bit binary input code into M output lines such
that only one line is activated for each one of those possible combinations of inputs. Aim:
• To design and implement Decoders and Encoders.

Components and Equipments Required:

• ICs 74139, 74138, 74154, 74148
• Basic gates, universal gates
• IC trainer kit, connecting wires

i) Design and implement 2 to 4 decoder using basic gates:

Fig. 7.1- Logic Diagram

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Table 7.1

ii) Design and implement 2 to 4 decoder with enable input using only NAND gates

Fig. 7.2- 2 to 4 decoder using NAND Gate Table 7.2

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EXPERIMENT 12

STUDY OF FLIP-FLOPS
Aim:
• To study the operations of SR Flip-flop, D Flip-flop, JK Flip-flop, T Flip-flop.
• To study the IC –7474 & IC – 7473.

Components and Equipment Required:

ICs 7400, 7473, 7474
• IC trainer kit, connecting wires
• Cathode Ray Oscilloscope
Note: Refer the IC data manual, draw the block & pin diagram of ICs 7473 & 7474.

i) SR Flip-flop using NAND gates:

Fig. 8.1

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ii) JK Flip-Flop using NAND gates:

Fig. 8.2

iii) T-Flip Flop using NAND gates:

Fig. 8.3

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EXPERIMENT 13

COUNTERS
Aim:
• To design and test 4-bit Synchronous up counter using IC7473.
• To test Johnson and Ring counters.

Components and Equipment Required:

ICs 7408, 7473, 7474
• IC trainer kit, connecting wires
• Cathode Ray Oscilloscope

Note: Refer the IC data manual, draw the block & pin diagram of ICs 7473 & 7474.

i) 4-bit Synchronous up – counter: Excitation

Table of J K Flip-Flop:

• In the Excitation table shown above Qnand Qn+1 are present and next state outputs. For a
4 bit counter, it is required to count from 0 to 15, which requires 4 J K Flip-Flops.
• Let the outputs of these Flip-Flops be QD,QC,QB,QArespectively and JA,KA be the inputs
of Flip-Flop A. JB,KB of Flip-Flop B & so on. State Table:

Draw K-maps for various Js & Ks and simplify. Implement the logic circuit and verify.
NOTE: To implement the circuit, two nos. of 7473 and one no. of 7408 ICs are required.
For IC7473 : Vcc is pin 4, Gnd is pin 11

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For IC7408 : Vcc is pin 14 , Gnd is pin 7

Fig. 13.1

Procedure:
1. Connect the circuit.
2. Momentarily clear all the inputs by giving Cr = 0 & then make it permanently high by giving
Cr = 1.
3. Verify the circuit by observing the output for each clock pulse. After the 15th clock pulse (i.e.
for the 16th clock pulse) output DCBA = 0000

Tabular Column: Table . 13.1

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EXPERIMENT 14

Digital to Analog Converter

Aim:

• To design R-2R Ladder type Digital to Analog Converter

• To design binary weighted type Digital to Analog Converter
Most physical variables are analog in nature. Quantities such as temperature, pressure and
weight can have an infinite number or values. Converting an analog value to a digital
equivalent (binary number) is called digitizing the value. Such operation is performed by an
Analog-to-Digital Converter (ADC). After processing the digital data, it is often necessary to
convert the results of such operation back to analog values; this function is performed by a
Digital-to-Analog converter (DAC).

A DAC having a 4-bit input produces only 24 = 16 different analog output voltages,
corresponding to the 16 different values that can be represented by the 4-bit input, The output
of the converter is, therefore, not truly analog, The greater the number of input bits, the
greater the number tile output values and the closer the output resembles a true analog
quantity. Resolution is a measure of this property.

The above can also be said about the ADC except that the output will determine its resolution
instead of the input.

Procedure
* R-2R Ladder DAC: Figure 8.1 illustrates a simplified approach to DAC (4-bit). The
buffer op-amp is used to provide a high impedance to the R-2R ladder.
1. Find analytically the output (Vo) in terms of D0, D1, D2 and D3.
2. Design a 4-bil, R-2R ladder DAC whose full-scale output voltage is -10 V. Logical levels
are 1 (+5 V) and 0 (0 V).
3. Find the output for the following binary combination 1010, 1110, 0001, 0101, and 1100.

Fig. 14.1 R-2R Ladder DAC

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A Simplified version of A/D Converter

There are a number of methods to perform analog-to-digital conversion. The fastest is the
flash and the modified flash because the signal is processed in a parallel fashion. The
successive approximation is widely used but it is not faster than the flash. Figure below
shows a simplified version of the flash-type ADC.

Fig. 14.2 A simplified version of the Flash-type ADC

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