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DIGITAL LOGIC DESIGN

NUMBER SYSTEM

Presented by
Mr. K.M.D.Rajesh babu,
Assistant Professor,
Department of ECE, Vemu Institute of Technology

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MODULE–III
NUMBERSYSTEMS
Number systems: Complements of Numbers,
Codes- Weighted and Non-weighted codes and its
Properties, Parity check code and Hamming code.

Boolean Algebra: Basic Theorems and Properties,

Switching Functions- Canonical and Standard Form,
Algebraic Simplification, Digital Logic Gates, EX-OR
gates, Universal Gates, Multilevel NAND/NOR
realizations

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• Number System is a way to represent the numbers in the

computer architecture. There are four different types of the
number system, such as:

 Binary number system (base 2)

 Octal number system (base 8)
 Decimal number system(base 10)
 Hexadecimal number system (base 16).

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BINARY OCTAL DECIMAL HEXA DECIMAL

Has 2 symbols Has 8 symbols Has 10symbols Has 16 symbols

Symbols are 0,1 Symbols are Symbols are from Symbols are from
0,1,2,3,4,5,6 and7 0-9 0-9 and
A,B,C,D,E,F

BIT position value Position value Position value Position value

system system system system

Value expressed Value expressed Value expressed Value expressed

in base of 2 in base of 8 in base of 10 in base of 16

101010 2 765 8 925 10 F2F1 16

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REPRESENTATION OF NUMBERS: Binary

Facts to Remember:
• Binary numbers are made up of only 0’s and 1’s.
• A binary number is represented with a base-2
• A bit is a single binary digit.

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REPRESENTATION OF NUMBERS: Octal

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REPRESENTATION OF NUMBERS: Decimal

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REPRESENTATION OF NUMBERS: Hexa decimal

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Conversion between Numbers: Binary to Decimal

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Conversion between Numbers: Octal to Decimal

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Conversion between Numbers: Hexadecimal to Decimal

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Conversion between Numbers: Decimal to Binary

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Conversion between Numbers: Decimal to Octal

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Conversion between Numbers: Decimal to Hexadecimal

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Octal to Binary

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Binary to Octal

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Hexa to Binary

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Binary to Hexa

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Number Conversion chart

Oct

Dec Bin

Hexa

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Number Conversion chart

Oct

Dec Bin

Hexa

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Complements

r’s Complements r-1 ‘s complements

Ex: 2’s and Ex: 1’s and 9’s
10’s . (r-1)’s compliment of
r’s compliment of N is defined as
N is defined as (𝑟𝑛−1) − 𝑁
𝑟𝑛 − 𝑁

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Subtraction using 1’s Complement

1. Take the minuend as it is and 1’c of subtrahend
2. Add the 1’C of subtrahend to minuend
3. If carry come in MSB remove the carry and add it
to the ‘sum’ to get result
4. If carry does not come in MSB 1’C of ‘sum’ is the
result

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Subtraction using 1’s Complement

1. Take the minuend as it is and 1’c of subtrahend
2. Add the 1’C of subtrahend to minuend
3. If carry come in MSB remove the carry and add it
to the ‘sum’ to get result
4. If carry does not come in MSB 1’C of ‘sum’ is the
result

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Subtraction using 2’s Complement

1. Take the minuend as it is and 2’c of subtrahend
2. Add the 2’C of subtrahend to minuend
3. If carry come in MSB discord the end carry and
remaining value is the result
4. If carry does not come in MSB 2’C of ‘sum’ is the
result

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Subtraction using 2’s Complement

1. Take the minuend as it is and 2’c of subtrahend
2. Add the 2’C of subtrahend to minuend
3. If carry come in MSB discord the end carry and
remaining value is the result
4. If carry does not come in MSB 2’C of ‘sum’ is the
result

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ANALOG AND DIGITAL ELECTRONICS

BINARY CODES

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1.The main characteristic of a weighted code is, each binary bit is

assigned by a “weight” and values depend on the position of the binary
bit.

2.The sum of the weights of these binary bits, whose value is 1 is equal to
the decimal digit which they represent.

3.Inother words, if w1, w2, w3 and w4 are the weights of the binary
digits, and x1, x2, x3 and x4 are the corresponding bit values, then the
decimal digit N=w4x4 + w3x3+w2x2+w1x1 is represented by the
binary sequence x4x3x2x1.

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• Two types binary codes

1.Weighted Binary Systems and
2.Non Weighted Codes.
• Weighted binary codes are those which follow the positional
weighting principles wherein each position of the number
represents a specific weight.
Ex: BCD(8421), 84-2-1, 2421, and 5043210 …
• Non-weighted codes are codes that are not placed weighted. It
means that each position within the binary number is not
assigned a fixed value.
Ex: Excess-3 and Gray codes

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DIGITAL LOGIC DESIGN

PARITY CHECK CODE AND HAMMING
CODE.

Presented by
Mr. K.M.D.Rajesh babu,
Assistant Professor,
Department of ECE, Vemu institute of Technology

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Parity check code

• Parity check is a simple way to add redundancy bits to the
packets such that the total number of 1's is even (or odd).
• A single bit is appended to the end of each frame, the bit is
1 if the data portion of the frame has odd number of 1's.
Otherwise, it is 0.
• The total number of 1's in each data frame is always even.
• The problem with this approach is that if there are even
number of errors, it can not be detected
• Therefore it has a one bit error detection capability but
no error correction capability.

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Networks must be able to transfer data from one device

to another with complete accuracy.

 Data can be corrupted during transmission.

 For reliable communication, errors must be detected

and corrected.

 Error detection and correction are

implemented either at the data link layer or the
transport layer of the OSI model.

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 Types of errors
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Parity bits
Decimal Message Parity bits Parity bits
no. bits (even) (odd)

0 000 0 1

1 001 1 0

2 010 1 0

3 011 0 1

4 100 1 0

5 101 0 1

6 110 0 1

7 111 1 0

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Hamming code
• It is an error detection and correction code
• Invented by Richard W. Hamming
• Steps involved in the Hamming code
1. Selecting the number of redundant bits
2. Choosing the location of redundant bits
3. Assigning the values to redundant bits
4. How to detect and correct the error in the hamming code?

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• Selecting the number of parity bits

2𝑃 ≥ 𝑛 + 𝑃 + 1
For example msg bits n=4
Let p=2
22 ≥ 4 + 2 + 1
4≥ 7(condition fail)
Let p=3
23 ≥ 4 + 2 + 1
8≥8(condition true)
So select 3 parity bits for 4 bit message to create hamming code

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2. Choosing the location of parity bits

Bit Location 7 6 5 4 3 2 1

Bit designation D4 D3 D2 P3 D1 P2 P1

Binary representation 111 110 101 100 011 010 001

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3. Assigning the values to parity bits

Bit Location 7 6 5 4 3 2 1

Bit designation D4 D3 D2 P3 D1 P2 P1

Binary representation 111 110 101 100 011 010 001

(data bits)

(parity bits)

𝑃1 = 3 𝑥𝑜𝑟 5 𝑥𝑜𝑟7
𝑃2 = 3 𝑥𝑜𝑟 6 𝑥𝑜𝑟7

𝑃3 = 5 𝑥𝑜𝑟 6 𝑥𝑜𝑟7
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• How to detect and correct the error in the hamming

code?.
• Given the 4 bit data word 1010, generate the 18 bit
composite word for the hamming code that corrects
and detects single errors.

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Bit Location 7 6 5 4 3 2 1

Bit designation D4 D3 D2 P3 D1 P2 P1

Binary 01
111 110 101 100 011 001
representation 0

(data bits)

(parity bits)

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DIGITAL LOGIC DESIGN

BOOLEAN ALGEBRA

Presented by
Mr. K.M.D.Rajesh babu,
Assistant Professor,
Department of ECE, Vemu Institute of Technology

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Theorem Name AND form OR form

Identity 1.A=A 0+A=A

Null law 0.A=0 1+A=1

Idempotent law A. A = A A+A=A
Inverse law A A’ = 0 A + A’ = 1
Commutative law AB =BA A+B =B+A
Associate law (AB)C=A(BC) (A+B)+C=A+(B+C)
Distributive law A+BC = A(B+C)= AB+AC
(A+B)(A+C)
Absorption law A(A+B)=A A+AB= A
De Morgan’s law (AB)’ = A’ +B’ (A+B)’ = A’ B’

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• Consensus
AB+A’C+BC=AB+A’C
(A+B) (A’+C) (B+C)=(A+B) (A’+C)

• Transposition theorem
(A+B)(A+C)= A + BC

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• Simplify the expression y= AB’D+AB’D’

• Simplify the expression X= ACD+A’BCD

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• Simplify AB’+ABC’+AB’C’D =AB’+AC’

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• Combinational circuits are more frequently constructed

with NAND or NOR gates rather than AND and OR gates.
• It is important to be able to recognize the relationships
between AND-OR and NAND or NOR.
• NAND and NOR universal gates.

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multilevel NAND diagram

• From the given Boolean expression, draw the logic diagram with AND,
OR, and inverter gates. Assume that both the normal and complement
inputs are available.
• Convert all AND gates to NAND gates with AND-invert graphic
symbols.
• Convert all OR gates to NAND gates with invert-OR graphic symbols.
• Check all small circles in the diagram. For every small circle that is not
compensated by another small circle along the same line, insert an
inverter (one-input NAND gate) or complement the input variable.

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ത+ 𝐶)(𝐷
• 𝐹 = 𝐴 + (𝐵 ഥ+ 𝐵𝐸ത)

• From the given Boolean expression, draw the logic

diagram with AND, OR, and inverter gates

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• Convert all AND gates to NAND gates with

AND-invert graphic symbols.
• Convert all OR gates to NAND gates with
invert-OR graphic symbols

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• NAND logic

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• MULTI LEVEL NOR CIRCUITS

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• From the given Boolean expression, draw the logic diagram

with AND, OR, and inverter gates. Assume that both the
normal and complement inputs are available.
• Convert all AND gates to NAND gates with AND-invert
graphic symbols.
• Convert all OR gates to NAND gates with invert-OR graphic
symbols.
• Check all small circles in the diagram. For every small circle
that is not compensated by another small circle along the same
line, insert an inverter (one-input NAND gate) or complement
the input variable.

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• 𝐹 = 𝐴𝐵 + 𝐸 (𝐶 + 𝐷)

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• Karnaugh Map Method - Up to five Variables, Don't Care

Map Entries, Tabular Method.

• Combinational Logic Circuits: Adders, Subtractors,

comparators, Multiplexers, Demultiplexers, Encoders,
Decoders and Code converters, Hazards and Hazard
Free Relations.

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KARANAUGH MAP
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Boolean functions may be simplified by algebraic theorems.

However, this procedure of minimization is awkward.
KARANAUGH Map is a simple straightforward procedure.
The map is made up of squares. Each square represents one
minterm
A two-variable function has four possible minterms. We can re-
arrange these minterms into a Karnaugh map.

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• By recognizing various patterns, the user can derive alternative

algebraic expressions for the same function, from which he can
select the simplest one. We shall assume that the simplest
algebraic expression is anyone in a sum of products or product
of sums that has a minimum number of literals.

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3 variable function

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• One square represents one minterm, giving a term of

three literals.
• Two adjacent squares represent a term of two literals.
• Four adjacent squares represent a term of one literal.
• Eight adjacent squares encompass the entire map and
produce a function that is always equal to 1.

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Simplify the Boolean function F(x, y, z) = σ (2, 3, 4, 5)

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Given the following Boolean function:

F = A'C + A'B + AB'C + BC
(a) Express it in sum of minterms,
(b) Find the minimal sum of products expression,

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4-variable K-map
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𝒎𝟎 𝒎𝟏 𝒎𝟑 𝒎𝟐 𝒘 ′ 𝒙 ′ 𝒚′ 𝒛 ′ 𝒘′ 𝒙′ 𝒚′ 𝒛 𝒘′ 𝒙 ′ 𝒚 𝒛 𝒘′ 𝒙′ 𝒚 𝒛′

𝒎𝟒 𝒎𝟓 𝒎𝟕 𝒎𝟔 𝒘 ′ 𝑥 𝒚′ 𝒛 ′ 𝒘′ 𝑥 𝒚′ 𝒛 𝒘′ 𝑥 𝒚 𝒛 𝒘′ 𝑥 𝒚 𝒛 ′

𝒎𝟏𝟐 𝒎𝟏𝟑 𝒎𝟏𝟓 𝒎𝟏𝟒 𝑤 𝑥 𝒚′ 𝒛 ′ 𝑤 𝑥 𝒚′ 𝒛 𝑤𝑥𝑦𝑧 𝑤 𝑥 𝑦 𝒛′

𝒎𝟖 𝒎𝟗 𝒎𝟏𝟏 𝒎𝟏𝟎 w 𝒙′ 𝒚′ 𝒛′ 𝒘 𝒙′ 𝒚′ 𝒛 𝒘 𝒙′ 𝒚 𝒛 𝒘 𝒙′ 𝒚 𝒛′

• 4 variable k-map has maximum of 16 minterms.

• Map has 16 square boxes
• Possibilities of adjacent squares

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• One square represents one minterm, giving a term of four

literals.
• Two adjacent squares represent a term of three literals.
• Four adjacent squares represent a term of two literals.
• Eight adjacent squares represent a term of one literal.
• Sixteen adjacent squares represent the function equal to 1.

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• Simplify the Boolean function

F(w, x, y, z) = σ (0, 1,2,4,5,6,8,9, 12, 13, 14)

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• The map method of simplification: convenient for < 5 variable

• The tabulation method overcomes this difficulty:

specific step-by-step procedure

• It is also known as the Quine-McCluskey method.

• The tabular method of simplification consists of two parts

• Exhaustive search for prime implicant

Don’t write or
place any image
• Find least number of literals from prime implicant search
in this area

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DETERMINATION OF PRIME
IMPlICANTS
• List of minterms that specify the function in first coloumn.

• The process compares each min term with every other minterm.
If two min terms differ in only one variable, that variable is
removed and remaining variables are considered.

• This process is repeated for every minterm until no further

elimination of literals

Simplify the following Boolean function by using Don’t write or

the tabulation method: place any image
F(w, x, y, z) = σ ( 0, 1,2,8,10,11,14, I5) in this area

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Step I: Group binary representation of the minterms according to the

number of 1's contained

Step2: Any two min terms that differ from each other by only one
variable can be combined,
and the unmatched variable removed. The minterms in one
section are compared with
those of the next section down only.

Step 3: The terms of column (b) have only three variables. The
searching and comparing Don’t write or
place any image
process is repeated for the terms in column (b) to form
in this area
the two-variable terms of column (c).

Step 4: The unchecked terms in the table form the prime implicant
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Simplify the following Boolean function by using the tabulation method: F(w, x, y, z) =
σ ( 0, 1,2,8,10,11,14, I5)
Quine-McCluskey minimization
a method
b c
w x y z w x y z w x y z
0- 0 0 0 0 (0,1)- 0 0 0- (0, 2 8,10) - 0 - 0
(0, 8 2,10) - 0 - 0
1- 0 0 0 1 (0,2)- 0 0 -0
2- 0 0 1 0 (0,8)- - 0 00 (10,11,14,15) 1 - 1–
(10, 14, 11, 15) 1 - 1 -
8- 1 0 0 0
10-1 0 1 0 (2,10) - 010 F= W’ X’Y’ + X’Z’+ WY
(8, 10) 10-0
11-1 0 1 1 (10,11) 101–
14-1 1 1 0 (10,14) 1–10
15-1 1 1 1 (11,15) 1 - 1 1
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Quine-McCluskey minimization
method

Don’t write or
place any image
in this area

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Quine-McCluskey minimization
method
Simplify the following Boolean function by using the tabulation method: F(w, x, y, z) =
σ (1,4,6,7,8,9, 10, 11, 15)

Don’t write or
place any image
in this area

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Quine-McCluskey minimization
method

Don’t write or
place any image
in this area

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Cominational Logic
Circuits
Logic circuits for digital systems may be combinational or sequential

Don’t write or
place any image
in this area

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DESIGN PROCEDURE

1. The problem is stated.

2. Define input and output variables.
3. The input and output variables are assigned
letter symbols.
4. Derive truth table (The truth table that
defines the required relationships between Don’t write or
place any image
inputs and outputs is derived). in this area

5. The simplified Boolean function for each

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ADDERS
• Digital computers perform the basic arithmetic
operation is the addition of two binary digits.
• A combinational circuit that performs the addition of
two bits is called a half-adder. Performs the addition of
three bits is Full-adder.

Half-Adder.
1. Define problem: Addition of two binary digits.
2. Define i/o variables: input variables are 2 and
Don’t write or
output are 2 place any image
in this area
3. Assign x, y as input and Sum, Carry are output
variables .
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4. Define TT
x y Sum
carry
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

5. The simplify Boolean function

S = 𝑥ҧ 𝑦 + 𝑥 ഥ𝑦
Don’t write or
C = 𝑥𝑦 place any image
in this area

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6. Draw the logic diagram

Don’t write or
place any image
in this area

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1. Problem statement : A full-adder

is a combinational circuit that
forms the arithmetic sum of three
input bits.
2. Define I/O: It consists of three
inputs and two outputs
3. Notation: Input variables are
denoted by x,y and Z and output
are denoted by S,C. Don’t write or
place any image
in this area

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4. Truth table
xyz S C
000 0 0
001 1 0
010 1 0
011 1 1
100 1 0
101 0 1
110 0 1
Don’t write or
111 1 1 place any image
in this area

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5. Simplify the boolean function

Don’t write or
S = x’y’z+ x’yz’+xy’z’+xyz place any image
in this area
C = xy + xz + yz

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6. Draw the logic diagram

Don’t write or
place any image
in this area

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MAGNITUDE COMPARATOR

Don’t write or
place any image
in this area

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6. Draw the logic diagram

Don’t write or
place any image
in this area

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Cominational Logic
Circuits
Logic circuits for digital systems may be combinational or sequential

Don’t write or
place any image
in this area

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DESIGN PROCEDURE

1. The problem is stated.

2. Define input and output variables.
3. The input and output variables are assigned
letter symbols.
4. Derive truth table (The truth table that
defines the required relationships between Don’t write or
place any image
inputs and outputs is derived). in this area

5. The simplified Boolean function for each

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ADDERS
• Digital computers perform the basic arithmetic
operation is the addition of two binary digits.
• A combinational circuit that performs the addition of
two bits is called a half-adder. Performs the addition of
three bits is Full-adder.

Half-Adder.
1. Define problem: Addition of two binary digits.
2. Define i/o variables: input variables are 2 and
Don’t write or
output are 2 place any image
in this area
3. Assign x, y as input and Sum, Carry are output
variables .
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4. Define TT
x y Sum carry
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

5. The simplify Boolean function

S = 𝑥ҧ 𝑦 + 𝑥 ഥ𝑦
Don’t write or
C = 𝑥𝑦 place any image
in this area

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6. Draw the logic diagram

Don’t write or
place any image
in this area

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FULL-ADDER

1. Problem statement : A full-adder

is a combinational circuit that
forms the arithmetic sum of three
input bits.
2. Define I/O: It consists of three
inputs and two outputs
3. Notation: Input variables are
denoted by x,y and Z and output
are denoted by S,C. Don’t write or
place any image
in this area

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4. Truth table
xyz S C
000 0 0
001 1 0
010 1 0
011 0 1
100 1 0
101 0 1
110 0 1
Don’t write or
111 1 1 place any image
in this area

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5. Simplify the boolean function

Don’t write or
S = x’y’z+ x’yz’+xy’z’+xyz place any image
in this area
C = xy + xz + yz

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6. Draw the logic diagram

Don’t write or
place any image
in this area

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6. Draw the logic diagram

Don’t write or
place any image
in this area

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Full-Subtractor

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MAGNITUDE COMPARATOR

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place any image
in this area

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Decoder

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place any image
in this area

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Don’t write or
place any image
in this area

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8X3 Encoder

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place any image
in this area

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Encoder

Don’t write or
place any image
in this area

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Enabled Decoder

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Implement a full-adder circuit with a decoder

and two OR gates.

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Multiplexer

MULTIPLEXER

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place any image
• It is a combinational circuit in this area
• Many input and one output
• Depending on select i/p, one of the data i/p is transferred to
the o/p
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Multiplexer
• Example of multiplexers are 2𝑛 𝑋1 where n = 1,2,3,4, … etc.

• For example 2x1

• Implement by following combinational design steps.

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place any image
in this area

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Multiplexer
• Example of multiplexers are 2𝑛 𝑋1 where n = 1,2,3,4, … etc.

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place any image
in this area

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4x1 Multiplexer

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in this area

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Multiplexer
Construct a 8X1multiplexer using 4X1multiplexer

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in this area

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16 X 1 muxer

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16 X 1 muxer
Construct a 16 : 1 Mux using only 2 : 1 Mux

Implement a 64:1 MUX using 8:1 MUXs.

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Demultiplexer

• It is a combinational circuit

• Single input and many outputs

• Depending on select i/p, i/p is transferred to

the any one of the selected o/p.

• Also known as data distributor.

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in this area

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Demultiplexer

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Demultiplexer

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place any image
in this area

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Code convertor

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Code convertor

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Code convertor

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