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95

536 MARCH & APRIL 2025

ELEKTORMAGAZINE.COM
S

*
1

*
IN
CE 196

Including

RISC-V:
16 Bonus Pages
by eeNews
Europe!

It's In Your Embedded Industry

Trends, R&D and
More

Future
16 Boards &
MCUs You
FOCUS ON
Should Know
Embedded & AI

AI Prevents An FPGA-Based i n g D i g i t al
x
Damage Audio Player with Mi
Au

Equalizer a n A rd u i n o M io
d

Predictive with
KR
Maintenance Vi d o r 4 0 0 0
in Practice

Dual-Core Programming USB 2.0 Isolator Modular Sensor Testing

Parallel Programming with a Electrically Isolated Connections The ESP32-S3-Based Sensor
Raspberry Pi Pico for USB Devices Evaluation Board
Create trust in your
embedded system
Enhance data protection and ensure secure
access, perfectly suited for retrofit solutions.

www.swissbit.com Visit us at booth 1-510

 colophon editorial

Jens Nickel
Volume 51, No. 536 International Editor-in-Chief, Elektor Magazine
March & April 2025
ISSN 1757-0875

Elektor Magazine is published 8 times a year by

Elektor International Media b.v.
RISC-V in Practice
PO Box 11, 6114 ZG Susteren, The Netherlands
When my former colleague, Mathias Claussen, suggested years ago that I should report on
Phone: +31 46 4389444
www.elektor.com | www.elektormagazine.com
“RISC-V,” I was immediately fascinated. It had been about 25 years since I had last dealt with
processor instructions and registers. But, I could instantly see how valuable it was to have a
Content Director: C. J. Abate modern, standardized, and freely usable instruction set, developed by the brightest minds
Editor-in-Chief: Jens Nickel from many companies and universities.

For all your questions Since then, I’ve had the opportunity to learn more firsthand: I met an expert at a symposium
service@elektor.com who is himself part of a standardization committee, and I also spoke with Calista Redmond, at
that time CEO of the RISC-V Foundation, at a trade fair. Today, RISC-V has become an everyday
Become a Member
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hands-on magazine, we wanted to show that there are now high-quality boards available for
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every need and performance class, which can be used for developing IoT, audio/video, AI, and
Tel. +49 (0)241 95509178 many other projects (page 6).
busra.kas@elektor.com
www.elektormagazine.com/advertising Personally, I’m not particularly fascinated by the high-end boards costing several hundred
euros, but rather by the other end of the spectrum. RISC-V makes it possible to use a microcon-
Copyright Notice troller for just 10 cents in your own projects. Here’s a small preview of the next issue: Frequent
© Elektor International Media b.v. 2025 contributor Tam Hanna will bring such a controller to life in a hands-on article and test how
well it works with the associated IDE.
The circuits described in this magazine are
for domestic and educational use only. All
Our colleagues from news platform eeNews Europe also regularly report on RISC-V. In this issue,
drawings, photographs, printed circuit board
layouts, programmed integrated circuits,
you’ll find about 16 extra pages from their news portal, including articles created exclusively
digital data carriers, and article texts published for us. On page 120, for example, we cover a RISC-V processor that can handle GPU, CPU, and
in our books and magazines (other than even FPGA functions within a single architecture.
third-party advertisements) are copyright
Elektor International Media b.v. and may not What else is in this Embedded and AI issue? As an audio enthusiast, I highly recommend
be reproduced or transmitted in any form our FPGA-based audio mixer (page 14). It’s amazing what can be achieved in terms of quality
or by any means, including photocopying, and features with an Arduino MKR board for well under €100. You should also check out the
scanning and recording, in whole or in part tool we introduce on page 50, which provides developers with valuable insights into what’s
without prior written permission from the
happening inside their microcontrollers during program execution. Both articles impressively
Publisher. Such written permission must also
demonstrate how far you can go with hobby projects.
be obtained before any part of this publication
is stored in a retrieval system of any nature.
Patent protection may exist in respect of
Get involved in development!
circuits, devices, components etc. described
in this magazine. The Publisher does not
accept responsibility for failing to identify such
patent(s) or other protection. The Publisher
disclaims any responsibility for the safe and
proper function of reader-assembled projects
based upon or from schematics, descriptions
or information published in or in relation with
Submit to Elektor! Elektor Labs
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Sylvia Sopamena, Patrick Wielders | Publisher: Erik Jansen | Technical Questions: editor@elektor.com

March & April 2025 3

 THIS EDITION Volume 51, No. 536
March & April 2025

6 Audio Player with

Equalizer

The RISC-V Open-

Source Processor Mixing Digital
Architecture 14 Audio with an
Arduino MKR Vidor 4000

Regulars Projects
3 Colophon 14 An FPGA-Based Audio Player with Equalizer (1)
Mixing Digital Audio with an Arduino MKR Vidor 4000
92 From Life’s Experience
Choice Overload 20 Laser Head for Pico-Based Sand Clock
Drawing with Light
94 Starting Out in Electronics…
…Continues Filtering and Controls Tone 24 A Multi-Sensor Environmental Monitoring System for Plants
Wireless Measurement of Water Supply and Lighting
108 2025: An AI Odyssey
Conditions
The Rise of Foundation Models and
Their Role in Democratizing AI 34 Maixduino AI-Powered Automatic Doorman
Face Detection with a Camera
117 Err-lectronics
Corrections, Updates, and Readers’ Letters 56 USB 2.0 Isolator
Electrically Isolated Connections for USB Devices
74 ECG Graph Monitoring

Features An Implementation with Hexabitz Modules and an

STM32CubeMonitor

6 The RISC-V Open-Source Processor Architecture 97 Quasi-Analog Clockwork

16 Boards and MCUs You Should Know A Remake of an Elektor Classic

49 The Elektor Mini-Wheelie 102 A Modular Approach to Sensor Testing

A Self-Balancing Robot Kit The ESP32-S3-Based Sensor Evaluation Board

50 MCU, I See You 112 Raspberry Pi Standalone MIDI Synthesizer (1)

MCUViewer Open-Source Multiplatform Debugging Tool Preparing a Platform for Some Edge AI Experiments

60 Intervention Before Damage

20
Predictive Maintenance in Practice
82 The Battle for AI at the Edge
124 Dual-Core Programming with a Raspberry Pi Pico Laser Head for
Venture into the World of Parallel Programming Pico-Based
Sand Clock
Drawing with Light

4 March & April 2025 www.elektormagazine.com

 40

MCU, I See You 50 Embedded

MCUViewer Open-Source Electronics 2024
Multiplatform Debugging Tool AI Is Set to Redefine the Industry

Industry Next Editions

23 Enter the STM32 Edge AI Contest Elektor Magazine May & June 2025
As usual, we’ll have an exciting mix of projects, circuits, fundamentals,
40 Embedded Electronics 2024
and tips and tricks for electronics engineers and makers. Our focus
AI Is Set to Redefine the Industry
will be on Test & Measurement.
44 Charge-Based In-Memory Compute at EnCharge AI
46 AI Inferencing at 10 Times Lower Power and
> MPP Tracker and Charge Controller
20 Fold Lower Cost
> Sine Wave Generator with Adjustable Frequency
> Battery Monitoring System
48 Click Board Helps Develop and Train ML Models for > GUI for Optimizing PID Parameters
Vibration Analysis > Frequency Counter
68 SPoE — Electromagnetic Compatibility > 10-Cent Controller in Practice
Single-Pair with Power-Over-Ethernet Through the > Stand-Alone Crystal Tester
Eyes of EMC > FPGA-Based Audio Player: Mixing and Filters

72 Color TV: A Wonder of Its Time Elektor Magazine’s May & June 2025 edition will be published
Creating a New World around May 14, 2025.

87 HaLow Hits Record 16 km Wi-Fi Distance at 900 MHz Arrival of printed copies for Elektor Gold members is subject to transport.

88 First CHERI RISC-V Embedded Chip and Early Access

Program
90 Third-Generation Wildfire Detection Uses Satellite Links BONUS CONTENT
120 Universal AI RISC-V Processor Does It All — CPU, GPU,
Check out the free Embedded & AI bonus
DSP, FPGA edition of Elektor Mag!
122 CEO Interview: Ventiva’s Thin and Cool Tech
> Virtual Assistant with ChatGPT and Raspberry Pi
> Review: Makerfabs SenseLoRa
> The Connected Autonomous Vehicle and Its Environment
> Peculiar Parts: The Intel 8279 Keyboard/Display Interface
FOCUS ON > Infographics: Embedded and AI

www.elektormagazine.com/
Embedded & AI embedded-ai

March & April 2025 5

 PROCESSORS

The RISC-V Open-Source

Processor Architecture
16 Boards and MCUs You Should Know

By Saad Imtiaz (Elektor) and Jean-François Simon (Elektor)

of our readers may recall that we published a few
Discover how RISC-V, the open-source newcomer articles on this topic a few years ago, when hardware
in the microcontroller world, is benefiting many choices were much more limited [1][2]. Developed
at the University of California, Berkeley, starting in
engineers and innovators in the industry with 2010, RISC-V was envisioned as a forward-looking
its simplicity and other advantages. Join us as architecture unburdened by legacy compatibility.
we explore a selection of RISC-V-based boards to Unlike traditional processor architectures, RISC-V
is open-source, modular, and designed in a modern
experiment with! way. More precisely, it is an open-standard instruc-
! tion set architecture (ISA), i.e. a standardized defini-
tion of the instructions a processor can execute. It
is designed to overcome the proprietary restrictions
Microcontrollers are everywhere, powering every- of traditional ISAs, such as those from Intel, AMD
thing from your dishwasher to powerful computing or ARM. Unlike proprietary ISAs, RISC-V allows
systems and millions of wearable and IoT devices. For anyone to implement its specifications without legal
the processor cores and architectures, names such as restrictions, fostering innovation and collaboration
ARM, AVR, MIPS, Xtensa, 8051, etc., dominate the between companies and leading experts.
landscape, each with unique strengths and areas of !
application. These platforms, used in many very popular With an open ISA, many companies can develop
microcontrollers such as the STM32, ESP32-S3, ATmega and sell ready-to-use RISC-V cores, in the form of
and so on, share a common trait: They are proprietary. intellectual property (IP) blocks. A microcontroller
! manufacturer can buy a RISC-V core and use it in
Enter RISC-V (Figure 1), a relatively new player in a microcontroller, adding the manufacturer’s own
the world of microcontrollers and processors. Some peripherals. This encourages competition between IP

6 March & April 2025 www.elektormagazine.com

providers, stimulating innovation and driving down 
costs. Manufacturers can switch to higher-perfor-
Figure 1: RISC-V logo.
mance ICs without being locked into proprietary
Source: © RISC-V
ecosystems. Foundation, CC BY-SA 4.0
!
RISC-V: A Simple Concept
RISC-V, as its name implies, adheres to the Reduced
Instruction Set Computer (RISC) principles, which !
emphasize a small, optimized set of instructions. Modularity
This reduces the complexity of hardware design and The extensions enable processors to be custom-
facilitates faster development cycles. Unlike legacy ized to specific needs. There are about 30 of them,
architectures such as x86, which carry decades of including multiplication and division (M) for arith-
backward-compatibility baggage, RISC-V starts with metic operations, atomic instructions (A) for multi-
a clean slate, incorporating only what’s necessary threaded programming, single and double-precision
for modern applications. For example, RISC-V’s floating-point (F and D) for scientific computing and
base consists of just 47 instructions, compared to signal processing, vector processing (V) for parallel
hundreds on the x86. You can find details about the data operations, compressed instructions (C), etc. The
instruction set here [3], summarized by GitHub user full list can be found at [4] along with more detail. This
msyksphinz-self. This lean design makes it easier to modularity optimizes silicon utilization and energy
implement and verify, resulting in lower costs and efficiency: Chip manufacturers can produce micro- Figure 2: Instruction
fewer bugs. While this base instruction set is indeed controllers that contain just what is needed for a given Set for the RV32I base
quite minimalist, there are optional extensions that application, without wasting resources, thus reducing core with M, A, and C
can be added as needed. costs. For instance, a microcontroller for IoT devices extensions. Source:
github.com/kuashio/
risc-v-diagrams CC BY-
SA 4.0

RV32IMAC 

LR.W SC.W AMOAND.W AMOOR.W AMOXOR.W C.LW C.AND

AMOADD.W AMOMIN.W AMOMAX.W AMOMINU.W AMOMAXU.W C.FLW C.ANDI

AMOSWAP.W 32 bits
RV32A C.FLD C.OR
Atomic Instruction ISA Extension C.LWSP C.XOR

MULH DIV MUL REM REMU C.FLWSP C.LI

MULHU DIVU C.FLDSP C.LUI

MULHSU 32 bits
RV32M C.SW C.SLLI
Integer Multiplication and Division ISA Extension C.FSW C.SRLI

ADD ADDI BEQ LB SB C.FSD C.SRAI

SUB BNE LBU C.SWSP C.BEQZ

AND ANDI BGE LH SH C.FSWSP C.BNEZ

OR ORI BGEU LHU C.FSDSP C.J

XOR XORI BLT LW SW C.ADD C.JR

SLL SLLI BLTU C.ADDI C.JAL

SRL SRLI JAL LUI C.ADDI16SP C.JALR

SRA SRAI JALR AUIPC C.ADDI4SPN C.EBREAK

SLT SLTI ECALL FENCE C.SUB C.MV

SLTU SLTIU EBREAK 32 bits

RV32I 16 bits
RV32C
Base Integer ISA Compressed ISA Extension

March & April 2025 7

might exclude floating-point units to save power and silicon, while Qualcomm, IBM, and others have joined, further solidifying its
a processor for AI workloads would include vector extensions for presence in the market. NVIDIA uses RISC-V for specific cores in
accelerated computation. As an example, a nice diagram showing its GPUs, while Western Digital leverages it for storage devices.
the base integer instruction set for a 32-bit core (RV32I) together SiFive, a pioneer in RISC-V development, offers a range of proces-
with the M, A, and C extensions has been put together by Github sors for embedded and high-performance applications. The main
user kuashio (Figure 2). IP suppliers are Nuclei, SiFive, and T-Head, while some manufac-
! turers, such as Espressif and WCH, are developing their own IPs to
More Security? differentiate their products. Without knowing it, you may already
RISC-V’s openness has spurred innovation in processor security. have used RISC-V hardware, such as the ESP32-C3, ESP32-C6, and
If you have an application for which security is important, then ESP32-P4. Even Raspberry!Pi incorporated RISC-V cores into its
the open-source nature of RISC-V is a great feature: It’s then easier latest microcontroller, the RP2350, used on the Raspberry!Pi Pico!2.
to inspect. It’s for the same reason that many crypto wallets are !
open-source! Extensions such as CHERI (Capability Hardware RISC-V in Practice
Enhanced RISC Instructions) enable fine-grained memory protec- Despite the hype surrounding it, is RISC-V truly “revolutionary”
tion, reducing vulnerabilities to attacks such as buffer overflows. for the average user? Most engineers and hobbyists program in
Unlike proprietary architectures, RISC-V allows researchers to C/C++ or other high-level languages, meaning you won’t need to
experiment and implement security features without licensing learn this reduced instruction set. For developers and engineers,
restrictions. transitioning to RISC-V only requires modest changes to estab-
! lished workflows and habits. Tools such as compilers and devel-
Reducing Costs and Sharing Results opment environments are already available and getting better
An open ISA eliminates licensing fees associ- every day. If you’re interested in embedded
ated with proprietary ISAs. Microcontroller development, using RISC-V microcontrol-
manufacturers can develop their own RISC-V lers is a very relevant skill to acquire and add
cores or purchase ready-to-use intellectual to your toolbox. For those who enjoy getting
property (IP) blocks from vendors. This compet- hands-on and programming in assembly, one
itive ecosystem drives down costs, making of our authors has published a short article [6]
advanced microcontrollers and processors RISC-V ’s openess has on our website about programming the RISC-V
accessible to a wider audience. Further cost core on an ESP32-C3, with a companion Elektor
reduction is achieved by sharing the devel-
spurred innovation in book. For those who prefer programming in
opment of software ecosystems (compilers, processor security. C on ultra-low-cost microcontrollers such as
OS support, etc.) between several companies. the CH32V003 from WCH, we’ve discovered an
RISC-V’s open model encourages the pooling of excellent educational site [7] created by Vincent
resources and expertise, akin to how Linux revolutionized operat- Defert. The site is in French, but we encourage you to use a browser
ing systems or Ethernet transformed networking. Companies can extension for real-time translation to take full advantage of this
focus on unique differentiators rather than duplicating founda- outstanding content! Our bet is that the RISC-V standard is here
tional work, accelerating innovation and improving the overall to stay, and these skills will be easily reusable in the future. In the
ecosystem. second part of this article, we will present some of the exciting
! RISC-V-based development boards available today that you can
Legal Peace of Mind for Everyone use for your next project. Have fun!
For a university, how can you legally teach processor design to !
computer engineering students when x86 and ARM cores are not Notable RISC-V Development Boards
open-source? Beyond the legal constraints, there is also a technical RISC-V development boards have been gaining traction in recent
challenge: These are not modular, which requires students to imple- years as the RISC-V ecosystem continues to expand. These boards
ment a massive set of instructions before achieving a potentially cater to hobbyists, researchers, and professionals looking to leverage
functional processor. Semiconductor multinationals also value the flexibility and open-source nature of the RISC-V architecture.
this legal piece of mind. Have you heard about the legal dispute Below is a detailed look at some of the most notable RISC-V devel-
between ARM and Qualcomm [5]? RISC-V, on the other hand, offers opment boards available today, their uses, and potential advantages.
companies a different approach, with no licensing fees. !
! Right now, these are just the beginning of a small selection of RISC-V-
Adoption by Major Players based MCUs and CPUs. They range from Arduino!Nano-grade MCUs
RISC-V’s open approach has garnered significant attention, with to desktop and laptop-grade CPUs, and many more are expected
major companies integrating it into their products. By 2015, the to emerge in the coming years, reflecting the rapid growth and
RISC-V Foundation was formed, attracting major players such as potential of the RISC-V ecosystem.
Google, NVIDIA, Western Digital, and NXP. Over the years, AMD, 240736-01

8 March & April 2025 www.elektormagazine.com

High-Performance RISC-V Processors
Besides single board computers and microcontrollers for embed-
ded electronics, RISC-V processors are already making significant
inroads into high-performance computing (HPC) and AI applica-
tions. The SiFive Intelligence X280, for example, is optimized for
AI and machine learning workloads. It features scalable multi-
core configurations, integrated vector extensions, and support for
advanced AI operations such as tensor computations. Last year,
SiFive also announced their Performance P870-D processor for use
in servers and datacenters [8]. For more info on the deployment of
Large Language Models (LLMs) on their top-of-the-range hardware
with performance benchmarks, read this interesting blog post [9].
Similarly, Alibaba’s Xuantie C910 processor, which incorporates
AI-specific instructions and supports high data throughput, powers
cloud-based AI systems, including real-time inference platforms.
!
The future of RISC-V in high-performance computing is promising,
Related Products
with several ambitious projects underway. Ventana Micro Systems
[10] is developing a server-class RISC-V chip with up to 128 cores > Raspberry Pi Pico 2
per processor, targeting enterprise-level applications such as cloud www.elektor.com/20950
computing, database management, and large-scale AI training. > Milk-V Duo 256M SBC
Their designs prioritize parallelism and energy efficiency, targeting www.elektor.com/20973
resource-intensive workloads. Another player, Esperanto Technol- > WCH CH32V307V-EVT-R1 Dev Board
ogies, is building the ET-SoC-1, a processor that integrates over www.elektor.com/20448
1,000 RISC-V cores onto a single chip [11]. Designed for AI infer- > LilyGo TTGO T-Display-GD32
ence tasks, it follows the path of extreme parallelism. Let’s see www.elektor.com/19510
what comes next! > Seeed Studio XIAO ESP32C3
www.elektor.com/20265
> Luckfox Pico Mini B
Questions or Comments? www.elektor.com/21011
Do you have questions or comments about this article?
Email the authors at saad.imtiaz@elektor.com and
jean-francois.simon@elektor.com, or contact Elektor at
editor@elektor.com.

WEB LINKS
[1] Stuart Cording, “What Is RISC-V?,” elektormagazine.com, April 2021: https://elektormagazine.com/articles/what-is-risc-v
[2] Mathias Claussen, “BL808 and Cohorts: A Look at New RISC-V MCUs,” elektormagazine.com, June 2023:
https://elektormagazine.com/articles/bl808-and-cohorts-new-riscv-mcus
[3] RISC-V Instruction Set, RISC-V ISA pages, GitHub: https://msyksphinz-self.github.io/riscv-isadoc
[4] RISC-V on Wikipedia: https://en.wikipedia.org/wiki/RISC-V
[5] Arm vs. Qualcomm Dispute, Capacity Media: https://capacitymedia.com/article/arm-pulls-qualcomms-architecture-licence
[6] Warren Gay, RISC-V Assembly Language Programming (Elektor 2022):
https://elektormagazine.com/articles/why-risc-v-assembly-language
[7] Embedded Development with RISC-V [French]: https://riscv-mcu.defert.com
[8] High-performance RISC-V Datacenter Processor from SiFive:
https://sifive.com/press/sifive-announces-high-performance-risc-v-datacenter-processor-for-ai-workloads
[9] LLM Optimization and Deployment on SiFive RISC-V: https://sifive.com/blog/llm-optimization-and-deployment-on-sifive-intellig
[10] Ventana Micro Systems: https://ventanamicro.com
[11] 1,000 Cores on a Chip, VLSIFacts: https://tinyurl.com/et-soc-1-chip

March & April 2025 9

 HiFive Premier P550
The HiFive Premier P550 is a high-performance development board designed to push
the boundaries of RISC-V development. Powered by the Eswin EIC7700X SoC with a
quad-core SiFive P550 CPU, it provides a robust platform for developing and optimizing
RISC-V operating systems and applications across diverse markets. It starts at $399
for the 16!GB RAM variant, and can support up to 32!GB of LPDDR5-6400 memory,
128!GB of eMMC storage, and HDMI!2.0 display support, enabling intensive computa-
tional tasks. Pre-installed with Ubuntu Linux 24.04, this board is perfect for advanced
development in AI, operating system design, and high-performance application.
https://sifive.com/boards/hifive-premier-p550

HiFive1 Rev B
The HiFive1 Rev!B is an entry-level board designed for IoT and edge computing,
powered by the FE310-G002 processor, which includes a 32-bit RV32IMAC core.
Costing around $65, its 16!KB!L1 instruction cache, 16!KB data SRAM, and support
for flexible clock generation make it efficient for lightweight applications. With a USB
debugger upgraded to SEGGER J-Link-OB and compatibility with SiFive Freedom
Studio, developers benefit from seamless drag-and-drop flash programming and
robust debugging tools. This board is ideal for prototyping IoT devices, developing
low-power applications, and exploring the fundamentals of RISC-V development.
https://sifive.com/boards/hifive1-rev-b

VisionFive 2 SBC
The VisionFive 2 is the world’s first high-performance RISC-V SBC with an integrated
GPU, powered by the StarFive JH7110 SoC. With a quad-core CPU running up to 1.5!GHz
and support for up to 8!GB LPDDR4 memory, it excels in multimedia processing and
dual-display output via HDMI and MIPI DSI interfaces. Features such as three USB
3.0 ports, Gigabit Ethernet with PoE, and GPIO headers make it a strong contender
for IoT, lightweight servers, and edge computing. Its robust multimedia capabilities,
including 4K video decoding and encoding, make it ideal for developers exploring
high-performance RISC-V applications in cost-effective projects, which is currently
sold on Amazon’s website for $99.
https://starfivetech.com/en/site/boards

Milk-V Megrez
The Milk-V Megrez is a Mini-ITX RISC-V device powered by the Eswin EIC7700X SoC,
featuring a quad-core SiFive!P550 CPU at 1.8!GHz. Its built-in GPU supports advanced
graphics standards such as OpenGL ES 3.2 and Vulkan 1.2, while the 19.95 TOPS NPU
enables local AI processing for applications in machine learning and robotics. With
support for up to 32!GB LPDDR5 memory, multiple storage options, including SATA
SSDs and eMMC, and a range of connectivity options like HDMI, USB 3.0 and dual
Gigabit Ethernet, this board is ideal for AI development, high-performance computing,
and multimedia tasks. Its compatibility with Linux and versatile hardware interfaces
make it a significant step forward in RISC-V desktop computing. You can grab this
powerful board for $200.
https://milkv.io/megrez

10 March & April 2025 www.elektormagazine.com

 Milk-V Duo 256M
The compact Milk-V Duo 256M is a versatile embedded development platform powered
by the SOPHGO SG2002 chip. With a memory boost to 256-MB DRAM, it caters to
applications requiring larger memory capacities. The platform features a dual-core
RISC-V CPU (C906 at 1 GHz and 700 MHz) alongside a Cortex-A53 Arm CPU, enabling
seamless switching between RISC-V and Arm architectures. Its TPU delivers 1.0 TOPS
of AI computing power, making it ideal for edge intelligence in smart cameras, visual
doorbells, and IoT devices. Rich GPIO interfaces (SPI, UART) and multimedia capabili-
ties like H.265 video encoding, HDR, and noise reduction further enhance its suitability
for industrial and smart home applications. The Duo also supports Linux and RTOS,
offering developers a powerful and flexible platform for diverse projects. The boards
are available for about €30.
https://milkv.io/docs/duo/getting-started/duo256m

Bouffalo Lab BL616/BL618 and Sipeed M0S

The Bouffalo Lab BL616 and BL618 are 32-bit RISC-V wireless MCUs built for IoT
applications. They support Wi-Fi 6, Bluetooth 5.2, and Zigbee, making them ideal for
smart home devices and Matter-based automation. Running at up to 320!MHz with
an integrated FPU and DSP, they bawlance performance and efficiency. With 480!KB
SRAM, embedded flash, and multiple communication interfaces (USB!2.0, SDIO, SPI,
I2S), they are versatile for embedded projects. Their ultra-low-power modes and secure
boot features make them well-suited for battery-powered devices requiring reliable
connectivity and security. Additionally, Sipeed has launched the compact M0S module
based on the BL616. With 4!MB flash, 512!KB SRAM, and USB 2.0 support, this tiny
(11$10!mm) module is designed for ultra-low-cost IoT applications. With all these
features, a board is available for a modest $4.
https://openbouffalo.org/index.php/BL616
https://wiki.sipeed.com/hardware/en/maixzero/m0s/m0s.html

Milk-V Mars
The Milk-V Mars is a compact and high-performance RISC-V SBC powered by the
StarFive JH7110 SoC, featuring a quad-core CPU clocked up to 1.5!GHz. It supports
up to 8!GB of LPDDR4 memory, an eMMC slot, and SPI flash for bootloader storage,
making it highly adaptable for development tasks. With three USB!3.0 ports, one USB!2.0
port, and an HDMI!2.0 output supporting 4K resolution, it is well-suited for multime-
dia projects, lightweight servers, and general-purpose Linux development. Additional
features such as a 40-pin GPIO, PoE-enabled Ethernet, and MIPI interfaces for cameras
further enhance its versatility, enabling use in IoT, edge computing, and embedded
systems. At around $70 for the 8!GB variant, it’s a steal for the performance it delivers.
https://milkv.io/mars

MangoPi MQ-Pro SBC

Compact and efficient, this board serves as a viable alternative to the Raspberry Pi
Zero, tailored for IoT and lightweight embedded systems. Equipped with the D1 RISC-V
core, it supports Tina-Linux/Debian and runs complete Python applications. Its periph-
eral-rich design includes GPIO, I2C, SPI, and HDMI, making it ideal for small-scale
automation, portable gadgets, and educational projects requiring minimal space and
power. Its community-driven ecosystem ensures flexibility and ease of use in diverse
lightweight applications. Surprisingly, you can get all these features for as low as $35.
https://mangopi.org/mqpro

March & April 2025 11

 Nuclei DDR200T Development Board
This board by Nuclei System integrates a Xilinx XC7A200T-2 FPGA for hardware accel-
eration, prototyping, and custom logic development, along with abundant storage
and extended interfaces for versatile connectivity. The RISC-V microcontroller, the
GD32VF103, enhances programmability, making it ideal for control tasks and interfac-
ing with the FPGA. Its combination of FPGA flexibility and MCU integration supports
industrial automation and embedded development. While priced at $770, the board
justifies its cost with its advanced features and exceptional performance for demand-
ing applications.
https://nucleisys.com/developboard.php

Banana Pi BPI-F3
The Banana!Pi BPI-F3 is an industrial-grade RISC-V development board powered by
the SpaceMiT K1 8-core RISC-V processor, which integrates 2.0 TOPS of AI comput-
ing power. It offers flexible configurations with 2/4/8/16!GB DDR and up to 128!GB
eMMC storage. With dual Gigabit Ethernet ports, four USB 3.0 ports, PCIe for M.2
expansion, and support for HDMI and dual MIPI-CSI cameras, this board excels in
advanced prototyping, industrial applications, and AI-driven tasks. Its compatibility
with Linux distributions and diverse hardware interfaces makes it ideal for high-per-
formance computing and robust development environments. Available at $70, it strikes
a perfect balance between cost and capability.
https://banana-pi.org/en/banana-pi-sbcs/175.html

Espressif ESP32 boards

Espressif’s RISC-V-based MCUs, including the ESP32-P4, ESP32-C3, and ESP32-C6,
are among our favorites and highly favored by the community for their versatility and
robust software ecosystem. The latest and greatest ESP32-P4 features a dual-core
CPU running at up to 400!MHz, an auxiliary low-power core, and 768!KB of on-chip
SRAM with external PSRAM support. It excels in AI, IoT, and HMI applications, boast-
ing 55 programmable GPIOs and extensive peripheral support, including USB!OTG
2.0!HS, Ethernet, and MIPI-CSI for high-resolution cameras. With hardware acceler-
ators and media encoding for H.264 at 1080p, it is a top choice for multimedia-rich
projects. The wider Espressif RISC-V family offers excellent framework compatibility,
making firmware development seamless across multiple platforms. These boards
are also budget-friendly, with prices ranging from as low as $3 to $50, depending on
the variant and features. One of the best options is the Seeed Studio XIAO ESP32C3,
equipped with the ESP32-C3 SoC, combining 400-KB SRAM and 4-MB Flash in a
compact thumb-sized design.!It is ideal for the IoT, wearables, and low-power networking.
https://espressif.com/en/products/socs/esp32-p4
https://wiki.seeedstudio.com/XIAO_ESP32C3_Getting_Started

BeagleV Ahead
The BeagleV Ahead is an open-source RISC-V SBC powered by the T-Head TH1520
SoC, featuring a 2!GHz quad-core XuanTie C910 processor with advanced GPU and
NPU capabilities. Its compatibility with BeagleBone Black cape headers allows for
hardware expansion, making it suitable for robotics, AI, and multimedia applications.
With support for Linux and open-source frameworks, it is designed to enable develop-
ers to explore the potential of RISC-V architecture in complex AI and machine learning
projects. For only $150, this SBC punches well above its weight.
https://beagleboard.org/boards/beaglev-ahead

12 March & April 2025 www.elektormagazine.com

 WCH CH32V003 boards
The CH32V003 by WCH is the most cost-effective of this bunch, a 32-bit RISC-V MCU
designed for industrial and general-purpose applications. It features a QingKe!V2A
core running at up to 48!MHz, 16!KB flash, and 2!KB SRAM. With support for multiple
low-power modes, it is optimized for energy-efficient operations. It includes a 10-bit
ADC, op-amp comparator, and standard interfaces such as USART, I2C, and SPI. The
ultra-small package and 1-wire serial debug interface make it ideal for compact embed-
ded systems, automation, and low-power IoT devices. The chip itself costs less than
$0.20, and I was even able to spot a CH32V003 development board on AliExpress,
being sold for less than $1 — a deal that’s hard to resist. By the way: In one of the next
editions, author Tam Hanna will try out the CH32V003 and the corresponding IDE.
https://wch-ic.com/products/CH32V003.html

WCH CH32V307V-EVT-R1
The WCH CH32V307 on the CH32V307V-EVT-R1 board is a feature-rich RISC-V
microcontroller designed for interconnected applications. It runs at up to 144!MHz,
with a single-precision FPU and hardware stack area for improved performance. The
controller includes 64-KB SRAM, 256-KB Flash, and a wide range of peripherals, such
as eight UART ports, USB 2.0 HS, Ethernet with built-in PHY, and multiple timers. Its
GPIOs can be mapped to external interrupts, and it supports ADC, DAC, SPI, and I2C
interfaces, making it versatile for industrial automation, real-time data processing, and
communication-centric tasks. Its efficient low-power modes and robust connectivity
make it a solid choice for advanced embedded systems. You can find the dev board
at different suppliers (including the Elektor Store) for around €20.
https://github.com/openwch/ch32v307

GigaDevice GD32VF103CBT6 boards

The GD32VF103CBT6 microcontroller by GigaDevice can be found on development boards like the
Sipeed Longan Nano and the LilyGo TTGO T-Display-GD32 RISC-V Development Board (available
in the Elektor Store for a discounted price of just €12.95). Both boards are equipped with a small
LCD and SD card socket, making all kinds of stand-alone devices possible. The 32-bit RISC-V
CPU integrates a Bumblebee Core by Nuclei System, 128-K Flash and 32-K SRAM, an RTC, 3$
USART and many other interfaces like USB, I2C, SPI, I2S and CAN.
www.gigadevice.com/product/mcu/main-stream-mcus/gd32vf103-series

Raspberry Pi Pico 2
Raspberry Pi surprised everyone by adding two Hazard3 RISC-V cores to the recent
RP2350 powering the Raspberry!Pi Pico!2! It offers 520!KB of SRAM, 4!MB of flash
storage, 26 multi-purpose GPIO pins, including 4 that can be used for ADC, and a
comprehensive set of peripherals including two UART interfaces for serial communi-
cation, two SPI plus two I2C controllers and 24!PWM channels. Additionally, the board
includes 12!PIO (programmable I/O) state machines and a USB!1.1 controller with PHY
supporting both host and device modes. Priced at only $5, the Pico!2 is perfect for
learning and experimenting with RISC-V.
https://raspberrypi.com/products/raspberry-pi-pico-2

March & April 2025 13

 PROJECT

An FPGA-Based
Audio Player
with Equalizer (1)
Mixing Digital Audio with an Arduino MKR Vidor 4000

By Dr. Christian Nöding (Germany)

The Challenge: Building a
Have you ever wanted to know what is inside a Versatile Audio Mixer
digital audio mixing console? Or have you already Studying the P16-I fascinated me and gave me
the idea of designing my own audio mixer. My
programmed some MP3-player based on an ESP32 and goal was to design an audio system capable
the great Arduino libraries, but without the option for of inputting up to 20!channels from various
processing these audio signals? In this two-part series, analog and digital sources, processing these
signals in real time, and mixing them with
we will create a multichannel digital mixing console advanced audio features like equalization
with multiband equalizers, an audio !le player and an and dynamic control. This project replicates
analog input. Rock your next party with an expandable a mixing console’s core functionality, and we’ll
also keep it flexible and see how to expand
DIY system! its functionality.
!
Choosing the Right Platform
This is the first part of a two-part series The P16-I features 16!analog inputs and six Since the advent of digital audio, signals
exploring the design and implementation of Ethernet-like jacks for digital audio output via have been processed at specific bit depths
an FPGA-based audio player with equalizer Cat5e cables, using a protocol called “Ultranet.” and sample rates. Modern audio, often
functionality, using the Arduino MKR Vidor Ultranet is a slightly modified AES/EBU signal, 24-bit with sample rates starting at 48!kHz,
4000. In this part, I’ll explain the foundational which we’ll explore later in detail. demands high processing power, which
aspects of the project, including the required !
toolchain, the interplay between FPGA logic
and microcontrollers, and an introduction to
the basics of audio signal processing. By the
end, you’ll have a clear understanding of the
project and its goals. The full documentation
and source files are available online, with links
provided at the end of the article.
!
The Starting Point
For over 10!years, I’ve been a fascinated user of
digital audio mixing consoles without question-
ing their inner workings. However, when I
found a defective digital Behringer P16-I at a
flea market, I saw an opportunity to dig deeper
and understand how such a device operates. Figure 1: Arduino MKR Vidor 4000.

14 March & April 2025 www.elektormagazine.com

smaller microcontrollers struggle to manage must flip the bit order of the file to generate The FPGA will be able to receive digital audio
in real time. This is where digital logic, and an Arduino-compatible header file. We can data from a variety of sources: either from a
particularly FPGAs, excel. So, how to find the use the small program vidorcvt from [5] on coaxial or optical S/PDIF or TOSLINK jack
right FPGA board for our needs, one that’s the command line: (stereo), an analog-to-digital converter with
both user-friendly and appealing in terms of ! stereo I2S output, the ESP32 (with playback
hardware? vidorcvt.exe < FPGA.ttf > bitstream.h from MP3 files on an SD Card) via I2S and
! ! finally, the already mentioned 16-channel
While researching an FPGA solution for this At each boot of the SAMD21, when the input from the Behringer Ultranet signal. In
project, I came across the Arduino MKR function setup_fpga() is called within our this article, I will focus on the digital signal
Vidor 4000. This board from Arduino’s MKR Arduino sketch, the FPGA is configured processing aspect of the project. For testing,
family combines an ideal set of components with the content of bitstream.h copied to I used jumper wires for all connections. To
for digital audio processing: two microcon- the onboard SPI-Flash during flashing the read data from a micro SD card, you can use
trollers, built-in Wi-Fi and Bluetooth, and of SAMD21. This occurs at every power-up, as an extension board like the Arduino MKR SD
course an FPGA — making it a perfect starting FPGAs are losing their logic on a voltage loss. Proto Shield or a similar module. To implement
point for this project. ! all these audio inputs more neatly in a more
! Mixing C Code and Digital Logic advanced version, it would be necessary to
Figure 1 shows this Arduino board. Next to A digital audio system consists of both create a small motherboard with two rows of
the USB port, a SAMD21 microcontroller from time-critical real-time processing, as well as pins matching the headers of the MKR Vidor
Microchip connects to a host computer and less critical, but more complex calculations 4000 and equipped with all the appropriate
acts like a bridge to the onboard FPGA at the based on user inputs. The former use the connectors.
same time, as both share pins of the MKR fast and parallel processing properties of the !
pin header. The NINA W102 module made by FPGA; for the latter we benefit from the advan- Besides processing all the input signals, the
U-blox, containing a full-featured dual-core tages of microcontrollers to handle complex FPGA will be equipped with five full-fea-
ESP32, connects to the FPGA as well. In its calculations. Figure 2 shows the connection tured parametric equalizers followed by a
original condition the NINA module contains of all three devices on the MKR board: the Linkwitz-Riley Crossover filter to feed a 2.1
a special software from Arduino, to commu- USB port is used for software updates of the stereo set with connected subwoofer — we
nicate via Wi-Fi and Bluetooth. An onboard USB controller (SAMD21) piggy-backing the want to hear and “feel” the sound, right? As
Flash chip contains a predefined logic from bitstream of the FPGA and programming the mentioned, some calculations are better for
Arduino for the FPGA. But for our audio appli- onboard SPI Flash during the upload-process. a microcontroller. Calculating the filter coeffi-
cation we will change the setup of all three Once we have a working FPGA, we can route cients for the used IIR filters is certainly a task
devices for our own purpose. some communication lines through the FPGA for a CPU rather than FPGA, but we get back
! to the NINA/ESP32 to program it via the to this in a moment.
Setting Up the Toolchain built-in bootloader. Furthermore, the SAMD21 !
First, we must prepare our toolchain to is used for calculating some nice VU-meter Webserver
support all desired devices. For the NINA/ effects and has a lot of free program space and Another task for the ESP32 is the communica-
ESP32, follow the tutorial at [2] to install calculation time remaining for your own ideas. tion with the environment – specifically with
the ESP32 package to the Arduino IDE. For !
the SAMD21 you find the official Arduino
sources by searching for “SAMD” in the board
manager library. As we are planning to upload
our own bitstream to the FPGA, we must
download the design software Quartus Prime
Lite from Intel![3]. The usual way to upload
a new bitstream to these kinds of FPGAs
is using a special JTAG adapter. Thankfully,
there is an Arduino library under![4] to upload
own bitstreams by embedding it into a regular
header file of the Arduino sketch directly.
!
Quartus will output the created logic in several
output formats. One of them is the tabular
text file, containing the configuration data
for use outside of the Quartus software. To
feed our JTAG emulation with these data, we Figure 2: Overview of the multi-controller-system.

March & April 2025 15

 is the sync-block, that contains conventional
bits forming the so-called “preamble”, an eight-
bit pattern. For the preamble three different bit
patterns using invalid Manchester codes are
specified. That allows us to identify the begin-
ning of channel 1 on receiving the preamble Z
which is sent every 192!subframes. The four
status bits can be ignored when receiving the
pure audio samples.
!
Now, the first task for the FPGA is to decode
the Manchester-coded S/PDIF!serial data.
Figure 3: AES/EBU signal containing up to 24 bits of digital audio data. Therefore, it must collect the individual bits
into a shift-register and search for the three
high bits of the preamble. Within a state
machine, the synchronization to the signal
is monitored and the inherent bit clock of
the Manchester code is restored to an inter-
nal clock signal. As the space for this article
is limited, I’m not going into details of this
specific block as I’m using a slightly modified
VHDL block from OpenCores.org, a nice page
with lots of VHDL snippets [7]. The receiver
block outputs a conventional I2S signal, that
is much easier to handle.
!
As Ultranet is using AES/EBU, as S/PDIF, we
Figure 4: Inter-IC-Sound (I2S) signal. can convert our individual subframes into an
I2S signal with the same receiver block. The
only additional task is a channel counter,
our mobile phone. As shown in many projects From Stereo to Multi-Channel counting from channel 1 to channel 8 instead
in Elektor, we are using the SD card to load the But enough said about web interfaces – our of the stereo signals of S/PDIF, synchronized
webpages and we are using the well-known audio data waits to be processed. As FPGAs to the Z preamble again.
Bootstrap framework to style our interface. are great to handle parallel tasks, we can !
With some basic HTML knowledge, it is possi- implement the inputs for all desired signals “Inter-IC Sound,” or I2S (see Figure 4), uses
ble to create a fancy and responsive user inter- as parallel logic. The idea is, to convert the a fixed serial clock (bit clock) as well as a
face. A small Javascript within the website is serial data (mainly S/PDIF, Ultranet and I2S) word-select signal (also called word clock or
polling some update information using AJAX into individual 24-bit logic vectors that we can LR clock) to transmit audio data. So at least
over a REST-like API fed by the webserver of handle quite easily. Let’s start with S/PDIF three connection lines are necessary. Here
the ESP32, like current title, progress, volumes, and Ultranet. Both use AES/EBU, an inter- we must create a logic, that searches for the
equalizer settings, and more. User inputs are face for digital audio data specified in 1985. falling or rising edges of the word-select as
passed to the file cmd.php. Even though It transmits between 16 and 24!bits of stereo synchronization. So, we can read individual
we are not implementing a full-blown PHP audio data with sample rates between 32!kHz bits into a shift register on each rising edge of
server, the browser will transmit the param- and 192!kHz. According to the App Note [6], the serial clock. One pitfall is, that the word-se-
eters which our webserver will parse and call AES/EBU contains a data structure shown lect is shifted by one clock cycle.
the desired functions. For example the call in Figure 3, representing a single subframe. !
/cmd.php?mixer:volume:main=-6 will be Ultranet transmits four stereo channels on two The Digital Logic
translated to the C function executeComman separate lines with 48!kHz, to maintain the So, let’s dive into the digital logic (see
d("mixer:volume:main@-6") and set the maximum sample rate of 192!kHz. Listing 1). First, we define our input and output
volume to -6 dB. The same command can be ! signals. Here we need the main clock, which
sent via USB as well. With this ASCII-based Most of the S/PDIF data is encoded using a must be much faster as the signal to be read,
command system, it would also be very easy differential Manchester encoding, so that the followed by the other signals, each defined
to add MQTT commands to the firmware, like bit clock is transmitted multiplexed with the as logic signal as we are reading serial data
fbape/mixer/volume/main -6, for example. serial data (see Figure 3 again). An exception bits. The output then is defined with two
!

16 March & April 2025 www.elektormagazine.com

logic vectors with a width of 24 bit as we are
processing all audio data with this bit depth Listing 1: Defining the inputs and outputs.
within the FPGA. 16-bit signals will be scaled
entity i2s_32bit_rx is
to 24-bit by bit-shifting by 8!bits to the left to
port (
keep the 0!dB Fullscale (dBfs) level.
clk : in std_logic := '0'; -- Mainclock
!
sclk : in std_logic := '0'; -- I2S serial-clock
Now we are ready to detect the edges of our
sdata : in std_logic := '0'; -- I2S serial-data
three signals. The way to do this is shown
wordclk : in std_logic := '0'; -- I2S word-clock
in Listing 2. In this case, it is the bit clock
that is considered, but for the word clock it
out_l : out std_logic_vector(23 downto 0) := (others=>'0');
is comparable. Here we are only reacting on
out_r : out std_logic_vector(23 downto 0) := (others=>'0');
the positive edge and will create a process for
sync_out : out std_logic := '0' -- high for 1 clock if successful
this. Within this process, we will use a shift
);
register to detect a change within the serial
end i2s_32bit_rx;
clock sclk by comparing it to the previously
sampled zsclk. If a positive edge is detected,
we set b_pos_edge to 1, otherwise to 0.
!
On each positive edge of b_pos_edge we will
then store the read bit into a shift register. As in
the I2S signal the first received bit is the most
significant bit, we must add the current serial
bit sdata from the right into the register while
removing the left most bit (see Listing 3). Listing 2: Syncing with the clock.
!
detect_edge : process(clk)
We can now take the word clock into account
begin
to copy the correct bits to the output logic
if rising_edge(clk) then
vectors. As the word clock is shifted by one
zsclk <= sclk; -- save current serial-clock
bit clock, the shift register has more bits
if zsclk = '1' and bclk = '0' then
than the designated payload data. Finally,
b_pos_edge <= '1';
we remove the least significant 8 bits from
else
the 2× 32-bit buffer and output the desired
b_pos_edge <= '0';
24-bits (Listing 4).
end if;
!
end if;
FPGA Audio Processing
end process;
All serial audio data is now within our FPGA
represented in handy logic vectors with a bit
depth of 24!bits. These bits contain signed
audio-samples and will be updated with a
sample rate of 48!kHz (or whatever the origi-
nal signal will use). This represents a fairly
large number of signals: assuming an external
stereo ADC connected via I2S, the I2S stream
from the ESP32’s SD card, and the AES/EBU Listing 3: Bit-shifting the received signal.
input (which represents between 2 channels
in case of S/PDIF and 2 × 8 channels in case get_data : process(clk)
of Ultranet), there are between 6 and 20 input begin
signals now. Great! if rising_edge(clk) then
! if b_pos_edge = '1' then
Going Further s_shift <= s_shift(s_shift'high - 1 downto 0) & sdata;
With the toolchain prepared and the founda- end if;
tional concepts of FPGA and microcontrol- end if;
ler interaction established, we’ve also begun end process;
our journey into audio signal processing by

March & April 2025 17

 Listing 4: Processing the output data.
detect_sample : process(clk)
begin
if rising_edge(clk) then
if wclk_neg_edge = '1' then
signal_l <= s_shift(62 downto 31);
elsif wclk_pos_edge = '1' then
signal_r <= s_shift(62 downto 31);
sync_out <= '1';
else
sync_out <= '0';
end if;
end if;
end process;
-- take only 24 bits beginning at MSB (signed-bit)
output_l <= signal_l(31 downto 8);
output_r <= signal_r(31 downto 8);

converting stereo data into a manageable

format for FPGA-based manipulation. In the
next part of this series, we’ll build on this
groundwork to implement advanced features
like volume control, parametric equalizers,
dynamic compressors, and crossover filters,
bringing the project to life as a full-fledged
digital audio system. The documentation is About the Author
available on my GitHub repository![8]. Stay Dr.-Ing. Christian Nöding studied electri-
tuned for the second part in the next edition cal engineering at the University of Kassel Related Products
of Elektor! from 2003 to 2009. He then began working
230632-01 at the department of Power Electronics at > Dogan and Ahmet Ibrahim,
Practical Audio DSP Projects
the University of Kassel and completed his
with the ESP32 (Elektor 2023)
Questions or Comments? PhD in 2016. His main interests lie in the www.elektor.com/20558
Do you have questions or comments about design and control of electronic power
this article? Feel free to contact the author converters for decentralized energy supply, > Elektor Audio Collection
at christian@noeding-online.de, or contact stage and lighting as well as music and (USB Stick)
www.elektor.com/19892
Elektor at editor@elektor.com. digital audio technology.

WEB LINKS
[1] The Arduino MKR Vidor 4000: https://docs.arduino.cc/hardware/mkr-vidor-4000/
[2] ESP32 Package for the Arduino IDE: https://docs.espressif.com/projects/arduino-esp32/en/latest/installing.html
[3] Quartus Prime Lite from Intel: https://www.intel.com/quartus
[4] An Arduino library that uploads your custom FPGA bitstream: https://github.com/HerrNamenlos123/JTAG_Interface
[5] Software for Arduino Vidor boards: https://github.com/wd5gnr/VidorFPGA/tree/master/C
[6] Application Note from NTI Audio: https://www.nti-audio.com/Portals/0/data/en/NTi-Audio-AppNote-AES3-AES-EBU.pdf
[7] Simple AES3 or SP/DIF receiver on OpenCores: https://opencores.org/projects/aes3rx
[8] Author’s GitHub repository: https://www.github.com/xn--nding-jua

18 March & April 2025 www.elektormagazine.com

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 PROJECT

Laser Head for Pico-Based

Sand Clock
Drawing with Light

b•
or la Elekt
kt

Ele

or
lab
ORIGIN
AL

Ele k

ab
rl rl

to
• Ele k to
ab
By Clemens Valens (Elektor)

The laser head kit presented in 2018

turned the Elektor Sand Clock of 2017
This version of the Sand Clock is currently available in the Elektor Store.
into a clock that writes the time on glow- Therefore, it is only logical to also reissue the laser head modification
in-the-dark film instead of in sand. A few for the current Sand Clock, which is what we did.
years later, the Sand Clock was redesigned !
Hardware Update
to use the Raspberry Pi Pico instead of the The new laser head kit is almost identical to the kit from 2018, except
Arduino UNO — this version is currently for the laser holder arm that was made a bit more robust. Instead of an
available in the Elektor Store. Therefore, open, clamping grip, the holder is now a closed ring that cannot break,
at least not easily (Figure 1). The laser is kept in place with two rubber
it is only logical to also reissue the laser rings with the arm sandwiched in between (Figure 2). Because the
head modification for the current Sand rest of the pantograph remained the same, assembling it is identical to
Clock. And why not use the clock to make the way described in 2018. Note that the stand-offs that carry the sand
bed must be turned upside down for use with the laser head (Figure 3).
drawings? In this article, we explain how !
you can achieve this. The UV laser replaces the two vibration motors used by the Sand Clock
to level the sand. These motors are powered with a voltage of about
!! 3!V. Diodes D2 and D3 take care of lowering the 5-V power supply to a

In January 2017, Elektor published the Sand Clock, a novel clock that
wrote the time in a sand bed [1]. It was based on an Arduino UNO. A
year later, a modification was published [2] that replaced the sand bed
by a sheet of glow-in-the-dark film and the pen by an ultraviolet laser.
The laser clock was more discreet than the Sand Clock, as it didn’t need
to shake the sand bed every time to clear it before writing the new time.
!
A second update [3] added a stand to allow the laser clock to be placed
vertically on a horizontal surface instead of hanging it on a wall. A PIR
sensor was added too, so the clock could be made to write the time
only if there was someone around to see it.
!
A few years later, the Sand Clock with the PIR sensor option was Figure 1: The new laser head mount has a ring rather than a grip to hold the
redesigned to use the Raspberry Pi Pico instead of the Arduino UNO. laser.

20 March & April 2025 www.elektormagazine.com

Figure 2: The laser is fixed with two rubber rings. Figure 3: The stand-offs must be faced pointy threaded-side down.

suitable level. The laser, on the other hand, needs a 5!V supply, and so V_USB

diodes D2 and D3 must be bypassed, see Figure 4. This is easily done

by running a length of wire from the 5-V pin of the PIR connector to the D2
M+ pin of the vibration motor’s screw terminal (Figure 5). That’s the
only modification required for the circuit board. D4 D3

! D2...D4 = S2J-E3

Note that the new laser head is compatible with the original Arduino-
DC1

C1
based Sand Clock from 2017. It requires a similar modification for the
laser’s power supply as described above. Refer to [2] and [3] for the VIBRATION
100n

details. MOTOR R10

Q1

! R11
330

Software Update

100k
The software of the Raspberry!Pi Pico-Based Sand Clock has been
updated to drive the laser instead of the vibration motors. The main
240647-001
changes are the dimensions of the new pantograph arms that differ
slightly from the Sand Clock and, of course, the On/Off control of the
laser that replaces the vibration motor control. Figure 4: The red line shows the electrical modification of the main board.
!
While we were working on the new software, it was thought interesting
to add a vector-drawing option to the clock. The functions required to
draw lines, arcs, and circles were already available in the clock’s software,
and the observant user might have noticed the comments describing
serial commands for them in the source code. Therefore, we added
the possibility to receive a drawing script and execute it. Instead of just
writing the time, the clock can now also be used to create ephemeral
works of art (Figure 6).
!
Furthermore, as the Raspberry Pi Pico has plenty of program memory,
scripts can also be placed in memory. This allows you to create anima-
tions, turning the clock in a fun decorative object for, e.g., Christmas
or other special events. Making a script is a bit laborious, though, as
it requires you to convert a drawing into line and arc segments with
millimeter coordinates. However, a PCB design program like KiCad or a
mechanical 2D-design program capable of drawing in millimeters can Figure 5: The electrical modification in practice.
help you here. We’ve left the implementation of a g-code interpreter as
used by CNC machines as an exercise to the reader. !
! The following commands can be used:
Drawing Commands !
The commands available for drawing are simple text-based commands f: Script start, not required when a script is stored in internal memory.
that can be sent over a serial link. Make sure that the serial port speed @: End of script, not required when a script is stored in internal memory.
of your terminal program is set to 115,200!baud (with eight databits, no !
parity, one stopbit, i.e., 115200n81). Also, serial commands must be termi- pld: Laser head down.
nated with both CR (carriage return) and LF (line feed). In Tera Term this plu: Laser head up.
is configured in Setup! Terminal! New-Line! Transmit: CR+LF. To le: Laser enable (on).
send a script file using Tera Term, use the File! Send File command. ld: Laser disable (off).

March & April 2025 21

 Numerical values may have decimals and signs, which in theory allows
for very precise positioning of the laser. In practice, however, this preci-
sion is not respected at all due to play in the pantograph joints and the
wideness of the laser beam that is highly dependent on the writing height.
!
Note that the real origin of the pantograph (0,0) is right between the
two servos that drive the arms. Therefore, it is unattainable by the laser.
Figure 6: A script received over the serial link is being processed. !
The file scripts.h included in the source code available from [4] contains
! a few example drawings. To execute a built-in drawing script from the
Moving command line, use the command z with the number of the script as
pm <x> <y> and ps <x> <y> parameter (starting at 0). For example, execute built-in drawing script
! no. 0.:
Move to position (x,y). Both commands pm and ps produce the same !
result. The values of <x> and <y> are in millimeters. The horizontal origin z 0
(x!=!0) of the canvas is in the horizontal middle of the bed, therefore !
x-values may be negative. The vertical origin (y!=!0) is 10!mm below You can, of course, add your own scripts to this file. Enjoy!
the bed; therefore, when drawing, the y-value should not be smaller 240647-01
than about 10!mm. The exact limits depend on your construction and
calibration. Example:
! Firmware Update for Raspberry Pi-Pico-Based Sand
Move to x!=!25!mm, y!=!48!mm (i.e., up and to the right): Clock
! A byproduct of adapting the Raspberry!Pi-based Sand Clock
pm 25 48 software for the laser head was a correction of an issue sometimes
! observed with the Sand Clock. When connected to a computer,
Arcs and Circles everything worked fine, but when in stand-alone mode (i.e., only
pa <rx> <ry> <ab> <ae> connected to a power supply), it would write the time just once.
! This issue has been fixed in V1.5. You can download it from [1].
Starting at the current position, draw an arc with a horizontal radius of
<rx>, a vertical radius of <ry>, and from angle <ab> to angle <ae>. If
the end angle <ae> is greater than the begin angle <ab>, the laser will Questions or Comments?
move counterclockwise, else the laser moves clockwise. The angles are Do you have technical questions or comments about his article?
in radians, unless they are postfixed with the letter d, in which case they Email the author at clemens.valens@elektor.com or contact Elektor
are interpreted as degrees. Example: at editor@elektor.com.
!
Draw a counterclockwise arc from 73° to 253° with a horizontal and
vertical radius of 5.2!mm:
!
pa 5.2 5.2 73d 253d Related Products
!
Draw an ellipse with a horizontal radius of 5!mm and a vertical radius > Laser Pen for Sand Clock
www.elektor.com/21107
of 10!mm:
! > Sand Clock Kit (based on Raspberry Pi Pico)
pa 5 10 0d 360d www.elektor.com/20679
!

WEB LINKS
[1] Ilse Joostens & Peter S’heeren, “Sand Clock - A Real Eye-Catcher,” Elektor 1-2/2017:
https://elektormagazine.com/magazine/elektor-201701/40130
[2] Ilse Joostens & Peter S’heeren, “Laser Time Writer - Writing with light,” Elektor 1-2/2018:
https://elektormagazine.com/magazine/elektor-201801/41254
[3] Ilse Joostens & Peter S’heeren, “Laser Time Writer - Revisited!,” Elektor 7-8/2018:
https://elektormagazine.com/magazine/elektor-201807/41746
[4] Downloads for this article: https://elektormagazine.com/labs/laser-head-for-raspberry-pi-pico-based-sand-clock

22 March & April 2025 www.elektormagazine.com

 CONTEST

ENTER THE STM32 EDGE AI CONTEST

By the Elektor Content Team

Unleash your creativity in the STM32 Edge AI

Contest! Turn bold ideas into reality with the
STM32N6 and showcase your Edge AI skills.
Submit a project idea by April 30, 2025, to
have a chance to get a free well-equipped
STM32N6570-DK Development Kit!

Explore the cutting edge of artificial intelligence and edge comput- The STM32N6570-DK Dev Kit
ing by participating in the STM32!Edge AI!Contest, powered by The first high-performance STM32 MCU with AI acceleration is
STMicroelectronics. This is your chance to bring your most innova- your ultimate tool for advanced prototyping and development.
tive Edge!AI ideas to life using the STM32N6570-DK Discovery Kit. With the STM32N6570-DK Discovery Kit, you can bring your AI
Whether you’re an experienced developer or a passionate maker, this vision projects to life with unparalleled ease and efficiency. Whether
competition is your platform to demonstrate your expertise, creativity, you’re developing next-gen applications or exploring innovative
and problem-solving skills. prototypes, this kit has everything you need to succeed. Elevate
! your AI projects today!
Timeline
> Deadline for Project Ideas:!30!April 2025 Key Features
> Deadline for Final Project Submissions:!1!September 2025 • STM32N657!microcontroller — with Neural-ART accelerator and
> Nominees Revealed: 30!September 2025 4.2 MB SRAM
> Grand Winner Announcement: November!2025 — Stay Tuned! • STLINK-V3 debugger — Effortless debugging and programming
! • STMod+!& Arduino UNO connectors — Expand with unmatched
Prizes flexibility
> 1st!Prize: €2,500 • MIPI connector — High-speed camera interface for seamless
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Visit www.elektormagazine.com/stm32ai for details and to submit a • 32 MB Hexadeca-SPI PSRAM — Power your most complex tasks
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!
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Partner Content March & April 2025 23

 PROJECT

A Multi-Sensor
Environmental
Monitoring
System
for Plants
Wireless Measurement of
Water Supply and Light Conditions
Source: Adobe Stock

By Alain Romaszewski (France) My goal was to create a multi-sensor environmental monitoring system
for plants and greenhouses, using a wireless development board from
This project was designed to care STMicroelectronics and various sensors to measure soil moisture,
for indoor plants or a greenhouse temperature, humidity, air quality, and light conditions. It wirelessly
transmits data via the Zigbee protocol, with the ability to remotely
during times when you may be control irrigation and lighting, and stores the collected data in an
away, while also storing data to SQL database. Automation is managed through Node-RED, allowing
analyze and optimize watering real-time adjustments and remote monitoring through a web interface.
!
cycles. It uses the An overview of the project is shown in Figure 1. The STM32WB5MM-DK
STM32WB5MM-DK board with development board is coupled to a custom-made extension shield, all
multiple sensors and Zigbee integrated in a 3D-printed case. This main module integrates several
internal sensors to measure environmental conditions. External sensors
communication, alongside are used to monitor soil moisture and soil temperature for three differ-
software like Node-RED and ent plants. For water supply management, the board controls the
Zigbee2MQTT for automation irrigation pumps for the three plants and checks that enough water
is left in the reservoir using the sensor. When it comes to lighting,
and remote control. The project the system measures luminosity and controls the lighting based on
was entered in the ST Wireless these readings.
Innovation competition organized !
The data gathered by these various sensors are transmitted as attri-
by Elektor and ST — and won the butes over the Zigbee protocol. (See more details in the text frame
second prize. More about Zigbee.) A USB dongle is used as a wireless interface
and the ZigBee2MQTT application, installed on a Windows!11 machine,
creates a Zigbee Coordinator, which additionally bridges between
ZigBee events and a remote MQTT server. Each attribute defined in the
measurement system updates on the MQTT server, and any changes
made on the server can be sent back to the measurement system.
!

24 March & April 2025 www.elektormagazine.com

 Web Browser

Internet
RF USB dongle

Zigbee2mqtt Coordinator Mosquitto MQTT Broker

Zigbee2mqtt Frontend Internet NodeRed Dashboard

Windows 11 PC Linux Server

Zigbee

Figure 2: The system in use.

STM32WB5MM-DK + Sensors

Water Tank

x 3 plants Light Control

Figure 1: General architecture of the project. Figure 3: The STM32WB55MM-DK development board.

Since the data is accessible via the MQTT server, I chose to use water each plant individually from a shared reservoir. A three-part
Node-RED to subscribe to the server and track events, enabling enclosure, designed for easy mounting of the PCB and the additional
automation. In my case, Node-RED is running on a Virtual Private daughterboards (see below) while allowing button access, was 3D
Server (VPS) hosted by OVH and running Debian. The Dashboard printed with ASA material.
feature of Node-RED provides a user interface accessible through a !
web browser from all over the world. Furthermore, all data is stored in Sensors
an SQL database for further analysis. The system can be seen being For each plant, a soil moisture sensor is used. Like all the sensors in this
used in Figure 2. project, these are easy to find at various places on the internet. They
! are capacitive, with two electrodes forming a capacitor. A 1-MHz signal
Main Board is applied to the electrodes. The capacitance between the electrodes
The STM32WB5MM-DK board (Figure 3) is built around the changes with the soil’s moisture content, which changes the frequency.
STM32WB5MMG microcontroller from STMicroelectronics, which That frequency change is finally converted into an output voltage.
includes a Cortex M4 core and a Cortex M0+ communication copro- To protect the electronic components of the sensor, I 3D-printed an
cessor. To operate, the coprocessor needs to be flashed with the appro- enclosure in ASA material and filled it with two-part resin. The result
priate firmware based on the selected protocol and settings. The board is shown in Figure 4.
provides 1!MB of flash memory and 256!KB of RAM. !
! An ADS1115 (16-bit, four-channel analog-to-digital converter) from TI
I use the integrated temperature sensor on the board. This board connected via the I2C1 bus is used to measure the voltage from the
has two I2C interfaces named I2C1 and I2C3; the temperature sensor soil moisture sensors. I found this converter and sensor arrangement
connects to the latter. Measurements are displayed on the onboard to be fairly robust against interference caused by noise and long wire
LCD screen, and navigation through the various display screens is lengths. The soil moisture sensors have been modified to operate on
controlled via two buttons. Other I/Os (including the I2C1 bus and six
other GPIOs) available through the Arduino-compatible set of headers
are used for managing pump and light controls, water level readings,
and interfacing with the soil temperature sensors.
!
The board is powered through USB; I also installed a battery backup
to supply three low-power water pumps (operating at 3!V), used to Figure 4: Soil moisture sensor.

March & April 2025 25

 A Short Review of the STM32WB5MM-DK
The STM32WB5MM-DK is a good development board offering
many options for those working on IoT projects. On the plus side,
the board is equipped with a rich set of sensors, an integrated
debugger, and a well-sized flash memory and RAM. The processor
also integrates the entire RF part, which is a notable advantage,
although its implementation on a PCB can be tricky and adds
to production costs. It’s very easy to use, and the abundance of
provided examples allows for quick learning and implementation.
!
However, there are some limitations to be aware of. The Zigbee
firmware is somewhat obscure, though ST can provide the sources
under certain conditions. Additionally, custom endpoints and clusters
do not behave as expected, and only 8 attributes can be edited or
read per request, which can be restrictive. Managing two processors
with two applications can also feel cumbersome. In this respect,
using the NUCLEO-WBA52CG board (also available for this ST
contest) would have been more flexible, as it only has a single
microcontroller.
!
While the board offers great functionality, the lack of examples using
FreeRTOS, no external antenna option, and no Arduino support
for Zigbee are drawbacks. Furthermore, the examples don’t use
STM32CubeMX, which complicates adding peripherals or tweak-
ing settings. Overall, it’s a solid development board, you just need
to keep its limitations in mind.

Programming
Figure 5: Custom PCBs to connect sensors. Firmware (version 1.18 in this case) from the manufacturer must be
downloaded into the memory area reserved for the M0+ radio proces-
sor. There are several firmware options for BLE, Thread, Zigbee, and
3.3!V by removing the voltage regulator and are connected to three BLE-Zigbee combinations, which are selected based on the specific
inputs of the ADS1115 analog-to-digital converter. One input of the use case. These firmware versions (the current version is 1.20) can
converter is used to measure the battery voltage, which is divided by be found online [1].
two to respect the ADS1115’s maximum input voltage. !
! The programming for this project was carried out using the C language
To monitor soil temperature, three DS18B20 sensors from Analog and the STM32CubeIDE 1.14 environment. The project is based on an
Devices are used, each housed in a stainless steel tube. These sensors example from the STM32WB library [2]. The example program can be
operate over a shared 1-wire bus. Other environmental measurements, found online [3]. The system uses a pseudo-preemptive multitask-
such as temperature, humidity, and pressure, are provided by a BME280 ing model specific to STMicroelectronics and includes
sensor from Bosch, while CO2 , total volatile organic compounds advanced functions for processor communication.
(TVOC) and indoor air quality (IAQ) levels are measured using an However, the provided example does not utilize a
ENS160 sensor from ScioSense. An AHT25 sensor (Aosong) is also known real-time operating system (RTOS).
used for temperature and humidity compensation. Finally, luminosity !
is measured by a VEML7700 lux meter from Vishay. All these sensors
operate on the I2C1 bus. The water level in the tank is monitored using
a capacitive sensor mounted at the low level of the tank.
!
External Interfaces
An Arduino-compatible interface card was developed to simplify sensor
connectivity. This card includes a switching power supply module to
power the sensors and recharge the battery, which provides additional
power for the pumps. It also houses the ADS1115 converter on a PCB
module. Additionally, a custom interface card was made to control the
pumps. This PCB has several N-channel power MOSFETs connected
to the microcontroller’s ports. The interface boards are shown on
Figure 5; see the connected sensors in Figure 6. Another external
module, equipped with a solid-state relay in a custom 3D-printed
enclosure, is used to control a 230!V!/ 200!W light source. Figure 6: Connected sensors.
!

26 March & April 2025 www.elektormagazine.com

 Initialization
Zigbee stack
I2C and I/O port
Sensors

Configuration of cluster
and fix atrtributes default
values

Automation thread Start Zigbee Stack thread

Zigbee
Stack
started ? yes
Button 1 Erase NVM memory
pressed

no
Read each Sensor and write
Attributes
Already yes Start Commissioning to
commissionned coordinator
?
no
Zigbee no
Stack
started ? Load NVM memory Wait for coordinator

yes

Display Attributes on screen Zigbee Stack Running Save in NVM memory

selected

Read Attribute Time Loop

and wait
Time Loop ms yes
Button1 Previous screen
pressed ?

yes
Button2 Next screen
pressed ?

Figure 7: Flowchart of the program.

In this case, for physical measurements, a client-server architecture running time pump. If this attribute is non-zero, the pump starts
is used, where the client is the PC while the server is the STM32WB- and the value is decremented until it reaches zero, at which point
5MM-DK. The Zigbee coordinator/client is responsible for regularly the pump stops. Each pump is controlled by a separate I/O pin, and
querying the server’s attributes in order to retrieve and store the infor- the ON/OFF status of each pump is reflected in the state pump
mation. To perform actions, the coordinator can modify the values of attribute. Lighting control is similarly managed through the light
the attributes on the endpoint, the latter upon receipt will execute state attribute.
the requested tasks, indicating its status by modifying the attributes. !
! A flowchart of the program is shown in Figure 7, with the automation
To help with this, STMicroelectronics provides a pre-compiled library thread detailed in Figure 8. The function for reading sensor data and
for cluster management. A Zigbee cluster is a group of related attri- transmitting it to the cluster attributes is too lengthy to show in full,
butes and commands within a Zigbee device that defines a specific but key portions are displayed in Listing 1.
functionality, such as temperature measurement or lighting control, !
standardized across Zigbee devices for interoperability. I chose to Zigbee Processing
use a standard temperature measurement cluster. The application The Zigbee stack is initialized in the file Application/User/STM32_
was configured on Zigbee channel!15, with a single server endpoint. WPAN/App/app_zigbee.c, with the the functions APP_ZIGBEE_Init,
A basic cluster is automatically added by the stack. Proprietary attri- APP_ZIGBEE_StackLayersInit, APP_ZIGBEE_ConfigEndpoints, as
butes are then added to this standardized cluster. well as some other functions managing commissioning and persistence
! with non-volatile memory (NVM).
All sensors are queried cyclically, and the results are stored in the !
respective cluster attributes. By default, this occurs every 20!s, though Network formation is carried out by the APP_ZIGBEE_NwkForm function.
the time interval can be modified through the measuring time loop A standardized temperature measurement cluster was created, and
cluster attribute. additional attributes necessary for the project were added. This
! was done in the modules app_cluster.c and app_cluster.h, with the
Automation of the pumps is handled by setting a pump activation AddProjectCluster(void) function, which adds a cluster to the
time, specified in milliseconds, via the corresponding Zigbee attribute application. The implementation of this function is shown in Listing 2.
!

March & April 2025 27

 Automation thread every
1 ms

Current light
yes
Light state attribute value state different
Start or Stop light of attribute
value ?

yes yes
Pump Value Pump State Pump State Started
Different of Started ? Start Pump

Pump State Stopped Pump State Pump Value decrease of

Stop Pump Stopped ? 1 ms or if 1

yes

End

Figure 8: Details of the automation thread.

Listing 1: Reading sensors

void Measuring(void) {
enum ZclStatusCodeT status;
float temp, mes;
int16_t vint16t;
uint16_t vuint16t;
uint16_t als, white;
// Read temperature value of the main board
STTS22H_getTemperatureValue(&temp);
vint16t = (int16_t)(temp * 100);
status = ZbZclAttrIntegerWrite(zigbee_app_info.clusters[IDCLUSTER_CARD],
ZCL_TEMP_MEAS_ATTR_MEAS_VAL, (int16_t)vint16t);

if (status != ZCL_STATUS_SUCCESS) {
APP_DBG("Error Writing Att. temperature in cluster %d", status);
}
APP_DBG("T:%.1f C", temp);
// Read temperature, pressure and ambient humidity with BME280
read_bme280();
if (dev.Error != 0) {
APP_DBG("Error reading BME280: %d", dev.Error);
}
vuint16t = (uint16_t)(dev.pressure * 10);
status = ZbZclAttrIntegerWrite(zigbee_app_info.clusters[IDCLUSTER_CARD],
ATTENVPRESS, (uint16_t)vuint16t);

if (status != ZCL_STATUS_SUCCESS) {
APP_DBG("Error Writing Att. Pressure in Cluster");
}
vint16t = (int16_t)(dev.temperature * 100);

28 March & April 2025 www.elektormagazine.com

 status = ZbZclAttrIntegerWrite(zigbee_app_info.clusters[IDCLUSTER_CARD],
ATTENVTEMP, (int16_t)vint16t);

if (status != ZCL_STATUS_SUCCESS) {
APP_DBG("Error Writing Att. temperature in Cluster");
}
vuint16t = (uint16_t)(dev.humidity * 100);
status = ZbZclAttrIntegerWrite(zigbee_app_info.clusters[IDCLUSTER_CARD],
ATTENVHUM, (uint16_t)vuint16t);

if (status != ZCL_STATUS_SUCCESS) {
APP_DBG("Error Writing Humidity in Cluster");
}
APP_DBG("Temp: %.2f - Hum: %.2f - Press: %.2f", dev.temperature, dev.humidity, dev.pressure);
return;
}

Listing 2: The AddProjectCluster(void) function.

void AddProjectCluster(void)
{
struct ZbApsmeAddEndpointReqT req;
struct ZbApsmeAddEndpointConfT conf;
enum ZclStatusCodeT status;
uint8_t i = 0;

// Create Endpoint Gen

memset(&req, 0, sizeof(req));
req.profileId = ZCL_PROFILE_HOME_AUTOMATION;
// profile >0x7FFF if proprietary
req.deviceId = ZCL_DEVICE_ENVIRONMENTAL_SENSOR;
// Normalized Endpoint else >0x2FFF if proprietary
req.endpoint = ENDPOINT_GEN;
ZbZclAddEndpoint(zigbee_app_info.zb, &req, &conf);
assert(conf.status == ZB_STATUS_SUCCESS);
zigbee_app_info.clusters[IDCLUSTER_CARD] =
ZbZclTempMeasServerAlloc(zigbee_app_info.zb, ENDPOINT_GEN, -4000, 14500, 10);
assert(zigbee_app_info.clusters[IDCLUSTER_CARD] != NULL);
ZbZclClusterEndpointRegister(zigbee_app_info.clusters[IDCLUSTER_CARD]);
status = ZbZclAttrAppendList(zigbee_app_info.clusters[IDCLUSTER_CARD],
attr_list_Main, ZCL_ATTR_LIST_LEN(attr_list_Main));

// Initializing default Pump alimentation and state

for (i = 0; i <= 2; i++) {
status = ZbZclAttrWrite(zigbee_app_info.clusters[IDCLUSTER_CARD], NULL,
ListAttrPumpAlim[i], (uint8_t *)&Automat.PumpValue[i],
2, ZCL_ATTR_WRITE_FLAG_NORMAL);
if (status != ZCL_STATUS_SUCCESS) {
APP_DBG("Error Initialising Att Water Alimentation in Cluster Plant %d", i + 1);
}
status = ZbZclAttrWrite(zigbee_app_info.clusters[IDCLUSTER_CARD],
NULL, ListAttrPumpState[i], (uint8_t *)&Automat.PumpState[i],
1, ZCL_ATTR_WRITE_FLAG_NORMAL);
if (status != ZCL_STATUS_SUCCESS) {
APP_DBG("Error Initialising Att Water Alimentation
State in Cluster Plant %d", i + 1);
}
}
}

March & April 2025 29

 More About Zigbee
The Zigbee communication in this system is based on the IEEE
802.15.4 physical protocol, which shares the 2.4 GHz frequency
band with Wi-Fi. The band is divided into 16 channels (11 to 26),
with some channels not used by Wi-Fi and thus more suitable for
Zigbee use (e.g., channels 15, 20, and 25). All devices connected to
the main coordinator must operate on the same channel. At power-up, pressing button erases the NVM memory and forces a
! re-commissioning process. The list of attributes added within Endpoint 1,
Zigbee operates on a mesh network architecture and follows a to the base cluster (of type TempMeasServer), is shown in Table 1.
master-slave communication model. A brief explanation of how !
Zigbee functions is provided below. Zigbee uses a mesh topology, Program Modules
meaning each device or node can communicate directly with other In the directory Drivers/BSP/Component/, you’ll find drivers for various
nearby nodes. There are three primary types of Zigbee nodes: sensors. The ADS1115 is for a 16-bit AD converter, the BME280 handles
! temperature, humidity, and atmospheric pressure, and the ENS160
> Zigbee Coordinator: The main node responsible for network supports CO2 , air quality index and TVOC sensing. The SSDL1315
initialization and organization. driver is for OLED displays. Other drivers in the directory include AHTxx,
> Zigbee Router: Participates in routing information and can DS18B20, Dwt, OneWire, STS22h, and VEML7700. On the other hand,
function as an end device within the network. the STM32WB5MM-DK directory includes drivers for the buttons, RGB
> Zigbee End Device: A simple device that connects directly to LED and OLED display.
a coordinator or via a router. !
! Finally, the directory Application/User/Core contains the files used
Each router or end device must first connect to the coordinator to to provide a high level control interface to the various sensors and
establish a secure connection, exchanging a key to create an associ- manage system functions. The app_ads1115, app_bme280, app_ahtxx,
ation. This association is stored between the router/end device and app_ds18b20 etc. control the corresponding sensors listed above.
the coordinator, each device having a unique 64-bit MAC address.
The coordinator authorizes associations for a limited time and gener-
ates a 16-bit short address to identify each Zigbee node. Table 1: Zigbee Attributes.
!
In the Zigbee network, master-slave communication is implemented Address Attribute Size (bits) Unit or Range
where the coordinator functions as the master, and end devices
0x000 Temperature Card 16 °C * 100
act as slaves. End devices report data to the coordinator when
the data is modified or at regular intervals, a process referred to 0x101 Battery Voltage 16 0 to 5000 mV
as reporting and binding. 0x303 Temperature 16 °C * 100
! 0x300 Luminosity 16 0 to 65535
Each Zigbee node can consist of one or more endpoints (ranging 0x30B White Luminosity 16 0 to 65535
from 1 to 240). Each endpoint contains one or more clusters, which
0x301 Pressure 16 Hp * 10
represent specific functionalities. Clusters can be standard Zigbee
protocol functions or proprietary ones, with default attributes defined. 0x302 Humidity 16 % * 100
Custom attributes can be added to any cluster. 0x304 AQI 8 0 to 4
! 0x305 CO2 16 ppm
Each attribute is identified by a standardized 16-bit identifier and
0x306 TVOC 16 ppb
contains a value, which can be of varying types (e.g., 8, 16, 32, or
0x307 Resistance 1 32 Ω
64-bit, strings, enumerations, tables, etc.). Attributes can be read,
written, or reported to the coordinator or other nodes at set inter- 0x308 Resistance 2 32 Ω
vals or persistently (its value is then memorized by the endpoint). 0x309 Resistance 3 32 Ω
It’s important to note that Zigbee nodes regularly report to routers 0x30A Resistance 4 32 Ω
and coordinators, which must remain active at all times. This is one
0x30C Tank Level 8 0 or 1
of the protocol’s main drawbacks.
0x340 Light State 8 0 or 1
0x102 Measuring Time loop 16 ms
0x3X0 Temperature Plant X 16 °C * 100
The Zigbee stack handles the protocol for reporting and binding attri- (X from 1 to 3)
butes to other nodes; in this example the only other node is the Zigbee 0x3X1 ID Adress DS18B20 X 64 Address
coordinator on the PC. The program mainly involves updating attri- (X from 1 to 3)
butes and managing automation when attributes change. A portion
0x3X2 Soil Moisture X 16 % * 100
of flash memory is reserved as a Non Volatile Memory (NVM) to store
(X from 1 to 3)
commissioning, reporting, binding, and attribute values. When this
memory is blank, the Zigbee thread attempts to commission with a 0x3X3 Running time pump X 16 ms
coordinator. Once the process is successful, the information is saved (X from 1 to 3)
in NVM memory. On the next startup, this information is reloaded from 0x3X4 State Pump X 8 0 to 2
memory, preventing the need for re-commissioning. (X from 1 to 3)
!

30 March & April 2025 www.elektormagazine.com

 Listing 3: JSON Payloads.
JSON payload sent for writing attribute PlantWaterAlimentation1:

{
"write":
{
"cluster": "msTemperatureMeasurement", "options": {},
"payload": {
"PlantWaterAlimentation1": 1000
}
}
}

JSON payload sent for reading here eight attributes:

{
"read":{
"attributes" :[
"Luminosity",
"WhiteLuminosity",
"PlantTemperature1",
"PlantSoilMoisture1",
"PlantMACDS1",
"PlantWaterAlimentation1",
"PlantWaterAlimentationState1"
],
"cluster":"msTemperatureMeasurement", "options":{}
}
}

The driver app_automat controls automations like pumps and lights,

while app_screen handles the display of measurement results and
app_ScheduleMeasure manages cyclical measurements and Zigbee
attribute updates. Other files include ee, flash_driver, hw_flash to
emulate an EEPROM on a Flash memory area of the processor. Finally,
hw_timerserver, hw_uart, main, and stm_logging are for timers,
serial interfaces and debug display. For example, a typical MQT T topic path would follow the
! <path>/<device>/<endpoint>/set pattern and could be:
Zigbee2MQTT – The Zigbee Coordinator !
To operate, the system requires access to a Zigbee coordinator. In zigbee2mqtt/STM32WB5MM-DK/1/set
this case, an open-source application, Zigbee2MQTT, is used, running !
on either Windows or Linux. The application supports a radio copro- This allows MQTT to modify one or more attributes via a specific topic.
cessor on a USB stick, based on the Silicon Labs EFR32MG21 chip Zigbee2MQTT subscribes to this topic and transmits read or write
with EZSP v8 firmware, and it manages the Zigbee protocol through requests to the Zigbee network. The ZigBee device responds with
a web interface. the attribute values, and Zigbee2MQTT publishes these results with
! separate MQTT topics. Examples of JSON payloads used for reading
Zigbee2MQTT allows commissioning of Zigbee devices, viewing and or writing attributes are shown in Listing 3.
modifying attributes, and interfacing with an MQTT server. When a !
Zigbee device is commissioned, the coordinator receives its description Once the attributes are read, their values are published with the
and distinguishes it by name and manufacturer. While many existing corresponding MQTT topics. Applications can subscribe to topics
devices are already supported by Zigbee2MQTT, custom configuration such as Luminosity, PlantTemperature1, etc., to receive updates
file is needed for the attributes specific to this project. This file specifies accordingly. Commands and attribute modifications can also be tested
the type of attributes and the names that are transmitted to the MQTT directly through the Zigbee2MQTT graphical user interface (GUI). The
server under a designated topic. As a reminder, a topic is a path to a complete configuration for Zigbee2MQTT is available online [4], along
value in the MQTT messaging system. with detailed installation instructions for Windows.
! !

March & April 2025 31

 activating the pumps based on soil moisture levels. Node-RED is highly
customizable, allowing users to adjust the system’s behavior to their
needs. The resulting dashboard is shown in Figure 10.
!
Online Resources and Software
The complete documentation for this project is available in my GitHub
repository![5], including the STM32Cube project in ZIP format, PCB
files, and 3D models for the enclosure. Detailed information regarding
the Zigbee2MQTT configuration can be found in the file ZigBee2MQTT_
on_Windows_install.pdf. Additional details about Node-RED configu-
ration, relevant datasheets, and project images are also included in the
repository. As far as software is concerned, apart from those already
mentioned, I’ve also used and can recommend DesignSpark [6] for
3D modeling, while PrusaSlicer [7] was used for preparing 3D prints.
Figure 9: Node-RED flow. The PCB was designed with EasyEDA [8].
!
Enriching and Motivating
Node-RED Interface and Automation This project provided an opportunity to evaluate STMicroelectronics’
Various home automation tools can be used to manage MQTT topics communication processor and establish a complete measurement
and create automation workflows, such as Node-RED, Home Assistant, system. Future plans involve further development with new products,
OpenHab, etc. For this project, I chose to use Node-RED. It is built on such as the STM32WBA5x, which will be integrated into each sensor
Node.js and allows users to create flows by connecting programma- and actuator. This will allow for battery operation, reducing wiring, and
ble graphical elements (see Figure 9) to manage MQTT publications the ability to work with multiple communication protocols. Last but not
and subscriptions. Node-RED integrates with databases like MariaDB least, this contest allowed me to discover and learn from the work of
and can store attribute values for historical analysis. A timer system other participants, which has been very enriching and motivating!
and a dashboard facilitate interaction, configuration, and automation 240578-01
generation.
! Questions or Comments?
In this implementation, general sensor values from three plants are Do you have questions or comments about this article? Email
displayed, and automation controls the lighting based on luminosity the author at alain@romaszewski.fr, or contact Elektor at
levels and sunset times. Another automation cycle controls watering, editor@elektor.com.

Figure 10: The resulting

dashboard.

32 March & April 2025 www.elektormagazine.com

About the Author Related Products
Alain Romaszewski is a specialist in IT and digital electronics based
in Amélie-les-Bains, Pyrénées-Orientales, France. He teaches IT, > Majid Pakdel, Advanced Programming with STM32
with a focus on Unix systems and networks, at the high school Microcontrollers (E-book, Elektor, 2020)
level. Alain is a founding member of the Physical Measurements www.elektor.com/19527
IUT in Maubeuge, France, and is an expert in the Windev-Webdev
> Node-Red Development Bundle
programming environment and Typo3 CMS. He is also interested www.elektor.com/20849
in research and development for natural resource management.

WEB LINKS
[1] Firmware Downloads: https://tinyurl.com/mw8xw3d4
[2] The STM32WB library: https://github.com/STMicroelectronics/STM32CubeWB
[3] Basic examples: https://tinyurl.com/yeypkdh3
[4] Zigbee2MQTT package and instructions: https://tinyurl.com/3uam3d83
[5] This project on GitHub (Online Resources): https://tinyurl.com/5yhmajkv
[6] DesignSpark Mechanical: https://www.rs-online.com/designspark/mechanical-software
[7] Prusa Slicer: https://www.prusa3d.com/en/page/prusaslicer_424/
[8] EasyEDA: https://easyeda.com/

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March & April 2025 33

 PROJECT

Maixduino AI-Powered
Automatic Doorman
Face Detection with a Camera

By Somnath Bera (India) Automatic doors usually do a great job of

protecting office workers from the outside
Tired of infrared proximity sensors opening a world. They help keep the office at an optimal
door every time someone passes by? With this temperature while still providing easy access
to anyone wanting to enter or exit. In most
project, you can build an AI-powered automatic cases, the conventional infrared (IR) proximity
door system that will help you minimize outside sensor controls doors very effectively.
noise disturbances and improve energy efficiency.
However, in noisy industrial environments,
The system uses a Maixduino development board a little more sophisticated technology may
with a Kendryte K210 chip, combining AI-powered be needed to offer more control. At one of
face detection with a camera and a TFT screen the power stations in India, there are three
massive 660-MW turbines situated on a large
to identify when a person approaches the door 100-meter-long turbine floor. These steam-
directly. The software is written in MicroPython, driven turbines, coupled with a generator at
leveraging the KPU neural network processor for one end, generate around 900 MW; enough
electricity to power a city twice the size of
real-time facial recognition, and controls the door San Francisco.
via GPIO-triggered relays.
The Common Control Room (CCR) for this
important power plant has one main entrance
door, located on the turbine floor side. The
only entrance is through a pair of swing glass
doors — an outer door and an inner door. This
two-door system protects the air-conditioned
atmosphere inside the CCR. When someone
approaches the door, whether from inside or
outside, the doors open one after the other,
allowing the visitor to enter or exit.

This double door setup helps keep the control

room cool and quiet, as the air trapped
between the doors acts as both insulation
and a sound barrier, shielding the CCR as
much as possible from the 140-dB noise of
the turbine generators.

However, there is one drawback common to

The double doors of the Central Control Room at the NTPC power station automatic doors everywhere; people walking
insulate the engineers inside from the high noise levels from the turbine floor. alongside the doors can cause the motion

34 March & April 2025 www.elektormagazine.com

 Figure!1: Maixduino
pinout diagram.
(Source: Sipeed)

sensors to open them, even if they have other remains fully closed. Once the first gate firing the GPIOs. More GPIOs can be deployed
no intention of entering or exiting. In noisy opens and the person enters the chamber, the if needed, depending on the gate mechanism.
environments such as these, it can cause the gate fully closes, isolating the chamber from The gate opening can be customized to field
engineers inside to be constantly disturbed both sides, and only then does the second requirements.
by the outside noise, triggered by the doors gate open. This is usually done by sequentially
opening unnecessarily as the turbine floor’s
loud noise pours in.

A Smarter Solution
The proximity sensor’s function is the root of
this unwanted issue because these IR sensors
have very limited functional capabilities. We
have therefore replaced the traditional IR
proximity sensors with AI-powered facial
detection hardware and proximity calcula-
tion capabilities to ensure the doors only open
when a human approaches.

A small Maixduino-powered development

board (Figure 1) — assisted by a camera,
a TFT screen, and AI code — determines
whether the approaching entity is a human
and how close their face is to the door. If it
crosses a set threshold, the door will open
to allow entry. If the distance criteria are not
met, the system continues scanning for faces,
preventing the doors from opening unneces-
sarily when people pass by.

The logic flow is shown in Figure 2. Note the

“start” and “end” milestones to understand
the built-in logic. Since this is an AI-based
face detection, if a person passes by without
looking at the door, the doors won’t open, even
if the distance logic is satisfied.

Gate-Opening Mechanism
When the conditions are met, two GPIO-pow-
ered relays trigger the gate opening mecha- Figure!2: Flowchart of the logic behind the project.
nisms. Typically, when one gate opens, the

March & April 2025 35

 Using the first distance calculation of up to 175 MaixPy IDE as the development environ-
cm, the width and height of the encompassing ment, tailored specifically for the Maixduino
box are then compared linearly against various board. The accompanying MicroPython code
distances from the camera using a linear is concise, less than 50 lines, leveraging the
model. The distance is extrapolated based on KPU for most of the computation. Facial detec-
the width of the object box. This is similar to tion involves comparing rectangle dimensions
how the base rectangle of a pyramid appears (width and height) against predefined linear
smaller as it moves upwards, eventually reach- models to determine proximity. When the
ing a point at the pinnacle (Figure 3). Likewise, threshold distance is met, the General-Pur-
the picture rectangle becomes smaller as it pose Input/Output (GPIO) pins are triggered.
moves away from the camera.
In this application, two GPIO pins (GPIO 13
Up to 175 cm, a simple linear formula is used: and 12, as shown in Figure 4) control the gate
mechanism via a 5 V relay. The GPIO pins are
Figure!3: Perspective view of the base of a Y=M*X+C connected through a BC547 transistor, with
pyramid. the emitter grounded, and the relay connected
X is the Pyramid Base Rectangle (Face Width), to +5 V. For a 12-V relay, a separate power
and Y is the Height of the Pyramid (distance). supply can be introduced via the transistor’s
Calculating the Distance collector, ensuring flexible power configura-
To determine when to trigger the gates, the AI However, beyond 175 cm, a quadratic equation tions for gate control.
algorithm detects a person’s face and draws is used:
a bounding box around it in the captured MaixPy FaceDetect Classifier
image, which can be seen in real-time on Y = A * X2 + B * X + C The MaixPy FaceDetect classifier uses
the TFT screen. The width of this box is used a pre-trained object detection AI model,
to estimate the distance between the face which provides more accurate results up to which simplifies the implementation of face
and the camera by applying a mathemati- 250 cm. With a better or longer focal-length recognition. This ready-made model can be
cal equation, with the parameters fine-tuned camera, this computation can be further downloaded here [1].
through experiments to ensure precision. improved.

The camera’s focal length is instrumental for Once the distance is within 250 cm, the GPIO
determining the relationship between the fires, and the gate opens or closes.
distance of the face and the size of the facial
box in the image. The change in size follows a Hardware +5V

linear relationship within the focal range, but The chip that sits as the heart of the Maixduino
beyond this range, the relationship becomes board, a Kendryte K210, is a highly integrated
nonlinear, requiring a more complex calcula- system-on-chip (SoC) designed for AI and Door
tion to maintain accuracy. IoT applications, incorporating machine vision 5V

and hearing capabilities. Manufactured using

GPIO12
Two types of distance logic have been imple- TSMC’s 28-nm ultra-low-power process, it
1k
mented: linear for distances up to 175 cm features dual-core 64-bit RISC-V proces-
and quadratic beyond that, up to 250 cm. sors for optimized power efficiency, stability BC547

This was done to enhance the AI-pow- and reliability. The K210 is designed for rapid
ered door system’s accuracy and efficiency. deployment, enabling “zero threshold” AI +5V

The linear model provides fast and reliable development for fast integration into products.
detection for close-range proximity, making
the door responsive when someone is A key component is the Knowledge Process- Door
nearby. The quadratic model ensures more ing Unit (KPU), a general-purpose neural 5V

accurate distance calculations at longer network processor. The KPU supports convo-
GPIO13
ranges, accounting for perspective distor- lution, batch normalization, activation, and
1k
tion as a person approaches from further pooling layers, making it capable of real-time
away. This combination optimizes perfor- object and facial detection. BC547
230050-013
mance across varying distances, preventing
premature triggers and enhancing overall user We are using MicroPython as the program-
experience. ming language to develop the code, with Figure!4: Connections for triggering the gate.

36 March & April 2025 www.elektormagazine.com

 A key component is the Knowledge Processing Unit
(KPU), a general-purpose neural network processor.
The KPU supports convolution, batch normalization,
activation, and pooling layers, making it capable of real-
time object and facial detection.

The MaixPy FaceDetect classifier is avail- > In kflash_gui, select the facedetect.kfpkg Set Auto-Play on Boot:
able in a *.kfpkg file, where * represents file and press Download to install the > To make the program auto-run every
the model name. These models are highly AI model onto the device. You can also time the MaixPy device is powered on,
efficient and fast-acting YOLO (You Only Look modify the flash-list.json file to change go to Tools in the MaixPy IDE and select
Once) Version 2 classifiers. Each scene is the registered model number (0x300000). Transfer File to Board. This will copy the
processed through the model, and the output Python script to the device as boot.py,
is checked against its defined classifiers. Upload a Project with MaixPy IDE: ensuring it automatically starts on boot.
YOLO v2’s speed allows it to quickly identify > Next, download and install the MaixPy > Alternatively, you can copy the Python file
a human face on the screen and draw a box IDE from here [4]. For a complete guide to the root directory of an SD card and
around it. The classifier model used here is to MaixPy IDE, visit the MaixPy wiki [5]. rename it boot.py. Inserting the card into
facedetect.kfpkg. > Open MaixPy IDE and connect your the MaixPy will make it auto-play as well.
MaixPy device by pressing the chain
Aside from simpler face detection, it is also symbol at the bottom left of the screen. Results
possible to use the MaixPy facial recogni- > Load the Python program (e.g., AI-powered face detection is nothing new
tion classifier, but it should be noted that doorman_mod3.py as shown in Figure 6) today. It can easily be accomplished using
this program currently only supports facial by selecting File and opening it in the IDE a powerful computer and camera. However,
recognition for a maximum of 10 faces. A more window. implementing this on a standalone, low-pow-
powerful development board would be needed > To run the program, press the play button ered (5 V) MaixPy microcontroller demon-
to run a more robust facial recognition model. at the bottom left. strates that AI can make life easier, not just

Getting Started: Uploading a

Project with MaixPy
By following these steps in order, you can set
up the software and install the necessary files
before running the project code.

Install MicroPython on the MaixPy Device

> First, connect your MaixPy device to your
laptop via USB.
> Download kflash_gui, the flashing tool
required to install software onto the
device, from this link [2].
> Open kflash_gui and select the correct
serial port for your device (Figure 5).
> If MicroPython is not installed, download
the firmware file (e.g., maixpy_v0.6.2_75_
g973361c0d.bin) from the MaixPy GitHub
repository [3].
> Load the firmware file in kflash_gui and
click the Download button to install
MicroPython on the MaixPy device.

Install the Face Detection Model

> After installing MicroPython, you’ll need Figure!5: Steps to
to select the pre-trained face detection connect the MaixPy
model [1] (facedetect.kfpkg) and upload it. device using kflash_gui.

March & April 2025 37

 Figure!7: The prototype in action. Works
flawlessly!

Figure!6: IDE window showing the Python program.

on powerful computers but also at the micro- been incorporated into the latest software
controller level. The cost-effective Maixduino version which can be downloaded from [8].
Related Product
offers several advantages, including having After making this improvement, it operated
a small yet fast TFT screen, the ability to run flawlessly the entire time I was there. > Sipeed Maixduino Kit for
small AI projects and Micropython codes, and 230050-01 RISC-V AI + IoT
it also offers the sipeed.com repository support. www.elektor.com/18972

This AI-powered automatic doorman was

installed on the CCR doors at the power Questions or Comments?
station where I worked once (Figure 7). If you have technical questions or
Initially, I used a linear proximity trigger with comments about this article, feel
a 175 cm range [6], but I later discovered that free to contact the author by email at
a quadratic solution [7] provides greater preci- berasomnath@gmail.com or the Elektor
sion beyond a certain distance, which has editorial team at editor@elektor.com.

WEB LINKS
[1] MaixPy FaceDetect classifier download: https://dl.sipeed.com/MAIX/MaixPy/model
[2] kflash_gui: https://github.com/sipeed/kflash_gui
[3] MaixPy MicroPython firmware: https://github.com/sipeed/MaixPy/releases
[4] MaixPy IDE: https://dl.sipeed.com/MAIX/MaixPy/ide
[5] MaixPy IDE wiki: https://wiki.sipeed.com/soft/maixpy/en/get_started/env_maixpyide.html
[6] Video demonstration for a range of 1.5 meters: https://youtu.be/-2GsDlSfZVo
[7] Video demonstration for a range of 2.5 meters: https://youtu.be/2NoueDvC3KM
[8] Software download: https://www.elektormagazine.com/230050-01

38 March & April 2025 www.elektormagazine.com

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 FEATURE

Embedded
Electronics
2024
AI Is Set to Redefine the Industry
By Jean-Pierre Joosting (eeNews Europe)
Source: Alif Semiconductor

There were many trends in embedded To address power consumption in edge devices, chip developers
electronics in 2024 ranging from AI at and manufacturers have designed microcontrollers and SoCs with
built-in machine-learning capabilities to enhance performance
the edge, on-chip machine learning, the and efficiency using dedicated low-power neural processing units
use of Generative AI for programming, (NPUs) that can execute machine learning algorithms natively.
collaborative robotics, wearable electronics, Another technology that has come to the commercial market is
event-based neuromorphic computing for very low-power and
the automotive transition to software- wake-up applications.
defined vehicles (SDVs), rising interest in IoT
cybersecurity, and multi-protocol wireless An emerging leader in microcontrollers with integrated NPUs,
Alif Semiconductor [1] has pioneered a different architecture with
devices to mention a few. Some of these key its Ensemble Arm-based microcontroller family (Figure 1), which
trends are highlighted below. can scale from a single core to a new class of multicore devices.
The Ensemble can combine up to two Cortex-M55 cores, up to
two Cortex-A32 cores capable of running high-level operating
systems, and up to two Ethos-U55 microNPUs for AI and machine
On-Chip Artificial Intelligence learning acceleration. These power-efficient microcontrollers can
AI is the major trend in technology at the moment but for many handle heavy AI and ML workloads for battery-operated IoT devices
things embedded, power consumption is a key issue. As a result, up to 250+ GOPs. By optimizing the microcontroller architecture
GPUs are typically integrated into CPUs, microcontrollers, and to tightly integrate the processing cores, low-power NPUs, and
SoCs that are aimed at applications that can support high power on-chip memory, the microcontroller family delivers at least two
requirements. However, for many embedded applications, a GPU orders of magnitude higher edge AI performance than traditional
consumes too much power and is often overkill. microcontrollers with the lowest power consumption levels possi-
ble for vision, voice, and vibration analysis.
A major trend that has come to the fore is the need for AI at the
edge. Here power consumption is critical as these devices typically At electronica 2024, Alif Semiconductor also showed its latest
operate on small batteries or implement energy harvesting technol- Balletto B1 Bluetooth microcontroller family along with a corre-
ogy. Often, these applications also rely on smaller AI models that sponding development kit. The Balleto B1 integrates a 160 MHz
are more tailored to specific requirements. Arm Cortex-M55 CPU core with Helium vector processing exten-

40 March & April 2025 www.elektormagazine.com

sion for fast and power efficient signal processing, an Arm Ethos- technology stores AI parameters directly in the processor, which
U55 NPU, a Bluetooth Low Energy and 802.15.4 radio, and a wide eliminates memory bottlenecks and claims to enable AI applica-
variety of digital and analog capabilities in tiny BGA or CSP package tions that are impossible or unviable today. Since the traditional
options. digital computing architecture needs to deal with transferring
billions of AI parameters between memory and processing, it
In another example, BrainChip [2] has leveraged neuromor- requires a lot of energy. Mythic removes this problem, claiming
phic computing to solve AI problems. Cconsuming signifi- to be 18,000 times faster, 1,500 times more energy efficient, and
cantly less power consumption than a GPU, Akida technology is 1,000 times more parallel.
a brain-inspired cognitive event-based compute platform ideal
for early detection, low-latency applications without massive In 2025, expect to see microcontroller and low-power AI architec-
compute resources for robotics, drones, automotive, and tradi- tures continue to evolve. On-chip Generative AI is set to follow
tional sense-detect-classify-track systems. For example, built on the on-edge devices as chip manufacturers look to make AI more
Akida event-based computing platform configuration engine, the efficient. It is also likely, that these new technologies move up
Akida Pico low-power acceleration coprocessor accelerates limited the food chain and replace traditional methods as the power
use case-specific neural network models and can execute using consumption of AI is currently a global problem. Other technol-
battery-powered operation of less than a single milliwatt. Akida Pico ogies such as neuromorphic computing are expected to bring
enables the creation of very compact, ultra-low power, portable new levels of tailored performance to low-power edge appli-
and intelligent devices for wearable and sensor-integrated AI into cations as well as event-based detection for very low-standby
consumer, healthcare, IoT, defense, and wake-up applications. power requirements.

A deep-tech Canadian startup, Blumind [3] has developed a Programming and Generative AI
disruptive all-analog neural signal processor technology — A fast-growing technology, Generative AI has found use in
Blumind AMPL. This AI compute fabric is ideal for micropower generating code, debugging, and rapid prototyping in embed-
AI applications and delivers deterministic and precise inferenc- ded electronics. For example, developers can use ChatGPT and
ing performance at up to ×1,000 lower power than legacy digital GitHub Copilot [5] to provide instant code suggestions as well
approaches. AMPL claims to be the first all-analog AI on advanced as help in debugging and optimization to resolve errors quickly.
standard CMOS architected to fundamentally mitigate process, Generative AI has also become a useful tool in rapid prototyp-
voltage, temperature and drift variations. Applications include ing as it can quickly generate bits of code to test functionality or
always-on keyword detection, image classification, and always-on explore different configurations.
visual image wake to enable rapid identification for access control.
While generative AI tools like ChatGPT and GitHub Copilot offer
Another startup, Mythic [4] has pioneered analog compute-in-mem- increased efficiency and faster prototyping, they also present
ory that is purpose-built for AI inference. This analog computing challenges regarding code accuracy, confidentiality, and intel-
lectual property. When using Generative AI, human oversight is
important to ensure code meets its functional and performance
metrics, as well as compiler and hardware requirements. Confi-
dentiality and adherence to IP laws also need to be considered.

In 2025 and beyond expect to see more tools addressing the use of
Generative AI to automate coding and programming.

Zephyr Open Source RTOS

Taking on FreeRTOS [6] and ThreadX [7], Zephyr [8] has become
an important RTOS with significant growth in use in embedded
electronics in 2024. This highly modular RTOS can scale to meet
the requirements of various applications from tiny space-con-
strained IoT devices to complex embedded systems. It supports a
wide range of hardware architectures and communication protocols
and is designed to easily port to new platforms for reuse. Zephyr
also offers a very secure kernel with support for multiple schedul-
Figure 1: The new E4, E6, and E8 Ensemble MCUs and fusion processors will ing algorithms, memory protection, and fault handling. Security
integrate the latest neural processing unit (NPU) from Arm, the Ethos-U85,
with a unique high bandwidth memory and intelligent power management
features include cryptography, secure boot, and firmware updates
architecture to support NPU operators required by transformer networks to and a comprehensive set of tools are available for managing depen-
execute generative AI workloads efficiently. (Source: Alif Semiconductor) dencies, toolchains, and builds.

March & April 2025 41

Figure 2: Humanoid robots are designed to work seamlessly together with humans in industries such as manufacturing, logistics, and healthcare.
(Source: NEURA Robotics)

While FreeRTOS is backed by Amazon, ThreadX is part of the Cybersecurity

open-source Eclipse Foundation [9], and Zephyr is managed by With the increasing connectivity of embedded systems, 2024 saw
the Linux Foundation—an important consideration for devel- advancements in cybersecurity that included hardware-based,
opers who prefer an RTOS not backed by a corporation. Zephyr full lifecycle, and zero-trust security, secure boot processes, and
offers broad hardware support, extensive connectivity options, AI-driven threat detection. However, it is legislation in the form
and robust networking, making it particularly useful for devel- of the Cyber Resilience Act (CRA) [23] that became a key issue in
opers transitioning from embedded Linux. 2024 that will affect markets in the years ahead.

Highlighting its success, the Zephyr Project added several members The CRA sets a minimum level of cybersecurity for all connected
in 2024, including CARIAD [10], Ac6[11], Alif Semiconductor, products available within the EU market. It aims to ensure that
Arm [12], Honda [13], Inovex [14], MicroEJ [15], Qt Group [16], there is an adequate level of cybersecurity in hardware and software
and STMicroelectronics [17]. According to the Zephyr Project, products with a digital component as well as timely lifetime security
Nordic Semiconductor [18], Intel [19], and NXP [20] contributed updates, whether they are embedded systems or standalone
the most to the ecosystem in 2024. software. It came into force on the 10th December 2024, starting a
36-month implementation period to full compliance.
Several technical milestones were achieved in 2024, including over
100,000 commits and added support for 150 new boards (bring- This means that organizations need to design hardware and
ing the total to over 750), including development platforms such software for security to minimize vulnerabilities from the start
as Raspberry Pi Pico 2 [21] and the WCH CH32V003EVT [22] — a and provide timely risk assessments and updates. In addition, clear
board powered by a 10 cent RISC-V MCU. information on security updates and known vulnerabilities must
be provided to users throughout the product’s lifetime. Expect
Going forward, Zephyr is expected to keep gaining traction in organizations to use automation and risk management to meet
embedded systems, IoT, and safety-critical domains as more devel- compliance from 2025 onwards. On the 11th of September 2026,
opers look to use open-source to cut costs, benefit from increased reporting obligations for manufacturers are expected to become
security, portability, wide support, and flexibility as well as to future- applicable.
proof development.

42 March & April 2025 www.elektormagazine.com

Robotics AI Is Dominating
According to the International Federation of Robotics (IFR) [24] the Of all the trends in embedded electronics, AI is dominating the
top five trends in robotics in 2024 are AI and machine learning, industry and is evolving quickly. In embedded applications,
Cobots moving to new applications, digital twins, mobile manip- low-power AI at the edge looks set to completely transform the
ulators, and humanoids. For example, generative AI-driven inter- automotive, industrial, and consumer industries. Moving forward,
faces are being developed to enable users to program robots by edge AI will benefit from more powerful AI chips that bring LLMs
using natural language instead of code. Machine learning is also onto microcontrollers and very low-power processors. Analog and
enabling predictive maintenance in robotics to minimize downtime neuromorphic computing will enable applications such as keyword
and cut costs. and image detection at extremely low power levels.

Humanoid robots have caught the attention of the world with the Future vehicles using AI, for example, will be customized to the
Tesla Optimus humanoid slated for 2026. However, mass market driver’s needs, boost the effectiveness of driver aids, and enable
adoption of humanoid robots remains a difficult challenge. predictive maintenance to address problems before they occur.
In the smart home, expect software and AI to dominate, enabling
Founded in 2019, German startup NEURA Robotics [25] has become interoperability (hardware-agnostic) and LLMs to provide natural
a global leader in cognitive and humanoid robotics, creating robots language interaction for the whole home. In industry, machine
designed to work seamlessly with humans in industries such as learning, digital twins, robotics, and AI will continue to automate
manufacturing, logistics, and healthcare (Figure 2). Using unique everything from setup to operation of smart factories. Predictive
sensor technology and AI integration, NEURA Robotics has devel- maintenance will also play a large role in cutting costs. However,
oped the first cognitive cobot on the market and is now leading a lot of these applications will require low-power AI chips.
the way in the development of market-ready humanoid robots. 250072-01

Linearly programmed and single-purpose robots are being super-

seded by versatile machines that are capable of reasoning. Moreover,
large language models (LLMs), vision language models (VLMs), and
robotics foundation models will provide robots with ever greater
autonomy and awareness in the physical world. Foundation models
are neural networks “pre-trained” on massive amounts of data WEB LINKS
without specific use cases in mind. These generalized models then [1] Alif Semiconductor: https://alifsemi.com
train to get better at specific tasks through “transfer learning.” [2] BrainChip: https://brainchip.com
Robots, in effect, learn on the job. [3] Blumind: https://blumind.ai
[4] Mythic: https://mythic.ai
Automotive — SDVs [5] GitHub Copilot: https://github.com/features/copilot
Apart from the EV trend of the last few years, software-defined [6] FreeRTOS: https://freertos.org
vehicles (SDVs) have seen a jump in activity in 2024, driven by [7] ThreadX: https://threadx.io
infotainment, cybersecurity, and LTE/5G connectivity. V2X and [8] Zephyr: https://zephyrproject.org
the ability of electric vehicles to support bidirectional power trans- [9] Eclipse Foundation: https://eclipse.org
fers to support the grid are key considerations. Typically, an SDV is [10] CARIAD: https://cariad.technology
built on what is known as a vehicle skateboard, which is similar to [11] Ac6: https://ac6-training.com
a common hardware platform — chassis, wheels, battery, and so [12] Arm: https://arm.com
on. On top of this, manufacturers add an operating system; SoCs [13] Honda: https://global.honda/en
for computing; a cloud platform such as Google Cloud, Azure, or [14] Inovex: https://inovex.de/en
AWS; user interfaces, and end-user applications. SDVs can then [15] MicroEJ: https://microej.com
be updated via software over the lifetime of the vehicle to add new [16] Qt Group: https://qt.io
applications or adjust to new regulations and technologies. As a [17] STMicroelectronics: https://st.com
result, car companies are investing increasingly into embedded [18] Nordic Semiconductor: https://nordicsemi.com
software. [19] Intel: https://intel.com
[20] NXP: https://nxp.com
For example, at CES 2025, Honda introduced its original vehicle [21] Raspberry Pi: https://raspberrypi.org
operating system, the Asimo OS, which will be installed in future [22] WCH CH32V003EVT: https://wch-ic.com
Honda 0 Series models. From 2025 onwards, expect to see more [23] Cyber Resilience Act:
vehicle manufacturers redefine automotive design and lean towards https://eur-lex.europa.eu/eli/reg/2024/2847/oj/eng
developing their own software to differentiate their brands through [24] International Federation of Robotics: https://ifr.org
infotainment, connectivity, end-user applications, voice recogni- [25] NEURA Robotics: https://neura-robotics.com
tion, ADAS, and in-cabin monitoring.

March & April 2025 43

 INTERVIEW

Charge-Based
In-Memory Compute
at EnCharge AI
Naveen Verma, CEO of EnCharge AI

By Nick Flaherty (eeNews Europe) is rather than using the current through a semicon-
ductor device we are using charge,” he said.
Naveen Verma, CEO of EnCharge AI, talks
to eeNews Europe about the company’s analog “We don’t use semiconductor devices, we use capac-
itors formed from the metal wires, they only depend
in-memory compute technology for edge AI. on the geometry and that’s something we can control
very well.”

US startup EnCharge AI [1][2] is reaching the next “This solves the analog accuracy and scalability
stage of its development of in-memory compute problems from the geometry control as we scale to
(IMC) for low-power AI. The company has raised $45 m more advanced nodes so the energy efficiency and
for its capacitor-based analog in-memory comput- density improve. The precision of patterning the wires
ing technology and is actively raising funds for the does scale, and what geometry you need is an inter-
commercialisation of AI chips for laptops. esting question. What we need is more of an order of
magnitude less (than approaches), and that allows
“There has been a lot of interest in analog computing you to use the upper metal layers.”
as it can be orders of magnitude energy efficient but
it is sensitive to noise so the big problem that we have EnCharge AI has built a macroblock that does the multi-
solved is managing analog IMC in a very robust and ply-accumulate (MAC) functions very efficiently for AI,
scalable way,” said Naveen Verma, CEO of EnCharge AI using SRAM to provide the addressability for the capac-
and professor of electrical and computer engineering itors in the metal layers that can store the weights for
at Princeton University since 2009. the frameworks. This approach has been demonstrated
in chips ranging from 130 nm in 2017 to 16 nm in 2021.
“AI is moving out of the data centre to scale up, moving
into laptops and desktops, edge servers. These are Building a Chip Is Not Enough
often battery-powered or space-constrained, and that’s “The trick is to re-architect the chip to get the advan-
where we have found a lot of traction.” tages,” he said. “The fundamental technology was a
breakthrough in 2017 and the next five years was to
“My research group at Princeton has been looking build an architecture around it with a software stack
at this for many years, with all sorts of optical and and a compiler to map applications to it.”
electrical computing. The big fundamental difference
“Because the fundamental capacitor technology does
not require any additional technology, that allows us
to be in the most advanced nodes and that gives us
$exibility to build programmability into this with all
the AI models.”

“We defined an architectural unit, a tile, that is

complete, highly efficient MAC engines with all the
other compute and control, localised vector units
and L2 memory cache, and you can build an array
Source: EnCharge AI of these tiles.”

44 March & April 2025 www.elektormagazine.com

 Re-architecting chips with the EnCharge analog AI IP is
key to running AI frameworks with billions of parameters.

“Then the problem is to map the software to this archi- of parameters. This uses well-established principles
tecture to use the units efficiently. This gives high of memory virtualisation.
levels of density and power efficiency. Now you can
very $exibly choose the parallelism of the AI graph.” “Virtualised memory takes a capacity-limited
L1 memory and couples that with the L2 cache all the
“So we had the full stack in a baseline from where we way out to DRAM and we have used the same princi-
understood the architecture, the compiler structure, ples to IMC, orchestrating the way memory moves
we spun that out in 2022 for customers that needed across the system so that we can scalably execute
the higher efficiency and performance.” models with billions of parameters,” he said.

“What we found was the first couple of models broke “What you have to have is some IMC hardware and
everything as there were small features in the first work out how it works with the L2 and L3 and off-chip
couple of AI workloads that were missing. Working memory for the right amount of data reuse so that the
with customers, we identified the features for the data movement doesn’t become the limiting factor. That
next spin of the hardware and the software. That’s drives the architectural design, and our systems are
the journey that we were on,” he said. optimised for multiple multi-billion parameter models.”

“We have been working with partners to prove out While the latest laptop devices such as Meteor Lake
the workloads that need to run. The systems need use chiplets, this is not a focus for the in-memory
to be optimised from top to bottom. We are building compute architecture, says Verma.
the chips and the software for a couple of reasons.
Really getting the full performance advantage requires “Chiplets are a very interesting technology but there
a top-to-bottom optimisation and being able to control are constraints, whether using UCIe as an interface or
that allows us to get the most out of the technology.” not. I do see opportunities around chiplets.”
240728-01
The initial form factor for this is simple discrete boards
on PCIe cards, and he sees M.2 as well aligned for Editor’s Note: Nick Flaherty first reported on this in
laptops. The existing technology can provide perfor- eeNews Europe, a publication in the Elektor network.
mance of over 150 8-bit TOPS/W, but the chip under www.eenewseurope.com/en/domain/eenews-embedded/
development for 2025 has an efficiency of 375 TOPS/W
and can also handle AI frameworks with billions of
parameters.

“Our target is to be 3 to 4× the capability of laptop

processors have 40 TOPS with an NPU in Snapdragon
or Intel’s Lunar Lake,” he said. “We have a significant
advantage at 16 nm over 5 nm digital so our prefer-
ence is to stay in those nodes where we have proven
our IP. The preference is to stay in very mainstream
technologies and the technologies that will allow us
to scale and these work very well for us.”

Re-architecting chips with the EnCharge analog

AI IP is key to running AI frameworks with billions
Source: EnCharge AI

WEB LINKS
[1] EnCharge AI: https://www.enchargeai.com
[2] R. Pell, “In-memory computing startup launches to enable edge AI at scale,” eeNews, 2022:
https://www.eenewseurope.com/en/in-memory-computing-startup-launches-to-enable-edge-ai-at-scale/

March & April 2025 45

 NEWS

Source: Adobe Stock

AI Inferencing at
10 Times Lower Power
and 20-Fold Lower Cost
By Jean-Pierre Joosting (eeNews Europe)

Sagence AI has emerged from stealth to unveil a groundbreaking advanced analog in-
memory compute architecture that directly addresses the untenable power/performance/
price and environmental sustainability conundrum facing AI inferencing.

Based on industry-first architectural innova- price, and 20 times smaller rack space. Using “A fundamental advancement in AI inference
tions using analog technology, Sagence AI [1] a modular chiplet architecture for maximum hardware is vital to the future of AI. Use of
makes possible multiple orders of magnitude integration, the technology enables a highly large language models (LLMs) and Genera-
improvement in energy efficiency and cost efficient inference machine that scales from tive AI drives demand for rapid and massive
reductions for AI inferencing, while sustaining data center generative AI to edge computer change at the nucleus of computing, requir-
performance equivalent to high performance vision applications across multiple indus- ing an unprecedented combination of highest
GPU/CPU based systems. tries. The technology balances high perfor- performance at lowest power and economics
mance and low power at an affordable cost that match costs to the value created,” said
Compared to the leading volume GPU — addressing the growing ROI problem for Vishal Sarin, CEO & Founder, Sagence AI.
processing the Llama2-70B large language generative AI applications at scale, as AI “The legacy computing devices today that
model with performance normalized to computing in the data center shifts from are capable of extreme high-performance AI
666 k tokens/s, Sagence technology performs training models to the deployment of models inferencing cost too much to be economically
with 10 times lower power, 20 times lower to inference tasks. viable and consume too much energy to be

46 March & April 2025 www.elektormagazine.com

 In-memory computing
aligns closely with the
environmentally sustainable. Our mission is to essential elements of machines requires extremely complicated
break those performance and economic limita- hardware reuse and hardware scheduling.
tions in an environmentally responsible way.” efficiency in AI inference The natural hardware solution is not a gener-
applications. al-purpose computing machine, but rather an
“ The demands of the new generation of architecture that more closely mirrors how
AI models have resulted in accelerators biological neural networks operate.
with massive on-package memory and
consequently extremely high-power consump- Sagence innovated a new analog path forward The statically scheduled deep subthreshold
tion. Between 2018 and today, the most power- leveraging the inherent benefits of analog in in-memory compute architecture employed
ful GPUs have gone from 300 W to 1200 W, energy efficiency and costs to make possible by Sagence chips is much simpler and elimi-
while top-tier server CPUs have caught up mass adoption of AI that is both economically nates the variabilities and complexities of the
to the power consumption levels of NVIDIA’s viable and environmentally sustainable. dynamic scheduling required of CPUs and
A100 GPU from 2020,” said Alexander Harrow- GPUs. Dynamic scheduling places extreme
ell, Principal Analyst, Advanced Computing, In-memory computing aligns closely with the demands on the SDK to generate the runtime
Omdia. “This has knock-on effects for data essential elements of efficiency in AI inference code and contributes to cost and power ineffi-
center cooling, electrical distribution, AI appli- applications. Merging storage and computing ciencies. The Sagence AI design flow imports
cations’ unit economics, and much else. One inside memory cells eliminates single-pur- a trained neural network using standards-
way out of the bind is to rediscover analog pose memory storage and complex sched- based interfaces like PyTorch, ONNX and
computing, which offers much lower power uled multiply-accumulate circuits that run TensorFlow, and automatically converts it into
consumption, very low latency, and permits the vector-matrix multiplication integral to AI Sagence format. The Sagence system receives
working with mature process nodes.” computing. The resulting chips and systems the neural network long after GPU software
are much simpler, lower cost, lower power and created it, negating the further need for the
Sagence AI leads the industry on the frontier with vastly more compute capability. GPU software.
of in-memory computing innovation. It is the 240730-01
first to do deep subthreshold computing inside Sagence views the AI inferencing challenge
multi-level memory cells, an unprecedented not as a general-purpose computing problem, Editor’s Note: Jean-Pierre Joosting first
combination that opens doors to the orders but as a mathematically intensive data reported on this in eeNews Europe, a publi-
of magnitude improvements necessary to processing problem. Managing the massive cation in the Elektor network.
deliver inference at scale. As digital technology amount of arithmetic processing needed to www.eenewseurope.com/en/domain/
reaches limits in ability to scale power and cost, “run” a neural network on CPU/GPU digital eenews-embedded/

WEB LINK
[1] Sagence AI: https://sagence-ai.com

With or Without magnetics knowledge.

Anyone can design

a power transformer!
c/o $29 special
www.diogenes-resources.com

March & April 2025 47

 NEWS

Click Board Helps

Develop and Train
ML Models for
Vibration Analysis
By Jean-Pierre Joosting (eeNews Europe)

MIKROE has launched the compact add-

on ML Vibro Sens Click board, which is
designed for precise motion and vibration
sensing and analysis.

Based on the FXLS8974CF, a 3-axis low-g accelerometer from NXP, this

Click board offers high performance and versatility ideal for develop-
ing and training machine learning (ML) models for vibration analysis.

Comments Nebojsa Matic, CEO of MIKROE [1]: “A new member of

our company’s 1750-strong mikroBUS-enabled Click board family of
compact add-on boards, ML Vibro Sens Click can be used to collect customizable vibration signals, ranging from low-intensity to specific
data for training ML models to recognize different types of vibrations, frequency-based vibrations.
and to monitor the health of machines and industrial equipment based
on vibration patterns. It can also be used to track motion and activity The FXLS8974CF accelerometer from NXP captures detailed data
in wearable devices, and to detect vibrations caused by earthquakes from the balanced and unbalanced motors, enabling the differentiation
or other seismic events.” between healthy baseline states and anomalous conditions. It commu-
nicates with the host MCU via a standard 2-wire I2C interface.
The FXLS8974CF offers the versatility of ultra-low-power operation 240733-01
alongside high-performance modes, ensuring efficient use in diverse
scenarios. Its integrated digital features simplify data collection and Editor’s Note: Jean-Pierre Joosting first reported on this in eeNews
reduce system power consumption, while its robust performance over Europe, a publication in the Elektor network.
extended temperature ranges enhances reliability in demanding appli- www.eenewseurope.com/en/domain/eenews-embedded/
cations, including industrial diagnostics, wearable technology, and
environmental monitoring.

This Click board incorporates two DC motors to simulate vibration

stimuli for machine learning. The balanced motor generates steady WEB LINK
“nominal” vibrations, serving as a baseline signal for training ML models [1] MIKROE: https://mikroe.com
in a “healthy” state. The unbalanced motor is designed to provide

48 March & April 2025 www.elektormagazine.com

 PROJECT

The Elektor
Mini-Wheelie
A Self-Balancing Robot Kit
By The Elektor Team

Powered by an ESP32-S3 microcontroller, the Specifications

robot is fully programmable using the Arduino with
environment and open-source libraries. Its > ESP32-S3 microcontroller
wireless capabilities enable remote control Wi-Fi and Bluetooth
rement
via Wi-Fi, Bluetooth, or ESP-NOW. They also > MPU6050 inertial measu
allow for communication with a user or even unit (IMU)
led 12 V
another robot. An ultrasonic sensor facilitates > Two independently control
eter
obstacle detection, while its color display can electric motors with tachom
show cute facial expressions or — for the more > Ultrasonic transducer
display
practically inclined — cryptic debug messages. > 320×240-pixel TFT color
> microSD card slot
The prototype of the self-balancing Mini-Wheelie The robot comes as a neatly packaged kit that > Battery power monitor
geable
robot during one of its test runs. requires self-assembly. Everything you need, > 3S (11.1 V, 2200 mAh) rechar
rger)
even a screwdriver, is included. Li-Po battery (including cha
ce
In 2009, Elektor published the Elektor- 250112-01
> Arduino-based open-sour
Wheelie, a DIY, two-wheeled, self-balanc- software
8×13 cm
ing, battery-powered vehicle inspired by the > Dimensions (w/l/h): 23×
Segway PT, which was then hailed as the
future of personal transportation. The Elektor-
Wheelie brought this exciting new self-bal-
ancing technology to within makers’ reach.

Now, some 15 years later, we introduce what

we might call the Mini-Wheelie. While it
operates on the same principles as its larger
predecessor, its purpose has changed. Instead Related Product
of transporting you from point A to B (riding
it is strongly discouraged), the Mini-Wheelie > Elektor Mini-Wheelie
Self-Balancing Robot Kit
serves as an experimental, autonomous, The robot comes as a kit of parts that you must www.elektor.com/21087
self-balancing robot platform. assemble yourself. Everything is included —
even a screwdriver.

WEB LINK
[1] This project on Elektor Labs: https://elektormagazine.com/labs/self-balancing-robot-with-maker-fabs

March & April 2025 49

 SOFTWARE

MCU,
I See You
MCUViewer Open-Source Multiplatform Debugging Tool

By Piotr Wasilewski (Poland)

years for many developers, it has certain limitations, as it does
MCUViewer is an open-source graphical not support Unix platforms or the import of C++ objects. There
debugging tool for microcontrollers, are some other similar tools available, such as CubeMonitor from
STMicroelectronics or FreeMASTER from NXP, but they are limited
featuring two core modules that allow to specific vendors and also have varying capabilities and features.
developers to visualize and interact with
microcontroller data in a non-intrusive way. That’s when the spark struck: why not create a custom tool that
could address these gaps, not just for me but for the broader devel-
The Variable Viewer module enables real- oper community? Initially, I was hesitant to start such a large
time monitoring, logging, and manipulation project, especially without the resources of a full software team.
of variables through a debug interface However, as I made progress, I found the process rewarding. It
allowed me to guide the development in a direction that made
(SWDIO, SWCLK, GND). Trace Viewer MCUViewer unique, particularly in the hobbyist community.
graphically represents real-time SWO trace
outputs, offering deeper insights into high- I likely would not have taken on this task without the positive
feedback from others during development. It soon became clear
speed data. The multiplatform tool requires that I was not developing this tool just for my own benefit — many
either an STLink or a J-Link programmer other developers have found a tool like MCUViewer useful and have
for operation and will work for ARM-based expressed their encouragement and appreciation. SEGGER also
provided me with valuable assistance to integrate J-Link support
and other types of microcontrollers that are into MCUViewer, for which I am grateful.
compatible with either type of probe.
How Does It Work?
The Variable Viewer module of MCUViewer can sample microcon-
troller memory at constant time intervals, making it useful for
The MCUViewer project began as a straightforward attempt to create monitoring real-time data. By parsing the provided ELF file, the
a workaround alternative to STMicroelectronics’s STM Studio, but it software identifies variables and their corresponding memory
soon grew into a fully independent, open-source GPLv3 [1] tool for addresses, which are accessed via a debug probe to read the values.
debugging a wide variety of embedded systems. The idea emerged
from my own experiences as an embedded systems engineer. Over As Figure 1 shows, this memory data can be visualized in one of
a year ago, while working intensively on motor control algorithms, three formats: a curve view for time-based graphs, a bar view for
I was using STM Studio to visualize system behaviors and debug visual insights, or a table view for reading and modifying values.
controllers. Although STM Studio has served its purpose over the The table view also allows developers to modify variable values

50 March & April 2025 www.elektormagazine.com

 Figure 1: In Variable
Viewer mode, users can
visualize memory data
as time-based graphs,
bar charts, or tables, and
edit variables directly
for dynamic testing and
development.

directly, providing a way to adjust program flow and trigger specific Currently, ST-Link and J-Link probes are supported and they can
actions during development or testing. work in different modes: ST-Link probes support only normal mode
which samples variables’ values one by one, whereas J-Link can work
In addition, MCUViewer offers basic statistical analysis of the in both normal and HSS (High-Speed Sampling) mode in which it’s
gathered signals and enables exporting the data to CSV format for capable of sampling at rates of tens of kilohertz. Depending on the
further analysis. Variable Viewer is especially useful for visualizing debugging scenario, you can easily switch between the two modes.
many signals at once; for example when tuning a PID controller
you could display all three P, I and D components together with After picking the debug probe we can set up the tracked variables
the setpoint and output value. and create some plots. The main rule is that all tracked variables
have to be global; they have to persist throughout the program
However, Variable Viewer is not sufficient in all cases — especially lifetime in order to have a constant address and be detected by the
for very high-frequency signals such as inductor current responses. parser. At the moment all basic types up to 32-bits are supported.
Depending on the number of logged variables and the type of probe
used, Variable Viewer can reach up to a few tens of kilohertz. While After the import, plots can be added by selecting their type, then
this frequency may be adequate in many situations, there are times drag and drop the variables onto the canvas. Clicking the large
when it falls short. button in the top left window’s corner will start the acquisition.
When stopped, the user can zoom in on particular parts of the
To address this, the Trace Viewer module was developed. Unlike collected data and analyze it. Additional tools are cursors which
Variable Viewer, which samples memory, Trace Viewer processes can be used to quickly measure time difference and check signal
SWO trace data from the embedded firmware. Variables are written values, and simple statistics windows that measure and display
to the ITM peripheral with hardware-generated timestamp packets, some basic properties of the signal.
ensuring synchronization with code execution. Thanks to the
optimized SWO protocol, Trace Viewer can achieve sub-micro- For example, Variable Viewer can be used with a cascaded PID
second timestamp resolutions, making it suitable for high-fre- of a servo drive. In Figure 2, I have created two plots, one for
quency signal analysis, and much more. the outer position control loop and the inner one for the veloc-
ity control loop.
How To Use Variable Viewer
Initially designed as the core feature of MCUViewer, Variable At first glance, it seems the step response of the position controller
Viewer collects the values of variables using a selected debug probe. looks good — a nice critically damped response. However, when

March & April 2025 51

 SWO pin bandwidth — in other words, to help you identify where
the bottleneck is and modify how the data is logged or transmitted
to fit within the available bandwidth.

This is how you can measure a memcopy function execution time

with different sizes of the copied buffer:

1. On entering a function we place an entrance marker —

ITM->PORT[X].u8 = 0xaa — when plotted on the MCUViewer
plot it will be shown as a transition from low to high state.

2. On the function’s exit we place the exit marker — ITM->PORT[X].

u8 = 0xbb — when plotted it will be shown as a transition from
high to low state.
Figure 2: Variable Viewer is used here in a cascaded servo drive PID with
separate plots created for the position control loop and for the velocity As Figure 2 shows, both markers are single register writes to the
control loop. ITM peripheral. In TraceViewer each channel has its own plot, and
the X stands for the number of channels used. After the write is
done the frame is automatically composed by the hardware and
looking at the velocity PID response you can easily spot some sent using the SWO pin.
oscillations. These could be not noticed when simply tuning the
controllers without this type of visual feedback. Below you can see a simple code example for copying a buffer using
the memcopy function:
Besides only reading out the response, it is possible to command
values by using a table view with setpoint values. This can be used volatile uint8_t dest[1024];
to quickly test different setpoints or adjust the PID gains on the fly. volatile uint8_t src[1024];
volatile uint16_t size = 1;
How To Use Trace Viewer for (size_t i = 0; i < 10; i++)
Trace Viewer works a bit differently compared to the Variable {
Viewer, and this difference brings a range of useful features, partic- ITM->PORT[1].u16 = size;
ularly for dealing with high-frequency signals. One notable feature ITM->PORT[0].u8 = 0xaa;
enabled by its synchronous nature is execution time profiling. memcpy(dest, src, size);
Typically, when developers want to measure how long a specific ITM->PORT[0].u8 = 0xbb;
function takes to execute, they rely on a logic analyzer or an oscil- size += 64;
loscope, using a GPIO pin that toggles on function entry and exit. for (size_t a = 0; a < 300; a++)
While this approach is largely non-intrusive, it requires extra __asm__ volatile("nop");
setup, such as connecting additional pins to external measure- }
ment devices. Moreover, if there is a need to measure relative
timings between multiple functions or events, more GPIO pins We’re measuring the execution time on channel 0 and plotting
are needed, which can quickly become impractical, if not impos- the size on channel 1.
sible — especially on low-pin-count microcontrollers.
In Figure 3 you can see the result in the Trace Viewer module
Trace Viewer addresses these challenges by using a single SWO pin window.
connected to the debug probe, which is connected to the target
during the development anyway. Thanks to a highly optimized serial The execution times can be easily measured with cursors — in this
protocol, it can manage up to 32 channels. This means that depend- case, copying 577 bytes took approximately 27,31 μs.
ing on the frequency of each channel and total SWO bandwidth
we can use 32 channels on a single GPIO pin. The main limitation Analog Signal Example
is that SWO needs additional peripherals that are present only in In order to plot an analog float-type signal, a slightly different
Cortex M3/M4/M7/M33 cores. approach is taken:

The SWO pin can be used to track the execution times of multiple float a = sin(10.0f * i);
functions and the real-time values of several variables. However, //some high speed signal to trace
if these monitoring operations produce more data than the SWO ITM->PORT[0].u32 = *(uint32_t*)&a;
pin can handle, then the Trace Viewer module can debug the probe // type-pun to desired size

52 March & April 2025 www.elektormagazine.com

 Figure 3: Trace Viewer
can identify where
bottlenecks are in the
SWO pin bandwidth.
This is shown here by
measuring a memcopy
function execution time
with different sizes of the
copied buffer.

// sizeof(float) = sizeof(uint32_t) gives a lot of additional info about the system as CPU-intensive
tasks can be easily spotted and fixed if needed.
Basically, we need to type-pun the value to a suitable type, and
select the proper type in MCUViewer plot settings. First, set the plot Results and Future Improvements
domain to analog, and then select the type from the drop-down list. MCUViewer has evolved into a robust, open-source solution
designed to make embedded systems debugging more efficient
In Figure 4, a response of an inductor current for a given voltage and accessible. Total downloads over all released versions have
command is plotted. reached over 2500, and it now offers features that cater to a variety
of sensor- and actuator-related applications, such as debugging
When registered, we can use cursors to measure the time constant power electronics, robotics and embedded control systems in
and estimate the inductance. Registering analog signals can be general. My hope is that MCUViewer can empower developers
very useful in the power electronics field, where controllers usually across a range of fields, providing a reliable and adaptable tool for
operate at tens of kilohertz, which makes them more challenging solving their most pressing challenges.
to analyze and debug.
MCUViewer is under constant development. I am currently working
Interrupt Profiling Example on some new features that will make the debugging process even
The last demonstration example uses Trace Viewer to analyze the better. One of the most important of these is plot groups, which
execution order and priorities of interrupts. By placing markers will allow users to switch quickly between plot collections.
on the interrupt enter and exit we can easily visualize the relative
interrupt timings as well as execution times and preemption Other important features to come are:
events.
> XY plot
Figure 5 shows a TIM7 interrupt with the highest priority, TIM17 > fixed point interpretation of variables
with medium priority, and TIM6 with lowest priority. The preemp- > the ability to read arbitrary memory addresses
tion can be easily spotted in places where the frequency of TIM6 > the ability to perform basic preprocessing on collected
and TIM17 is affected by TIM7 interrupt execution. This use case variables

March & April 2025 53

Figure 4: Trace Viewer
can also visualize analog
signals; here measuring
the response of an
inductor current for a
given voltage command.

About the Author

Piotrek Wasilewski is an embedded systems enthusiast with a deep
passion for software development in power electronics and brush-
less motor controllers. His experience includes working on projects
involving power electronics, quadruped and sumo robots, and the
development of a milling machine. Through these varied ventures,
he has developed a strong background in designing and imple-
menting advanced embedded solutions.

Questions or Comments?
Do you have questions or comments about this article? Email
the author at piwasilewski@interia.pl or contact Elektor at
editor@elektor.com.

Figure 5: Trace Viewer visualizes interrupt execution order, timings,

durations, and preemption events by using enter and exit markers for
detailed analysis. Related Product
> Dogan Ibrahim, Nucleo Boards Programming with the
If you would like to try out MCUViewer in your future projects, the STM32CubeIDE (Elektor, 2020)
project is hosted on GitHub [2], and contributions from the commu- www.elektor.com/19530
nity are always welcome. If you have ideas for improvements, need
to report a bug, or are interested in contributing to a specific feature,
feel free to start a new issue or contact me directly. Even small
contributions can make a big difference in improving the tool and WEB LINKS
expanding its capabilities. Engaging with the community has been [1] GPLv3 Public License:
one of the most rewarding parts of developing MCUViewer, and https://www.gnu.org/licenses/gpl-3.0.en.html
I look forward to collaborating with others who share an interest [2] MCUViewer project on GitHub:
in embedded systems development. https://github.com/klonyyy/MCUViewer?tab=readme-ov-file
230602-01

54 March & April 2025 www.elektormagazine.com

 Getting Started
Installation Trace Viewer
First, you’ll need to download MCUViewer installer on GitHub 1. Enable SWO Pin by configuring CubeMX: System
[2]. Core → SYS Mode and in Configuration choose the
Trace Asynchronous Sw option.
Linux
Ensure you have GDB version 12.1 or higher installed. 2. Add enter and exit markers:
Download the *.deb package and install it For example, you can profile digital data as follows:
with sudo apt install ./MCUViewer-x.y.z-Linux.deb
All dependencies will be installed automatically. ITM->PORT[x].u8 = 0xaa;
//enter tag 0xaa - plot state high
For ST-LINK Users: foo();
If your ST-LINK is not detected, copy the files from the / ITM->PORT[x].u8 = 0xbb;
launch/udevrules/ folder to /etc/udev/rules.d/. //exit tag 0xbb - plot state low

Windows For profiling analog signals:

Download and run the MCUViewer installer from the Releases
section found in the right-hand menu of the repository’s main float a = sin(10.0f * i);
page. // some high frequency signal to trace
ITM->PORT[x].u32 = *(uint32_t*)&a;
For ST-LINK users: // type-pun to desired size: sizeof(float) =
Ensure that ST-LINK is in STM32 Debug + Mass Storage + VCP // sizeof(uint32_t)
mode, as STM32 Debug + VCP may cause libusb errors.
Or
To improve performance, assign the external GPU to
MCUViewer. uint16_t a = getAdcSample();
// some high frequency signal to trace
Quick Start ITM->PORT[x].u16 = a;
Variable Viewer
1. Setup variables: 3. Run the program:
> Open Options → Acquisition Settings in the top menu. Compile and download to STM32 and set the correct
> Select your project’s ELF file (compiled in debug mode) and System Core Clock value in Settings in kHz — this is very
click Done. important as it affects the timebase.
> Click Import Variables form *.elf to select variables, or
manually add variables if needed. 4. Set prescaler:
> Report issues with undetected variables by attaching the Adjust to stay within the max trace speed of your
ELF file. programmer (e.g., ST-Link V2: 2 MHz, V3: 24 MHz).
> Click Update variable addresses and ensure types/ Example: for 160 MHz clock, ST-Link V2 prescaler should
addresses are valid. be ≥ 80.

2. Visualize variables: 5. Start recording:

> Drag and drop variables to the plot area. Configure analog channel types and press the STOPPED
> Connect the debug probe (ST-LINK/J-Link), download the button to begin.
executable, and press the STOPPED button.

3. Troubleshooting:
> Try the example/MCUViewer_test CubeIDE project with the
corresponding MCUViewer_test.cfg project file. Remember
to build the project and update the ELF file path in
Options → Acquisition settings.

March & April 2025 55

 PROJECT

USB 2.0 Isolator Electrically Isolated Connections for USB Devices

By Alfred Rosenkränzer (Germany)

In most cases, connecting

peripherals to a PC is not
a problem. The fact that a
USB stick, for example, has
the same ground potential
as a laptop is hardly a
problem. But when it comes
to measuring devices
connected via USB, the
situation is different. Here,
electrical isolation protects
the PC from potentially
harmful voltages. Isolation
also helps to avoid ground
Figure 1: The evaluation board from TI with the designation ISOUSB211DPEVM, built into
loops. Specific chips are a metal casing.
available for this purpose.
The circuit presented here Isolator Chips these ICs are available for less than €10. Since
uses such a chip to provide A USB isolator can be used to prevent a I found these ICs interesting, I first bought
electrical isolation for a USB ground connection and only transmit the the evaluation board for the ADUM4166 and
connection. digital signals. For the slow USB 1.1 standard, successfully tested this chip with a memory
there are, for example, ICs from Analog stick and a USB hard disk. Unfortunately,
Devices and boards equipped with them that controlling an older Audio Precision 2422
can be purchased for a low price on eBay. audio analyzer with an external USB inter-
Unlike in the past with GPIB, these days the However, reasonable data transfer rates today face did not work at all. With the QA403
individual devices in automatic test setups require at least a USB 2.0 connection. Devices analyzer from QuantAsylum, the control only
are usually controlled via USB. Since ground for this speed are also available on the market. worked sporadically. Analog Devices’ support
loops have always been a problem, GPIB had Their main disadvantage, however, is that they confirmed the problem and also pointed out
special devices for electrically isolating the are quite expensive. Instead of just €10 to €20 that there seem to be problems with other
control unit (usually a PC) from the measur- for USB 1.1, you often have to pay three-digit devices as well. Tests with an ADUM4165
ing instruments and generators connected sums for USB 2.0. In this case, building your evaluation board yielded the same result.
to it. Unfortunately, the transition to USB has own device can save you a lot of money. Unfortunately, ADI was unable to provide any
not changed this challenge. This is because information on the cause of this problematic
there is also a ground connection between Suitable chips for USB 2.0 have been devel- behavior.
the devices, and it is not uncommon to oped by Analog Devices (ADUM4165 and
have interference from the PC affecting the ADUM4166) and TI (ISOUSB211). These can Fortunately, an ISOUSB211 evaluation board
peripherals. be used to implement low-cost isolators, as from TI (Figure 1) was already available after

56 March & April 2025 www.elektormagazine.com

 board for this IC. It should only contain the
most essential components; in most cases,
a DC/DC converter can be dispensed with.
Figure 3 shows the resulting circuit and
Figure 4 the layout. The layout files in Eagle
format can be downloaded for free from the
Elektor website for this article [2].

Figure 2: Block diagram of the ISOUSB211 isolator IC. IC2 in the center separates the left side, where
the host or PC is connected, from the right
side, where the peripheral is connected. Inter-
these sobering first attempts. And hooray: It The board offers a wide range of settings and nally, the integrated circuit has not only 3.3 V
works with all the devices I was able to try has a fairly sophisticated power supply. The TI regulators on both sides that supply the logic,
out. In addition to the USB connection, it has website [1] provides a data sheet and techni- but also integrated 1.8 V regulators to supply
a DC/DC converter with electrical isolation cal specifications. Figure 2 shows the block other logic parts. However, since the use of
on board, which generates the 5 V sometimes diagram of the ISOUSB211. the integrated 1.8 V regulators significantly
required for the device side from the 5 V on the heats up IC2, the use of external 1.8 V regula-
input side. If the power provided is insufficient The Circuit tors (IC1 and IC3) is recommended instead. In
or the switching converter causes interference, After the first encouraging tests with the addition, a 5 V regulator is provided around
an external supply can also be used. ISOUSB211, I decided to design my own circuit IC4 on the right, which can also be used to

LT1117CST1.8 LT1117CST1.8

IC1 IC3
C1 C2 C4 C5 C6 C7 C8 C9 C10 C12 C13 C11 C15 C16 D1

22µ 100n 100n 2µ2 2µ2 100n 100n 100n 100n 2µ2 2µ2 100n 100n 22µ
SK56
16V 16V 16V 16V 16V 16V

OUT
IN

JP2 JP3 JP4

1 3 3 1 3 1
IC2
2 ISOUSB211DPR 2 2
IN OUT OUT
R1 R14 R15
1 28
0Ω1 VBUS1 VBUS2 0Ω1 0Ω1
2 27
V3P3V1 V3P3V2
R2 R3 R4 3 26 R11 R12 R13
GND1_1 GND2_2
4 25
V1P8V1_1 V1P8V2_2
10k

10k

10k

10k

10k

10k

5 24
VCC1 VCC2
1 6 23 1
VBUS 1 JP6 V2OK V1OK 1 JP7 VBUS
2 7 22 2
J1 D– UD– DD– D– J2
3 8 21 3
USB D+ UD+ DD+ D+ USB
4 9 20 4
GND 2 EQ10 EQ20 2 GND
10 19
EQ11 EQ21
C3 11 18 C14
V1P8V1_2 V1P8V2_1
12 17
GND1_2 GND2_1
100n 13 16 100n
CDPENZ1 CDPENZ2
R5 R6 R7 14 15 R9 R10 R8
NC_1 NC_2
10k

10k

10k

10k

10k

10k

IN OUT
LM317MABT
D2
JP2, JP3, JP4: Connectors for Current measurement in VBUS line
IC4
JP6, JP7: Connectors for High Speed Probe R16
SK56
261Ω

X2
C17 C18 C20 2
1
R17 R18
22µ 100n C19 22µ
16V 16V
820Ω

39k

22µ
16V

Figure 3: The circuit of the DIY USB 2.0 isolator. OUT 240616-003

March & April 2025 57

 Component List
Resistors:
Unless otherwise specified:
Thin film SMD 0603, 1%
R1, R14, R15 = 0Ω1, 1206
R2…R13 = 10 kΩ *
R16 = 261 Ω
R17 = 820 Ω
R18 = 39 kΩ

Capacitors:
C1, C16, C17, C19, C20 = 22 %F / 16 V,
electrolytic, tantalum, SMC-B
C2…C4, C7…C11, C14, C15, C18 = 100 nF,
X7R, SMD 0603
C5, C6, C12, C13 = 2.2 %F / 16 V, X7R,
SMD 0805

Semiconductors:
D1, D2 = SK56, Schottky diode, DO214AA
IC1, IC3 = LT1117CST-1.8, SOT223
IC2 = ISOUSB211DPR, DP0028A
Figure 4: The PCB layout for the circuit. IC4 = LM317MABT, TO220

Miscellaneous:
supply the circuit from an external DC power for signals, which of course depend on the JP2…JP4 = 3-pin header, 1/10″ pitch
supply with 8…15 V. IC4 is powerful enough to specific PCB layout and can be quite relevant JP6, JP7 = 2-pin header, 1/10″ pitch
supply USB 2.0 devices connected to J2 with at the data rates occurring with USB 2.0. Since X2 = 2-pin screw terminal, 5 mm pitch,
up to 400 mA. the EQXX pins can process three levels (high, AK300/2,
open, and low), 32 = 9 different compensa- J1 = USB socket for PCB mounting, type B
There are six resistors on each side (R2… tions can be set per side. The details are J2 = USB socket for PCB mounting, type A
R7 and R8…R13) that can optionally be used described in the data sheet [3]. In general, Enclosure Hammond 1593NTBU
to configure certain functions. The levels the circuit works well with open inputs, which Circuit board 240616-01
at the inputs EQ10, EQ11, and CDPENZ1 as is why I did not fit R3, R4, R6, and R7, nor
well as EQ20, EQ21, and CDPENZ2 deter- R8, R10, R12, and R13. The CDP function is * see text
mine the configuration of an equalizer (the EQ not needed for the purposes described here,
pins) and the use as a charging port (CDP = so it can be disabled by fitting R2 and R11.
Charging Downstream Port, active low). The All settings are queried each time the IC is
equalizer is a switchable compensation of the switched on and stored internally until the
electrical properties of the conductor tracks next time it is switched off. Measurement Options
Since I was interested in the currents flowing
in the circuit, especially when something was
not working properly, I added 0.1-Ω resistors
R1, R14, and R15. The voltage drop can be
conveniently measured at JP2, JP3, and JP4.

The quality of the signals can be assessed at

JP6 and JP7 using a differential high-speed
oscilloscope probe, for example. The circuit is
largely symmetrical. On the right side, there is
an additional voltage regulator configured for
a voltage of 5 V, which can be supplied exter-
nally via X2 and is sufficient to provide enough
power to supply a USB device connected to J2.

Miscellaneous
Figure 5 shows the assembled board in the
plastic casing for which it was designed. My
homemade USB isolator works well, and I am
Figure 5: The custom-made, assembled circuit board in its housing. satisfied. Barely had the board been installed

58 March & April 2025 www.elektormagazine.com

in the casing and tested when support About the Author
from Analog Devices contacted me with a Alfred Rosenkränzer worked for many years
Related Products
workaround: It was suggested that an ordinary as a development engineer, initially in the
USB hub be connected between the PC and field of professional television technology. > LabNation SmartScope USB
the ADUM4165 evaluation board. I tried this Since the late 1990s, he has been develop- Oscilloscope
suggestion, and it actually worked: The Audio ing digital high-speed and analog circuits www.elektor.com/17169
Precision analyzer can now be controlled. The for IC testers. Audio is his private passion.
> Aoyue Int 866 (3-in-1) SMD Hot Air
same trick also works for the ADUM4166. Rework Station
However, the cause of the problem (and why www.elektor.com/20783
the USB hub fixes it) remains a mystery. Questions or Comments?
Do you have questions or comments
By the way: I still have a few empty circuit about this article? Email the author at
boards left over for the ISOUSB211 solution. alfred_rosenkraenzer@gmx.de, or contact
Translated by Jörg Starkmuth — 240616-01 Elektor at editor@elektor.com.

WEB LINKS
[1] ISOUSB211DPEVM evaluation board: https://www.ti.com/tool/ISOUSB211DPEVM
[2] Elektor web page for this article: https://www.elektormagazine.com/240616-01
[3] ISOUSB211 data sheet from TI: https://www.ti.com/lit/ds/symlink/isousb211.pdf

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March & April 2025 59

 SOFTWARE

Intervention
Before Damage
Predictive Maintenance in Practice

By Tam Hanna (Hungary) The term “anomaly detection” is based on a highly important theory:
The AI learning process shown in the middle of the figure usually
One of the most valuable applications of has no direct knowledge of what is going on inside the machine.
AI is certainly predictive maintenance Instead, the system examines measurement data from various
sensors and compares it with training data in order to detect devia-
– the forward-looking servicing of tions and report them.
machines. The neural analysis of data
streams, usually from multiple sensors, Controller Zoo
The MCX family, which was introduced at the beginning of 2024,
makes it possible to detect critical is NXP’s path to the future. Figure 2 shows the options that devel-
system states at an early stage and to opers will be faced with in this now very extensive microcontrol-
intervene before any damage actually ler portfolio. The MCX N series, designed primarily for the needs
of AI applications, is presented as shown in Figure 3. It should
occurs. In this article, we will provide be noted here that the smallest variant, 2X, does not come with
not only background information a Neural Processing Unit (NPU) — this is only available from the
but also a practical application of the MCX 5X upwards.

method. We will use an inexpensive For the sake of convenience, we will use the high-end version
development board and example MCX N9X in the following steps (see box Start with Large
software from NXP, as well as an Controller Types). The controller is available at a relatively low
price in the form of the FRDM-MCXN947 evaluation board (see
acceleration sensor, to detect anomalies also the Related Products box).
in the operation of a fan.

With the right parameterization, self-learning algorithms enable

predictive maintenance systems to detect almost any measurable
problem state. In principle, the systems are represented as in the
flowchart shown in Figure 1.

Figure 1: Where there are input and output parameters, predictive

maintenance or anomaly detection is possible. Figure 2: NXP’s portfolio is teeming with choice (Source: [9]).

60 March & April 2025 www.elektormagazine.com

Figure 3: The AI accelerator is not available in all variants (Source: [10]).

Start with Large Controller Types The following practical example requires an accelerometer (in
Particularly for small series, the price differences between addition to an NXP-specific TFT display for showing the calculated
the various memory configurations are marginal. The author results). This sensor is connected to the fan we want to monitor, in
therefore likes to start with the largest possible variant of a way that couples as much vibration as possible. The accelerom-
a chip in his consulting business — if the system works, eter and evaluation board are connected via I2C, while the display
you can scale down later. However, it should be noted that is connected to the designated port.
a small reserve of resources can be helpful — you never
know what additional functions the customer might want Software Setup
in the field. Similar to the compulsory registration for Cube introduced by
STMicroelectronics some time ago, NXP also only allows people
with an NXP account to download the documentation and
A USB-C cable is required to communicate with the computer. In toolchain. The download process (probably inspired by Android) is
addition, of course, various (sensor) hardware is needed to enable also interesting: The SDK and the integrated development environ-
the ingestion of the required information as shown in Figure 1. ment have to be obtained in two separate transactions.

Figure 4: The board assistant asks you to select the appropriate evaluation kit.

March & April 2025 61

The first step is to visit the SDK downloader available at [1], where 300 MB in size, which on the author’s workstation is named
we select the option Select Development Board. After clicking the SDK_2_14_0_FRDM-MCXN947.zip.
button, the website prompts us to log in. The next step is to use
the SDK search and download assistant, something we are familiar The next step is to actually download the IDE. Fortunately, there
with from other providers. is a link at the bottom right of the MCUXpresso SDK Dashboard
that we can click on in the next step: Download MCUXpresso IDE.
The first thing to do is to click on the text field Search for hardware,
where the string FRDM-MCXN947 must be entered. The Boards The reward for our efforts is the appearance of a new browser
section then shows the board, which can be selected as shown in window, in which — analogies to the download process of STMs
Figure 4. Of particular note is the turquoise selection button on CubeIDE are recognizable — we click again on the yellow Download
the right, which allows the compilation and assembly of a specific button in the first step. The result is that the browser has left us
SDK version. Since we want to experiment with a skeleton project further down the download web page. The link that is relevant for
provided by NXP in the following steps, the correct version is 2.14.0. us is MCUXpresso Integrated Development Environment (IDE) updated.
Then click the Build SDK button to start the assembly wizard.
Occasionally, yellow error messages may appear on the website,
In the next step, the wizard asks for various settings. In addition to the indicating that the license service is temporarily offline. This is
Host OS (Windows 10 will be used in the following steps), the toolchain because NXP manages the distribution of MCUXpresso using the
must be selected. Here we want to opt for the MCUXpresso IDE. Flexnet license system, which is familiar from various games and
other software. In this case, it is usually sufficient to wait a few
The list that appears below then allows us to select the additional minutes for the confirmation email to arrive. After that, refresh
components we want (see Figure 5). For convenience, it is recom- the page to get to the list of all licensed program packages.
mended that you download everything that NXP provides for this
microcontroller family by clicking Select All. Once there, a click on the MCUXpresso IDE link is required — at the
time this article is written, the product is available in version 24.9.
Once the work is done, click the Build button again. After a few After accepting the licenses, NXP offers binary files for Windows,
seconds, the SDK will appear in the view labeled MCUXpresso SDK MacOS and Linux, all of which are around 1.1 GB in size. In the
Dashboard, where it can be downloaded by clicking the Download following steps, the author will work with the file MCUXpres-
option. At the time this article is written, this is a file of around soIDE_24.9.25.exe.

Figure 5: NXP allows modular configuration of the SDK.

62 March & April 2025 www.elektormagazine.com

 Figure 6:
Lateral entrants could be
in for a surprise here.

During the installation, which generally goes as expected, Windows

sometimes displays several UAC warnings. These have to be
acknowledged because developers in the NXP ecosystem have to
deal with a wide variety of programming devices.

When using the default settings, the MCUXpresso installer creates

a desktop icon that can be used to launch the integrated develop-
ment environment “directly”. Since the IDE is based on Eclipse
in the background, the tool asks for a path to a workspace during
the first start — this can be set more or less as you like, the default
settings worked without problems in the test, at least on the author’s
workstation. It is also important to allow all access — in the firewall
warning, you must explicitly allow the integrated development
tool to interact with local networks.

For developers unfamiliar with MCUXpresso, a small pitfall lurks

in the welcome screen: the window responsible for accepting the
SDK downloaded in the previous step cannot be activated via the
link for installing SDKs. Instead, you have to close the welcome
screen to switch to the actual MCUXpresso working environment.
There you will find a window, as shown in Figure 6, in which the Figure 7: NXP spreads the useful functions all over the system.
SDKs can be managed.

In the next step, the .zip file is dragged and dropped into this In the case of anomaly detection, NXP provides an example project
window. You can safely ignore the warning message displayed by on GitHub at [2] that we will use in the following steps. Note that
the IDE. A few seconds later, the new toolchain is ready for action the IDE allows direct rehydration of source code from GitHub
as part of the MCUXpresso IDE. — it is not necessary to use the command line client to load the
project skeleton into the workstation file system in the first step.
Examining the (Complex) Example Code Specifically, the function Import from Application Code Hub is avail-
Samsung’s now defunct Bada operating system was popular with able for this purpose, which is hidden in the Quickstart panel shown
developers in part because it put handheld software developers in in Figure 7.
the role of “plumbers” to a certain extent. Developing an applica-
tion for this operating system generally involves connecting the The search string on-device training fan anomaly on mcxn947 then
various building blocks provided by Samsung. In the opinion of the leads to the display of a tab with the desired example, which you
author, this development method, which at the time was revolu- click on with the left mouse button in the next step. MCUXpresso
tionary and ingenious, is also recommended when working with responds by displaying a rotating progress bar, which you have to
artificial intelligence systems. confirm after a while.

Since most AI tasks are structured according to one of just a The appearance of a tab with the content shown in Figure 8, which
relatively small number of schemes, developers should start by appears on the right of the screen, then allows you to click on the
looking for an example that can be run, and then adapt this to the GitHub link symbol. In the next step, a Next option appears in the
needs of the given task. Eclipse IDE.

March & April 2025 63

Figure 8: Here you have
to click on the GitHub
link to get to the practical
example.

The reward for your efforts is the display of a more or less standard A queue will then work in the background, which — fed by the
GitHub deployment assistant. In tests by the author, it was possible sensor task and harvested by the algorithm task — ensures the
to simply accept all the settings as proposed — due to the limited transfer of the incoming information from the accelerometer.
speed of GitHub, a little waiting time is sometimes required. If
an error message appears as shown in Figure 9, you can update Brief Analysis of the Sensor Task
the SDK. NXP supports two different sensor types here. In addition to the
FXLS8974 from NXP itself, the MPU6050 from TDK InvenSense,
After successfully completing the loading process, we can start which is well known for its low-cost availability on AliExpress and
analyzing the code. The “entry point” of the example, which is other sites, is also on the support list. In the sensor task, however,
based on FreeRTOS and LVGL, can be found in the file source/main.c, this selection does not have a significant effect. There is a kind of
where the creation of the sensor and algorithm tasks is of partic- hardware abstraction layer that performs the following breakdown
ular importance: of the incoming accelerometer data and provides it for harvesting
via a uniform interface:
int main(void) {
. . . int IMU_ReadSensorData(int16_t *pBuf,
if (xTaskCreate(app_sensor_task, "SENS", 4096, uint16_t fifo_cnt, uint16_t readSize)
NULL, configMAX_PRIORITIES-1, NULL) != pdPASS) { {
PRINTF("Failed to create sensor task.\r\n"); if (sensor_id == IMU_6050)
while (1) {} return MPU_ReadSensorData(pBuf, fifo_cnt, readSize);
} else if (sensor_id == IMU_FXLS8974)
if (xTaskCreate(app_algo_task, "ALGO", 0x1000, return IMU_FXLS8974_ReadSensorData(pBuf,
NULL, configMAX_PRIORITIES-1, NULL) != pdPASS) { fifo_cnt, readSize);
PRINTF("Failed to create sensor task.\r\n"); else return 0;
while (1) {} }
}
The architecture of this example is interesting in that the raw data
supplied by the accelerometer never actually reaches the ML model.
Instead, the ML model is only presented with a frequency spectrum
that the example code obtains by applying an FFT process to the
raw data supplied by the accelerometer.

The way in which FFT is implemented is always an interesting

topic — for example, in issue 3-4/2023, we reported on the K210
developed by Kendryte, which included an FFT accelerator unit
Figure 9: The SDK version mentioned in the documentation no longer and accordingly had “dedicated” FFT APIs. [3].
matches the content of the Application Code Hub.

64 March & April 2025 www.elektormagazine.com

In the case of working with an ARM controller, the CMSIS DSP
library documented at [4] has established itself as a de facto
standard. It is interesting to note that Arm points out in several
places in the documentation that the name “DSP” is only retained
for legacy reasons; the library itself now sees itself as a kind of
general store for all kinds of code in the field of signal processing.

Developers can find out which types of hardware acceleration are

used in the background by visiting the GitHub repository with the
library’s source code, which is provided at [5]. For example, the
following statement can be found there:

It provides optimized compute kernels for Cortex-M and for Cortex-A.

Different variants are available according to the core and most of the Figure 10: To understand how a support vector machine works, let’s imagine
functions are using a vectorized version when the Helium or Neon that we only get two coefficients per measurement, which determine the
extension is available. coordinates in this two-dimensional diagram. The SVM then tries to group
the points by imaginary lines.

The purpose of “windowing” the FFT raw data is to reduce the effects
of inaccuracies occurring in the edge areas due to the limited length rmsAry[j] += ftmp * ftmp;
of the data array [6]. It is also interesting to note that the FFT data }
is windowed by a float field, which the NXP example code creates arm_sqrt_f32(rmsAry[j] / APP_FFT_LEN, rmsAry + j);
according to the following scheme: arm_rfft_q15(&s, fft_buffer, g_app.rfftOutBuf[j]);

void hanning_window(float *window, int length) { Data Analysis Using an SVM

for (int n = 0; n < length; n++) { If we assume, for the sake of simplicity, that the measurement data
window[n] = 0.5 * (1 - processing would only provide two coefficients per measurement,
cosf(2 * 3.141593f * n / (length - 1))); then these could be plotted in a two-dimensional diagram. In the
} best case, the various operating states are then located in differ-
} ent areas of the plane, which can be separated by imaginary lines
(Figure 10). In a three-dimensional space, good and critical states
The actual sensor task then begins by creating various memory could be separated by surfaces – and this basic principle can easily
areas that are parameterized by the respective initialization be applied in higher-dimensional spaces as well.
function:
For years, this type of task has been solved by algorithms known
void app_sensor_task(void* parameters) as support vector machines (SVMs). For those seeking a detailed
{ mathematical introduction, Wikipedia offers a surprisingly detailed
. . . explanation of the topic [7].
ringbuffer_init(&ringbuffer_handler,
(uint8_t*)ring_buffer, sizeof(ring_buffer)); For the realization of SVMs, the LIBSVM library developed by
hanning_window(hanning_ary, APP_FFT_LEN); Chih-Chung Chang and Chih-Jen Lin has become established as
arm_rfft_instance_q15 s; a de facto standard. At the time of writing this article, the website
arm_rfft_init_q15(&s, APP_FFT_LEN, 0, 1); with the (open-source) library code can be found at [8].

The “meat” of the sensor data processing is then found in an endless Next, we will turn to the actual application evaluation logic. Pleas-
loop. For reasons of space, I will just show the innermost working ingly, it begins with the realization of a state machine:
part here. What is important here is the call of the method arm_
rfft_q15, which is responsible for the actual application of the typedef enum {
transformation to the sensor data. kAppPredicting,
// in main screen, predicting data
for (int i=0; i < APP_FFT_LEN; i++) { kAppWaitForCollect,
g_app.rfftInBuf[j][i] -= g_app.dcEMAs[j]; // in train screen, wait for "Start" button
fft_buffer[i] = g_app.rfftInBuf[j][i] * kAppCollecting,
hanning_ary[i]; // in train screen, collecting data
ftmp = (float)(g_app.rfftInBuf[j][i]) / g_rmsDiv; kAppWaitForReturn,
}AppState_e;

March & April 2025 65

 Introduction to State Machines ad_get_support_vector(g_app.pADModel,
If you are not familiar with state machines, you should get &(g_features[APP_FEATURE_CNT]), &pre_svs_cnt);
the textbook Code Reading written by Diomidis Spinellis. g_app.inc_train = 0;
It is very inexpensive on the second-hand market, and in }
the opinion of the author, it is an absolute must-read for g_app.pADModel = ad_train(g_features,
anyone who does not have a strong background in techni- APP_FEATURE_CNT + pre_svs_cnt, g_app.gamma, g_app.nu);
cal computer science. deSlideAcc = 0;
if (g_app.pADModel) {
g_app.appState = kAppWaitForReturn;
}
To actually feed the model, NXP defines wrappers for the methods }
created in LIBSVM. Of particular importance are the two functions
for training and analysis — note that AD_Predict returns a float In this area, two things are relevant: firstly, training the model and,
value with the result of the algorithm, as shown here: secondly, updating the state machine.

__WEAK void* ad_train(float features[][APP_FEATURE_DIM], The next task of the prediction code is to call the actual predict
int featureCnt,float gamma, float nu) { method, which — as discussed above — returns a result from the
return svm_train_mode(features, featureCnt,gamma, nu); model.
}
volatile float g_modelRetPlaceHolder; Practical experience shows that the bulk of the intelligence in such
__WEAK float ad_predict(void* pvModel, AI tasks lies in the weighting of the results – here, in addition to a
float feature[APP_FEATURE_DIM]) { multiplication, we also note an inclusion of the sign. In any case,
return svm_model_pre(pvModel, feature); the reward for our efforts is that the variable g_app.health now
} shows the current state of health of the system to be maintained.

The SVM task starts by harvesting the most recent accelerome- ret = ad_predict(g_app.pADModel, feature);
ter value, which is written to a FreeRTOS queue by the previously float retSign = -1.0f;
discussed task. From now on, the content of the feature variable if(ret > 0){
is a representation of the most recent sensor values in both the retSign = 1.0f;
training and prediction cases. ret *= 25;
} else {
void app_algo_task(void* parameters){ ret *= 1;
. . . }
float feature[APP_FEATURE_DIM]; g_app.health = (g_app.health + ret + 0.5 * retSign);
. . .
for (;;) { Practical experience in design shows that a plausibility check or
xQueueReceive(g_app.qh_NewSample, value restriction of the results returned by an AI model always
feature, portMAX_DELAY); makes sense. This applies in particular if the values — as is the case
g_app.isNewFeature = 1; here in the variable g_app.health — are integrated or accumu-
lated over the program runtime.
In the next step, we can turn to the training logic. The first task is
to collect the incoming sensor samples — a buffer is filled via the if (g_app.health > APP_HEALTH_ABS_MAX)
g_app.featureNdx variable: g_app.health = APP_HEALTH_ABS_MAX;
if (g_app.health < -APP_HEALTH_ABS_MAX)
memcpy(g_features + g_app.featureNdx, g_app.health = -APP_HEALTH_ABS_MAX;
feature, APP_FEATURE_SIZE);
g_app.featureNdx++; The next step of the program then implements a hysteresis. This
ensures that the model does not oscillate in borderline cases:

When the buffer reaches the limit stored in APP_FEATURE_CNT, the if (g_app.fanState == kFanOn) {
actual training takes place. if (g_app.health < APP_ABNORMAL_LEVEL - APP_SWITCH_BAND)
g_app.fanState = kFanErr;
if (g_app.featureNdx == APP_FEATURE_CNT) { } else if (g_app.fanState == kFanErr) {
int32_t pre_svs_cnt = 0; if (g_app.health > APP_ABNORMAL_LEVEL + APP_SWITCH_BAND)
if(g_app.inc_train){ g_app.fanState = kFanOn;

66 March & April 2025 www.elektormagazine.com

 } else {
g_app.fanState = kFanOn;
}

The rest of the code is then just responsible for switching the various
LEDs on and off to make the ML model’s results visible to the user: About the Author
Engineer Tam Hanna has been working with electronics, comput-
if(fanState == kFanErr){ ers, and software for more than 20 years; he is a freelance devel-
LED_OFF(GREEN); oper, book author and journalist (www.instagram.com/tam.hanna).
LED_ON(RED); In his free time, Tam is involved in 3D printing and selling cigars,
LED_GREEN_OFF(); among other things.
LED_RED_ON();
}else{
LED_OFF(RED); Questions or Comments?
LED_ON(GREEN); Do you have questions or comments about this article? Email
LED_RED_OFF(); the author at tamhan@tamoggemon.com, or contact Elektor at
LED_GREEN_ON(); editor@elektor.com.
}

Perspective
The experiments shown here have demonstrated that the reali-
Related Product
zation of predictive maintenance is nowhere near as complicated
as the AI development community, which is always eyeing “other > Get Started with the NXP FRDM-MCXN947
people’s money”, likes to present it. Development Board (Bundle)
www.elektor.com/20990
In particular, anyone who invests a little time in the background
of SVM and Co. can quickly develop quite powerful systems. The
author hopes that the experiments carried out here will provide
a first incentive for readers to delve deeper into this fascinating
area of software technology.
Translated by Jörg Starkmuth — 240452-01

WEB LINKS
[1] SDK downloader for MCUXpresso IDE: https://mcuxpresso.nxp.com/en
[2] Example project for anomaly detection (GitHub):
https://github.com/nxp-appcodehub/dm-on-device-training-fan-anomaly-on-mcxn947
[3] Tam Hanna, “FFT with a Maixduino,” ElektorMag 3-4/2023: https://www.elektormagazine.com/magazine/elektor-292/61493
[4] CMSIS DSP library, Documentation: https://arm-software.github.io/CMSIS_5/DSP/html/structarm__rfft__instance__q15.html
[5] CMSIS DSP library (GitHub): https://github.com/ARM-software/CMSIS-DSP
[6] Introduction to the windowing of FFT raw data (Application Note LDS Dactron): https://tinyurl.com/FFT-Windows
[7] Support Vector Machine (Wikipedia): https://en.wikipedia.org/wiki/Support_vector_machine
[8] LIBSVM — A Library for Support Vector Machines: https://www.csie.ntu.edu.tw/~cjlin/libsvm/
[9] NXP MCX portfolio: https://tinyurl.com/NXP-MCX-MCUS
[10] AI accelerators in the NXP MCX portfolio: https://www.nxp.com/docs/en/fact-sheet/MCXNFS.pdf

March & April 2025 67

 BACKGROUND

SPoE - Electromagnetic
Compatibility
Single-Pair with Power-Over-Ethernet Through the Eyes of EMC

net interface that transmits data over two wires and

By Adrian Stirn (Würth Elektronik eiSos) simultaneously supplies power, combining “Single Pair
Ethernet” (SPE) with “Power over Data Lines” (PoDL).
Due to the simple cabling with only one
twisted pair of wires, single-pair Ethernet SPE enables Ethernet communication with only one
pair of wires, making it ideal for space-saving and
is extremely attractive. If the power supply cost-sensitive applications in industrial, automotive
function can be integrated in addition to data and IoT devices. PoDL extends Power over Ethernet
transmission, the solution “Single-Pair with (PoE) to SPoE enabling power and data transmission
over a single twisted pair of wires, simplifying instal-
Power-over-Ethernet” (SPoE) is unbeatable. lations and reducing costs.
This article describes the EMC behavior of the
SPoE reference design from Würth Elektronik. To carry out the EMC tests, the reference design
consisting of two boards (Powered Device — PD and
Power Sourcing Equipment — PSE) is operated with
a defined transmission path as the test object.
There are many possible applications for a
10 Mbit/s SPoE interface with integrated energy Figure 2 shows this transmission path with the auxil-
transmission, such as the operation of sensors at iary equipment required for operation shown in gray.
long distances. With the growing demand for data and A shielded SPE cable or an unshielded twisted pair
power in areas such as industrial automation, automo- cable can be used as the transmission path between
tive and IoT networks, SPoE (often referred to as Single- the PD and PSE. Laptop 1 is connected to the PD via a
Pair Ethernet with Power-over-Data-Lines — SPE PoDL) shielded 10 Mbit/s Ethernet interface. It receives its
offers an efficient solution that enables both data and IP address from the DHCP server (WLAN router) via
power transmission over a single twisted pair of wires. the SPoE interface, which connects the PSE and PD.
This article deals with the EMC behavior of the SPoE The PD is powered by the PSE board.
reference design RD041 from Würth Elektronik [1],
focusing on the low emissions and high immunity The PSE part of the reference design has a 24 V input
to continuous and transient disturbances. that supplies the SPoE reference design. In the refer-
ence design, this connection is designed as a port on
SPoE Reference Design and Test Setup the local DC power supply network. The 10 Mbit/s
The reference design RD041 in Figure 1 is an Ether- interface is connected to the router via a shielded
Ethernet cable and then on to the Laptop 2 being evalu-
ated. Both laptops receive their IP addresses from the
DHCP server. The reference design is therefore ready
and can be used as an adapter to extend an Internet
connection in a plug-and-play manner.

Test Software and Performance Criteria

Laptop 1 serves as a server that sends known test data
to Laptop 2. This evaluates the error rate in the trans-
Figure 1: PSE (bottom) mission and the transmission speed using a Windows
and PD (top) of the
RD041 during start-up. application. This monitoring application has already
been successfully used in the application notes for
 the GB-Ethernet design (ANP116 and ANP122) [2][3].

68 March & April 2025 www.elektormagazine.com Partner Content

 Figure 2: Test setup for evaluating the performance of the SPoE reference design.

Figure 3 shows that an average transmission rate

of slightly less than 9 Mbit/s can be achieved. In the
selected test case, the packets have a short transmis-
sion time compared to the tests on the Gigabit Ether-
net interface. During the tests, it is therefore possible
to test with a measurement and reaction time of one
second.

During the immunity tests, the performance of the

reference design is checked against the criteria in
Table 1.

When evaluating the performance criteria, the auxil-

iary equipment also has a relevant impact on the
performance of the transmission path. For example,

the transmission error rate increased when a WiFi
interface was used between the router and Laptop 2 Figure 3: Monitoring of
instead of a shielded Ethernet cable. the SPoE interface. PSE
and PD are connected
to the network via an
Shield Connection of the Ethernet Interface
Ethernet interface.
As already shown in Application Note ANP116 [2], the
following components are suitable for connecting the
shield of the Ethernet socket to the GND plane of the Figure 4: Shield
board as shown in Figure 4: connection of the
Ethernet socket
according to ANP116.
> 2× 10 nF X7R 1206 MLCC 100 V
There is an MLCC on
(part no. 885012208112) each side; the varistor is
> SMT varistor (part. no. 82551600) not shown.

The shield connection is used for the SPoE interface 

and for the 10 Mbit/s Ethernet interface. The varistor is
not shown in Figure 4. This can be placed parallel to the
capacitor on one side. The USB interface on the boards
is not used for the analyses in this article.
Measurand Performance Technical Evaluation Criterion
Emission of the Reference Design Criterion
The emission of the reference design in the configu- Data rate A Above 8 Mbit/s
rations described above is analyzed below. The USB B Below 8 Mbit/s
interface is not used for the emission measurements Error rate A 0%
in accordance with CISPR 32; communication takes B Error rate increased or communication loss with
place exclusively via the Ethernet and SPoE interfaces. automatic reconnection.
C 100% = communication loss, no automatic
Radiated Emissions reconnection possible.
PD and PSE are operated and tested together to test
radiated emissions. The cable length at the SPoE inter- Table 1: Performance criteria of the SPoE reference design.

Partner Content March & April 2025 69

 face for the emission test is 1 m horizontally in the
field between the two boards.

The PSE is supplied with 24 V via feed-through filters

from a laboratory power supply unit located outside
the anechoic chamber. The PSE and PD are located
inside the full anechoic chamber, whereby the PSE is
connected via 10 Mbit/s Ethernet with a shielded cable
to an Ethernet fiber optic converter, which establishes
the connection to the router and Laptop 2 outside the
measuring hall. The PD is connected to Laptop 1 via
a shielded Ethernet cable, which is inside a shielded
box (Figure 2).

This setup prevents interference from the router or

the laptops being measured during the emission tests.
As this set-up is also used in the radiated immunity
test, the laptops and the router are also protected from
being affected by the electric field of the immunity
test.

Figure 5: Comparison of the radiated interference emission of the SPoE reference design The interference spectrum of the reference design
when using shielded SPE cable or unshielded twisted pair cable. in Figure 5 is at least 9 dB below the limit value for
both cable types used, and the results are comparable.

Radio Interference Voltage

The PSE and the PD may be physically separated in the
subsequent setup and are therefore tested individually.
The DC input of the PSE is to be tested as a possible DC
mains input, the Ethernet cable of the 10 Mbit/s Ether-
net interface and SPoE interface are to be regarded as
a long network cable. The emission of the DC input on
the PSE is measured in accordance with CISPR 16 with
a 50 µH AMN (Artificial Mains Network), the emission
of the network ports is measured using 150 Ω CDNs
(Coupling Decoupling Network), which act as an AAN
(Asymmetric Artificial Network). The test setups for
measuring the radio interference voltage at the PSE
and PD are shown in Figures 6 and 7.

Figure 6: Measurement setup for testing the radio interference voltage on the PSE.
A CDN T2 is used to test the SPoE interface with an
unshielded twisted-pair cable; when measuring
the interference on the shielded SPoE interface, the
emission is tested using a self-built CDN for shielded
SPE cables. The interference on the shielded Ether-
net cable is measured using a CDN for shielded
Cat5e cables. Network replicas and CDNs must always
be terminated with 50 Ω in the test setup (either by
the test receiver or by means of a 50 Ω resistor).

The measurement setup of the conducted interfer-

ence emission on the PSE board of the SPoE reference
design is shown in Figure 8. The measurement results
Figure 7: Measurement setup for testing the radio interference voltage on the PD. of the conducted emissions on the SPoE interface of

70 March & April 2025 www.elektormagazine.com Partner Content

 Figure 8: Measurement
of the conducted
the PSE are shown in Figure 9, with the results of the interference emission
quasi-peak detector at the top and the mean value on the PSE board of the
SPoE reference design.
detector at the bottom. Further measurement results
of the conducted emission test are shown in detail in 
Application Note ANP141 [4].

The SPoE reference design is characterized by low Figure 9: Measurement

radiated and conducted emissions. Despite open results of the conducted
circuit boards without a shielded housing, the interference emission on
the SPoE interface of the
emission results are well below the EMC limit values
PSE. The results of the
for residential areas. Even with an unshielded twisted quasi-peak detector are
pair cable, the results of the SPoE interface are well shown at the top and the
below the EMC limit values for all measurements. results of the average
From the point of view of emission testing, shield- detector at the bottom.
ing of the SPoE interface is therefore not necessary.


Interference Immunity of the Reference

Design
A detailed examination of the immunity of the refer-
ence design to continuous and transient interference
as well as the ESD behavior is beyond the scope of this
article. Therefore, please refer to the comprehensive
Application Note ANP141 [4], where you will find a
detailed description of the test setups and measured
values.
250085-01

About the Author

Adrian Stirn studied electrical engineering at Heilbronn
University and then set up the company’s own EMC
laboratory at Würth Elektronik’s Waldenburg site. Since
2016, he has been supporting customers in trouble-
shooting EMC problems during development. He
also focuses on product conformity in the European
Economic Area and the protection of ESD-sensitive
components.

WEB LINKS
[1] Heinz Zenkner, “Design of a Single Pair Ethernet System with Power over Data Lines (SPoE),” Reference Design from Würth
Elektronik RD041: https://www.we-online.com/RD041
[2] Adrian Stirn, “Gigabit Ethernet interface from an EMC perspective,” Application Note from Würth Elektronik ANP116:
https://www.we-online.com/ANP116
[3] Adrian Stirn, “Gigabit PoE Interface from an EMC perspective,” Application Note from Würth Elektronik ANP122:
https://www.we-online.com/ANP122
[4] Adrian Stirn, “The SPoE Interface from an EMC Perspective,” Application Note from Würth Elektronik ANP141:
https://www.we-online.com/ANP141

Partner Content March & April 2025 71

 RETRO TECH

Color TV
A Wonder

(Source: Early Television Museum)

of Its Time
Creating a New World the center of the RCA!CT-100’s revolutionary design were its techni-
cal components that paved the way for the future of color television.
!
Cathode-Ray Tube
By Vince Sosko (Mouser Electronics) The heart of the system was the cathode-ray tube (CRT), responsible
for rendering the images on the screen. Unlike its monochromatic
Seventy years ago, the!RCA CT-100 opened predecessors, the CT-100 incorporated a shadow mask —!a metal
our eyes to a new visual experience. This sheet with precision-drilled holes!— to ensure precise placement
of color phosphors. These phosphors emitted light when struck
groundbreaking device featured a 15-inch by the electron beam, allowing for a wide range of color hues and
screen!and was the first color TV to be mass- saturation. This breakthrough allowed viewers to experience a
produced. Let’s take a trip back!! level of visual richness previously unseen, making the CT-100 a
symbol of technological advancement and innovation.
!
CTC-2 Chassis
Earlier this year, over 120!million people tuned in to watch the The CT-100 incorporated capacitors, resistors, transistors, and
Super!Bowl, and many made a big purchase in the weeks prior vacuum tubes into its CTC-2 chassis (Figure!1) to process and
to capture the spectacle in all its grandeur and glory. The newest amplify the incoming television signal. Included among its complex
smart TVs, with their amazing picture quality and immersive sound layout of 36!vacuum tubes was the 15GP22 color picture tube, which
experience [1], afford viewers the ability to feel like they’re at the used electrostatic convergence that necessitated static and focus
game without paying an astronomical amount for a ticket. Today, adjustment knobs on the cabinet. Between their short service life
an array of advanced light-emitting diode (LED) technologies lights and higher cost compared to other picture tubes of the time, the
up our home screens with magnificent colors. But to fully appreci- 15GP22 became a rare component that, while essential for synchro-
ate the majesty of modern televisions, let’s take a trip back to 1954, nizing the color and brightness information and driving the CRT
when color televisions first broke into the market. to produce the final image, has made restoration projects for the
! CT-100 rather difficult.
While the collector community debates between the !
Admiral!C1617A and the Westinghouse!H84OCK15 as the first true In addition to these new-age picture tubes, the CT-100 featured
color TV to be released, we’ll focus on the RCA!CT-100, which came sophisticated color decoding circuits responsible for processing the
out right on their heels and was the first color TV to be mass-pro- color information contained in the broadcast signal. These circuits
duced (while the Admiral and Westinghouse were both discon- decoded, or “demodulated,” the chrominance (color) signal and
tinued only months after release). synchronized it with the luminance (brightness) signal to accurately
! reproduce colors on the screen.
What Was the CT-100? !
Marketed as “The Merrill” (nicknamed after RCA executive George Tuner and RF Components
H.!C.!Merrill), the CT-100 marked a turning point in the evolu- Color was not the only marvel that set the CT-100 apart from other
tion of television, introducing vibrant hues to a world accustomed televisions during this broadcasting revolution. The CT-100 also
to monochrome screens. Manufactured by the Radio!Corpora- featured a turret-style tuner and RF components that allowed it to
tion of America (RCA), this groundbreaking device featured a receive broadcast signals over the airwaves. The tuner tuned into
15-inch!screen that brought a spectrum of colors into living rooms, specific channels, which surprisingly included very high frequency
transcending the limitations of black-and-white broadcasting. At (VHF) and ultra-high frequency (UHF) broadcasts emerging at the

72 March & April 2025 www.elektormagazine.com Partner Content

time, while RF components amplified and processed the incoming (LCD), and organic light-emitting diode (OLED). The journey from
signal before it was decoded and displayed on the screen. These the CT-100 to contemporary displays has seen improvements in
components, combined with color-rendering capabilities, forced resolution, contrast ratios, and overall visual fidelity.
television network companies of the time to play catch-up with !
the RCA!CT-100. Beyond hardware, the evolution of color television is evident in
! content production. Filmmakers and content creators now lever-
The Way It Was age the full spectrum of colors to tell compelling stories and create
The release of the RCA!CT-100 in 1954 unfolded against the backdrop visually stunning experiences. High-definition content, stream-
of post-World War!II optimism and the burgeoning consumer ing services, and smart TV capabilities have further transformed
culture of the 1950s. Television, already a popular medium, was how we consume television, offering a diverse range of content
evolving rapidly. The United States was experiencing economic accessible at our fingertips.
prosperity, and as households became more affluent, the desire for !
modern conveniences grew. The release of the CT-100 aligned with The transition from black-and-white to color television was not
this cultural shift, offering consumers a glimpse into the future of without its challenges. Concerns about compatibility, the cost of
television —!a future painted in vibrant colors. upgrading infrastructure, and the need for standardization initially
! slowed the widespread adoption of color broadcasting. However,
The timing of the CT-100’s release also coincided with the concur- as technology matured, these challenges were overcome, and color
rent efforts of major television networks to embrace color broad- television became the norm rather than the exception.
casting. NBC made history by airing the first coast-to-coast color !
broadcast of the Tournament of Roses Parade on January!1, 1954. The RCA!CT-100’s importance transcended its role as a technolog-
This event served as a dazzling showcase for the capabilities of color ical marvel; it marked a cultural and visual revolution. The intro-
television and generated tremendous excitement among viewers. duction of color television was a transformative moment in the
! history of mass media. It elevated the viewing experience, making
The Bigger Picture it more immersive, engaging, and reflective of the vibrant world
Since the launch of the RCA!CT-100, color television has become a it aimed to capture.
ubiquitous part of our daily lives. Technological advancements have !
propelled the evolution of television displays, moving from cathode- Recently, while watching an old black-and-white show on television,
ray tubes to flat-panel technologies such as LED, liquid crystal display my daughter asked me if that’s how the world looked back then. A
silly question filled with curiosity and innocence, and one I likely
asked my parents as a child, but it reveals just how magical the
advent of color TV was. For many in the 1950s, the world outside
their own town was accessible only through their television screens,
and when vivid colors found their way onto those screens, other
parts of the world became even more real and people’s imagina-
tions were lent a color palette of possibility.
!
As we look back at the journey from the CT-100 to the present, it’s
clear that color television has not only survived but thrived. It has
become an integral part of our visual experience, enriching our lives
in ways unimaginable to those first viewers in 1954. The evolution
of color television mirrors the broader trajectory of technologi-
cal progress —!a journey marked by innovation, adaptation, and
an unending quest to enhance daily experiences to new heights.
Reflecting upon the introduction of the CT-100, we celebrate not
Figure 1: The RCA CT-100’s CTC-2 chassis was not only a wonder of its just the evolution of technology but the enduring impact of a device
time but has proven to be a treasure for collectors and restoration projects. that brought color to our screens and changed the way we view
(Source: HumanisticRationale, Wikimedia Commons, https://commons.
the world.
wikimedia.org/wiki/File:CT-100_with_CTC-2_chassis.JPG)
250016-01

WEB LINK
[1] New Tech Tuesdays (Mouser Electronics), “A New Era of Movie-Watching,” January 2024:
https://resources.mouser.com/new-tech-tuesdays/new-era-movie-watching

Partner Content March & April 2025 73

 PROJECT

ECG
Source: AI-generated by the author
Graph Monitoring
An Implementation with Hexabitz Modules
and an STM32CubeMonitor

By Aula Jazmati (Syria)

I describe a real-time ECG monitoring system using the flexible and
Imagine being able to monitor ECG data in customizable Hexabitz modules. The goal is to create an a"ordable
real-time, wherever you are. This project and portable solution that allows users to monitor their heart’s electri-
cal activity, wherever they are.
aims to make this a reality by developing !
a portable and affordable ECG monitoring I conducted several experiments to validate the functionality and
system, utilizing Hexabitz modules, performance of our real-time ECG monitoring system. These tests
include:
STMicroelectronics IDE software, and sensor !
electrodes. > Signal acquisition and processing — Testing the accuracy and
reliability of the ECG signal acquisition. I analyzed the quality of
the signals and ensured they were free from noise and artifacts.
ECG monitoring is crucial for diagnosing heart conditions such as > Data transmission and storage — Evaluating the e"iciency of
arrhythmias and heart attacks. Traditional ECG monitoring systems data transmission between the Hexabitz modules and the central
are often expensive and complex. Various ECG monitoring systems monitoring system. I also tested the storage capabilities to ensure
have been developed over the years, starting from the use of galva- that the ECG data is securely saved for future analysis.
nometers in the early 20th!century, up to modern systems that rely on > Real-time monitoring — Assessing the system’s ability to provide
advanced technologies. There are many existing systems around, that real-time monitoring of ECG signals. This involved checking the
o"er ECG monitoring, but they are often costly or complicated to use. responsiveness and latency of the system to ensure it can deliver
! timely information to the user.
Why This Project? > User interface and experience — Testing the user interface to
What motivated me to carry out this project was the need for an ECG ensure it is intuitive and user-friendly. I gathered feedback from
monitoring system that could be easily used by individuals at home users to make any necessary improvements to the design and
without requiring complex or expensive equipment. In this article, functionality.
!

74 March & April 2025 www.elektormagazine.com

Figure 1: The typical ECG waveform. (Public Domain image created by Figure 3: The compact, yet powerful EXG Monitor for heart signals
Agateller [Anthony Atkielski] — https://commons.wikimedia.org/w/index. acquisition. (Source: https://hexabitz.com/product/single-lead-exg-
php?curid=1560893) monitor-h2br0x/)

These experiments help us to refine the ECG monitoring system and block; a programming and data transmission block; and a monitor-
demonstrate its potential for real-world applications. ing block.
! !
What Is an ECG? The signal acquisition and processing block, shown on the right,
An ECG is a paper chart or a digital recording of the electrical signals is responsible for acquiring the bio-potential signals from the body
in the heart. These signals — whose typical waveform is shown in and made by two main components, the Single-Lead, EXG Monitor
Figure 1 — can be analyzed by studying their components, repre- (H2BR0x) and the Sensor cable with electrode pads (3!Leads).
senting the cardiac electrical activity. To know more about this, you !
might take a look at [1]. The Hexabitz Single-Lead, EXG Monitor Module (H2BR0) is a one-of-
! a-kind module that can record publication-grade biopotential signals
The Project from your body be it from the heart (ECG), brain (EEG), eyes (EOG), and
Figure!2 illustrates the functional diagram of this design, that could be muscles (EMG). The two sides of this compact, yet powerful module
divided into three main logic blocks: a signal acquisition and processing are shown in Figure 3, whilst two YouTube introductory videos about

Figure 2: Functional
diagram of the design.

March & April 2025 75

it can be watched at [2] and [3]. The fact sheet of this EXG monitor board. It also provides bridge interfaces to several communication
is available at [4]. protocols allowing, for instance, the programming of the target through
! the bootloader.
What are the points of strength of this unit? !
! The monitoring block, shown on the left of Figure!2, provides a real-time
> Record publication-quality biopotential signals like ECG, EMG, feedback. It includes the STM32CubeMonitor Dashboard to display
EOG, or EEG. the ECG signals and a buzzer, that emits a sound at each peak of the
> Small size allows easy integration into mobile and space-con- ECG signal indicating the heartbeats.
strained projects. !
> Notch filter (second order) to remove 50-Hz noise from AC!mains. Software Tools, IDE, and Libraries
> H2BR0 is based on an STM32G0 MCU. For the realization of this ECG monitor project, the software plays a
> Advanced C!code can be programmed with easy-to-use APIs. crucial role. Therefore, I decided to implement it using a combination
> Possibility to be connected to external hardware or combined of specialized tools and libraries that ensure optimal performance
with other Hexabitz modules! and reliability.
> Equipped with an open-source MATLAB interface. !
! > STM32CubeMonitor: a versatile tool that allows real-time
The Sensor Cable with three!electrode pads is a simple, three-conduc- monitoring and visualization of variables in STM32 applications. It
tors cable with electrode pads (red, black and blue leads). The cable provides a user-friendly interface to create custom dashboards.
is 24" long and features a 3.5-mm audio jack connector on one end > STM32CubeIDE: an integrated development environment (IDE)
with snap-style receptacles for biomedical sensor pads. The latter are designed for STM32 microcontrollers. It provides a comprehen-
attached to the body to capture the ECG signals, which are then fed sive suite of tools for coding, debugging, and optimizing embed-
into the EXG!Monitor module for processing. It can be sourced from ded applications.
local retailers or here [5], for example. > Hexabitz Single-Lead, EXG Monitor Module Firmware: this
! firmware is essential for capturing high-quality biopotential
The programming and data transmission block, mainly made of the signals such as ECG. You can download it from its respective
STLINK-V3MODS Programmer (H40Rx), is illustrated in Figure 4 and GitHub page at![6].
shown in the mid-part of Figure!2. This block handles the program- > Application Code (main.c): the core functionality of this project
ming and debugging of the Hexabitz modules and is responsible for is implemented in the main.c file, written by me. This includes the
transmitting the processed ECG data to the monitoring system. initialization of peripherals, data processing, and communication
! routines. You can find the detailed code at![7].
The H40Rx is a stand-alone debugging and programming mini probe !
for STM32 microcontrollers (Hexabitz modules and other MCUs). It Writing Code with STM32CubeIDE Software
supports the Serial Wire Debugging (SWD) interface for the commu- 1) Download the latest version of STM32CubeIDE at![8].
nication with any STM32 microcontroller located on an application 2) Clone or download the firmware for the EXG Monitor Module. The
latest stable release is always on the master branch, at the bespoken
GitHub page![6].
!
The functionality of the project will be implemented in the main.c file
of the module firmware. Add your one-time initialization code at the
top of UserTask before the endless loop.
!
float Sample;
float ecgFilteredSample;
!
Add your recurring code inside the endless loop in UserTask. Ensure
that MCU periodically checks the ECG sample value and ECG filtered
sample value of the sensor, using the API.
!
ECG_Sample(& Sample, & ecgFilteredSample);
!
3) The module has several ports for communication with other modules.
In our case, we want to control the pins of one port independently.
Figure 4: Component and solder side view of the multipurpose STLINK- This can be accomplished by configuring the module port to function
V3MODS Programmer (H40Rx). (Source: https://hexabitz.com/product/ as a stand-alone port.
stlink-v3mods-programmer-h40rx-2/) !

76 March & April 2025 www.elektormagazine.com

 if(Sample > 2.2) {
HAL_GPIO_WritePin(GPIOD,GPIO_PIN_3, 1);!
HAL_Delay(50);
HAL_GPIO_WritePin(GPIOD,GPIO_PIN_3, 0);
}
!
The STM32CubeIDE debugging function can be used to monitor the
sample values.
!
Designing and Implementing the Dashboard
The screenshot of Figure 6 figures illustrates the overall flow design
in STM32CubeMonitor, which is based on the popular Node-RED
development tool. It shows how data are collected from the sensor,
processed, and finally displayed on the dashboard. This dashboard
Figure 5: Flow chart of the sampling sequence. provides a real-time interface for monitoring and visualizing sensor
data. Figure 7 shows the final layout of the dashboard, highlighting
various interactive elements like charts and buttons.
!
First, reduce the number of ports in the .h file. This can be achieved by The configuration of the nodes is another relevant step in the process.
replacing the original number of ports with one less, and comment- Figure 8 shows the configuration of the Acq IN node, which is respon-
ing out the last port along with its related USART port and UART Init sible for acquiring ECG data from the sensor, whilst Figure 9 details
prototype. For example, if the original number of ports is 6, it should the settings for the Acq OUT node. It plays a crucial role in transmit-
be reduced to 5 by commenting out ting the processed data to the subsequent nodes in the flow, enabling
//#define _P6, //#define _Usart6 1 and seamless data transfer and ensuring that the data is ready for further
//extern void MX_USART6_UART_Init(void); processing or visualization.
! !
Second, comment the MX_USART6_UART_Init() port inside the Figure 10 illustrates the configuration of the Clear Button node, which
Module_Peripheral_Init() function in the .c file, also comment- provides a user interface element to clear or reset the data displayed
ing this port inside the GetPort function. Now we can use the pins on the dashboard. This node enhances interactivity by allowing users
as GPIO (input/output).!In our case, to connect a buzzer. to manage and refresh the data views as needed.
! !
Figure 5 illustrates the flow chart of the sampling sequence. If the The chart configurations are illustrated in Figure 11. This node will be
ECG sampled value achieves the required condition, the buzzer is responsible for plotting the values of the sensor on the user interface.
turned on at a certain time. The Variables node will always contain ECG filtered sample variable,
!

Figure 6: The flow-

based, user-friendly
graphical interface of
STM32CubeMonitor,
showing the building
blocks of the design.

March & April 2025 77

Figure 7: The Node-RED
dashboard window,
showing real-time sensor
data.

Figure 8: Configuration of the Acq IN node. Figure 9: Settings for the Acq OUT node.

Figure 10: Configuration of the Clear Button node. Figure 11: The chart configuration window.

78 March & April 2025 www.elektormagazine.com

 Figure 13: Setup window for the Processing node.

To simulate the remote access on our dashboard, we can use the link
http://localhost:1880/. The dashboard can be controlled using any
browser, as shown in Figure 14.
Figure 12: Configuration settings for the Variables node. !
Hardware Setup
Figure 15 shows the wiring of the buzzer, that must be connected to
which will be plotted on a line chart as curves. Figure 12 details the P5 and GND pads. You can also solder it directly onto an Hexabitz
configuration settings for the Variables node, which holds the neces- Proto module.
sary variables for collecting and displaying ECG data. It ensures the !
correct variables are tracked and updated. You also need to connect the ST-Link (H40Rx Module) to the EXG
! module using SWD (Serial Wire Debugger), and supply the module with
In Figure 13, the settings of the Processing node are shown. We a 3.3!VDC source. The analog EXG module outputs can be checked
selected the filtered sensor readings without performing any additional with any oscilloscope.
processing, as the filtering is done within the sensor module itself. !
! Testing the System
To modify your layout, you need to click on the Dashboard menu, on The live testing of this system obviously implies the proper place-
the top-right side, select the layout and edit the layout; in theme, you ment of the electrodes on di"erent body parts. Figure 16 shows three
can change the background color, the buttons color, etc. di"erent options for the placement of LA, RA and LL electrodes: on
!

Figure 14: Simulation of

remote access through
http://localhost:1880/.

March & April 2025 79

Figure 15: Buzzer
connections to the EXG
Monitor.

check is an advisable procedure to assess the correct operation of

1 2 3 the whole design. To this extent, you may use a known signal source
from a reference ECG generator or, as an alternative, the output of any
LL ECG pulses emulator, like the one described in this Elektor project [12].
RA LA !
RA LA
Connect the chosen signal generator to the analog input of the ECG
LL
RA LA monitoring system. Although — on our Hexabitz module — o"set and
gain are fixed, this check will show us that the system is operating
correctly. During testing, monitor the output closely, and compare it
with standard ECG readings, to verify its consistency. Regularly check
LL connections and components to maintain system reliability.
!
Operating the ECG Graph Monitoring system is straightforward. Ensure
Figure 16: Examples of correct placement for LA, RA and LL electrodes. the electrodes are placed correctly on the subject to obtain clear signals.
Practical tips include keeping the system away from electronic inter-
ference and ensuring the subject remains still during measurements.
chest, wrists and limbs. Figure 17 illustrates the correct placement My experience with this project has been rewarding, as it provides
of the RA electrode on the right wrist, whist in the background the real-time heart monitoring, which is invaluable for early detection of
actual ECG trace is displayed on the screen. Figure 18 shows one of cardiac issues.
the final phases of dashboard testing, with all the involved hardware !
visible on the right. Future Developments
! Here are some potential future developments for this project, that could
General Hints make the system even more versatile and beneficial for the users:
Building the ECG Graph Monitoring system involves several key steps. !
First, ensure all components are correctly connected according to the > Enhanced Data Analysis, implementing advanced algorithms for
schematic; then, test your system. Performing an overall functionality more accurate and detailed analysis of ECG data.

Figure 17: The RA electrode in place, with a “live” signal acquisition visible in Figure 18: Final phases of dashboard testing. The involved hardware is
the background. shown on the right.

80 March & April 2025 www.elektormagazine.com

> Wireless Connectivity, adding Bluetooth or Wi-Fi capabilities for About the Author
seamless data transfer to mobile devices or cloud storage. After her bachelor’s degree in 2009 and a master’s degree in 2015,
> Integration with mobile App, allowing integration with monitoring Aula Jazmati obtained a PhD in Electronic Engineering in 2023.
apps for comprehensive health tracking. Since 2010, she has been working at the Advanced Electronic
> Multi-Lead ECG Monitoring, expanding the system to support Systems Laboratory. In her spare time, she has been volun-
multi-lead ECG monitoring for more comprehensive heart health teering with the translation team at Raspberry Pi since 2016.
analysis. Additionally, since 2019, Aula has served as an ambassador for
> Portable Device Design, developing a portable ECG monitoring the Hexabitz firmware team. You can find more of her projects at
device with a rechargeable battery. The device will use the LiPo www.hackster.io/aula-jazmati and!https://github.com/aula9.
Charger with USB-C for e"icient charging.
240142-01

Related Product
Questions or Comments?
Do you have technical questions or comments about his article? > M. Pakdel, Advanced Programming with STM32
Microcontrollers (Elektor, 2020)
You may contact the author at aulajazmati7@hotmail.com or the
www.elektor.com/19520
editorial team of Elektor at editor@elektor.com.

WEB LINKS
[1] Wiki page for Electrocardiography: https://en.wikipedia.org/wiki/Electrocardiography
[2] EXG Monitor Module YT introductory video - Part 1: https://tinyurl.com/yc9hmmpf
[3] EXG Monitor Module YT introductory video - Part 2: https://tinyurl.com/48dx894h
[4] Hexabitz Single-Lead, EXG Monitor Module webpage: https://tinyurl.com/5b6a97dz
[5] BCRobotics sensor cable: https://tinyurl.com/tukpw7vb
[6] Hexabitz Single-Lead, EXG Monitor Module Firmware: https://tinyurl.com/4s9vdj7n
[7] Code for this project (GitHub): https://tinyurl.com/y6sumenz
[8] STM32CubeIDE download: https://www.st.com/en/development-tools/stm32cubeide.html
[9] How-To write code with STM32CubeIDE: https://tinyurl.com/2vujcv29
[10] How-To control ports independently: https://tinyurl.com/rftuharu
[11] Build GUI using STM32CubeMonitor: https://tinyurl.com/2zcfhy5p
[12] J. Holzhauer, “ECG simulator,” Elektor 5/2000: https://tinyurl.com/4zaudfsd

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 BACKGROUND

The Battle
for AI at the Edge
By Stuart Cording (Germany)
can be built that recognizes the six peaks (P,
The news around AI mainly reports on the achievements of Q, R, S, T, and U), ECG anomalies, and deliv-
tools like ChatGPT and Midjourney — powerful, cloud-based ers the results typically required by a physi-
cian (Figure 1). This will range from heart
tools. But there are plenty of other non-cloud applications rate and regularity of the beat to deviation
where even a little intelligence can make a big difference. in the cardiac axis and other anomalies [2]
(Table 1).

Embedded systems have traditionally relied and then apply an ECG algorithm that is Such an AI model is also easier to modify
on procedural programming to solve their robust enough to respond to a wide range of when changes are made to the analog front
tasks, especially those constructed for differing and distorted pulse shapes, signal end, different use cases are needed, or newly
battery operation and using microcon- transitions, and amplitudes. discovered ECG signal classifications arise
trollers clocked at tens of megahertz and through research. And the demand on a
with limited memory. This restricts these On the software side, ECG samples are microcontroller is not exceptionally high,
devices to tasks that can be implemented collected, and then an algorithm is coded meaning a decent 32-bit device running at
by a series of decisions supported by an using procedural programming decisions. tens of MHz with a few hundred KB of flash
algorithm such as a fast-Fourier trans- These choose different detection algorithm and tens of KB SRAM can be used instead of
form or PID control loop. But many tasks options and approaches depending on the relying on cloud-based AI resources.
are simply a pattern-matching activity. And distortions detected. This can lead to a long
this is something that AI is really good at. list of di%cult-to-manage options. Research Into Tiny Machine
Learning
Applying AI to Everyday Medical The alternative approach is to use AI. As a result, plenty of research is going
Diagnostics Because AI algorithms are good at pattern on into AI at the tiny, non-cloud end of
Take, for example, an electrocardiogram matching, real ECG samples can be provided the user spectrum. The primary goals of
(ECG). Used to monitor the activity of the as training data. From this point, a model such research are to support privacy by
heart, these time-varying signals have an
amplitude of around 10 µV to 5 mV and
contain frequencies of around 0.05 to
35 Hz [1]. Such tiny signals are the first
R-R Interval
challenge. The next is that the electrodes
aren’t permanently fixed in place like a R R
sensor of an industrial system delivering
well-defined signals. They are temporarily
attached to the human body; even when a
T T
health professional performs this, there is P P
wide signal variation and noise. Further- U U
more, humans move continuously, which
causes deviations in the shape of signals.
Q S Q S
The typical approach to this signal detec-
tion challenge is to build a high-quality Figure 1: The key features of an electrocardiogram are labeled from P to U. The R-R Interval is the heart
analog front end, perform digital filtering, rate and normally lies between 0.6 and 1.2 seconds.

82 March & April 2025 www.elektormagazine.com

 Table 1: Selection of ECG features, their typical duration, and how any The German numbers above twenty take
anomalies may be interpreted. [1] the longest (except for the French in the 70s
and 90s), needing as much as twice as long
Feature Typical Duration Anomaly Interpretation as Mandarin to express a value.
R-R Interval 0.6 – 1.2 s Paroxysmal atrial fibrillation
Their research delivers an artificially
Congestive heart failure
generated, multilingual spoken number
P-R Interval 0.12 – 0.2 s Stroke dataset from four speakers consisting of
QRS Complex 0.06 – 0.1 s Ventricular enlargement 12,800 samples called SpokeN-100 [4]. They
Heart failure also propose using the E%cientNet convo-
Tachycardia lutional network that has a scaling architec-
ture that, essentially, scales uniformly with
Acute Coronary Syndrome
the size of the input data (Figure 2). This
T Wave 0.05 – 0.25 s Myocardial infarction has led to work on their EvoNAS algorithm
Pulmonary embolism [5] (End-to-end eVOlutionary Neural Archi-
tecture Search for microcontroller units)
running on an nRF52840 Arm Cortex-M4
device from Nordic Semiconductor. Current
processing data locally; keep latency low explores voice recognition for spoken results indicate an inference (word recogni-
by not communicating with cloud services, numbers. This is a task that needs to tion) time of 200 ms, a memory footprint of
which is essential for time-critical systems; function locally inside automotive telemat- ~800 kB at an energy consumption of 2 mJ.
reduce communication bandwidth by trans- ics systems or smartwatches. They note
mitting results, not the raw sensor data; and that most datasets used for training are AI Made for MCUs
often executing such tasks with minimal monolingual. Datasets are the initial Most AI ideas start on a PC, trained in the
energy expenditure, an important consid- challenge when developing machine learn- cloud, with significant amounts of train-
eration for battery-powered applications. ing models since, without some represen- ing data. Once they’ve achieved a certain
tative data in enough quantity, it is di%- level of maturity, the discussion of moving
Since such embedded systems sit where cult to train the model to attain the desired to an embedded platform starts. This can
the sensors are located and often directly accuracy. They also explain that simply be a significant shock to development
control actuators based upon the measure- combining the datasets isn’t enough to teams. Microcontrollers don’t have the
ments acquired at the farthest edge of a produce a multilingual number recogni- mature development environments used
network in industrial systems, automo- tion model. in MLOps (machine learning operations),
tive, or Internet of Things (IoT), this field as they are laid out to debug at register
is typically termed Edge AI. Further issues arise because the time level and require a lot of manual periph-
needed to express a number varies consid- eral configuration. And there typically isn’t
Organizations like the Edge AI Foundation erably between languages. Units and tens any support for Python, relying on C/C++
(formerly the tinyML Foundation) organize are short, with Mandarin being the shortest. as the programming language.
regular summits that provide researchers
and experts the opportunity to share their
learnings in this field. They’re supported by
a range of the industry’s key semiconductor
vendors and technology suppliers, such as
Qualcomm, STMicroelectronics, NXP, and 0
1
Arm, but also startups like Greenwaves and 2
3
single-board computing (SBC) suppliers like Waveform
4
5
Arduino.
97
How Many Did You Want? 98
99
Sifting through the presentations from the Deep Neural Network Prediction
EMEA Innovation Forum from June 2024, Probabilities
it’s clear that the focus is on the sub-field
of machine learning, as the name of the Spectrogram
foundation infers, which is AI applied to
a single and specific task. One paper from Figure 2: Speech algorithms typically turn audio into a visual image before presenting it to a deep
the Friedrich-Alexander-Universität [3] neural network for analysis.

March & April 2025 83

Tackling these challenges is Edge Impulse,
another sponsor of the Edge AI Foundation
and one of the most prominent players in
the Edge AI space. Their platform helps
engineers from all walks of life, from begin-
ners to machine learning practitioners,
streamline data acquisition, preprocess-
ing, and model optimization for embedded
devices.

According to Alessandro Grande, their Head

of Product, “the shift in mindset from cloud
to edge development” is most developers’
biggest challenge. “Instead of seemingly
endless cloud resources, you’re constrained
by limited device memory, tight power Figure 3: The Edge Impulse dashboard enables the ingestion of sensor data directly from your
budgets, and the need for real-time respon- microcontroller.
siveness. It’s a new paradigm with unique
challenges demanding a different approach
that requires embedded expertise.” are present, and an NVIDIA TAO image supplier of the GAP8 and GAP9 processors.
classification model is trained. The resul- The devices target low-power, battery-op-
Grande notes that there are major tant model can be tested in a smartphone’s erated applications like hearing aids that
challenges around “collecting and prepar- web browser before being deployed on a want to leverage neural networks to deliver
ing suitable data from edge devices for ML Raspberry Pi. Further optimization enables next-generation electronic products.
development. This is particularly di%cult the model to be shrunk, fitting into less than
when dealing with sensor data, as there is 250 kB of RAM and running at 10 frames- The GAP9 includes the hardware interfaces
often a lack of publicly available, labeled per-second on an Arm Cortex-M7-powered needed for audio (I2S) and video (MIPI and
datasets for modalities like accelerometer, Nicla Vision [7] microcontroller board. CPI) along with the traditional array of
sound, or vibration.” standard microcontroller peripherals. A
Hardware for Edge AI Smart Filter Unit (SFU) provides low-latency,
Getting Your Own Labeled Data Of course, the semiconductor indus- low-power audio stream processing and
To tackle this, an ingestion service is try is trying to ensure microcontrollers filtering (Figure 4). But it is the compute
provided. Even microcontrollers that are adapt to provide the processing perfor- performance that is fascinating, deliv-
connected to your PC can directly upload mance required for Edge AI applications ered by ten RISC-V cores and an AI accel-
raw data from attached sensors, provid- while retaining their reputation for low erator interfaced with a fabric controller
ing the starting point for model train- power. The Nicla Vision uses a standard that maintains the balance between power
ing (Figure 3). Data engineering is also STM32H747AI MCU from STMicroelectron- consumption, latency, flexibility, and ease
supported, helping to get your data classi- ics. In addition to the Cortex-M7 core, it also of use.
fied if this step hasn’t already been done. includes a Cortex-M4, which would proba-
GPT-4o can be integrated into a label- bly be dedicated to real-time control tasks Dr. Tinoosh Mohsenin provided the EMEA
ing block, allowing acquired data, such in this type of application. This leaves the Innovation Forum participants insights on
as images or video, to be given labels. Cortex-M7 core available for performance the capabilities of Greenwaves’ processors
Once complete, the classifications can be tasks, like running miniaturized machine when applied to Vision Language Models
reviewed for accuracy, deleting outliers that learning models. (VLMs). Such generative models take
would reduce the accuracy of the resultant image and text inputs and generate text
model. The PC industry quickly learned that more outputs. In cloud implementations, such
cores was the way to go once clock frequen- AI models work with billions of parameters
The simplicity with which complex vision cies alone couldn’t deliver more perfor- while examining images of disaster zones
AI tasks can be trained and trialed is impres- mance. So, is this the next development provided by satellite imagery.
sive. In one demonstration, Jan Jongboom, phase for MCUs?
CTO and co-founder, uploads a video The team’s research explores whether a
containing children’s toys lying on the Well, more cores alone in embedded camera-equipped drone kitted out with
floor in a typical family home [6]. A train- systems don’t help unless the power a compressed VLM could help rescuers
ing dataset is created using a simple GPT-4o consumption issue is addressed in parallel. answer questions such as “Is this area
prompt to classify video frames where toys This is the approach taken by Greenwaves, flooded,” “How many buildings are there,”

84 March & April 2025 www.elektormagazine.com

Figure 4: The Greenwaves GAP9 processor targets low-power applications in audio and video and features a total of 10 RISC-V cores. (Source: Greenwaves)

and “Is this road accessible?” (Figure 5). VLM is executed on an NVIDIA Jetson powerful Arduino, you’ll be eager to get
A baseline AI for this task requires over TX2 with its 256 Pascal GPUs, dual-core started. But clearly, the path from one to
81 MB of memory for the model and deliv- 64-bit Denver 2 cores, and quad-core the other requires a heap of skills, from
ers an accuracy of 81%. Their tiny version of Arm Cortex-A57, energy consumption was programming to data analysis.
this model for a microcontroller fits in just 5.6 J with an inference latency of 213 ms.
339 kB of memory, with a loss in accuracy The GAP8 achieved a latency of 56 ms while To make things easier, work is being under-
of just 1.5%. requiring just 200 mJ. taken on Automated Machine Learning, or
AutoML [9]. This provides processes and
This particular VLM leverages the capability Such developments open up a wealth of methods that make machine learning
of the GAP8 processor utilizing the cache opportunities in processing and power-con- more accessible to non-experts, improves
memory for double-buffering, DRAM strained systems like MCUs. algorithm e%ciency, and supports research-
attached via a DMA (direct memory access), ers. The reach of activities is enormous and
and the PULP-NN multicore comput- Improving Getting Started has led to tools like Auto-PyTorch that
ing neural network software library [8]. Now that you know that a billion-parameter optimize AI network architectures and
And the results are impressive. When the AI model can be squished into a reasonably training hyperparameters.

AutoML also appears in Microchip’s MPLAB

Machine Learning Development Suite
[10], helping developers tune algorithms
to reduce resource use while retaining the
achieved model accuracy.

How Will Edge AI Change MCU

Designs?
Microchip’s solution isn’t just for its 32-bit
devices. The 16-bit and 8-bit MCUs can also
be selected as targets for a machine-learn-
ing application. However, as we have
seen in the examples provided, hundreds
of kilobytes of memory are needed for
complex AI models, meaning the small
memory devices are only suited to the most
simple pattern-matching type tasks.
Figure 5: A microcontroller connected to a camera fitted to a drone can perform basic real-time image
analysis of a disaster area, answering human-generated questions. (Source: Adobe Stock/MariKa, AI What this means is that, as Edge AI grows
generated) in importance, we’ll see MCUs coming onto

March & April 2025 85

 About the Author
Stuart Cording is an engineer and journalist
with more than 25 years of experience in
the electronics industry. He specializes in
video content and is focused on technical
deep-dives and insight. This makes him
particularly interested in the technology
itself, how it fits into end applications, and
Figure 6: predictions on future advancements. You
Arm’s Ethos-U55 is can find many of his recent Elektor articles
a Neural Processing at www.elektormagazine.com/cording.
Unit (NPU) designed
to operate alongside
its range of Cortex-M
processors typically Questions or Comments?
found in microcontrollers. If you have questions about this article, feel
(Source: Arm) free to email the Elektor editorial team at
editor@elektor.com.

the market with more flash and RAM, and Processing Unit (NPU), which is available in
potentially interfaces for external memory the Alif Semiconductor Ensemble E5 [12]
that provide the space for applications and E7 [13] families alongside Cortex-M55
Related Product
where integrating internal memory is no and Cortex-M32 processors (Figure 6).
longer business viable. > D. Situnayake and J. Plunket,
Of course, as always, engineers will AI at the Edge (O’Reilly)
Heterogeneous multicore processing, which ultimately decide which architectures and www.elektor.com/20465
uses several cores of different architectures, approaches are preferred. Referring back
will also be more common. Both Arm and to Alessandro Grande from Edge Impulse:
RISC-V are the key technology providers “Ultimately, the optimal choice between
here. However, there is growing interest in a dedicated accelerator, a basic core, or a
AI accelerators, processors with an archi- hybrid solution will depend on the specific
tecture well suited to the convolution and needs of each application, balancing perfor-
matrix calculations used by AI algorithms. mance, power e%ciency, and cost consid-
Arm already offers its Ethos-U55 [11] Neural erations.”
240687-01

WEB LINKS
[1] Xie L, Li Z, Zhou Y, He Y, Zhu J., “Computational Diagnostic Techniques for Electrocardiogram Signal Analysis,” National Library of
Medicine, Nov 2020: https://pmc.ncbi.nlm.nih.gov/articles/PMC7664289/
[2] Dr M. Jackson, “How to Read an ECG,” Geeky Medics, Nov 2024: https://geekymedics.com/how-to-read-an-ecg/
[3] R. Groh, N. Goes, A. M. Kist, “SpokeN-100,” Presentation: https://cms.tinyml.org/wp-content/uploads/summit2024/Rene-Groh.pdf
[4] R. Groh, N. Goes, A. M. Kist, “SpokeN-100,” Zenodo, March 2024: https://zenodo.org/records/10810044
[5] R. Groh, A. M. Kist, “End-to-end evolutionary neural architecture search for microcontroller units,” tinyML:
https://tinyurl.com/EvoNAS-algorithm
[6] Edge Impulse, “Label image data using GPT-4o”: https://tinyurl.com/label-image-data-gpt-4o
[7] Arduino Nicla Vision: https://store.arduino.cc/products/nicla-vision
[8] PULP-NN library [GitHub]: https://github.com/pulp-platform/pulp-nn
[9] AutoML: https://www.automl.org/automl/
[10] Microchip, “MPLAB Machine Learning Development Suite”: https://tinyurl.com/MPLAB-Microchip
[11] Ethos-U55: https://developer.arm.com/Processors/Ethos-U55
[12] Ensemble E5 Series from Alif Semiconductor: https://alifsemi.com/ensemble-e5-series/
[13] Ensemble E7 Series from Alif Semiconductor: https://alifsemi.com/ensemble-e7-series/

86 March & April 2025 www.elektormagazine.com

 NEWS

HaLow Hits Record

16-km Wi-Fi Distance
at 900 MHz
By Nick Flaherty (eeNews Europe)

Morse Micro has achieved a record 16-km distance for a Wi-Fi HaLow link at 900 MHz.

The tests of Wi-Fi HaLow at the rural Joshua Tree National Park in the In theory, Morse expected a link at a sensitivity of -95 dBm, which
US covered 16 km [1], up from the 3 km shown in January in an urban provides a throughput of 4.5 Mbit/s or a UDP MAC throughput of
environment. HaLow is a variant of the Wi-Fi standard designed for 4 Mbit/s. The tests at the Joshua Tree National Park achieved a stable
lower data rates and frequencies for the Internet of Things and the connection of 2 Mbit/s UDP throughput at 15.9 km.
Morse tests achieved a data rate of 2 Mbit/s. 240734-01

The tests used an evaluation kit as an access point (AP) at the edge Editor’s Note: Nick Flaherty Joosting first reported on this in eeNews
of a quiet rural valley. The off-the-shelf MM6108-EKH01 evaluation kit Europe, a publication in the Elektor network.
is based around a Raspberry Pi 4 with the Morse MM6108-MF08651 www.eenewseurope.com/en/domain/eenews-embedded/
Wi-Fi HaLow reference module.

The evaluation kit outputs 21 dBm (125 mW) through a standard 1 dBi
low-gain dipole antenna, resulting in a total radiated power of 22 dBm
without tweaking the 802.11ah parameters to increase the range or
using high-gain directional antennas.

The Morse Micro [2] chips adhere to the 802.11ah standard, which
specifies a slot time of 52 µs. Morse Micro’s implementation allows
for a maximum time of flight of 53 µs to allow for slight variations
between devices. This results in a theoretical maximum range of 15.9 km
(approximately 10 miles).

WEB LINKS
[1] Wi-Fi HaLow delivers throughput at 16 km range: https://youtu.be/fBMgZah2Z7g
[2] Morse Micro: https://morsemicro.com

March & April 2025 87

 NEWS

Source: Adobe Stock

First CHERI RISC-V
Embedded Chip and
Early Access Programme
By Nick Flaherty (eeNews Europe) The CHERIoT technology uses a hardware architecture that avoids
memory safety issues. As well as developing its own devices, the
SCI Semiconductor in Cambridge has company is supplying IP to a tier-one supplier for a system-on-
developed the first CHERI-enabled chip (SoC) design.

family of chips for embedded designs. “We are riding both horses at the moment as the primary goal is
The ICENI microcontroller chips are a device maker as the biggest challenge is being able to buy the
based on the RISC-V RV32E architecture technology for automotive, smart energy, and telecoms. We have
a design that is qualified for extended temperature operation and
and use the Microsoft CHERIoT-Ibex we have partners looking at after-market telematics applications.
processor core. The chips are built Moving to autonomous vehicles [1] means more communications
by GlobalFoundries and are aimed at and that increases the attack surfaces,” he said.

a wide variety of applications, from Over 70% of modern software vulnerabilities are based on these
simple microcontrollers to advanced memory safety software issues, creating the explosion of cyber-se-
microprocessor applications, with curity attacks taking advantage of memory misconfiguration and
software-reuse issues to rapidly escalate attacks and are endemic
availability in 2025. in modern code bases globally.

The ICENI family of microprocessors from SCI Semiconductor use

The first device is a single-core microcontroller but the company the 32-bit CHERIoT-Ibex RISC-V core for the world’s first high-integ-
is planning multicore and has designed an extended temperature rity intrinsically-Memory Safe devices. The device’s architecture,
version with a view to the automotive market, Haydn Povey, Chief integrating fine-grained hardware-enforced compartmentalisation,
Executive, SCI Semiconductor tells eeNews Europe. supports complete spatial and temporal memory safety.

88 March & April 2025 www.elektormagazine.com

 The CHERIoT technology uses a hardware architecture
that avoids memory safety issues.

This supports existing code with a compilation without rewriting making its way into production silicon. This is one of the main
the C code, and has an overhead of 1 to 3%, says David Chisnall, reasons why Microsoft developed and open-sourced the CHERIoT
co-founder of SCI Semiconductor and Director of Systems Ibex core,” said David Weston, VP of Enterprise and OS Security
Architecture. at Microsoft.

“Everything on the market is embarrassing,” said Chisnall at the SCI has also launched an Early Access Program, which will enable
High Integrity Systems Conference yesterday. “You are trying to selected customers and partners early access to silicon devices,
replace appliances that people expect to last ten years but compa- alongside advanced development systems. These systems use
nies think three years is long-term support and they are building the lowRISC FPGA Sonata platform [3] enabled by the UKRI Digital
these in an incredibly cost-sensitive environment so the hardware Security by Design programme.
is not able to support the features that we rely on for security. So
we looked at designing the hardware and software stack from the Selected partners can start development immediately on the EAC
ground up with all the things we have learned since the 1960s.” program with rapid portability to silicon devices in 2025, accel-
erating to transition to next-generation Memory Safe systems.
“We have a production quality core, and an open source core is
great with an FGPA dev system but if you actually want to deploy SCI Semiconductors has also signed a strategic distribution deal
this in production you just want to buy a chip and that’s what we with EPS Global, which also handles IC Programming and Embed-
are doing at SCI Semiconductor,” he added. ded Security for automotive Tier One suppliers and contract
manufacturers.
“The ICENI family marks the start of a new epoch of secured devices,
secured applications, and secured society,” said Povey. “The modern “SCI’s value proposition is compelling, and they’re ahead of the
cyber-security industry is focused on treating the technological market in terms of delivery,” said Colin Lynch, CEO at EPS Global.
symptoms of poor hardware and software architecture, with CHERI “They are providing key security chips that meet customers’ needs
and the new ICENI device family, we can now finally start to treat the for secure-by-design solutions. The key markets are infrastructure,
disease, enabling rapid code reuse without importing vulnerabili- defense, automotive, and aerospace. EPS Global can add significant
ties, accelerating development and reducing update requirements.” value in this space through our customer engagement, distribution
expertise, and secure provisioning capabilities.”
The ICENI family of devices uses the open-source CHERIoT
Platform [2] originally developed by Microsoft Research and now SCI Semiconductors is a founder member of the CHERI Alliance,
maintained as a cross-vendor open-source project, with Microsoft and was formed to lead the commercialisation of CHERI technolo-
and SCI Semiconductor as co-owners of the repository, along with gies, which took on the SDK developed by Codasip in Germany for
contributions from Google and rapidly evolving host of ecosys- CHERI RISC-V cores for SoCs and automotive designs.
tem partners including open source hardware developer lowRISC. 240727-01

“Microsoft is pleased to see that the open-source CHERIoT Ibex

core is being used by SCI Semiconductor in an upcoming silicon Editor’s Note: Nick Flaherty first reported on this in eeNews Europe,
product. We believe that CHERI is a promising technology that can a publication in the Elektor network.
be used to enhance computer security, and we are happy to see it www.eenewseurope.com/en/domain/eenews-embedded/

WEB LINKS
[1] N. Flaherty, “£2.2m for CHERI automotive, embedded security projects,” eeNews, 2023:
https://www.eenewseurope.com/en/2-2m-for-cheri-automotive-embedded-security-projects/
[2] CHERIoT Platform: https://cheriot.org
[3] N. Flaherty, “CHERI moves into RISC-V, x86 for embedded,” eeNews, 2024:
https://www.eenewseurope.com/en/cheri-moves-into-risc-v-x86-for-embedded/

March & April 2025 89

 NEWS

Source: Adobe Stock

Third-Generation
Wildfire Detection
Uses Satellite Links
By Nick Flaherty (eeNews Europe) adds an extra layer of redundancy resulting in unpar-
alleled network reliability, enabling fallback to satellite
Dryad Networks in Germany has connectivity in case of a loss of terrestrial connectivity.
launched its third-generation
Other enhancements include improved reliability and
Silvanet border and mesh gateways extended network coverage, making the third-gener-
for early wildfire detection and ation gateways ideal for large-scale deployments in
forest management via satellite challenging environments with maintenance-free
operation of 10 to 15 years.
links.
The Silvanet Border Gateway is placed at the
border of a target forest area, and the Silvanet
The Silvanet gateways developed by Dryad [1] include Mesh Gateway extends network coverage into the
direct-to-satellite connectivity via EchoStar for the depth of the forest using a unique multi-hop mesh
first time and extended LoRa radio range, as discussed networking architecture. The gateways are the core of
in eeNews Europe in June [2]. A new mounting bracket Dryad Networks’ Silvanet Software Suite for wildfire
and ruggedized, weather-resistant design with an detection and forest management, providing a robust
IP67 waterproof rating eases forest deployment. communications network for the Silvanet Wildfire
Sensors and additional sensors currently under
The satellite connectivity in the third-generation development.
gateway reduces reliance on terrestrial networks, offer-
ing real-time monitoring and bi-directional communi- The built-in satellite communication in North
cation, including remote configuration and firmware America and Europe comes from EchoStar and also
updates. By including direct-to-satellite connectivity in provides redundancy to 4G network communication, if
mesh gateways in addition to border gateways, Dryad gateways cannot connect over 4G. A built-in embedded

90 March & April 2025 www.elektormagazine.com

SIM card (NB-IOT / LTE-M) with multi-IMSI provides reliability, network performance, coverage, and ease of
global out-of-the-box mobile network connectivity use. The upgrades re%ect our commitment to contin-
and there is an easily accessible, user-serviceable uously advancing our technology to meet the evolv-
SIM card slot enables the replacement of the built-in ing needs of our partners and end users,” said Carsten
embedded SIM card with a local SIM for optimized Brinkschulte, CEO of Dryad Networks.
local connectivity.
“The introduction of direct-to-satellite connectivity
Extended LoRaWAN (long-range wide area network) and extended LoRa range in our new gateways marks a
range enables the third-generation gateways to pivotal advancement in wildfire detection technology.
communicate over longer distances, up to 10 km These features ensure that even the most remote and
(6 miles), reducing the number of gateways required challenging environments can be monitored in real
per deployment. time, without reliance on terrestrial networks. This
technological breakthrough sets a new standard in
The third-generation border gateways include two the industry,” said Dryad Networks Chief Technology
solar panels, doubling the energy available and Officer Pedro Silva.
adding thirty percent more energy storage than the
second-generation gateways: An increased number The third-generation gateways can be installed 50%
of supercapacitors in the third-generation gateways faster than second-generation gateways, due to a new
provides more energy storage in the solar-powered mounting bracket and locking system which is used to
gateways and helps ensure continual operation, attach the gateways to trees or poles. This solution is
especially in difficult lighting conditions and shaded substantially faster and easier to install and improves
environments. radio connectivity.

A fully integrated PCB (printed circuit board) antenna Built-in near-field communication (NFC) interface
design with no external antennas improves reliability provides local configuration and testing. This is
and eliminates a weak point of other gateway designs especially helpful in areas where there is no commu-
and there is a single rigid-%ex PCB for maximum nication infrastructure that may prevent or impede
durability: The advanced rigid-%ex PCB design elimi- installation or maintenance communication between
nates any internal connectors and cables, further a gateway and the Silvanet Cloud Platform. Techni-
improving reliability and longevity of the devices in cians can access the gateway configuration and testing
challenging environmental conditions. controls at the gateway site with an NFC-enabled
device such as a smartphone, with no need to scan
“At Dryad Networks, our mission is to protect QR codes during installation and maintenance.
the world’s forests by developing innovative and 240729-01
scalable solutions for wildfire detection and forest
management. Our third-generation Silvanet border Editor’s Note: Nick Flaherty first reported on this in
and mesh gateways represent a significant leap eeNews Europe, a publication in the Elektor network.
forward in achieving this goal, offering unmatched www.eenewseurope.com/en/domain/eenews-embedded/

The introduction of direct-to-satellite connectivity and

extended LoRa range in our new gateways marks a pivotal
advancement in wildfire detection technology.

WEB LINKS
[1] Dryad Networks: https://dryad.net
[2] “Satellite connection for solar-powered forest wildfire sensor network,” eeNews June 2024:
https://eenewseurope.com/en/satellite-connection-for-solar-powered-forest-wildfire-sensor-network

March & April 2025 91

developer’s zone
Tips & Tricks, Best Practices and
Other Useful Information

From Life’s
Experience
Figure 1: Plenty… (Source: Adobe Stock / nonnie192).

And when we finally make a choice, doubt

strikes us mercilessly. Did we make the right
Choice Overload choice, or were there better options? Regret
over our choice soon lurks, and in time we
begin to search everywhere for the best
option compulsively. There is an acronym
By Ilse Joostens (Belgium) for this too, FOBO or Fear of Better Options.
Actually, we all unconsciously become “The
We live in interesting times, and I am not talking about very hungry caterpillar” [2], we are never
geopolitical tensions in the world or crises, but the fact satisfied and constantly looking for more
and better, a time-consuming activity that
that we live in an era of unprecedented technological gives a permanently unsatisfied feeling.
growth and societal social change. Our poor brains get
a huge amount of information and stimuli to process Enough whining; after all, this is not a
psychology magazine. Recently, I was going
every day, and it gets a little more every year. through the fifth edition of the 1988 book
A person would get stressed for less. Even to make 300 Schakelingen (300 Circuits, in Dutch).
trivial everyday choices these days, you have to slog
through such an abundance of choices and information
every time that you end up with stress to making a
decision [1].

In my local supermarket, you will find TUN, TUP and DUS

no less than 14 different types of table However, we do not become happier from Source: Adobe Stock / Ivan.

salt. Trivial as it gets, I almost dare not to these endless choices. We’d love to try
mention the number of different types of everything, but we can’t, and out of helpless-
butter and margarine (Figure 1). Even ness and the flood of information we have to
worse with all the apps that every supermar- wade through, we don’t really know what to
ket offers these days, discounts and other choose anymore. The result is an unfulfilled
promotions, some time pressure, and you’ll feeling, the gnawing subcutaneous fear of
feel like your brain is about to burst out of having overlooked something important,
your head while shopping. FOMO, an acronym for Fear of Missing Out. Source: Adobe Stock / Avi.

92 March & April 2025 www.elektormagazine.com

Many designs in the book can be rebuilt tion, you order just in time, stressed out. sion that I am keeping up with my field,
with standard components that every- Afterwards, according to another, more but also because I just think it’s cool. Until
one still has lying around somewhere, general document from the manufacturer, I bang my head against the wall, of course.
called TUN (Transistor Universal NPN), the difference turns out to be something
TUP (Transistor Universal PNP) and DUS obscure such as packaging or the coating For example, in a circuit, I needed multiple
(Diode Universal Silicon) in the book. The of the IC’s pins. current sources, the type you can discretely
huge difference with ordering online from build with a transistor, some resistors, and a
a major electronics distributor could not Even equivalent components with varying few diodes. Something like that also exists
be greater. For something as simple as prices always make me despair. The differ- in an integrated SOT353 package [4], so I
an E12 series resistor, you already have ences can be great, and then you wonder selected that. During the global shortages
dozens to hundreds of options per value if the more expensive ones are better or of parts some time ago, this component was
and a choice of multiple manufactur- if you are paying for a brand name. And no longer available and also not replaceable
ers. For single N-channel MOSFETs, it’s what about the so-called “white products” of with a pin-to-pin equivalent. Then I had to
already over 10,000 references, albeit in electronics? So the house brands of certain modify the design and just build everything
various packages and with overlapping distributors are reviled by some or praised with discrete components. The same with
type numbers from different semiconduc- by others. Good or not, who’s to say? a modern DC/DC step-down module in an
tor manufacturers. In any case, there are LGA package barely nine by nine millime-
still countless references, and the fact that Brand-New Components ters and less than three millimeters high.
new and better types are constantly coming With each new version of a programming When they were finally available again, the
onto the market makes the list even longer. language, programmers tend to use the new manufacturer’s representative wanted to
Fortunately, parametric searching usually syntax and language elements immedi- point me in the direction of the successor.
allows you to reduce the number of types ately within their projects. Similarly, I am Things can move that fast, and perhaps the
to a more manageable list [3]. tempted every time to use the latest compo- slightly older but familiar components are
nents because it not only gives the impres- not so bad after all.
Even worse is when a part is out of stock, Translated by Hans Adams — 240710-01
and you have to find an alternative part
or also consider non-technical matters
such as price, tiered pricing, availability,
discount and other promotions, backorders,
commercial sensitivities or even aesthetic
considerations. Then you have already
passed an entire order through the website
and not kept track of time. Suddenly, you
have only 10 minutes left to complete your
order for delivery the next business day and
need to order some more ICs. It turns out
that the IC you typically order is out of stock,
but you find that the IC in question, albeit
with a different suffix after the type number
and a different price, is still available. The
housing is the same, but what on earth is
the difference? Then quickly click open
the datasheet and nervously start reading
diagonally as the clock ticks relentlessly
on (Figure 2). In the absence of informa- Figure 2: Ordering stress… (Source: Adobe Stock / Sergey Nivers).

WEB LINKS
[1] insideBE: Choice Overload – How Having Too Many Options Can Shut Down Your Brain:
https://insidebe.com/articles/choice-overload/
[2] Wikipedia: The Very Hungry Caterpillar: https://en.wikipedia.org/wiki/The_Very_Hungry_Caterpillar
[3] Choosing MOSFETs / So Many Options! – Circuit Tips and Tricks (YouTube): https://youtu.be/f9Mgcf6EcTg
[4] PSSI2021SAY Constant current source in SOT353 package: https://www.nexperia.com/product/PSSI2021SAY

March & April 2025 93

 BASIC COURSE

Starting Out in
Electronics…
…Continues Filtering and Controls Tone

By Eric Bogers (Elektor)

In the previous installment, we

overwhelmed you with a lot of formulas
for calculating the various unity-gain
filters. However, that is by far not
the worst of it – after all, calculating
machines were invented exactly for this
Figure 1: Low-pass filter
purpose. In order to obtain the desired with equal resistors and
filter characteristic, resistor or capacitor capacitors.

values with “awkward” values are

often required. This brings into doubt With R2 and R3 the gain of the opamp is set to a value greater
whether the theoretical performance of than one. With this design all popular filter characteristics can
be realized. If the overall gain is greater than 3, then the circuit
the filter can actually be realized. In this will become an oscillator. Even with a gain between two and three
installment, we will try to do something the circuit already has a tendency to overshoot and exhibit under-
about that. damped behavior.

The gain of an operational amplifier follows the by now familiar

formula for the non-inverting amplifier:
Filters With More Than Unity Gain
The circuits that we discussed in the previous installment [1] all
share the significant disadvantage that they require either resistors
(in the high-pass filters) or capacitors (low-pass filters) that have
widely varying and, additionally, unusual values. In the typical For the different filter characteristics, the factors and values from
cross-over filters that are used in stage sound installations — read: Table 1 need to be used.
fourth-order Linkwitz-Riley filters — the ratio of the component
values is one to two. Although this double value is easily obtained
Table 1: Gain factors/resistor values.
with components connected in either series or parallel it is never-
theless inconvenient because precision capacitors are expensive,
and therefore we would like to use as few of them as possible. Filter characteristic Gain R2 (R3 = 10 kΩ)
Linkwitz-Riley 1 0
It becomes even more of a challenge when the cross-over frequency Bessel 1.268 2.68 kΩ
has to be adjustable: a further complication is the stereo potentiom- Butterworth 1.586 5.86 kΩ
eter, which can be very difficult to obtain. To avoid these problems
Chebychev 3 dB 2.234 12.34 kΩ
it is possible to use a filter where all the frequency-determining
components have the same value — see Figure 1. Oscillator 3 20 kΩ

94 March & April 2025 www.elektormagazine.com

 Figure 2: High-pass filter
with equal capacitors
and resistors.

In the final column you can read the value of R2 that you have to
select when R3 has a value of 10 kΩ.

A high-pass filter looks exactly the same — except all the resistors
and capacitors have swapped places (Figure 2). Figure 3 shows
the characteristics of the four filter types mentioned in the table.
Figure 4 shows the same characteristics, but here we have made Figure 3: Frequency characteristics.
the different gains equal by using a voltage divider at the input.

The formulas below only apply to Butterworth (–3 dB) and

Linkwitz-Riley (–6 dB) filters:

To make a 24 dB/octave Linkwitz-Riley filter, we can simply connect

two second-order Butterworth filters in series.

From the frequency characteristics of Figure 3 and Figure 4, it is

very clear that the gain of the Chebychev filter around the transi-
tion region is greater than the gain in the pass-band. The unavoid-
Figure 4: The same frequency characteristics, but now with equal gain in
able consequence is that the filter exhibits ringing behavior, as is the pass band.
shown in the waterfall chart in Figure 5. By the way, a waterfall
chart is simply a series of frequency charts that show the behavior
of the filter as a function of time; not that you need to remember
that. Along the horizontal axis we see as usual the frequency, along
the vertical axis the attenuation and diagonally on the right is the
time, increasing towards the front. This goes hand in hand with
a deterioration of the impulse behavior. This is why Chebychev
filters are almost never used in audio applications.

Band-Pass Filters
Band-pass filters are generally made by connecting a high-pass
filter and a low-pass filter (with the appropriate transition frequen-
cies) in series. With these it is perfectly okay to combine filters that
have different orders or are not of the same type.

Tone Control
We usually speak of a tone control when there are no more than four
controls (and therefore filters) available; with five or more filters
we speak of an equalizer. However, the basic operating principle is
the same for both. We make a distinction between nonparametric,
semi-parametric and parametric filters. Figure 5: Ringing of a 3-dB Chebychev filter.

March & April 2025 95

Figure 6: The high-pass filter.

Figure 8: The high tone filter.

The High-Tone Filter

This filter exhibits a shelving characteristic (Figure 7): from the
cross-over frequency until the end of the transfer range all frequen-
cies are amplified. Of note is the broad range of this filter.

The wiper of the potentiometer (see the schematic in Figure 8)

sits between the input and the output of the circuit and in this
way provides either gain or attenuation. Between the wiper of this
potentiometer and the inverting input of the opamp is the frequen-
cy-determining network, which is reminiscent of a Wien filter.

We will leave it here for the time being. In the next installment, we
will continue with this tone control.
Translated by Arthur de Beun — 240711-01

Editor’s note: This series of articles, “Starting Out in Electronics,” is

based on the book, Basiskurs Elektronik, by Michael Ebner, which
Figure 7: Frequency characteristic of the high tone filter. was published in German and Dutch by Elektor.

> With nonparametric filters only the gain can be adjusted Questions or Comments?
(where an attenuation is the same as a gain of less than one). If you have any technical questions regarding this article, contact
Nonparametric filters are found in “simple” tone controls and the Elektor editorial team at editor@elektor.com.
in graphic equalizers.
> With semi-parametric filters, the gain as well as the cross-
over frequency can be adjusted. Mixing panels in the medium
price range typically have two parametric intermediate filters
Related Product
combined with nonparametric high and low tone filters.
> With parametric filters, besides the gain and cross-over > B. Kainka, Basic Electronics for Beginners (Elektor, 2020)
frequency, the filter quality (Q-factor) is also adjustable. This Book: www.elektor.com/19212
latter parameter determines whether the filter operates over a Ebook: www.elektor.com/19213
narrow or a wide frequency band.

We will now look at a practical example, specifically the tone control

of the Mitec Event mixing panel (with thanks to Mr. Pape for permis-
sion to publish the relevant schematics). This tone control is a
typical example of a “middle-of-the-range” panel: two semi-para-
metric intermediate filters, nonparametric high and low tone filters
and a switchable high-pass filter.

The High-Pass Filter

The high-pass filter is the first element in the signal path, so we will
begin with that. This is a second-order, Linkwitz-Riley filter where
the cross-over frequency can be switched between about 10 Hz and WEB LINK
about 80 Hz (Figure 6). The purpose of the two 3.3-MΩ resistors [1] “Starting Out in Electronics…Filters Actively,” Elektor 1-2/2025:
is to ensure that there is no DC voltage across the 33-nF capacitors https://www.elektormagazine.com/magazine/240637-01
and so prevents spurious audible noise when switching on.

96 March & April 2025 www.elektormagazine.com

 ELEKTOR CLASSIC KIT

Quasi-Analog
Clockwork
A Remake of an Elektor Classic or la
b • Elek
kt t

or
Ele

lab
T E S T-
By Ton Giesberts (Elektor)
Ele

la b
or

k
Original Project by P. Hogenkamp or
t
la b
• E l e kt

Mechanical timepieces have always had a

certain appeal because of the beauty of the
analog dial and its convenience in reading,
despite their limitations in accuracy.
On the other hand, the digital models are
very accurate, but cold and impersonal.
Why, then, not combine the two
worlds as is done in this analog- > To make the circuit independent of the mains
frequency (50!Hz or 60!Hz), a separate reference
looking digital watch design? clock signal of 32.768!kHz is used instead of using
50!Hz only as was in the original 1995 design. A
higher divisor is needed for a 5-minute pulse, i.e.,
Digital watches with displays consisting of numbers 9,830,400 instead of 15,000, requiring an additional
only have lost much of their popularity over the last few counter/divider circuit.
years. They are now outnumbered by traditional dials with > 4000-logic CMOS ICs are no longer widely avail-
hour and minute hands actuated by a digitally controlled able, so their functionality is taken over by HCMOS
stepper motor. These watches (and clocks) are the best logic throughout the design (except a CD4060,
of both worlds because they have an analog readout with used for the reference clock). For example, the 4093
digital control. The LED clock described in this article is ICs have been replaced by 74HC132, the 4082 by
based on the same principle, only there are no moving 74HC21, and each 4067 by two 74HC4051s.
parts at all. > The supply voltage is reduced from 12!V to 5!V. The
! external transformer, bridge rectifier, smoothing
The dial is made of 144!×!3!mm!LEDs in a circle, showing capacitors and stabilizing network using a Zener
12!hours with a 5!minute resolution. In this new design, diode are no longer needed, avoiding the risk of
11 standard logic ICs are used, and all parts are through having the mains voltage in the circuit. Instead, any
hole. The power supply can be sourced from any 5!V!DC small 5!VDC mains adapter can be connected via a
mains adapter. small screw-terminal block on the board.
! > Various changes affect the current settings of the
This project is based on an article that is about 30 years LEDs. Apart from that, present-day LEDs have
old [1]. A kit is available at the Elektor shop [2]. much higher efficiency, so the LED currents can be
! kept really low.
Notes on the Remake > The actual PCB design is double-sided, avoiding a
A number of changes were made by the Elektor Lab mass of jumper wires.
Team to make this 30-year-old design compatible with > The blinking LED — rather than the power LED — is
components, insights and technologies available. placed in the center of the dial.
!

March & April 2025 97

 > Two transistors were added to increase the current power delivered to the crystal is well below the maximum
of the green LEDs lighting on the full hour — this is drive level of 1!µW (a more aggressive drive of this quartz
to compensate for their lower efficiency, compared would reduce its lifespan).
to the red LEDs. !
! The total divider for the 5-minute pulse is created in two
Circuit Description parts. The CT11 output of counter/divider IC1 (a CD4060
As anticipated, the quasi-analog clockwork uses 144 made by Texas Instruments, which also produced all the
LEDs to indicate the time on a round, quasi-analog dial other ICs used for this project) ticks at 8!Hz and clocks
with a diameter of about 143!mm. One of twelve green the second counter divider, IC11 (a 74HC4040). IC11 must
LEDs lights at maximum intensity to mark the hours, divide 8 Hz by 2400 to create a 1/300!Hz pulse rate (i.e.,
while the other eleven are dimmed. Between two green a 5-minute pulse).
LEDs sit 11!red LEDs, each of which represents a period !
of five minutes. In this way, the time is indicated with an A total divisor of 9,830,400 is achieved by detecting the
accuracy of five minutes. This would seem to be enough, binary code 2400 at the output of IC11 through IC2A. In
considering the mostly decorative function of the present numbers: 2400 = 211 + 28 +26 + 25. When the value of
clockwork. 2400 is reached, a CLK pulse is generated via R5, C1,
! IC3C, and IC3D, resetting IC11 (CT=0). The CLK pulse
The complete circuit diagram of the clockwork is given also increments the count of IC5 by!1 (see symbol
Figure 1: Schematic in Figure 1. The oscillator section of counter/divider IC1 CLK at pin 1). The other input of IC3D is connected
diagram of the Quasi is configured as a quartz oscillator with a 32.768!kHz to pushbutton S1, whose purpose is to adjust the time
Analog Clockwork. crystal. The high value of R21, 330!k%, ensures the total after power-on. The pulse supplied by the pushbutton

98 March & April 2025 www.elektormagazine.com

 Component List
Resistors
(body 2.5 × 6.8 mm)
R1, R22, R24 = 2.2 k%
R2 = 390 k%
R3, R5, R6, R7 = 82 k%
is debounced by network R3-R2-C2 and IC3D. Every R4 = 1 k%
time the button is pressed, the readout advances by R8-R19 = 8.2 k%
one LED position. R20 = 20 M%
! R21 = 330 k%
IC5, a 74HC4024 counter/divider, operates as a 5-minutes R23 = 560 %
counter and has 12 states, corresponding to 0, 5, 10, 15, R25 = 470 %
20, 25, 30, 35, 40, 45, 50 and 55 minutes. Its outputs R26 = 100 k%
determine which channel of multiplexers IC7 and IC9 !
(both 74HC4051) is actuated. The multiplexers’ COM!pins Capacitors
(pin!3) are connected. C1...C4, C8...C18 = 100 nF, 50 V, ceramic X7R, pitch 5 mm
! C5 =22 pF, 50 V, ceramic C0G/NP0, pitch 5 mm
For example, when all multiplexer SEL inputs and the C6 = 10 pF, 50 V, ceramic C0G/NP0, pitch 5 mm
active-low E (enable) pins (pin!11, 10, 9 and 6, respec- C7 = 3...10 pF trimmer, BFC280823109 Vishay/
tively) are held at!0, the anode terminals of the LEDs BC Components
connected to output A0 (D1, D13, D25, D37, D49, D61, !
D73, D85, D97, D109, D121 and D133) are connected to Semiconductors
the +5!V supply rail via a 2.2!k% resistor, R1. IC4A inverts D1, D13, D25, D37, D49, D61, D73,
the fourth bit of counter IC5 to enable IC9 when IC7 is D85, D97, D109, D121, D133 = LED, green, 3!mm
disabled and vice versa. D2…D12, D14…D24, D26…D36, D38…D48, D50…D60,
! D62…D72, D74…D84, D86…D96, D98…D108, D110…D120,
To make an LED light, however, its cathode must be D122…D132, D134…D144, D162, D163 = LED, red, 3mm
pulled to ground and that is done by multiplexers IC8 !
and IC10 (both 74HC4051), which have their COM pins Important: 3 mm round LED’s D1…D144 must have a
joined and tied to ground via R4 (1!k%). The binary pattern flat side, no ledge!
out of the counter/divider IC6 (74HC4024) is applied to !
the SEL and E inputs (IC8 and IC10, where IC4B has the D145…D156 = 1N4148, DO-35
same function as IC4A) and determines which LEDs D164 = 1N4004, DO-41
have their cathodes connected to ground through the T1, T2 = BC547B
MX0…MX11 signal lines. IC1 = CD4060, DIP-16
! IC2 = 74HC21, DIP-14
As soon as IC5 reaches state “12” (corresponding to IC3, IC4 = 74HC132, DIP-14
0!minutes), the counter is reset via IC4C and IC4D. Also, IC5, IC6 = 74HC4024, DIP-14
IC6 receives a clock pulse which marks the start of a new IC7…IC10 = 74HC4051, DIP-16
hour. Incrementing the count in IC6 results in the next IC11 = 74HC4040, DIP16
output of IC8 or IC10 becoming active. The multiplex- !
ers ensure that the cathodes of the selected LEDs are Miscellaneous
connected to R4. As soon as IC6 supplies the binary code K1 = 2-way PCB terminal block, 3.5!mm grid
“12”, a reset pulse is generated via IC3B, R7, C4 and IC3A. S1 = 6 mm tactile pushbutton
This pulse resets IC6 to state “0” enabling the counter to X1 = 32.768 kHz crystal, 20 ppm, Cload 12.5 pF,
start counting another 12 hours. 8 x 3 mm cylinder package (X32K768L104,
! AEL Crystals, pitch 1.1 mm)
As already mentioned, the display has 132 red and 12 Optional: DIP IC sockets, 14 contacts (IC2…IC6),
green LEDs. The green LEDs light continuously at low 16 contacts (IC1, IC7...IC11)
intensity, due to their cathodes connected to ground PCB 240118-1
via 8.2 k% resistors (R8…R19). Since the anodes of the
green LEDs are connected to R23, a constant current of
about 0.2!mA flows through each LED. At the full hour,
the relevant green LED must light at maximum intensity. connected to virtually +5!V through IC7 and R1. Due to
! buffer T1, the voltage drop across R1 is then only 0.1!V.
This increase in brightness is achieved by connecting R4 !
(via MX0…MX11) through a diode (D145…D156). This trick LED D162 lights as soon as the supply voltage is present.
explains why the LEDs connected to line A0 are wired The last LED of the project, D163, is located in the center
differently in the matrix. The current is also increased of the dial and flashes slowly at 0.5!Hz to indicate that
by connecting R25 in parallel with R4 via T2. R26 is the clock is “ticking.” The 5!V!DC supply voltage for the

March & April 2025 99

 clock is provided by an external mains adapter that is
connected to the screw-terminal block K1. D164, a 1N4004
diode, protects against accidental polarity reversals. The
current demand from the clock varies from 6 to 11!mA, so
the AC/DC adapter can be a low-power type.
!
Construction
The PCB — whose layout is available at the Elektor Labs
page for this article [3] — is doubled-sided and wire
jumpers aren’t necessary in this design. Special LEDs
are required for this clock, as can be seen in Figure 2,
which illustrates all the components included in the kit.
Because of the type of mounting intended, all dial LEDs
must be of the rimless type, in order to be mounted
adjacent to each other.
!
Mount these LEDs close to the board surface, to keep the
clockwork as flat as possible. Also use miniature ceramic
decoupling capacitors. If you are confident about your
soldering skills, you may fit the ICs without sockets. In

that case, take the necessary precautions against ESD
when soldering them. A fully detailed construction manual
Figure 2: for this kit is available for download at [4].
All the components !
needed for this project Figure!3 shows a front view of the fully populated PCB,
are included in the kit.
If you source them by
just after its first power-up. Maintaining Elektor’s tradi-
yourselves, keep in mind tion for all Elektor Classic kits, the silkscreen print within
to order rimless LEDs. the dial shows the complete circuit diagram, making this
special clock a collector’s item and an interior design
piece at the same time!
!
The finishing touches to the clock depend on your own
creativity. For instance, the dial may be covered by a
bezel, which partly obscures the components but leaves
the active LEDs clearly visible. Alternatively, a piece of
transparent acrylic panel leaves “the works” in sight.
And that, arguably, will be the best option for the true
electronics enthusiast.
!
32.768 kHz Reference Clock Testing
The clock should start to work the moment 5!VDC is
applied to K1 (read 32.768 kHz reference clock). Which
LED will light first is random and depends on the state of
counters IC5 and IC6 at power-up. The LED at the top is
green LED D1, indicating 12:00. Every time S1 is pressed,
the clock is advanced by five minutes.
!
While testing the standard quartz oscillator with a
74HC4060 and a 32.768!kHz crystal, the oscillator
▶ worked fine, but produced a wrong and too high random
Figure 3: Front view of
frequency. Adding a small low-pass filter (330!%/100!pF)
the completed PCB, just seemed to work. Anyhow, to be sure, a test was done
after the initial power-up. with nine different crystals from eight manufacturers.
One out of nine crystals didn’t work with the extra filter.
!

100 March & April 2025 www.elektormagazine.com

Testing the same oscillator circuit with a standard 4060, Questions or Comments?
from the 4000-logic series, the oscillator worked correctly Do you have technical questions or comments about
with all crystals. The HC-logic version apparently causes this article? You can write to the editorial team of
enough interference in the circuit of the oscillator, due to Elektor at editor@elektor.com.
its very high impedance, most likely caused by the higher
switching speed, even on a PCB with a ground plane.
And even when the frequency was almost correct, it
wasn’t as stable as is to be expected from a quartz oscil-
lator. Fortunately, the CD4060 is still widely available and About the Author
still manufactured. Ton Giesberts started working at
! Elektuur (now Elektor) after his studies,
A small capacitive trimmer (C7) was added to adjust the when we were looking for someone with
frequency to exactly 32,768.000!Hz, so the clock will show an affinity for audio. Over the years, he has worked
the correct time for a long while, despite the 5!minute mainly on audio projects. Analog design has always
resolution, of course. The frequency at pin 1 of IC1 is 8!Hz, been his preference. Of course, projects in other fields
and the oscillator frequency is divided by!212. On this pin, of electronics are also part of the job. One of Ton’s
a probe can be easily connected to measure its signal mottos is: “If you want to have it done better, do it
with a frequency counter. yourself.” For example, for a PCB design for an audio
! project with distortion figures on the order of 0.001%,
However, some readers have reported a bug that a a good layout is crucial!
32.768!kHz crystal oscillator with a 4060 was not start-
ing at power-up. I noticed this as well, at times; touch-
ing the crystal was enough to make the oscillator start.
Changing values didn’t help; replacing the crystal with
different types didn’t solve it either. Even stranger, adjust- Related Products
ing the frequency to a sharp 8!Hz makes it most likely a
permanent issue. > Elektor Quasi-Analog Clockwork Kit
www.elektor.com/20944
!
Observe if LED D163 is blinking at power-up. Tuning the > Joy-IT JDS6600
oscillator to a slightly deviating frequency can make the Signal Generator & Frequency Counter
oscillator start at power-up (but sometimes not). It’s up www.elektor.com/18714
to you if this is acceptable. Otherwise, simply touch the
crystal and the oscillator will start. After a power outage,
you will need to set the clock again anyway and then also
watch if D163!LED is blinking. Another way is to place the
crystal fully upright, this seems to solve it. So somehow
the parasitic capacitance between the crystal and the
ground plane is the culprit.
240118-01

WEB LINKS
[1] P. Hogenkamp, “Quasi-analogue clockwork,” Elektor 1/1995:
https://www.elektormagazine.com/magazine/elektor-199501/33259
[2] Elektor Store webpage for the clock:
https://www.elektor.com/products/elektor-quasi-analog-clockwork-kit
[3] Elektor Labs page for this project:
https://www.elektormagazine.com/labs/quasi-analog-clockwork-an-elektor-classic-a-remake
[4] Quasi-Analog Clockwork construction manual: https://tinyurl.com/34nuvjtb

March & April 2025 101

 PROJECT
ab • Elek
or l t
kt

or
Ele

lab
ORIGINAL

Ele

b
or

kt
or

la
la b
• Ele k t

A Modular Approach to
Sensor
Testing
The ESP32-S3-Based
Sensor Evaluation Board Figure 1: The Sensor
Evaluation Board in its
assembled state.

By Saad Imtiaz (Elektor)

The Sensor Evaluation Board was

created to solve the hassle of repeatedly again — think temperature, humidity, light, motion sensors and more.
These essential sensors form the building blocks for a range of appli-
swapping sensors during development. cations, from straightforward environmental monitors to sophisticated
Based on the ESP32-S3, it includes IoT devices. But as projects and applications grow, so does the need
two high-precision ADS1015 ADCs, for various setups, each requiring careful testing of both hardware and
software compatibility. The process of rewiring, rearranging setups,
Grove connectors, and modular edge and managing a cluttered workspace can quickly become tedious.
card slots. These features allow one
to effortlessly test and swap sensors, The idea of modular edge cards for each of these commonly used
sensors can be employed to tackle this issue. By simply plugging in an
addressing the ESP32’s ADC limitations edge card dedicated to a specific sensor, one can now swap sensors
and ensuring consistent, accurate effortlessly, with no wire clutter or reconfiguration required. This modular
data for a smoother, more efficient approach streamlines testing and keeps desk space optimized, allow-
ing multiple sensor setups to be tested on the same board seamlessly.
prototyping process. Integrated with high-precision external ADCs, the Sensor Evaluation
Board transforms the process, saving time and ensuring that every
setup can be tested with accuracy and ease. Whether one is involved
Before starting any project, we begin with an idea — a way to solve in environmental monitoring, IoT applications, or simply experimenting
a problem or improve an existing solution. Then comes the planning with sensor data, this board offers a seamless and structured approach
stage, where we identify what’s needed to bring that idea to life: the to transforming concepts into fully functional prototypes.
tools, equipment, and components that will make the project a reality.
For sensor-based projects, this can often mean repeatedly testing Design and Architecture
different sensors, swapping out hardware, and troubleshooting to get The schematic in Figure 2 outlines a design aimed at simplifying sensor
everything working just right. That’s where the Sensor Evaluation Board testing with the ESP32-S3 module as the central controller. The ESP32-S3
comes in (Figure 1). was chosen for its dual-core capabilities and strong support for Wi-Fi
and Bluetooth, making it suitable for IoT applications. Compared to
Designed to make sensor testing simpler and more efficient, the options like STM32, the ESP32 offers broader community support and
board allows developers to quickly change sensors, optimize code, simpler integration for Wi-Fi-focused projects. Moreover, integrating a
and troubleshoot without the usual hassle. In almost every embedded ESP32 WROOM Module is much easier in your projects as compared
systems project, there’s a core set of sensors we rely on time and time to other microcontrollers as the WROOM modules already have the

102 March & April 2025 www.elektormagazine.com

 +3V3 +3V3

K10
0 0 +5V 1
R7 R8 R11 R6 GND
0 0 2
B1 A12 VCC
GND GND D2 3
ADC2_2

10k
10k
10k
10k
D3 B140HW-7 4
K11 1 IC2 8 ADC2_1
ADDR VDD
B4 A9 1N5819HW-7-F +5V +3V3 2 4 IO
VBUS VBUS TLV75733PDBVR ALERT RDY AIN0
B5 A8 9 5 +3V3
CC2 SBU1 SDA AIN1
B6 A7 1 5 10 6
DP2 DN1 IN OUT SCL AIN2 K9
B7 A6 R4 3 7 1
DN2 DP1 R1 IC3 GND AIN3 GND
B8 A5 3 4 AD51515IDGS 2
SBU2 CC1 100k EN NC VCC

1k
B9 A4 +3V3 3
VBUS VBUS C2 C10 GND C6 ADC2_3
4
2 LED3 ADC2_4
R10 USB C R9
22µ 1µ 22µ 1 IC1 8 IO
B12 A1 10V 10V ADDR VDD
4k7

4k7

GND GND 2 4
ALERT RDY AIN0
0 0
9 5 +3V3 +5V
0 0 SDA AIN1
10 6 J2
SCL AIN2
3 7 1
GND AIN3
2
AD51515IDGS
J1 3
EN 1 2 4
UART_P 3 4 D0 5
+3V3 UART_N 5 6 6

+3V3 7
PROG 8
C1
9
R2 10
100n
1 40 11
10k

GND GND
2 39 12
3V3 IO2
3 38 13
EN IO2
SW1 4 37 14
C3 C4 IO4 TXD0
5 36 15
IO5 RXD0
6 35 16
EN
100n 100n IO6 MOD1 IO42
7 34 17
IO7 ESP32-S3-WROOM-1 IO41
8 33 18
IO15 IO40
9 32 19
IO16 IO39
10 31 20
IO17 IO38
11 30 21
IO18 IO37
12 29 22
IO8 IO36
13 28 23
IO19 IO35
14 27
IO10

IO12
IO13
IO14

24
IO11
IO46

IO21
IO47
IO48

IO20 IO0
IO9

IO3 IO45 SW2 25

+3V3 +5V 26
C7
15
16
17
18
19
20
21
22
23
24
25
26

27
100n

BOOT 28
D1 6 5 4 3 1
29
30

R3
MOSI

MISO

LED1
+3V3

SDA

SCK
CS4

CS3

CS2

CS1

SCL

SMF05C.TCT 2 1k

R5
LED2
1k

+3V3

+3V3 +3V3 +3V3 +3V3

K1 K2 K3 K4
1 2 1 2 1 2 1 2
3 4 SDA 3 4 SDA 3 4 SDA 3 4 SDA
5 6 SCL 5 6 SCL 5 6 SCL 5 6 SCL
CS2 7 8 CS2 7 8 CS2 7 8 CS2 7 8
CS3 9 10 CS3 9 10 CS3 9 10 CS3 9 10
11 12 CS1 11 12 CS1 11 12 CS1 11 12 CS1
13 14 MOSI 13 14 MOSI 13 14 MOSI 13 14 MOSI
15 16 SCK 15 16 SCK 15 16 SCK 15 16 SCK
17 18 MISO 17 18 MISO 17 18 MISO 17 18 MISO
CS4 19 20 CS4 19 20 CS4 19 20 CS4 19 20

K5 K6 K7 K8
1 1 1 1
GND +3V3 GND +3V3 GND +3V3 GND +3V3
2 2 2 2
VCC VCC VCC VCC
3 3 3 3
SDA SDA SDA SDA
4 4 4 4
SCL SCL SCL SCL
Qwiic IO IO IO 240472-001

Figure 2: Schematic diagram of the project.

March & April 2025 103

 Component List
Resistors
R1 = 100 kΩ
R2, R11, R6, R7, R8 = 10 kΩ
R3, R4, R5 = 100 Ω
R9, R10 = 4.7 kΩ

Capacitors
C1 = 100 nF, 50V
C2, C6 = 22 µF
C3, C4, C7 = 0.1 µF
C5, C8, C9, C10 = 0.01 µF

Semiconductors
D1 = SMF05C.TCT
D2 = 1N5819HW-7-F
D3 = B140HW-7
IC1, IC2 = ADS1015IDGS
IC3 = Regulator TLV75733PDBVR
LED1 = NCD0805A0 (Amber)
LED2 = NCD0805G1 (Green)
LED3 = NCD0805R1 (Red)
MOD1 = ESP32-S3-WROOM-1

Others
SW1, SW2 = Button SKRKAEE020
J1 = 2×3 Pin, 2.54 mm Vertical Header
J2 = 2×15 Pin, 2.54 mm Vertical Header Figure 3: PCB layout, highlighting the reference numbers for connectors
and component placement.
K1, K2, K3, K4 = 408-52020-000-11 (ept Card Edge Connectors)
K5 = Qwiic Connector
K6, K7, K8, K9, K10 = Grove Connectors
K11 = USB-C GSB1C41110SSHR One I2C interface of the ESP32 (GPIO8 = SDA) and GPIO9 = SCL) is
routed to the edge card receptables K1 to K4 and additionally to three
Grove connectors K6 to K8 and one Qwiic connector K5. Similarly, the
SPI communication interface is allocated as follows: SDI on GPIO11, SCK
antenna front end designed along with other core components to use on GPIO12, and SDO on GPIO13. These lines are also connected to the
with the MCU, which further decreases the number of components to edge card receptables; together with four CS (Chip Select) lines. This
make your prototype work. You can address to Figure 3 which shows enables simultaneous use of SPI sensors across the edge card connec-
the PCB layout of the board. tors without conflicts, enabling greater flexibility in sensor testing setups.

The board includes two ADS1015 ADCs (IC1 and IC2) to address As said, the four edge card connectors (K1...K4) enable straightforward
the limitations of the ESP32-S3’s internal ADCs. Both of them have sensor swapping without any rewiring. These connectors are EC.8 edge
four analog inputs (channels). The analog inputs of the first ADC are card SMT connectors from ept [3], which are indeed quite robust for
connected to 2.54-mm pitch header pins and the analog inputs of the this application; they support up to 28-Gbps data transmission and
second ADC to two Grove connectors (two channels each, together a current capacity of 3.2 A (specs well above what is required here).
with VCC and GND). The ADS1015 provides reliable 12-bit resolution However, their main advantage lies in their ease of use, allowing for
[1], which is adequate for most sensor tasks while remaining cost-ef- seamless, frequent sensor module changes in a testing environment.
fective. Although a higher-resolution ADC like the ADS1115 [2] was Compared to traditional pin headers, these edge connectors make it
considered, the ADS1015’s balance of performance (3300 Samples/s significantly easier to streamline testing setups, with a claimed 500
vs. 860 Samples/s) aligned better with the board’s purpose. However, insertion cycles that should hold up well over time.
one can use ADS1115 instead of the ADS1015 on the same PCB as
both of these ICs share the same pinouts and footprint. As you can Connector J1 is dedicated to programming the ESP32-S3 via UART,
see, the ADDR pin of one ADC is connected to GND, the other one providing a straightforward interface for uploading firmware and making
to VCC — which gives these chips different I2C addresses (more on initial configurations. However, one can also flash firmware via the USB
this can be found in the datasheet [1]). Type C Connection (K11) as well. J2, on the other hand, is a 2.54-mm
header that grants access to the remaining GPIO pins of the ESP32-S3
For status indication, the board features two LEDs (LED1 and LED2) and the first ADC (IC1). This additional access is valuable for connect-
connected to GPIO14 and GPIO21 of the ESP32-S3. These LEDs can be ing external modules or custom peripherals directly to the ESP32-S3,
configured for any application, such as displaying power status, commu- allowing flexibility for expanding the board’s functionality as needed
nication activity, or custom debugging signals during sensor testing. during development and testing.

104 March & April 2025 www.elektormagazine.com

 +3V3

R1 R2
6 8
J1

10k

10k
VIO VDD
1 2 2
CSB
3 4 SDA 3
SDI IC1 handling, and more. For the BME280, I relied on the Adafruit_BME280_
5 4 BME280
Library [7], which is well-known for its simplicity and ease of use.
6 SCL
SCK
7 8 5
SDO
9 10
JP1 GND GND
11 12
1 7 When designing the edge card modules, I selected the 02x10 Connector
13 14
15 16
ADD SEL
odd/even symbol in the schematic and used the Samtec_HSEC8:Sam-
17 18 tec_HSEC8-110-X-X-DV-BL_2x10_P0.8mm_Edge footprint from KiCAD’s
default library for the PCB layout. For the edge card connectors on
19 20

the Sensor Evaluation Board, I downloaded the footprint file directly

240472-005 from the manufacturer’s website and added it to my KiCAD library
using the Library Loader program [8].
Figure 4: Schematic diagram of BME280 Edge Card module, outlining its
pin configurations. Regarding the physical specifications, the EC.8 connectors used on the
board are designed to support 1.6-mm-thick PCBs. To ensure compat-
ibility, I specified a 1.6-mm PCB thickness when ordering the edge
As stated before, the Chip Select (CS) line poses a unique challenge, card modules from the PCB manufacturer.
as each sensor requires a dedicated CS pin when operating over SPI.
To accommodate this, four separate CS lines are available on the edge
card connectors, each with a unique GPIO assigned by the micro-
controller. While this solution meets the needs of the current design,
a multiplexing approach, or a GPIO expander could be considered for
future versions to allow dynamic assignment of CS pins. For now, this
configuration effectively supports simultaneous operation of multiple
sensors, enabling flexible and straightforward sensor module swapping.

Modular Sensor Options

Two edge card sensor modules were created for the board: a BME280
environmental sensor [4] and an ICM42688 IMU sensor [5]. The
schematic diagrams of these modules were based on their respective
datasheets; however, for reference, you can see them in Figure 4 and
Figure 5. Both edge cards share identical dimensions 23.55 × 13.55
mm (Figure 6), with standardized pinouts for I2C and SPI lines to
maintain compatibility.

For testing these sensors, I utilized libraries that simplified the integra-
tion process. For the ICM42688, the ICM42688 library by finani was
used [6], which proved to be user-friendly and included examples Figure 6: Size comparison of the Edge Card modules with a 1 Euro coin for
covering various functionalities such as I2C and SPI modes, interrupt scale.

+3V3 TP5 TP1 TP3 TP4 TP2

C1 C2 R1 R2 JP3 C3
10k

10k

10n 100n 100n

8
J1
VDD I2C Mode
5 1 1 2
VDDIO AP_SDO/AD0
14 3 4 SDA JP2 JP1
AP_SDA/SDIO/SDI
2 13 5 6 SCL
RESV1 AP_SCL/SCLK
3 12 7 8
RESV2 IC1 AP_CS ADDR SEL
7 CS 9 10
RESV3 ICM-42688-P COMM SEL
11 4 INT1 11 12
RESV5 INT1/INT
10 9 13 14 SPI_MOSI
RESV4 INT2/FSYNC/CLKIN
15 16 SPI_SCK
GND
17 18 SPI_MISO
6

Figure 5: Schematic
CLK/INT2 19 20

240472-004
diagram of ICM42688
Edge Card module.

March & April 2025 105

 sitting next to it in Figure 8, making it a perfect desk-friendly tool. This
modular approach has proven incredibly useful for testing sensors and
has earned a permanent spot on my workbench.

Closing Thoughts and Future Enhancements

Like any project, there’s always room for improvement, and reflecting
on this design has given me several ideas for the next iteration. One
area for refinement is the layout of the edge card connectors. While the
present arrangement works, I encountered some difficulty soldering
them using a rework station due to the tight spacing (Figure 9). This
Figure 7: The Sensor Evaluation Board with sensor modules inserted, led me to use a hot plate method instead, just for these connectors.
illustrating the modular approach. In future designs, I plan to space the connectors more generously to
ensure better accessibility for soldering on both sides.

Testing and ADC Limitations of ESP32 Another improvement would be relocating the bottom ADC (IC2) slightly
During testing, I evaluated both of the onboard ADS1015 ADCs. Unfor- further from the power section of the board. While the noise difference
tunately, only a single ADS1015 IC was available with me at the time, observed during testing was very minimal, optimizing its placement
so I tested it in both locations separately. Despite this limitation, both could further enhance signal integrity. At the time of designing, I specu-
configurations performed identically under normal conditions. However, lated this might have a very minor impact, and testing confirmed that
the ADC at IC1 showed slightly better noise performance. This is likely even small adjustments in layout can make a measurable difference.
due to its position, being closer to its header pins and further from the
board’s power section. That said, this noise difference is negligible for Additionally, I would explore incorporating a multiplexer for the Chip
practical purposes. Select (CS) lines on the edge card connectors. This would allow
dynamic assignment of CS pins, making the design more scalable
When comparing these external ADCs to the ESP32-S3’s built-in ADC, and reducing the reliance on predefined GPIOs for each edge card.
the improvement is stark. The ADS1015 offers far better accuracy and It would streamline the integration of multiple edge cards and enable
significantly reduced noise, even with the ESP32-S3 clocked at 20 MHz. more flexibility in future designs.
The difference in performance is almost incomparable — truly a “day and
night” contrast — making these external ADCs a worthwhile addition. Lastly, I’d consider adding an onboard OLED display for real-time
feedback during testing. Features like displaying the sensor status or
Beyond the ADC testing, this board’s modular design truly shone ADC readings directly on the board could enhance its usability and
when swapping and testing the edge card sensor modules. While I speed up debugging.
currently have only two modules — the BME280 and ICM42688 — the
flexibility, they provide has inspired me to expand the collection. As Overall, this project has been a valuable experiment in modular design
shown in Figure 7, the compact size of the board, measuring just and has proven its utility during sensor testing. While there’s always
64.7 × 66.6 mm, is another advantage. It’s smaller than the mouse room for improvement, this version serves its purpose well and provides

Figure 8: A size comparison of the Sensor Evaluation Board next to a Figure 9: Side-angle view showing the tight spacing of the edge card
keyboard and mouse, demonstrating its desk-friendly dimensions. connectors, highlighting potential for future improvements.

106 March & April 2025 www.elektormagazine.com

a strong foundation for future enhancements. With a few adjustments, About the Author
I’m confident this board can evolve into an even more powerful and Saad Imtiaz, Senior Engineer at Elektor, is a mechatronics engineer
adaptive tool for embedded development. who has extensive experience in embedded systems and product
240472-01 development. His journey has seen him collaborate with a diverse
array of companies, from innovative startups to established global
Questions or Comments? enterprises, driving forward-thinking prototyping and development
If you have questions about this article, feel free to email the projects. With a rich background that includes a stint in the aviation
author at saad.imtiaz@elektor.com or the Elektor editorial team industry and leadership of a technology startup, Saad brings a
at editor@elektor.com. unique blend of technical expertise and entrepreneurial spirit to
his role at Elektor. Here, he contributes to project development in
both software and hardware.

Related Product
Visit our IoT & Sensors page
for articles, projects, news, and > Dogan Ibrahim, The Complete ESP32 Projects Guide,
videos. Elektor 2019
www.elektormagazine.com/ www.elektor.com/18860
iot-sensors

WEB LINKS
[1] ADS1015 (12 bit, 3.3 kSamples/s, 4 channels), TI Datasheet: https://www.ti.com/product/ADS1015
[2] ADS1115 (16 bit, 860 Samples/s, 4 channels), TI Datasheet: https://www.ti.com/product/ADS1115
[3] EC.8 straight, ept connectors Product page: https://www.ept-connectors.com/index.php?EC8-SMT-HighSpeed-Direct-Connector
[4] BME280, Bosch Sensortec Product page:
https://www.bosch-sensortec.com/products/environmental-sensors/humidity-sensors-bme280/
[5] ICM-42688-P High-Precision 6-Axis IMU, TDK Product page:
https://invensense.tdk.com/products/motion-tracking/6-axis/icm-42688-p/
[6] ICM42688 Sensor Libaray (GitHub): https://github.com/finani/ICM42688
[7] Adafruit BME280 Library (GitHub): https://github.com/adafruit/Adafruit_BME280_Library
[8] Setting up Library Loader for use with KiCad: https://www.samacsys.com/kicad/

Join our Community

www.elektormagazine.com/community

March & April 2025 107

 AI

2025: An AI Odyssey
The Rise of Foundation Models and
Their Role in Democratizing AI

Source: Adobe Stock

By Brian Tristam Williams (Elektor)

Foundation models are transforming

artificial intelligence by making powerful, These powerful, general-purpose AI systems — think GPTs (gener-
ative pretrained transformers) [2], BERTs (bidirectional encoder
general-purpose tools available to a representations from transformers) [3], or the Stable Diffusion
wider audience than ever before. From model [4] for image generation — are paving the way for a new era
generating essays to creating artwork, of accessibility, creativity, and innovation. But, while they promise
to democratize AI, they also raise important questions about ethics,
these versatile AI systems are reshaping equity, and control. Let’s unpack what foundation models are, why
industries and empowering individuals. they matter, and how they’re shaping the future of AI.
But with great potential comes great What Are Foundation Models?
responsibility, as questions about ethics, At their core, foundation models are AI systems trained on
equity, and control loom large. Let’s massive datasets to perform a wide range of tasks. Unlike tradi-
explore how these models work, their tional machine learning models, which are typically designed for
individual specific functions, foundation models are generalists.
impact, and the challenges they present. For example, OpenAI’s GPT-4 can write essays, draft code, answer
complex questions, and much more. Similarly, models such as
Stable Diffusion generate incredible images based on simple text
prompts.
Artificial intelligence is no longer the stuff of science fiction — it’s
reshaping our world in ways that affect everyone, from businesses The secret sauce lies in their architecture, usually based on trans-
to hobbyists. At the center of this transformation are foundation formers, which enable these models to understand and generate
models, a groundbreaking type of AI that’s suddenly everywhere patterns across various types of data. They’re called “foundation”
(of the 10 biggest companies in the world [1], seven are actively models because they serve as a base that can be fine-tuned or
creating foundation models) and unlocking new possibilities but adapted for specific applications — a veritable Swiss Army knife
also stirring important debates. for AI.

108 March & April 2025 www.elektormagazine.com

Transformers are a type of neural network architecture that revolu-
tionized artificial intelligence when introduced [5] in 2017. Accord-
ing to AI hardware powerhouse NVIDIA, they “are among the newest
and one of the most powerful classes of models invented to date.
They’re driving a wave of advances in machine learning some have
dubbed transformer AI.” [6]

The transformer’s key innovation is the “self-attention mecha-

nism,” which allows the model to evaluate relationships between
all elements in a sequence of data simultaneously, rather than
processing them sequentially, like earlier models. This enables
transformers to understand context more effectively, such as how
words relate to each other in a sentence or across paragraphs.

Making AI Accessible to All

One of the most exciting aspects of foundation models is their
potential to make AI accessible to a much broader audience. In
the past, deploying AI solutions often required a deep understand-
ing of machine learning, access to specialized hardware, and the
resources to train models from scratch. Now, thanks to foundation
models, anyone with an internet connection can tap into advanced
AI capabilities.

Cloud-based platforms such as OpenAI’s API [7] or Amazon’s AWS

SageMaker [8] make it possible for businesses and individuals
to integrate AI into their workflows without breaking the bank.
Meanwhile, open-source initiatives, such as Hugging Face’s model
repository [9] or Meta’s Llama [10], offer free or affordable alter-
natives to proprietary systems, further lowering barriers to entry.

This accessibility has sparked a wave of innovation. Small

businesses can use these models to analyze data or automate
customer interactions. Independent creators are using tools such as
DALL·E to generate unique art (“unique” may be the most charitable
Figure 1: The tip of the iceberg from Hugging Face’s over 1.2-million-model
adjective, at least sometimes). Even we hobbyists are finding ways
library. (Source: Hugging Face website)
to apply AI to our projects — the possibilities are nearly endless.

Challenges and Ethical Questions

However, the rise of foundation models isn’t without its challenges.
First, there’s the issue of bias. Because these models are trained on The Role of Open Source
vast amounts of publicly available data, they can inadvertently learn Fortunately, the open-source community is stepping up. Organi-
and perpetuate societal biases. For instance, language models might zations such as EleutherAI [11], Hugging Face, and Stability AI are
generate responses that reflect stereotypes or exclusionary language. developing models that rival proprietary systems while emphasiz-
ing transparency and collaboration. These efforts are essential in
Then there’s the question of misuse. Just as with any useful tool ensuring that the benefits of AI are distributed more equitably.
since one of our ancestors picked up the first rock, foundation
models can be used by bad actors — create deepfakes, spread misin- For example, Hugging Face not only hosts a vast library of models
formation, or automate cyberattacks. At scale, it poses a signifi- (Figure 1), but also provides user-friendly tools to fine-tune them
cant ethical dilemma. for specific tasks. Stability AI’s Stable Diffusion model has democ-
ratized image generation, giving anyone with a decent GPU the
Another concern is control. Many of the leading foundation models ability to create professional-quality visuals on their own computer.
are owned by tech giants, raising questions about monopolies
and power dynamics in the AI ecosystem. On the flip side, while While open-source initiatives are a step in the right direction,
open-source models promise transparency and accessibility, they they’re not a silver bullet. Striking a balance between openness
can also be weaponized, leaving us to grapple with the trade-offs and responsible use remains a challenge that the community must
of openness versus security. address.

March & April 2025 109

What Lies Ahead? About the Author
As foundation models continue to evolve, we can expect them to Brian Tristam Williams has been fascinated with computers and
become more specialized, efficient, and multimodal — capable of electronics since he got his first “microcomputer” at age 10. His
handling text, images, audio, and video in a unified framework. journey with Elektor Magazine began when he bought his first issue
This evolution will unlock new possibilities in fields ranging from at 16, and since then, he’s been following the world of electron-
healthcare to education, but it will also require robust governance ics and computers, constantly exploring and learning. He started
and oversight. working at Elektor in 2010, and nowadays, he’s keen on keeping
up with the newest trends in tech, particularly focusing on AI and
The democratization of AI is a double-edged sword. On the one single-board computers such as Raspberry Pi.
hand, it empowers individuals and small businesses to harness the
power of advanced technology, and helps us get up and running
with electronics passion projects quickly. On the other, it amplifies Questions or Comments?
the risks associated with bias, misuse, and concentrated control. If you have questions or comments, brian.williams@elektor.com is
As a community, we must navigate these challenges thoughtfully, my email address. You can also catch me on Elektor Engineering
ensuring that AI serves as a tool for good rather than harm. Insights each month on YouTube, and you can find me @briantw
on X.
Looking Ahead
Foundation models represent a monumental leap forward in AI,
offering unprecedented opportunities for innovation and creativity.
However, their rise also underscores the need for vigilance, collab-
Related Products
oration, and ethical responsibility. As these models become an
integral part of our lives, it’s up to all of us — developers, businesses, > D. Situnayake & J. Plunkett: AI at the Edge
policymakers, and users alike — to shape a future where AI is truly (O’Reilly Media, 2023)
accessible, equitable, and beneficial for everyone. www.elektor.com/20465
230181-L-01

Foundation models are everywhere. (Source: @Tada Images/@Koshiro K/@Robert — Adobe Stock)

WEB LINKS
[1] Forbes India — “Top 10 Companies in the World by Market Cap in 2025”: https://tinyurl.com/forbesmc
[2] GPT Wikipedia entry: https://en.wikipedia.org/wiki/GPT
[3] BERT (language model) — Wikipedia: https://en.wikipedia.org/wiki/BERT_(language_model)
[4] Stability AI: https://stability.ai
[5] “Attention Is All You Need,” arXiv Cornell University: https://arxiv.org/abs/1706.03762
[6] “What Is a Transformer Model?” — NVIDIA blog: https://blogs.nvidia.com/blog/what-is-a-transformer-model
[7] OpenAI Developer Platform — Getting Started documentation: https://platform.openai.com/docs/overview
[8] Amazon SageMaker — build, train, and deploy ML models: https://aws.amazon.com/sagemaker
[9] Hugging Face: https://huggingface.co
[10] Llama: https://llama.com
[11] EleutherAI — empowering open-source artificial intelligence research: https://eleuther.ai

110 March & April 2025 www.elektormagazine.com

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March & April 2025 111

 PROJECT

Raspberry Pi
Standalone MIDI
Synthesizer (1)
Preparing a Platform for Some Edge AI Experiments

By Brian Tristam Williams (Elektor)

nize, play together, or control synthesizers and computers. It’s light-
With AI on the edge in embedded weight, flexible, and integral to digital music production. See more
systems now, single-board computers about MIDI at [1].
!
have been doing a lot of camera-related Why I Want My Raspberry Pi to Make Sounds
tasks such as object recognition and Back in 1994, I bought a Roland JV-30 keyboard/synthesizer. It wasn’t
pose estimation. What if we tried super high-end, but it did let me play the keyboard and let me hear
what I was playing (via external speakers or headphones — it had no
something music-related instead? built-in speakers). It was also my first instrument with MIDI.
Let’s get started. !
It so happened that in that same year, I got my first “multimedia” PC,
meaning it had an actual sound card capable of playing stereo, 16-bit
digital audio, rather than relying on the motherboard’s digital On/Off
I have been thinking of a novel task for portable AI: Perhaps it could signals from a single pin to provide beeps and buzzes to an internal
help me musically — being a live backup player for me as I play my speaker [2]. The sound card fed a couple of powered speakers next
keyboard. In this first part, let’s tackle how to actually get a keyboard to the monitor, and it could also play CDs directly from its double-
MIDI controller talking to a Raspberry Pi, and having the latter make speed CD-ROM drive!
the hills come alive with the sound of music. !
! That certainly made the game of DOOM, which released in Decem-
What Is MIDI? ber of 1993, a lot more immersive to play (although early versions of
MIDI (Musical Instrument Digital Interface) is a communication proto- DOOM were mono, not stereo).
col that allows electronic musical instruments, computers, and other !
audio devices to connect to and control each other. Introduced in the
early 1980s, MIDI transmits digital messages rather than audio signals.
The types of digital messages include:
!
Note On/Off: Tells a device when to start or stop playing a note.
Velocity: Indicates how hard a key was pressed (volume expression).
Control Changes: Adjust parameters such as volume, modulation,
pitch, or sustain.
Program Changes: Switch between instrument sounds (e.g., piano,
strings).
!
Back then, MIDI data was sent via 5-pin DIN cables (legacy devices),
but, nowadays, new gear will have USB (Figure!1). The protocol Figure 1: The M-Audio Keystation 88 MK3 has both USB and legacy 5-pin
operates at a 31,250 baud rate and allows instruments to synchro- DIN connectors for its MIDI tra!ic.

112 March & April 2025 www.elektormagazine.com

 Then I discovered that the music keyboard’s inability to play sound
directly was more cumbersome than I expected. I found the process
of connecting it to my PC every time and opening some compli-
cated software unwieldy. After considering various solutions — such
as upgrading to a keyboard/synthesizer, using my broken keyboard as
a synthesizer unit for the new keyboard, or using a modular external
synth (which you can see in Figure 3), I felt that all of these options
Figure 2: A badly damaged Roland JV-30. Viewer discretion is advised. took up too much space, used too much power, and were too heavy.
!
I thought of the Raspberry Pi, a compact option that might solve the
As was typical, my sound card had 3.5!mm minijack connectors for problem, even though I doubted its compatibility with complex music
stereo line in, stereo line out, and a mono microphone input, but there software like you’d get on Windows or Mac, but I thought it was worth
was also another standard connector: the 15-pin joystick connector. a try.
Apart from the anomaly that sound cards were responsible for connect- !
ing PCs to joysticks, that connector had extra capabilities: MIDI input Having done some research, I found out that you don’t even need
and output, which used only two of the 15 pins. slick, complicated music production software. You don’t even need
! a monitor! If all you want to do is play your keyboard and have the
Ah yes, instead of using the cheap FM synthesis on my Media Vision computer synthesize the sounds you’re going to hear, the Raspberry!Pi
Pro AudioSpectrum sound card [3] to play the music during a DOOM is more than capable of doing that headlessly (i.e., without any need
match, I could tell the game to send its music out via the MIDI output, for monitor, keyboard, or mouse)! The Raspberry!Pi is tiny enough
and the Roland would render much higher quality music. Feeding to stick to the back of the music keyboard, and the keyboard uses
the audio output from the keyboard back into the sound card’s audio so little power that you can power it directly from the Raspberry Pi’s
input, we could have all the game’s audio come from the same pair USB connector. Just think of the simple connection flow: Raspberry!Pi
of speakers. Power!Supply → Raspberry!Pi → music keyboard powered by USB.
! That’s all you need (well, almost — we still need a way to hear the
So, that showed off the keyboard’s synth responding to outputs from sound, but we’ll get to that).
the PC, but, later on I got some music production software, such as !
MidiSoft Recording Session [4] that also allowed key presses from Which Raspberry Pi?
the keyboard to drive recordings and arrangement on the PC side, so While I used the Raspberry Pi!5 for my first experiments, the Raspberry
it was a two-way street. Pi!4 is more than capable of doing what we need it to do in this context.
! In fact, the Raspberry Pi!4 and predecessors have one distinct advan-
A couple of decades later, a self-made disaster struck. Rushing on a tage: They already have an analog audio output via a 3.5!mm minijack,
school morning, I tried to dry a damp jersey for my daughter by laying whereas the Raspberry Pi!5, by default, pushes audio out via one of
it over the conveniently located Roland JV-30 and using a hairdryer to its HDMI connectors to a monitor.
get the job done. I had zero idea how sensitive the plastic keys were, !
and while the jersey was nice and dry at the end of my mission, when Initially, for setup purposes, I used the Raspberry Pi!Monitor, which
I lifted it off the keyboard, I was met with a disaster: All of the keys in not only has two tiny built-in speakers, but also a headphone output,
the region were bent, buckled, and irreparable (Figure!2). I thought which proved to be extremely useful — just plug in my studio monitor
of buying new spare keys, but there were so many damaged that it
would have cost less just to replace the keyboard.
!
I left it for a few years, but I was getting an itch to play again. I didn’t
want to spend a fortune on a stage-worthy keyboard/synthesizer, and
I also wanted a full complement of 88!keys (like a piano), because the
lack of keys down on the bass end (left-hand side) of the Roland JV-30
was a bit limiting for me in the past. I noticed that keyboards without
built-in synthesizers were a lot cheaper, and I’d be able to get 88 keys
for a reasonable price if I just bought a keyboard.
!
So, I opted for an M-Audio Keystation 88 MK3 [5], which is precisely
that: a keyboard. Just like the one I’m typing on now, it has a USB
interface, zero circuitry to create any kind of sound, uses very little
power (so, while it has a power input, it can also be powered directly
via USB), and simply sends details of every key I press (and subse- Figure 3: The 1988 Roland D-110 synthesizer promises “80s in a box!” But it
quently let go of) back to the computer. sure isn’t convenient.
!

March & April 2025 113

 devices (such as keyboards) to output devices (such as synthesiz-
ers or software), and dynamically route MIDI signals. This makes it
essential for linking MIDI hardware or virtual ports in real-time during
music production or performance.
!
The best part is that aconnect is included in Raspberry!Pi!OS, so just run
!
aconnect -l
!
to get a list of detected devices. You can see the output I got in Figure!5.
Under client 24, you see my keyboard listed as 'Keystation 88
MK3 Keystation 88'. It has two ports, but port 0 is the one of signif-
icance here.
!
Great, so our keyboard, connected via USB, is detected. What we need
now is some software that can turn the keyboard’s low-bitrate digital
chatter into music. FluidSynth is my go-to right now [6]. FluidSynth is
an open-source software synthesizer that converts MIDI data into audio
using SoundFont files. SoundFonts are collections of audio samples
and instrument definitions that allow FluidSynth to generate realistic,
high-quality sound. It operates in real-time, making it suitable for live
performances, music production, and MIDI playback. It’s widely used
due to its flexibility and ability to produce professional-grade audio on
various platforms, including Linux, macOS, and Windows. It boasts
low-latency performance, making it ideal for interactive applications or
live input from MIDI controllers. It also has a command-line interface
Figure 4: My test system up and running: Raspberry Pi, Raspberry Pi and integration options, so it can be a powerful “Swiss Army knife”
Monitor, keyboard, mouse, headphones and music keyboard connected for MIDI debugging, composition, and performance.
via USB.
!
Install it like this:
!
headphones, and I was set to play music and hear it at the same time sudo apt install fluidsynth
— what a concept. Throw in the Raspberry!Pi Keyboard and a mouse, !
and we have a little test system running (Figure!4). Prepare to wait a couple of minutes, as it will likely download many
! files from the Bookworm repository. Once it’s done, test it using:
Setting Up MIDI Playback on the Raspberry Pi !
Here’s the process I followed to get a Raspberry Pi!5 listening to my
Keystation’s activity and making music from it.
!
Firstly, connect the Raspberry!Pi to the mouse, monitor, and (typing)
keyboard. Then, connect a cable between the Raspberry!Pi’s USB-A
and the music keyboard’s USB-B connector (just like a printer). Finally,
power up the Raspberry!Pi and wait for it to boot into its desktop GUI
(for now).
!
Open the Terminal application and start with the usual step of making
sure all the software is updated, then reboot:
!
sudo apt update && sudo apt full-upgrade
sudo reboot
!
Once the board is back from its reboot, open the terminal again, and
we’ll turn to the aconnect program to give us some information about
our setup. aconnect is a Linux command-line tool used to manage
MIDI connections. It allows us to list MIDI devices, connect input Figure 5: aconnect-l shows the MIDI port configurations.

114 March & April 2025 www.elektormagazine.com

Figure 6: FluidSynth’s warning doesn’t stop it from entering its interactive mode.

fluidsynth -a alsa -g 1 -o synth.polyphony=64 /usr/share/ Time to run the fluidsynth command again with bated breath and…
sounds/sf2/FluidR3_GM.sf2 Nope. noteon works, but still nothing when I play the keyboard. OK,
! I have to verify that MIDI data is, in fact, coming in to the system.
In my case, FluidSynth complained about failing to “set thread to Let’s use the aseqdump tool. We’ll first confirm that it recognizes the
high priority” (Figure!6). It tries to do this to minimize latency and known ports:
improve real-time audio performance. This is merely a warning, but !
FluidSynth is indeed now running in “interactive mode,” so there’s aseqdump -l
nothing to worry about. The “high priority” preference may be an issue !
on older Raspberry!Pis, but given that I’m running on a Raspberry Pi!5, Yes indeed, it confirms that the keyboard is at 24:0. Now let’s monitor
I discerned no noticeable lag. In fact, I was presently surprised at how any data that comes from the keyboard as we play a few notes:
responsive the whole system was. So, I moved on to the next step. !
! aseqdump -p 24:0
At that point, I was supposed to be able to play the keyboard and !
hear audio. Deafening silence. I tried telling FluidSynth to play a note You can see the output in Figure!7. Well, the notes are coming in. (Side
manually. As mentioned, if it’s already running in interactive mode, you challenge: The first person to email me with the name of the tune gets
just tell it what to do by typing a command. For example: a €20 Elektor Store voucher!)
! !
noteon 0 60 100 Eventually, I got suspicious of FluidSynth — I found it showing up on
! port 128:0 before I even started it (even immediately after a reboot).
This tells it to play the Middle C note (60) at a velocity of 100 on That’s fine, but what if I did explicitly start it from the terminal?
channel!0. But still, no audio. Sigh. To test this, I started FluidSynth as normal, then opened a separate,
! new terminal window and ran aconnect -l again. Well, what do
After a bit of troubleshooting, it turned out that the Raspberry Pi’s audio
was being channelled to one of its two HDMI outputs — of course not
the one I was using. Loath to do more software configuration, I just
did a clean shutdown:
!
sudo shutdown
!
Then I plugged the HDMI cable into the other Micro!HDMI output, and
powered back up again. After starting FluidSynth again, the noteon
command yielded the expected result and made a sound.
!
However, still no sound when playing the keyboard. Ah yes, there
is another step: We need to route the keyboard’s port (as listed in
aconnect -l) with FluidSynth’s port. From Figure!5, we saw that
our keyboard was client 24, port 0. We just need to connect that (in
software) to FluidSynth’s port. And now that FluidSynth is installed,
running the aconnect -l command tells us that FluidSynth is client
128, port 0. Let’s connect them:
! Figure 7: aseqdump -l tells you exactly what tra!ic is coming in via the
aconnect 24:0 128:0 MIDI port.
!

March & April 2025 115

Figure 8: Using two
terminal windows, while
not strictly necessary,
helped me track down
the extra process.

you know, there was a new instance of FluidSynth operating on port Questions or Comments?
129:0 (see Figure 8). So, in the new window, I told aconnect to route We’d love to hear about how you are using AI and how it has affected
to 129:0 instead of 128:0. you over the past two years. If you have questions or comments,
! email me at brian.williams@elektor.com.!You can also catch me on
aconnect 24:0 129:0 Elektor Engineering Insights each month on YouTube, and you can
! find me @briantw on X.
I tickled a few keys, and was immediately greeted by the glorious
sounds of FluidSynth’s default piano. Finally! I’m not sure what I could
have done wrong to get FluidSynth showing up on two different ports
simultaneously — I never added any startup configuration or scripts
to the Raspberry!Pi earlier.
! About the Author
To restore default behavior, where I could use ports 24:0 and 128:0, I just Brian Tristam Williams has been fascinated with computers and
killed all instances of FluidSynth from the new terminal window with electronics since he got his first “microcomputer” at age 10. His
! journey with Elektor Magazine began when he bought his first issue
killall fluidsynth at 16, and since then, he’s been following the world of electronics and
! computers, constantly exploring and learning. He started working
and watched the process die in the original window. Then I ran at Elektor in 2010, and nowadays, he’s keen on keeping up with the
aconnect 24:0 128:0, started FluidSynth again in the original window newest trends in tech, particularly focusing on AI and single-board
( just up-arrow followed by Enter, of course), and now it’s working as computers such as Raspberry Pi.
expected. Wow, it “just works.”
!
Getting Ready for More
Now that we have our gadgets talking and making sounds, we have
the potential to write our own scripts to take output from the keyboard Related Products
and turn it into sound using available tools. But, can we take it to the
edge, i.e., doing some AI processing on our local hardware? I don’t > Pimoroni Piano HAT for Raspberry Pi
www.elektor.com/20552
know how much brain power it really takes a computer to fiddle with
a few plaintext MIDI messages containing a little bit of information. > Raspberry Pi 5 Ultimate Starter Kit (4 GB)
Stay tuned! www.elektor.com/20720
240714-01

WEB LINKS
[1] What Is MIDI?: https://instructables.com/What-is-MIDI
[2] PC speaker: https://en.wikipedia.org/wiki/PC_speaker
[3] Media Vision Pro AudioSpectrum: https://en.wikipedia.org/wiki/Media_Vision_Pro_AudioSpectrum
[4] Demonstration of MidiSoft on Reddit: https://tinyurl.com/redditmidisoft
[5] M-Audio: Keystation 88 MK3: https://tinyurl.com/keystation88
[6] FluidSynth project wiki: https://github.com/FluidSynth/fluidsynth/wiki

116 March & April 2025 www.elektormagazine.com

 UPDATES & MAIL

Err-lectronics
Corrections, Updates, and Readers’ Letters
Compiled by Jean-François Simon (Elektor)

Low Voltage Converter for LED

M. A. Shustov, Electronic Circuits For All
(Elektor 2017), p. 35
I have a question about Shustov’s book Electronic Circuits
for All. The section on LED drivers is interesting. One
circuit claims to run an LED on just a few hundred!mV
(e.g., p. 35). It needs a germanium transistor for these
very low voltage circuits and more than once they use
what they call a 1N1585. To me, that is a diode. Is this a
Opamp Tester typo or a mistake in translation from a Russian code?
Elektor 3/2005, p. 74 (030386)
I have noticed an error in the circuit. The schematic Jonathan Hare (United Kingdom)
shows the power to IC4 as: +Ve on pin 11 and -Ve on !
pin 4. These are incorrect and need to be transposed.
This is most probably a typo that went unnoticed. We are
Nigel Bowers sorry about that! Thank you for pointing it out. Surely
! the authors meant 2N1585 instead. That one may be
slightly difficult to buy, but it’s supposedly similar to the
Thank you for your email. You’re absolutely correct! GT311 which is available on eBay, but I don’t have experi-
I’m sorry about this error. Unfortunately the error is ence with either. Good luck with your experiments!
present in both the schematic and the PCB. Fortunately,
it shouldn’t be too difficult to correct the wiring. Pins!4 Jean-François Simon (Elektor)
and!11 can be isolated from the tracks with an x-acto
knife and connected correctly to +9!V and -9!V with a
few solder bridges, as these power rails are close by. Also,
note that the DIP sockets meant to hold the Opamps
Under Test should be soldered on the back (copper)
side of the PCB. This way the PCB can be mounted flush
against a front panel that you may build for the tester,
with the sockets accessible through holes in the panel.
The LEDs are mounted on the back for the same reason.
Enjoy the build!

Jean-François Simon (Elektor) _

Ideas or Feedback?
Got a bright idea or valuable feed
back
for Elektor? Reach out to us at
editor@elektor.com. We’re eager to
hear from you!
_

March & April 2025 117

 Electronic Load Resistor
Elektor 1-2/2025, p. 94 (240201)
How can it be ensured that all four MOSFETs always
draw the same partial current at every adjustment of
the load current? Were all four MOSFETs selected in
this regard, or measured in the finished device?

Henning Weddig (Germany)

C1
! R1
330Ω

680n
With this arrangement, there is no way to ensure that the
current is perfectly equal in each of the four MOSFETs. If
Mains
you want to recreate the setup, you can use four identi-
B1

cal MOSFETs (preferably bought at the same time from

the same place, so there is some probability that they C2

come from the same batch and have similar proper- 47µ
ties), or you can match them by checking that they let
through similar drain-source currents for a fixed gate
voltage. This can be done using two regulated power
250015-006

supplies and a multimeter, or better yet, a transistor

curve tracer if you have access to one. Indeed, paral- Failing LEDs
leling MOSFETs is a complicated subject. Commercial Our workshops are, of course, lit with LED tubes,
electronic loads often have multiple current-sensing typically for about five hours a day. Unfortunately, I’ve
shunts (one per MOSFET) and multiple gate-driving noticed that longevity isn’t great. I had two failures of
op-amps (also one per MOSFET) to allow more control “Müller Licht” LED fixtures within a year, as well as one
over current distribution. failure from “Osram”, and one from “Philips”. With the
Müller Licht ones, one of the three LED strips failed first,
Jean-François Simon (Elektor) then the remaining two got a bit brighter, and shortly
! afterward, it went completely dark. The Osram and
Philips ones just stopped working abruptly. I also have
In my experience, the parallel connection of MOSFETs is an E27 LED lamp, it flickered at first and then stopped
significantly less problematic than with bipolar transis- working. I opened it up, and the LEDs themselves are
tors. This configuration is also commonly found in fine. What are your experiences?
commercial circuits. Unlike bipolar transistors, FETs
have a positive temperature coefficient. This means Alfred Rosenkränzer (Germany)
that their on-resistance increases as temperature rises. !
If one FET draws more current than its counterparts,
it heats up, its resistance increases, and consequently, Yes, unfortunately, that’s how it is. Most of the time, it’s
the current through it decreases, along with the power the power supply that fails because it’s not optimally
dissipation and temperature. The datasheet for the cooled due to lack of space. For Philips tubes, I’ve
IRF740 includes the graph “Normalized On Resistance sometimes replaced the miniature fuse (which blew
vs Temperature” on page 5, which should be similar to without other damage) with a stronger one, and that
other FETs. This graph clearly shows the significant was enough to fix it. With others, it’s not so simple.
increase in RDS(on) with rising temperature. If the four Especially when LEDs themselves fail, it means their
FETs are thermally well-coupled (as is the case in my cooling is suboptimal. There are models with a kind of
design), there is no issue to be expected, provided that aluminum cooling fin on the back. I’d prefer those. For
the parallel-connected FETs come from the same batch. E27 lamps with a switch-mode power supply, it’s likely
In the days of bipolar transistors, this was much more that the power supply is defective as well. A cost-ef-
critical: one transistor might perform slightly better, fective replacement could be a bridge rectifier with a
draw more current, heat up more than the others, and, series capacitor to limit the current, as shown in the
due to its negative temperature coefficient, draw even small circuit diagram.
more current as it got hotter — eventually leading to
its failure. In my case, the device successfully endured Thomas Scherer (Elektor)
a test dissipating 120!W without issues.

Peter Grundmann (Author of the article)

118 March & April 2025 www.elektormagazine.com

Remote Water Heater Monitor
Elektor Circuit Special 2024, p. 50 (240039)
I have a few comments on the article. Capacitor C1 (150!nF/400!V) should be at least class X2. A diode (1N4148 or similar)
should be added in anti-parallel to Q1 to protect the base-emitter junction, by connecting the anode to the emitter and
the cathode to the base. Current transformers should not be operated without a load to prevent the output voltage from
rising too much, which would be the case with a negative half-wave without an additional diode. Finally, C2’s charging
current should be limited with a series resistor.

Frank Mammen (Germany)

!

There are always several ways of solving a given problem indeed! For capacitor C1, you’re right, an X2 would probably be
safer. For points 2 and 3, I can’t comment. The author of the circuit told us that, in his case, the circuit had been working
without a problem for many years, so it seems that for him the open-circuit voltage of the current transformer was not
a problem in relation to the maximum emitter-base voltage of Q1. For your last point, it seems to me that the maximum
current in capacitor C2 is in any case limited by the impedance of C1 (of the order of 21!kΩ at 50!Hz) to a value of around
15!mA, which seems reasonable to me.

Jean-François Simon (Elektor)

!

Thank you for your comments. The device has been working for over 10!years without any problems. The toroid does
not produce any harmful voltages / currents and no additional protective component is needed for the transistor. For C1
I have indicated the working voltage and the choice of an X2 is agreeable. As Jean-François points out, the current this
capacitor lets through is very small, compatible with the characteristics of the limiting Zener.

Stefano Purchiaroni (Author of the article)

SW1 S1

L L
R1
Current Sensor
C1
Mains OUT
1M

150n
400V

N N
Bipolar 16A

D3 D1

4x 1N4007
D6 C3 D1

D4 D2
D5 47µ
C2 Blue Red
16V
R2 Q1
22µ
4V7 35V
82Ω

240039-006 BC547

250015-01

March & April 2025 119

 NEWS

Source: Adobe Stock

Universal
AI RISC-V Processor
Does It All — CPU, GPU,
DSP, FPGA
By Jean-Pierre Joosting (eeNews Europe) Instruments, and Dialog Semiconductor,
who brings extensive industry expertise.
Ubitium has secured $3.7 million in seed funding to
launch a universal RISC-V processor that eliminates the “The $500 billion processor industry is
built on restrictive boundaries between
need for specialized chips, enabling advanced AI at no computing tasks,” says Hyun Shin Cho, CEO
additional cost in embedded systems by reimagining of Ubitium. “We’re erasing those boundar-
IBM’s 1967 processing approach. ies. Our universal RISC-V processor does it
all — CPU, GPU, DSP, FPGA — in one chip,
one architecture. This isn’t an incremen-
tal improvement. It is a paradigm shift.
For over half a century, general-purpose Ubitium was founded by semicon- This is the processor architecture the AI
processors have been built on the Tomasulo ductor veterans dedicated to revolu- era demands.”
algorithm, developed by IBM engineer tionizing processor architecture.
Robert Tomasulo in 1967. It’s a $500 billion CTO Martin Vorbach, who holds over “For too long, we’ve accepted that making
industry built on specialised CPU, GPU and 200 semiconductor patents licensed by devices intelligent means making them
other chips for different computing tasks. major U.S. chip companies, spent 15 years complex. Multiple processors or proces-
Hardware startup Ubitium [1] has shattered developing this groundbreaking technol- sor cores, multiple development teams,
this paradigm with a breakthrough univer- ogy. Drawing from his pioneering work endless integration challenges — today,
sal RISC-V processor that handles all in recon$gurable computing, he created that changes. The universal RISC-V proces-
computing workloads on a single, efficient a workload-agnostic microarchitecture that sor delivers workload-agnostic and AI-en-
chip — unlocking simpler, smarter, and allows the same transistors to be reused for abling compute capabilities to edge devices
more cost-effective devices across indus- different processing tasks — eliminating with a single chip, at a fraction of the cost
tries — while revolutionizing a 57-year-old the need for multiple specialized cores and to develop and manufacture compared to
industry standard. enabling AI at no additional cost. Working today’s offerings.”
between Germany and Cupertino, Califor-
The new universal RISC-V processor does nia, Vorbach’s innovation forms the founda- With the semiconductor market projected
all functions — CPU, GPU, DSP, FPGA — in tion of Ubitium’s mission. to exceed $700 billion by 2025, Ubitium’s
one chip, with one architecture. technology initially targets embedded
Vorbach met CEO Hyun Shin Cho at the systems and robotics. By simplifying
The seed funding round, co-led by Karlsruhe Institute of Technology (KIT). system architectures and reducing costs,
Runa Capital [2], Inflection [3], and After two decades of gaining insights the universal RISC-V processor makes
KBC Focus Fund [4] will be used to develop across various industrial sectors, Cho advanced computing capabilities accessi-
the first prototypes and prepare initial reunited with Vorbach to commercialize the ble across all industries without requiring
development kits for customers, with the technology. Completing the team is Chair- specialized hardware for each application —
$rst chips planned for 2026. man Peter Weber, a veteran of Intel, Texas enabling advanced AI at no additional cost.

120 March & April 2025 www.elektormagazine.com

Dmitry Galperin, a Berlin-based General The new universal ing task without specialized hardware
Partner at Runa Capital, commented: modi$cations. The company’s goal is to
“Ubitium’s unique approach to proces- RISC-V processor does establish its universal processor as the new
sor microarchitecture makes it possible all functions — CPU, standard that $nally breaks down the cost
to adapt to any type of workload — from and complexity barriers that have limited
simple control logic to massive parallel data GPU, DSP, FPGA — the deployment of advanced computing and
flow processing.” in one chip, with one AI capabilities across industries.

“What Ubitium brings will provide a real architecture. “We envision a future where every device
breakthrough to develop and launch any operates autonomously, making intelligent
new product with embedded electronics. a complete portfolio of chips that vary in decisions in real-time and transforming the
Their approach will reduce the cost as well array size but share the same microarchi- way we interact with technology,” added
as the complexity, allowing a much faster tecture and software stack — enabling Hyun Shin Cho.
time-to-market. What previously required solutions from small embedded devices to 240731-01
multiple teams to collaborate on hardware high-performance computing systems. This
and software design now becomes purely super-scalable approach allows customers Editor’s Note: Jean-Pierre Joosting first
a software project,” said Rudi Severijns, to scale their applications without chang- reported on this in eeNews Europe, a publi-
Investment Director at KBC Focus Fund. ing their development process, while the cation in the Elektor network.
workload-agnostic design ensures the www.eenewseurope.com/en/domain/
Looking ahead, Ubitium plans to develop processor can adapt to handle any comput- eenews-embedded/

WEB LINKS
[1] Ubitium: https://ubitium.com
[2] Runa Capital: https://runacap.com
[3] Inflection: https://inflection.xyz
[4] KBC Focus Fund: https://www.kbcsecurities.com/en/investment-services/kbc-focus-fund.html

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March & April 2025 121

 With Carl Schlachte
(Chairman, President, & CEO, Ventiva)

CEO Interview:
Ventiva’s Thin
and Cool Tech
Carl Schlachte, chairman, president and CEO of Ventiva. (Source: Ventiva)

By Nick Flaherty (eeNews Europe)

After over a decade of development, thermal power, up from 25 W in earlier designs, and fits into the
miniature, silent cooling technology was space previously occupied by the fan so that the motherboard design
does not need to be changed. The control architecture also mimics
reducing the thickness of laptop designs, a fan so that the software doesn’t need to change.
shown at the CES 2025 show in Las Vegas.
“A lot of engineering went into making this easy to integrate, and
that is hard,” said Schlachte. “This is the benefit of having been
around for a decade. We go out, test things in the market, and go
Carl Schlachte, chairman, president, and CEO of the developer, back and re-engineer it. We initially went after spaces that couldn’t
Ventiva, is a veteran of the semiconductor industry, having worked be used in the laptop, such as the space around the hinge. Because
at Motorola and ARM before taking over as CEO of the UK proces- of how it is built we can turn a corner, and we are not taking any
sor design company ARC. Back in 2011, he bought into a small US more space.”
firm developing an innovative cooling technology.
“We spent a lot of time with designers to understand that to get
Now in 2025, Ventiva [1] is showing a proof of concept for its ion great performance you have to rearchitect the design. We were
cooling technology, replacing the fans in a laptop to show how the using an existing Lunar Lake motherboard but they were invest-
thickness of the design could be reduced by several millimetres ing in future products for the proof of concept and learning about
with the potential to be used in other consumer designs. the modeling and the air$ow.”

“Between Dell, Intel, and Ventiva, we had 30 engineers working “The strategic vision I have is that in the next five to seven years,
for over a year. This was a serious engineering effort. What was fans will be gone. If you go out to buy a laptop then, everyone will
fascinating was that a community formed between the engineers,” have the same reaction to fans that they had to hard drives that
he tells eeNews Europe. “This is the thinnest laptop they have ever moved to solid state drives.”
built, 2 mm thinner.”
“That’s what we are doing right now. We are taking out the exist-
The technology of the 3-mm-high ICE9 blower is only one element. ing blowers and putting our blowers in the exact same spot. That’s
The technology for manufacturing and integration into designs not the best way to get the best performance out of the system. We
has been as challenging. The latest version can address 40 W of take the exact same 4-pin connector and the system thinks it is

122 March & April 2025 www.elektormagazine.com

talking to a fan, and the system needs more cooling it ramps up
just like a fan. The economics clearly point that way by rethinking
the thermals just a little bit.”

“The blower is a 60 to 70 mm long device, and we designed it so it

can be ganged up like Legos to provide more air$ow.”

“We use an electrohydrodynamic (EHD) $ow, energizing a very thin

wire in the housing, creating the ions that collide with the air to
create the air$ow. Making this low cost enough for consumers is
the challenge. We use no novel materials, no rare earth elements,
we use injection molded plastics, stamped metal and standard PCB
manufacturing with a Microchip microcontroller so it’s highly
scalable,” he said.

The company has its own factory in Malaysia, and it is getting ready
to ramp production by the end of the year, along with second sourc-
ing deals. The system that will ship to the laptop makers includes
the heat pipe and the fins ready to replace the fan. A proof-of-concept thin laptop developed by Dell and Intel using the
Ventiva ICE9 cooling system. (Source: Ventiva)
“Every piece of the manufacturing $ow has been known for 40 years,
the novelty went into the development of the software, the control
of the power supply and the architecture of the blower to maximise a random lovely accident that occurred at a time we had all the
the air$ow,” he said. tools to tackle it,” he said.

“I am the only connection back to 2011, the product is different, The company also targets the $1000+ market as that has the margin
but the basic physics of the idea is the thing that has remained the and demand for thinner designs, as well as AI. He points to data
same. My partner and I bought it, and scaled it back to bare metal, that says 94% of the volume of these laptops is between 15 W and
negotiated partnerships that helped pay for things.” 40 W, hence the 40 W proof-of-concept design shown at CES.

“Even 18 months ago, we hit a product problem and I thought we “Laptop PCs are just the start. We have a counterintuitive view
were dead. So, going from that to the Intel keynote, with Dell people of the world — we don’t see a play for us in the gaming laptop or
at our booth, is fantastic. We have relationships with all the top PC data center. Instead, there are more compelling applications on
makers, but Dell is the furthest along. In six to eight months, we’ll the small side — in a handset, ultrathin tablets, at a certain level
have more news to share,” he said. there is nothing else that will move air at this size. Giving a handset
maker an extra 5 W of cooling is unheard of, especially if you add in
“We’ve spent the bulk of our time working with really smart laptop wireless charging and the more performance requirements of AI.”
engineers, and our credibility will start to show up in the way these 250043-01
products are developed.”

AI has been a boon for the company, as the higher energy consump-
tion of AI in both the CPU and any accelerators has highlighted Editor's Note
the need for more thermal management. Nick Flaherty first reported on this in eeNews Europe,
a publication in the Elektor network.
“The general figure of merit for large language models (LLMs) we www.eenewseurope.com
use is an extra 10 W in heat load, so what has happened is that their
problems have got worse overnight as everyone wants an AI PC that
people want to talk to, and fans are loud. To get a blower quieter, WEB LINK
you have to make it bigger and run it slower. For us, our technol- [1] Ventiva: https://ventiva.com
ogy is quiet no matter what. That converged on our technology,

March & April 2025 123

 SOFTWARE

Dual-Core Programming
with a Raspberry Pi Pico
Venture Into the World of Parallel Programming

By Prof. Dr. Martin Ossmann (Germany)

The Raspberry Pi Pico is powered by the Synchronization and the Volatile Attribute
RP2040 processor, equipped with two When programming software to run on multi-core CPUs, it’s often
necessary for threads to synchronize their activity. In the simplest
CPU cores. This characteristic makes case, Core 0 can activate Core 1. This can be achieved easily using
it an ideal platform for delving into a trigger variable:
the realm of “Parallel Programming.”
volatile int trigger ;
Through the utilization of tangible
real-world examples in digital signal void core1do(){

processing, this article illustrates the while(1){

while(trigger==0){ } ;
methodologies and considerations printf("trigger=%d\n",trigger) ;
employed to extract maximum benefits trigger=0 ;

from the dual-core architecture. }

}

void core0do(){
The examples showcased here employ various parallelization int cnt=0 ;
techniques. The acceleration of a program through the use of while(1){
multiple cores is referred to as “Speedup” (abbreviated as S). With trigger=cnt++ ;
two cores, the maximum theoretical speedup is S = 2. The speedup sleep_ms(1000) ;
score achieved by each example application will be provided in }
the following discussion. }

124 March & April 2025 www.elektormagazine.com

The variable trigger is used by both cores. To let the compiler know Both cores have their own stack; they also have their own stack
that the variable can change due to its use by multiple threads, it is frame. This means there will usually be two so-called incarnations
assigned the volatile attribute. Without this attribute, the compiler of delay() using the same code but via separate stack frames. If
might perform extensive code optimizations, potentially causing delay were to use global variables or other global resources, for
issues with the shared, parallel use of a variable by two threads. example, this separation would not exist, and parallel usage would
be problematic. This example illustrates well what needs to be
Shared-Function Usage considered when parallel programming.
The following example illustrates how Core 0 and Core 1 can simul-
taneously use the same function: Core 0 Can Throttle Core 1
This next example illustrates how the two cores influence each
void delay(int nn, int cnt){ other in ways that may not be immediately apparent.
volatile int k ;
printf("core %d cnt=%d\n",sio_hw->cpuid,cnt) ; void core1do(){
for(int k=0 ; k<nn ; k++){ asm volatile(
asm volatile( " nop\n" ) ; " nop \n"
} "loop2: b loop2\n") ;
} }

void core0do(){ void ASMdelay625(){

int cnt=0 ; asm volatile( // 3*205=615 cycles
while(1){ "ldr r0, =#205\n"
delay(10000000,cnt++) ; "loop1: sub r0,r0,#1\n" // 1 cycle
} "bne loop1\n"
} // 2 cycles if loop taken, 1 if not
) ;
void core1do(){ }
int cnt=0 ;
while(1){ void core0do(){
delay(20000000,cnt++) ; while(1){
} gpio_put(GPIO2, 1) ;
} ASMdelay625() ; // approx 625 cycles
gpio_put(GPIO2, 0) ;
The Function delay(nn,cnt) outputs a message indicating which ASMdelay625() ;
core is active and the value of cnt. Then, it enters a wait loop with // without core1: 100.08055 kHz
nn iterations using the local variable k. // with core1: 75.256 kHz
}
Essentially, Core 0 and Core 1 do the same thing: they run an }
infinite loop. Within the loop, delay(..,..) is called. Core 0 uses
nn = 10,000,000 as a parameter, while Core 1 uses nn = 20,000,000. Core 1 is running a simple infinite loop. Core 0 also runs an infinite
Thus, Core 1 performs twice as many loop iterations as Core 0. The loop, but in addition sets GPIO2 high, calls a time delay of 625 cycles
count of loop iterations is tracked in the variable cnt. Since both before it returns GPIO2 low and calls another 625 cycle delay. When
cores spend most of their time in the delay loop, they are mostly Core 1 is not running, Core 0, (which is clocked at the Pico default
in the delay function simultaneously. How does this work? The clock frequency of 125 MHz), performs 100,000 loop iterations
code of the function is stored in memory only once. Therefore, both per second (125 MHz / (2 * 625 cycles)) which produces a square
cores execute the same code. Since the code only involves read wave output signal of 100 kHz at GPIO2. When Core 1 is started,
instructions, accessing the code alone does not cause a conflict. the throughput of Core 0 drops to produce a 75 kHz signal. Even
though the two cores don’t seem to have anything obvious to do
Both cores naturally have their own program counter (PC) that with each other, they do influence each other. This is likely because
addresses or steps through the code instructions. When a function there is only one memory interface used by both cores. This effect
is called, the following happens: the PC value is pushed onto the is often responsible for the achievable speedup factor of many of
stack. The parameters are also placed on the stack. Space is then the programs used here being significantly below 2.
reserved on the stack to store local variables (here k). This collec-
tion of variables on the stack is often referred to as the stack frame. This example highlights the need to always be on the lookout for
unexpected effects. Debugging parallel programs like this can be
The PC is now loaded with the start address of the called function. challenging.

March & April 2025 125

FIFO Communication void doAdd(){
You can use two implemented FIFOs to send data back and forth int sum=0 ;
securely between the cores. There is a FIFO that works from Core 0 for(int k=0 ; k<MM ; k++){
to Core 1 and another from Core 1 to Core 0. The advantage of the sum +=k ; }
SDK’s FIFOs is that they are termed “Thread-Safe,” meaning they result=sum ;
operate correctly even with parallel usage. }

To test the FIFO’s performance, we can implement a simple “server” The timing measurement results in a value of approximately 56 ns
on Core 1: per loop iteration. If we let the server run the loop for N = 10 itera-
tions, we have a computation time of about 560 ns and a commu-
void core1do(){ nication time of about 620 ns. This results in a communication
int buffer1 ; overhead in excess of 100%. The server, therefore, needs to provide
while(1){ a substantial amount of computing power to prevent commu-
buffer1=multicore_fifo_pop_blocking() ; nication overhead from impacting overall performance. When
multicore_fifo_push_blocking(buffer1+1000) coding for parallel programming environments, it’s advisable not
} to focus on too fine a level of programming granularity. In addition
} to FIFOs, Queues are also provided, offering more flexibility as they
can send arbitrary data structures. Furthermore, the SDK offers
It just waits for a value from the FIFO of Core 0 and sends this value various mechanisms for thread synchronization; it is worthwhile
back to Core 0 increased by 1,000. taking a closer look at the available SDK facilities.

Whilst this routine runs on Core 0: SDR-Parallelization

The frontend of a software-defined radio (SDR) is often structured
void core0do(){ as shown in Figure 1. After multiplying the input signal with the
for(int k=0 ; k<NN ; k++){ Local Oscillator (LO) signal, you get the I-channel (In-Phase) and
multicore_fifo_push_blocking(k) ; the Q-channel (Quadrature Phase) [1]. These two channels arise
buffer2=multicore_fifo_pop_blocking() ; almost in parallel, making them ideal candidates for parallelization.
if(buffer2!=k+1000){ Core 0 processes the data of the I-channel, and Core 1 handles the
printf("communication error!\n") ; data of the Q-channel. Summation after mixing is still performed
} in the interrupt routine. The first parallelized part involves the
} implementation of Butterworth filters, which are performed with
float precision. In Figure 2, you can see the timing of the low-pass
The runtime of this routine was measured to find this program filter evaluation.
takes approximately 0.62 µs. Since twice 32 bits are transmitted
during each run, this corresponds to a bit rate of about 104 Mbit/s. The yellow curve is “high” when Core 0 calculates the I low-pass
The following addition loop is used to compare this data transfer filter. The turquoise curve is “high” when Core 1 calculates the
rate to the calculation speed of a Raspberry Pi Pico: Q low-pass filter. Interestingly, calculation of the I component

Figure 1: Signal flow diagram of

an SDR frontend.

126 March & April 2025 www.elektormagazine.com

 values, weighting the samples with the coe%cients ak of the filter
impulse response. The formula is:

For the calculation, it’s necessary to store the last N input values
xk. This can be most conveniently performed using a ring buffer.

Figure 2: Execution of the I and Q low-pass routines.

Listing 1: Serial and parallel scalar
product-calculation.
takes significantly longer than for the Q. This is because Core 0 #define NN 10
also executes the interrupt routine that processes the sampling.
Therefore, Core 0 is not always available, and the calculations of float xk[NN] ;
the I-channel take accordingly longer. float yk[NN] ;
float result ;
Scalar Product With Loop-Splitting
Another example is the calculation of a scalar product. The paral- float skpLoop(int k1, int k2){
lelization is based on the following observation: A whole set of float sum=0 ;
calculations is typically performed in a loop. If the individual loop for( int k=k1 ; k<k2 ; k++){
elements can be calculated independently, the loop can be split sum=sum+xk[k]*yk[k] ;
into two parts and processed in parallel using the two cores. The }
formula for calculating the scalar product of two vectors x and y return sum ;
is as follows: }

void core1Do(){
while(1){
multicore_fifo_pop_blocking() ;
A routine called skpLoop in this program performs the summa- result=skpLoop(NN/2,NN) ;
tion of k1 to k2: multicore_fifo_push_blocking(456) ;
}
}

void parallelSkp(){
In the non-parallel version, 1 to N are simply summed. In the paral- float sum ;
lel version, summations from 1 to N/2 and N/2 to N are performed multicore_fifo_push_blocking(123) ;
in parallel. sum=skpLoop(0,NN/2) ;
multicore_fifo_pop_blocking() ;
sum=sum+result ;
printf("parallel sum=%10.3f\n",sum) ;
The end result is obtained by adding the two partial results. sleep_us(10) ;
Core 0 and Core 1 simultaneously use the same summation loop }
skpLoop(..,..). Since the loop is used by each core with separate
sets of array elements xk and yk, there is no conflict. The speedup void seriellSkp(){
achieved here is S = 1.8. The programs are shown in Listing 1. float sum ;
sum=skpLoop(0,NN) ;
FIR Filters printf("seriell sum=%10.3f\n",sum) ;
Finite impulse response (FIR) filters are widely used for applica- sleep_us(10) ;
tions in digital signal processing. In an FIR filter of order N, the }
current output value is calculated by summing the last N input

March & April 2025 127

 Figure 3: Signal flow in the
FIR filter.

The parallelization can be carried out in principle in the same way The evaluation of a Biquad is dependent on the results of the previ-
as with the scalar product, using loop splitting. You just need to ous stage:
manage the ring buffer and correctly index its contents. The loop
is represented here: out1=biquad1(x) ;
out2=biquad2(out1) ;
float doSumLoop(int k1, int k2, int readPtr){ out3=biquad3(out2) ;
float sum=0 ; out4=biquad4(out3) ;
for( int k=k1 ; k<k2 ; k++){
sum=sum+ak[k]*xBuf[readPtr] This makes it di%cult to parallelize the evaluation of Biquads. There
readPtr-- ; is, however, a pipelining technique that can be applied here. The
if(readPtr<0){ readPtr=N-1 ; } term pipeline originates from the implementation of fast proces-
} sors. The execution of an instruction is divided into Fetch, Decode,
return sum ; and Execute phases, each of these phases is executed in separate
} processing stages in parallel.

The parameter readPtr points to the current start position in the When Instruction Ik is fetched, the previous instruction I(k-1) has
ring buffer xBuf. The parallel FIR calculation can be seen below. already been decoded and the instruction before that I(k-2) is being
The speedup factor achieved here is S = 1.7. executed. This form of parallelization results in a higher throughput
(Figure 5). The execution of a single instruction is not any faster.
float FIRdo(int x){
xBuf[writePtr]=x ; This concept can now be applied to the IIR filter. The correspond-
int readPtr1=writePtr ; ing code is as follows:
writePtr++ ;
if(writePtr>=N){ writePtr=0 ; } inp1=x ;
int readPtr2=readPtr1-N/2 ; inp2=out1 ;
if(readPtr2<0){ readPtr2=readPtr2+N ; } inp3=out2 ;
inp4=out3 ;
Program Development
Troubleshooting parallelized programs is often challenging and
complex. It has proven useful to initially write a version of the
program to run in a more flexible environment, such as the free,
open-source Processing environment (reference version), and
debug it there. During this process, you also generate test data
for parallelization. Once this version of the software has been
debugged it can be ported to the target system to initially use the
same test data there. For troubleshooting, you can then compare
the two versions.

IIR Filter with Pipelining

In the world of digital signal processing, Infinite Impulse Response
(IIR) filters are commonly used. An IIR filter is constructed from
so-called Biquads (Figure 4) connected in series. In the non-par-
allelized form, the input value of a Biquad is precisely the output
value of the previous Biquad. It is necessary to compute biquad1
before the computation of biquad2 can begin. Figure 4: Signal flow of a Biquad.

128 March & April 2025 www.elektormagazine.com

Figure: 5: Pipelining in a CPU. Figure 6: Signal flow in a Butterfly operation.

out1=biquad1(inp1) ; Table 1: IIR-filter execution times.

out2=biquad2(inp2) ;
out3=biquad3(inp3) ; Measurement # µs
out4=biquad4(inp4) ; Timer32Measure: 0 64
Timer32Measure: 1 26
Here, there are additional intermediate values inp1…inp4. This
Timer32Measure: 2 25
makes the Biquad operations independent of each other. The Biquad
evaluations can now be parallelized, and that’s precisely how IIR Timer32Measure: 3 25
filter routines are performed using Dual-Core CPUs. This method Timer32Measure: 4 25
achieves a speedup S = 1.8 approximately.

The XIP Feature Horner’s Method

If you measure the execution time of the IIR filter multiple times Now we can look at how to evaluate a polynomial at point x. In
consecutively, you can make a surprising discovery (Table 1): In the this example, the degree of the polynomial N = 5. According to
first run, the runtime is around 64 µs which takes nearly 2.5 times the definition of a polynomial:
longer than all subsequent runs. This acceleration can be explained
by considering how the RP2040 accesses code memory. The code is
stored in the serial QSPI flash memory, and the CPU can access this
code as if it were stored in the CPU (hence XIP = eXecute In Place). To evaluate the polynomial in this form, you need N - 1 multiplica-
Since the flash memory is accessed via a serial interface, access- tion operations to calculate the powers of x. In addition there are
ing the data stored here is relatively slow. For acceleration, the XIP N - 1 multiplications of the powers with the coe%cients ak and N
interface is equipped with a cache based on fast RAM. The recently
read words are stored here, so a re-access does not occur through
the QSPI interface but from the cache.

This process explains the values of the runtime measurements.

In the first run, the code does not make use of the cache, so QSPI
access is slow and serial. Once the code is in the cache, the accesses
in the subsequent runs are correspondingly fast. This is how intri-
cate the runtime behavior of modern CPUs can be. For correct and
reliable results, you need to be aware of such mechanisms.

Fast-Fourier Transformation (FFT)

In digital signal processing, Fast Fourier Transforms (FFTs) are often
used to analyze signals. An FFT calculation consists of so-called
butterfly operations. Figure 6 shows the data flow in a butterfly
operation.

The factor w is the cosine of a phase that is dependent on the butter-

fly operation.

The diagram in Figure 7 shows the data flow where N = 16. There
are log2 N = 4 iterations performed, and each iteration consists of
N/2 butterfly operations. Within an iteration, the butterfly opera-
tions are independent of each other. They can therefore be executed
in parallel, and that’s just what this program does. Half of the butter-
fly operations in one iteration are carried out by Core 0, while the Figure 7: Signal
other half are performed by Core 1. Each core performs N/4 Butter- flow of a 16-point
fly operations per iteration. This gives a speedup factor S of 1.85. FFT.

March & April 2025 129

addition operations. A more e%cient calculation can be performed Truly E#ective
using Horner’s Scheme or Method. Here you can calculate the value By exploring the series of examples detailed in this discussion, it
pk, k = N,..,0 using the formula: becomes clear how effectively tasks can be parallelized for execution
on the dual cores of the Raspberry Pi Pico. The attained speedup
values consistently approach around 1.8 — close to the theoretical
limit S = 2. The pivotal strategy for optimizing the advantages of
parallelization involves pinpointing suitable algorithms or methods
capable of independent execution to attain the desired outcomes
— only these will be truly effective when executed in parallel. You
can download the source code and all examples for free on the
In the end, you get the value p(x) and have used N multiplications Elektor website related to this article [2].
and N additions. Altogether, this has saved N-1 multiply operations. 230440-01
The Horner scheme cannot be parallelized as easily, because the
evaluations of pk are interdependent, the polynomial can, however,
be split into two halves. The corresponding formulae are: Questions or Comments?
Please contact the author at ossmann@fh-aachen.de or the team
at Elektor at editor@elektor.com if you have any queries related
to this article.

Now, we can evaluate the two polynomials q(x) and r(x) at the same
time. To find p(x) just multiply q(x) by x3 = x(N+1)/2 and add it to r(x).
Fast calculation of x3 = x(N+1)/2 is really important here. This can About the Author
be done using the exponents 1 , x , x2 , x4 , x8 , x16 successively, and Martin Ossmann began reading Elektor, and tinkering, at the age
multiplying the necessary powers for x(N+1)/2. For example, for x9 of 12. After studying electrical engineering and working for several
calculate x9 = x8 x1. Calculation of the powers can be performed in years as a development engineer, he became a professor in the
log2 N steps. Since log2 N is very small compared to N (at least for Department of Electrical Engineering and Information Technology at
larger values of N), the necessary calculation of the powers is quick FH Aachen. Not only is he an author of many scientific publications,
and does not impact too much on the runtime. but for more than three decades, he has been regularly publishing
novel circuits and software projects in Elektor Mag, showcasing his
The described algorithm was implemented on the Raspberry Pi wealth of technical expertise.
Pico using N = 100. The non-parallelized version takes 133 µs. The
Horner calculation for both polynomial halves running in parallel
each takes 71 µs. The fast polynomial calculation requires about
7 µs. The total runtime of the parallelized algorithm is therefore
Related Products
approximately 78 µs. This makes the parallel algorithm speedup
S = 133 / 78 = 1.7 times faster. It’s evident that the calculation of > Raspberry Pi Pico RP2040
x3 = x(N+1)/2 necessary for the parallelization eats into the achiev- www.elektor.com/19562
able speedup, but the value attained is nevertheless worthwhile.
> D. Ibrahim, Raspberry Pi Pico Essentials (Elektor 2021)
www.elektor.com/19673
Linear Algebra
In addition to parallelizing the dot product, the matrix-vector
product was also parallelized, achieving a speedup S = 1.6. The
solution for a linear equation system was also implemented, result-
ing in a speedup of 1.8. A simple loop-splitting technique was used
for both tasks.

WEB LINKS
[1] M. Ossmann, “Raspberry Pi Pico Makes an MSF-SDR,” Elektor 7-8/2022: http://www.elektormagazine.com/220006-01
[2] Software Download: http://www.elektormagazine.com/230440-01

130 March & April 2025 www.elektormagazine.com

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