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CAO -UNIT -1 - CAO NOTES

Btech (Visvodaya Engineering College)

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Computer Architecture & Organization

UNIT-1

SYLLABUS

Digital Computers: Introduction, Block diagram of Digital Computer, Definition of Computer

Organization, Computer Design and Computer Architecture.
Register Transfer Language and Micro operations: Register Transfer language, Register
Transfer, Bus and memory transfers, Arithmetic Micro operations, logic micro operations, shift
micro operations, Arithmetic logic shift unit.
Basic Computer Organization and Design: Instruction codes, Computer Registers Computer
instructions, Timing and Control, Instruction cycle, Memory Reference Instructions, Input 3 Output
and Interrupt.

Computer: Digital Computer is a fast electronic calculating machine that Accepts digitized input information,
processes it according to a list of internally stored instructions, And produces the resulting output information.

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BLOCK DIAGRAM OF COMPUTER: -

INPUT UNIT: Computer receives data and instructions through the input unit. Input unit consists of one or
more input devices.
Input device include:
1. Mouse

2. Keyboard

3. Joystick

OUTPUT UNIT: Computer provides information and results of computations to the outside world through the
output unit. Output unit consists of one or more output devices.
Output device include:

1. Monitor 2. Printer 3. Speakers

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CENTRAL PROCESSING UNIT:

 It is a brain of computer.
 The ALU and Control unit (CU) of a computer system are jointly known as
the Central Processing Unit(CPU)
 CPU performs actually processing of data, according to instructions from
programs

FUNCTIONS OF CPU:
 It performs all calculations.
 It takes all decisions.
 It controls all units of the computer.

CONTROL UNIT:
 It controls all units of the computer.

 It is the central nervous system of the computer that

controls and synchronizes its working

FUNCTIONS OF CONTROL UNIT:

 It instructs the input unit, where to store the data after receiving it from the user.
 It controls the flow of the data and instructions from the storage unit to ALU

ARITHMETIC LOGIC UNIT:

 All calculations are performed in the ALU of a computer

FUNCTIONS OF ARITHMETIC LOGIC UNIT:

 It performs all arithmetic operations (ADDITION, SUBTRACTION, MUL, DIV)
 It performs all logic operations

STORAGE UNIT:
 The storage unit of the computer holds data and instructions that are entered through the input unit,
before they are processed. Storage devices are divided into two categories:
 Primary memory or main memory
 Secondary memory

FUNCTIONS OF STORAGE UNIT:

 It received the data and instructions required for processing from the input unit
 It stores the intermediate results
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 It saves data for later use.

FUNCTIONAL UNITS: A digital computer consists of five functionally independent parts.

 Input
 Output
 Memory Unit
 Arithmetic and Logic Unit
 Control Unit

TYPES OF COMOPUTERS: Many types of computers exist that differ widely in

 Size,
 Cost,
 Computational Power and,
 intended Use.

Those are

1. Desktop
2. Note Book
3. Workstations
4. Mainframes
5. Servers
6. Supercomputer

Desktop: It has
 Processing & Storage units (e.g., Hard disks, CD‐ROMs),

 visual display &audio output units,

 Input units (keyboard, mouse, etc)
 It can be easily located on a home or office desk

 Used in homes, schools, business offices, …

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NOTEBOOK COMPUTERs: Compact form of personal computer

(laptop)
 Size of a thin briefcase
 Portable

WORKSTATIONs: Has high resolution graphics input/output

capability

 Has dimensions of desktop computer

 More computational power than PC
 Costlier
 Used to solve complex problems which arises in engineering
application

Mainframe: Also called Enterprise Systems

 More computational power and storage than Workstation
 Used for business data processing in medium to large
corporations.

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Servers:
 Contain big database storage units.
 Handles large volumes of data requests
 Requests and responses are transported via Internet
 They are widely accessible to all.

Supercomputers:
 Faster than mainframes
 Helps in large scale numerical calculations
 Used for aircraft design and testing, military
application, weather forecasting, etc.

Generations of computers:
There are 5 generations of computers
1.First generation (1946 -1957)
2. Second generation (1958 -1964)
3. Third generation (1965 -1971)
4. Fourth generation (1972 -1977)
5. Fifth generation (1978 -onward)
First generation (1946 -1957): First generation computers
use Vacuum tubes; Magnetic tape drives and magnetic core
memories were developed. Its size was too much large. This
was very hard to read and write programs
Advantages:
 It was only electronic device
 First device to hold memory
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Disadvantages:
 Large in size
 Vacuum tubes burn frequently
 There were producing heat
 Maintenance problems
Second generation (1958 -1964): Second generation
computers use Transistors instead of Vacuum tubes.
Storage capacity of computer also increase
Advantages:
 Size reduced considerably
 They are fast
 Very much reliable

Disadvantages:
 They are over heated
 Maintenance problems
Third generation (1965 -1971): Third generation
computers use ICs instead of Transistors. Which is
combination of number of transistors and other electronic
components fused together on single crystal.

Advantages:
 ICs are very small in size
 Improved performance
 Production cost cheap

Disadvantages:
 ICs are sophisticated

Fourth generation (1972 -1977): Fourth generation computers use

Microprocessors instead of ICs. Microprocessor chip consists of
entire central processing unit in a single chip. Computing speed
increased.
Advantages:

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 cheapest among all generations

No air conditioners required in most cases
Much faster in computations than previous generations
Disadvantages:
Highly sophisticated technology
Fifth generation (19̮78 -onward): In fifth generation computer
VLSI technology were replaced by Ultra large-scale integration
(ULSI) technology.
Advantages:
1.They are easily portable
2.Wireless
3. Having extra high-speed processing
Disadvantages:
1. If computer having own brain, then they can harm the humanity
Computer architecture: Refers to those attributes of a system visible to a programmer or, put another way,
those attributes that have a direct impact on the logical execution of a program. Examples of architectural
attributes include the instruction set, the number of bits used to represent various data types (e.g.,
numbers, characters), I/O mechanisms, and techniques for addressing memory.
Computer organization: Refers to the operational units and their interconnections that realize the
architectural specifications. Examples of. Organizational attributes include those hardware details
transparent to the programmer, such as control signals; interfaces between the computer and
peripherals; and the memory technology used.

Computer Architecture Computer Organization

Computer architecture explains what a Computer organization explains how a
computer should do. computer works.
Computer architecture provides functional Computer organization provides
behaviorof computer system. structural relationships betweenparts of
computer system.
Computer architecture deals with high Computer organization deals withlow
level design. level design.
Actors in Computer architecture are Actor in computer organization is
hardwareparts. performance.
Computer architecture is designed first Computer organization is started after
finalized of Computer architecture

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Computer Design: Is concerned with the h/w design of the computer. That is, it is concerned
with the determination of what h/w should be used and how the parts should be connected.
Once the computer specifications are formulated, it is the task of the
designer to develop h/w for the system
NOTE: All students of computing should acquire some understanding and appreciation of a
computer system’s functional components, their characteristics, their performance, and their
interactions. There are practical implications as well. Students need to understand computer
architecture in order to structure a program so that it runs more efficiently on a real machine.
In selecting a system to use, they should be able to understand the tradeoff among various
components, such as CPU clock speed vs. memory size.

Register Transfer Language and Micro operations:

Register Transfer languageAND ARCHITECTURE?
 The symbolic notation used to describe the micro-operation transfers among registers is called a Register
Transfer language. Registers are designed by capital letters, sometimes followed by numbers (e.g., A,
R12, IR…)
 Information transfer from one register to another is designed in symbolic form by means of a
replacement operator.

R2 ← R4
BLOCK DIAGRAM OF A REGISTER:

 Often, we want the transfer to occur only under a predetermined control condition.
 if (p=1) then (R2 ←R1)
 where 8p9 is a control signal generated in the control section.
 In digital systems, this is often done via a control signal, called a control function
 3 If the signal is 1, the action takes place
• This is represented as:
P: R2 ← R1

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HARDWARE IMPLEMENTATION OF CONTROLLED TRANSFERS:

Implementation of controlled transfer P: R2 ¬ R1

• The same clock controls the circuits that generate the control function and the destination register
• Registers are assumed to use positive-edge-triggered flip-flops
SIMULTANEOUS OPERATIONS: If two or more operations are to occur simultaneously, they are separated
with commas
P: R3← R5, MAR ← IR

• Here, if the control function P = 1, load the contents of R5 into R3, and at the same time (clock), load the
contents of register IR into register MAR

BASIC SYMBOLS FOR REGISTER TRANSFERS:

BUS AND MEMORY TRANSFERS A more efficient scheme for transferring information between
registers in a multiple-registerconfiguration is a Common Bus System.
A bus consists of a set of a common lines, one for each bit of reregister through
which binary information is transferred one at a time. Control signals determine
which reregister is selected by the bus during a particular register transfer.Different ways of constructing a
common bus system

 Using Multiplexers
 Using Tri-state Buffers
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common bus system with Multiplexers: The Multiplexers in common bus system select one of many
registers as the source register whose binary information is then placed on the bus using select inputs.
 The bus consists of four 4 x 1 multiplexers each having four data inputs, 0 through 3, and two

selection inputs, S1 and S0.

 For example, output 1 of register A is connected to input 0 of MUX 1 because this input is labelled
A1.
 The diagram shows that the bits in the same significant position in each register are connected to the
data inputs of one multiplexer to form one line of the bus.
 Thus MUX 0 multiplexes the four 0 bits of the registers, MUX 1 multiplexes the four 1 bits of the
registers, and similarly for the other two bits.
 The two selection lines Si and So are connected to the selection inputs of all four multiplexers.
 The selection lines choose the four bits of one register and transfer them into the four-line
common bus.
 When S1S0 = 00, the 0 data inputs of all four multiplexers are selected and applied to the outputs
that form the bus.
 This causes the bus lines to receive the content of register A since the outputs of this register are
connected to the 0 data inputs of the multiplexers.
 Similarly, register B is selected if S1S0 = 01, and so on.
 Table 4-2 shows the register that is selected by the bus for each of the four possible binary value of
the selection lines.

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 In general, a bus system has

 Multiplex`` K ``register
 each register of <n= bits
 to produce <n-line bus=
 no. of multiplexers required = n
 size of each multiplexer = k x 1

BUS TRANSFER IN RTL: Depending on whether the bus is to be mentioned explicitly or not, register transfer
can be indicated as either
R2 ←R1
or
BUS ←R1, R2 ←BUS
• In the former case the bus is implicit, but in the latter, it is explicitly indicated

Tri-state Buffers: Tri state buffer is a logic circuit element that has 3 states
0,1 and high impedance (output is disconnected)
The high impedance states behave like an open circuit and does not have logic significance.
 Because of this feature, a large number of three-state gate outputs can be connected with wires to
form a common bus line without endangering loading effects.

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ARITHMETIC MICROOPERATIONS:
Computer system micro-operations are of four types:
Register transfer micro-operations transfer binary information from one register to another
Arithmetic micro-operations perform arithmetic operations on Numeric data stored in registers.
Logic micro-operations perform bit manipulation operations on Non numeric data stored in
registers.
Shift micro-operations perform shift operations on data stored in Registers.

The basic arithmetic micro-operations are

Addition
Subtraction
Increment
Decrement
The additional arithmetic microoperations are
Add with carry
Subtract with borrow
Transfer/Load
etc. …

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Table: Arithmetic Micro-Operations

R3 ← R1 + R2 Contents of R1 plus R2
transferred to R3
R3 ←R1 - R2 Contents of R1 minus R2
transferred to R3
R2 ←R2’ Complement the contents
of R2
R2 ← R2’+ 1 2's complement the
contents of R2 (negate)
R3 ←R1 + R2’+ 1 subtraction
R1 ← R1 + 1 Increment
R1 ← R1 - 1 Decrement

The arithmetic Micro-operation defined by the statement below specifies the add micro-operation.
R3 ← R1 + R2
It states that the contents of R1 are added to contents of R2 and sum is transferred to R3.
To implement this statement hardware requires 3 registers and digital component that performs
addition
Subtraction is most often implemented through complementation and addition.
The subtract operation is specified by the following statement
R3 ← R1 + R2 + 1
instead of minus operator, we can write as

R2 is the symbol for the 19s complement of R2

Adding 1 to 19s complement produces 29s complement

Adding the contents of R1 to the 2's complement of R2 is equivalent to R1-R2.

Binary Adder:

Digital circuit that forms the arithmetic sum of 2 bits and the previous carry is called FULL ADDER.
Digital circuit that generates the arithmetic sum of 2 binary numbers of any lengths is called
BINARY ADDER.
Figure shows the interconnections of four full-adders (FA) to provide a 4-bit binary adder.

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The augends bits of A and the addend bits of B are designated by subscript numbers from right to
left, with subscript 0 denoting the low-order bit.
The carries are connected in a chain through the full-adders. The input carry to the binary adder
is Co and the output carry is C4. The S outputs of the full-adders generate the required sum bits.
An n-bit binary adder requires n full-adders.

Binary Adder – Subtractor:

 The addition and subtraction operations can be combined into one common circuit by including an
exclusive-OR gate with each full-adder.
 A 4-bit adder-sub tractor circuit is shown in Fig



 The mode input M controls the operation. When M = 0 the circuit is an adder and when M = 1 the circuit
becomes a sub tractor.
 Each exclusive-OR gate receives input M and one of the inputs of B
 When M = 0, we have B xor 0 = B. The full-adders receive the value of B, the input carry is 0, and
the circuit performs A plus B.
 When M = 1, we have B xor 1 = B' and Co = 1.
 The B inputs are all complemented and a 1 is added through the input carry.
The circuit performs the operation A plus the 2's complement of B.

Binary Incrementor:
The increment micro-operation adds one to a number in a register.
For example, if a 4-bit register has a binary value 0110, it will go to 0111 after it is incremented.
This can be accomplished by means of half-adders connected in cascade.
The diagram of a 4-bit 'combinational circuit incrementor is shown in Fig.

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One of the inputs to the least significant half-adder (HA) is connected to logic-1 and the other input is
connected to the least significant bit of the number to be incremented.
The output carry from one half-adder is connected to one of the inputs of the next-higher-order
half-adder.
The circuit receives the four bits from A0 through A3, adds one to it, and generates the
incremented output in S0 through S3.
The output carry C4 will be 1 only after incrementing binary 1111. This also causes outputs S0
through S3 to go to 0.
The circuit of Fig. can be extended to an n -bit binary incremented by extending the diagram to include n
half-adders.
The least significant bit must have one input connected to logic-1. The other inputs receive the number
to be incremented or the carry from the previous stage.

Arithmetic Circuit:

The basic component of an arithmetic circuit is the parallel adder.

By controlling the data inputs to the adder, it is possible to obtain different types of arithmetic
operations.

The diagram of a 4-bit arithmetic circuit is shown in Fig. It has four full-adder circuits that constitute
the 4-bit adder and four multiplexers for choosing different operations.

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There are two 4-bit inputs A and B and a 4-bit output D.

The four inputs from A go directly to the X inputs of the binary adder.

Each of the four inputs from B are connected to the data inputs of the multiplexers.

The multiplexer9s data inputs also receive the complement of B.

The other two data inputs are connected to logic-0 and logic-1.

The four multiplexers are controlled by two selection inputs S 1 and S0. The input carry Cin, goes to the carry
input of the FA in the least significant position. The other carries are connected from one stage to the next.

By controlling the value of Y with the two selection inputs S 1 and S0 and making Cin equal to 0 or 1, it is
possible to generate the eight arithmetic micro-operations listed in Table
Addition:

When S1S0= 00, the value of B is applied to the Y inputs of the adder.

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 If Cin, = 0, the output D =A+B.

 If Cin = 1, output D=A+B + 1.
Both cases perform the add micro-operation with or without adding the input carry.

Subtraction:

When S1S0 = 01, the complement of B is applied to the Y inputs of the adder.
 If Cin = 1, then D = A + B + 1. This produces A plus the 2's complement of B, which
is equivalent to a subtraction of A -B.
 When Cin = 0 then D = A + B. This is equivalent to a subtract with borrow, that is,
A-B-1.

Increment:

When S1S0 = 10, the inputs from B are neglected, and instead, all 0's are inserted into the Y inputs. The
output becomes D = A + 0 + Ci;n. This gives D = A when Cin = 0 and D = A + 1 when Cin = 1.
In the first case we have a direct transfer from input A to output D.
In the second case, the value of A is incremented by 1.

Decrement:

 When S1S0= 11, all l's are inserted into the Y inputs of the adder to produce the decrement
operation D = A -1 when Cin = 0.
 This is because a number with all 1's is equal to the 2's complement of 1 (the 2's complement of
binary 0001 is 1111). Adding a number, A to the 2's complement of 1 produces F = A + 2's complement
of 1 = A 4 1. When Cin = 1, then D = A -1 + 1=A, which causes a direct transfer from input A to output
D.

Logic Micro-operations:

 Logic microoperations specify binary operations for strings of bits stored in registers.
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 These operations consider each bit of the register separately and treat them as binary variables.
 For example, the exclusive-OR microoperation with the contents of two registers RI and R2 is
symbolized by the statement

 It specifies a logic microoperation to be executed on the individual bits of the registers provided
that the control variable P = 1.

List of Logic Microoperations:

 There are 16 different logic operations that can be performed with two binary variables.
 They can be determined from all possible truth tables obtained with two binary variables as
shown in Table 

 The 16 Boolean functions of two variables x and y are expressed in algebraic form in the first
column of Table.
 The 16 logic microoperations are derived from these functions by replacing variable x by the
binary content of register A and variable y by the binary content of register B.
 The logic micro-operations listed in the second column represent a relationship between the
binary content of two registers A and B.

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Hardware Implementation:
 The hardware implementation of logic microoperations requires that logic gates be inserted for
each bit or pair of bits in the registers to perform the required logic function.
 Although there are 16 logic microoperations, most computers use only four--AND, OR, XOR
(exclusive-OR), and complement from which all others can be derived.
 Figure shows one stage of a circuit that generates the four basic logic microoperations.
 It consists of four gates and a multiplexer. Each of the four logic operations is generated through a
gate that performs the required logic.
The outputs of the gates are applied to the data inputs of the multiplexer. The two selection inputs S1 and S0
choose one of the data inputs of the multiplexer and direct its value to the output

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Some

Applications:

 Logic micro-operations are very useful for manipulating individual bits or a portion of a word stored
in a register.
 They can be used to change bit values, delete a group of bits or insert new bits values into a register.
 The following example shows how the bits of one register (designated by A) are manipulated by
logic microoperations as a function of the bits of another register (designated by B).
 Selective set
The selective-set operation sets to 1 the bits in register A where there are corresponding l's in
register B. It does not affect bit positions that have 0's in B. The following numerical example clarifies
this operation:

 The OR microoperation can be used to selectively set bits of a register.

 Selective complement
 The selective-complement operation complements bits in A where there are corresponding 1's
in B. It does not affect bit positions that have 0's in B. For example:

 The exclusive-OR microoperation can be used to selectively complement bits of a register.

 Selective clear
 The selective-clear operation clears to 0 the bits in A only where there are

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corresponding l's in B. For example:

 The corresponding logic microoperation is

 Mask
 The mask operation is similar to the selective-clear operation except that the bits of A are
cleared only where there are corresponding O's in B . The mask operation is an AND micro
operation as seen from the following numerical example:

 Insert
 The insert operation inserts a new value into a group of bits. This is done by first masking
the bits and then ORing them with the required value.
 For example, suppose that an A register contains eight bits, 0110 1010. To replace the four
leftmost bits by the value 1001 we first mask the four unwanted bits:

 The
mask
operation is
an AND

microoperation and the insert operation is an OR microoperation.

 Clear
 The clear operation compares the words in A and B and produces an all 0's result if the two
numbers are equal. This operation is achieved by an exclusive-OR microoperation as shown by
the following example

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Shift Microoperations:
 Shift micro-operations are used for serial transfer of data.
 The contents of a register can be shifted to the left or the right.
 During a shift-left operation the serial input transfers a bit into the rightmost position.
 During a shift-right operation the serial input transfers a bit into the leftmost position.
 There are three types of shifts: logical, circular, and arithmetic.
The symbolic notation for the shift micro-operations is shown in Table

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Hardware Implementation:

 A combinational circuit shifter can be constructed with multiplexers as shown in Fig.

 The 4-bit shifter has four data inputs, A0 through A3, and four data outputs, H0 through H3.
 There are two serial inputs, one for shift left (IL) and the other for shift right (IR).
 When the selection input S=0 the input data are shifted right (down in the diagram).
 When S = 1, the input data are shifted left (up in the diagram).
 The function table in Fig. shows which input goes to each output after the shift.
 A shifter with n data inputs and outputs requires n multiplexers.
 The two serial inputs can be controlled by another multiplexer to provide the three possible types of
shifts.

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 

Arithmetic Logic Shift Unit:

 The shift micro operations are often performed in a separate unit, but sometimes the shift unit is
made part of the overall ALU.
 The arithmetic, logic, and shift circuits introduced in previous sections can be combined into one
ALU with common selection variables. One stage of an arithmetic logic shift unit is shown in Fig..
 Particular micro operation is selected with inputs S1 and S0. A 4 x 1 multiplexer at the output
chooses between an arithmetic output in Di and a logic output in Ei.
 The data in the multiplexer are selected
with inputs S3 and S2. The other two data
inputs to the multiplexer receive inputs Ai-
1 for the shift-right operation and Ai+1 for
the shift-left operation.
 The circuit whose one stage is specified
in Fig. provides eight arithmetic
operation, four logic operations, and two
shift operations.
 Each operation is selected with the five
variables S3, S2, S1, S0 and Cin.
 The input carry Cin is used for selecting
an arithmetic operation only.

 Table lists the 14 operations of the ALU. The first eight are arithmetic operations and are

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selected with S3S2 = 00.

 The next four are logic and are selected with S3S2 = 01.
 The input carry has no effect during the logic operations and is marked with don't-care x9s.
 The last two operations are shift operations and are selected with S3S2= 10 and 11.
 The other three selection inputs have no effect on the shift.

 
Basic Computer Organization and Design:

STORED PROGRAM ORGANIZATION: A computer instruction is often divided into two parts
An opcode (Operation Code) that specifies the
operation for that instruction

An address that specifies the registers and/or

locations in memory to use for that operation

In the Basic Computer, since the memory

contains 4096 (= 212) words, we need 12 bit to
specify which memory address this instruction
will use. In the Basic Computer, bit 15 of the
instruction specifies the addressing mode (0:
direct addressing, 1: indirect addressing) Since
the memory words, and hence the instructions,
are 16 bits long, that leaves 3 bits for the

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instruction’s opcode

ADDRESSING MODES: The address field of an instruction can represent either

Direct address: the address in memory of the data to use (the address of the operand), (or)

Indirect address: the address in memory of the address in memory of the data to use

Direct addressing Indirect addressing

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Common Bus System:

• Three control lines, S2, S1, and S0 control
which register the bus selects as its input
S
2 S1 S0 Register
000 x
001 AR
010 PC
011 DR
100 AC
101 IR
110 TR
111 Memory
• Either one of the registers will have its
load signal activated, or the memory will
have its read signal activated. Will
determine where the data from the bus gets
loaded the 12-bit registers, AR and PC,
have 09s loaded onto the bus in the high
order 4-bit positions. When the 8-bit
register OUTR is loaded from the bus, the
data comes from the low order 8 bits on the bus
• COMPUTER INSTRUCTIONS:

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• TIMING AND CONTROL: Control unit (CU) of a processor translates from machine instructions to
the control signals for the microoperations that implement them
• Control units are implemented in one of two ways
• Hardwired Control
3 CU is made up of
sequential and
combinational circuits to
generate the control
signals
Microprogrammed Control
3 A control memory on the
processor contains
microprograms that
activate the necessary
control signals

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Example:

INSTRUCTION CYCLE: In Basic Computer, a machine instruction is executed in the following cycle:
1. Fetch an instruction from memory
2. Decode the instruction
3. Read the effective address from memory if the instruction has an indirect address
4. Execute the instruction

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After an instruction is executed, the cycle starts again at step 1, for the next instruction

Memory reference instructions

 When the memory-reference instruction is decoded, D7 bit is set to 0.
15 14 12 11 0

I 000~110 Address

 The following table lists seven memory-reference instructions.

Symbol Operation Symbolic Description
Decoder
AND D0 AC  AC  M[AR]
ADD D1
AC  AC + M[AR], E  Cout
LDA D2 AC  M[AR]
STA D3
M[AR]  AC
BUN D4 PC  AR
BSA D5
M[AR]  PC, PC  AR + 1
ISZ D6 M[AR]  M[AR] + 1, if M[AR] + 1 = 0 then PC  PC+1

 The effective address of the instruction is in the address register AR and was placed
there during timing signal T2 when I = 0, or during timing signal T3 when I = 1.
 The execution of the memory-reference instructions starts with timing signal T4.

AND to AC
This is an instruction that performs the AND logic operation on pairs of bits in AC and the memory word
specified by the effective address. The result of the operation is transferred to AC.
D0T4: DR←M[AR]

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D0T5: AC ← AC ← DR, SC ← 0

ADD to AC
This instruction adds the content of the memory word specified by the effective address to the value of AC.
The sum is transferred into AC and the output carry Cout is transferred to the E (extended accumulator) flip-
flop.
D1T4: DR←M[AR]
D1T5: AC ←AC + DR, E ← Cout, SC 0
LDA: Load to AC
This instruction transfers the memory word specified by the effective address to AC.
D2T4: DR ← M[AR]
D2T5: AC ← DR, SC ← 0
STA: Store AC
This instruction stores the content of AC into the memory word specified by the effective address.
D3T4: M[AR] ← AC, SC ← 0
BUN: Branch Unconditionally
This instruction transfers the program to instruction specified by the effective address. The BUN instruction
allows the programmer to specify an instruction out of sequence and the program branches (or jumps)
unconditionally.
D4T4: PC ← AR, SC ← 0
BSA: Branch and Save Return Address
This instruction is useful for branching to a portion of the program called a subroutine or procedure. When
executed, the BSA instruction stores the address of the next instruction in sequence (which is available in PC)
into a memory location specified by the effective address.
M[AR] ← PC, PC ← AR + 1 M[135] ←21, PC ←135 + 1 =136

Figure Example of BSA instruction execution

It is not possible to perform the operation of the BSA instruction in one clock cycle when we use the bus
system of the basic computer. To use the memory and the bus properly, the BSA instruction must be executed
with a sequence of two microoperations:
D5T4:M[AR] ← PC, AR←AR + 1 D5T5: PC ←AR, SC ← 0
ISZ: Increment and Skip if Zero
These instruction increments the word specified by the effective address, and if the incremented value is equal
to 0, PC is incremented by 1. Since it is not possible toincrement a word inside the memory, it is necessary to
read the word into DR, increment DR, and store the word back into memory.
D6T4:DR ← M[AR] D6T5:DR←DR + 1
D6T4:M[AR] ← DR, if (DR = 0) then (PC ← PC + 1), SC ← 0
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Control Flowchart

Figure Flowchart for memory-reference instructions

Input-output configuration of basic computer

 A computer can serve no useful purpose unless it communicates with the external
environment.
 To exhibit the most basic requirements for input and output communication, we will use a
terminal unit with a keyboard and printer.

Figure: Input-output configuration

 The terminal sends and receives serial information and each quantity of information has
eight bits of an alphanumeric code.
 The serial information from the keyboard is shifted into the input register INPR.
 The serial information for the printer is stored in the output register OUTR.

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 These two registers communicate with a communication interface serially and with the
AC in parallel.
 The transmitter interface receives serial information from the keyboard and transmits it to
INPR. The receiver interface receives information from OUTR and sends it to the printer
serially.
 The 1-bit input flag FGI is a control flip-flop. It is set to 1 when new information is available
in the input device and is cleared to 0 when the information is accepted by the computer.
 The flag is needed to synchronize the timing rate difference between the input device
and the computer.
 The process of information transfer is as follows:

The process of input information transfer:

 Initially, the input flag FGI is cleared to 0. When a key is struck in the keyboard, an 8-bit
alphanumeric code is shifted into INPR and the input flag FGI is set to 1.
 As long as the flag is set, the information in INPR cannot be changed by striking another
key. The computer checks the flag bit; if it is 1, the information from INPR is transferred
in parallel into AC and FGI is cleared to 0.
 Once the flag is cleared, new information can be shifted into INPR by striking another
key.

The process of outputting information:

 The output register OUTR works similarly but the direction of information flow is
reversed.
 Initially, the output flag FGO is set to 1. The computer checks the flag bit; if it is 1, the
information from AC is transferred in parallel to OUTR and FGO is cleared to 0. The output
device accepts the coded information, prints the corresponding character, and when the
operation is completed, it sets FGO to 1.
 The computer does not load a new character into OUTR when FGO is 0 because this
condition indicates that the output device is in the process of printing the character.

Input-Output instructions
 Input and output instructions are needed for transferring information to and from AC
register, for checking the flag bits, and for controlling the interrupt facility.
 Input-output instructions have an operation code 1111 and are recognized by the control
when D7 = 1 and I = 1.
 The remaining bits of the instruction specify the particular operation.
 The control functions and microoperations for the input-output instructions are listed
below.
INP Input char. to AC
AC(0-7)  INPR, FGI  0
OUT Output char. from AC
OUTR  AC(0-7), FGO  0
SKI Skip on input flag
if(FGI = 1) then (PC  PC + 1)
SKO Skip on output flag
if(FGO = 1) then (PC  PC + 1)
ION Interrupt enable on
IEN  1
IOF Interrupt enable off
IEN  0
Table: Input Output Instructions

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 The INP instruction transfers the input information from INPR into the eight low-order
bits of AC and also clears the input flag to 0.
 The OUT instruction transfers the eight least significant bits of AC into the output
register OUTR and clears the output flag to 0.
 The next two instructions in Table 2.2 check the status of the flags and cause a skip of
the next instruction if the flag is 1.
 The instruction that is skipped will normally be a branch instruction to return and check
the flag again.
 The branch instruction is not skipped if the flag is 0. If the flag is 1, the branch instruction
is skipped and an input or output instruction is executed.
 The last two instructions set and clear an interrupt enable flip-flop IEN. The purpose of
IEN is explained in conjunction with the interrupt operation.
Interrupt Cycle
The way that the interrupt is handled by the computer can be explained by means of theflowchart shown in figure
 An interrupt flip-flop R is included in the computer.
 When R = 0, the computer goes through an instruction cycle.
 During the execute phase of the instruction cycle IEN is checked by the control.
 If it is 0, it indicates that the programmer does not want to use the interrupt, so control
continues with the next instruction cycle.
 If IEN is 1, control checks the flag bits.
 If both flags are 0, it indicates that neither the input nor the output registers are readyfor
transfer of information.
 In this case, control continues with the next instruction cycle. If either flag is set to 1
while IEN = 1, flip-flop R is set to 1.
 At the end of the execute phase, control checks the value of R, and if it is equal to 1, it
goes to an interrupt cycle instead of an instruction cycle.

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