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Mumbai University Question Papers

The document outlines the question papers for various modules of the Computer Engineering Department at Vidyavardhini’s College of Engineering & Technology, covering topics related to 8086 microprocessor, 80386 microprocessor, Pentium architecture, and associated technologies. Each module includes questions on configurations, assembly language programming, interrupt structures, and design specifications. Important points are highlighted for each module, summarizing key concepts and areas of focus for students.

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Jagruti Chavan
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0% found this document useful (0 votes)
54 views6 pages

Mumbai University Question Papers

The document outlines the question papers for various modules of the Computer Engineering Department at Vidyavardhini’s College of Engineering & Technology, covering topics related to 8086 microprocessor, 80386 microprocessor, Pentium architecture, and associated technologies. Each module includes questions on configurations, assembly language programming, interrupt structures, and design specifications. Important points are highlighted for each module, summarizing key concepts and areas of focus for students.

Uploaded by

Jagruti Chavan
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Vidyavardhini’s College of Engineering & Technology

Computer Engineering Department

Mumbai University Question Papers


Module -1
Dec-2024
1. Explain the minimum mode of 8086. (5m)
2. Explain what is ISR? How does 8086 decide the priority of interrupts. (10m)
3. Draw the timing diagrams for Read and Write operations in minimum and maximum
mode. (10m)
May-2023
1. Explain the maximum mode of 8086. (5m)
2. Draw the timing diagrams for Read and Write operations in minimum and maximum
mode. (10m)
December 2022
1. What is the advantage of Memory Banking in 8086 Processor? Justify with example.(5m)
2. Draw and explain write operation Timing diagram of 8086 Processor in Maximum mode.
(10m)
3. Explain the interrupt structure of 8086 processor. (10m)
December 2019
1. Explain memory banking in 8086. (5m)
2. Draw and explain demultiplexing of address bus in 8086. (10m)
3. Draw and explain maximum mode configuration of 8086 system. (10m)
May-2019
1. Give the advantages of memory segmentation of 8086 microprocessor. (5m)
2. Explain minimum mode configuration of 8086 microprocessor. (10m)
3. Draw and explain memory read and memory write machine cycle timing diagrams in
maximum mode of 8086. (10m)
4. Explain types of interrupts. (5m)
December-2018
1. Draw and Explain memory read machine cycle timing diagram in minimum mode of
8086. (5m)
2. Explain the maximum mode configuration of 8086 microprocessor. (10m)
3. Explain the interrupt structure of 8086 microprocessor. (10m)
4. Explain segmentation of 8086 microprocessor. Give its advantages. (10m)
Important Points –
➢ Demultiplexing of Address Bus in 8086
➢ Advantage of Memory Banking in 8086 Processor
➢ Memory Segmentation of 8086 microprocessor
➢ Interrupt Structure of 8086 processor
➢ Minimum and Maximum Mode of 8086 Block diagram explanation
➢ Timing diagrams for Read and Write Operations in Minimum and Maximum mode
Vidyavardhini’s College of Engineering & Technology
Computer Engineering Department

Module -2
Dec-2024
1. Explain the following instructions: XOR, NOP related to 8086. (5m)
2. Write an assembly language program for 8086 to exchange contents of two memory
blocks. (5m)
3. Write an ALP for 8086 to reverse a string of 10 characters (10m)
May-2023
1. Explain the following instructions: STOSB, DAA related to 8086. (5m)
2. Write an assembly language program for 8086 to exchange contents of two memory
blocks. (10m)
3. Write an ALP for 8086 to reverse a string of 10 characters. (10m)
December 2022
1. Write an assembly language program for searching a character in the given string. (5m)
2. Explain the following instructions: XLAT, DAA, LAHF, AAA related to 8086 (5m)
3. Write an ALP for 8086 to arrange 10 numbers in ascending order. (10m)
December 2019
1. Write Addressing Modes of the following instructions: (5)
1. MOV AX,[BX+SI]
2. AND CL,[2000]
3. IN AL,DX
4. JMP [BX+2]
5. ADD AX,[BX+SI+5]
2. Write a 8086 assembly language program with appropriate comments, to find if the given
year is a leap year or not. (10m)
3. Write a short note on Mixed Language Programming. (5m)
4. Explain the following instructions in 8086: LAHF and XLAT. (5m)
May-2019
1. Differentiate Procedure and Micro with example. (5m)
2. Write a short note on Mixed Language Programming. (5m)
3. Write a program to find the largest number from an array. (5m)
4. Explain different Addressing Modes of 8086 microprocessor. (10m)
December-2018
1. Write a short note on mixed language programming. (5m)
2. Differentiate Procedure and Micro. Write a program to find the factorial of a number
using procedure. (10m)
3. Explain different addressing modes of 8086 microprocessor. (10m)
Important Points
➢ All Instructions: eg. - XLAT, DAA, LAHF, AAA, STOSB, ….etc
➢ Different Addressing Modes of 8086 microprocessor
➢ Procedure and Micro with example
➢ Mixed Language Programming
➢ Assembly Language Programs for 8086
Vidyavardhini’s College of Engineering & Technology
Computer Engineering Department

Module -3
Dec-2024
1. Explain Modes of 8255 with proper diagram of each mode. (10m)
2. Design 8086 microprocessor-based on following specifications: (10m)
1. MP 8086 works at 10MHz minimum mode.
2. 16KB DROM using 4KB devices.
3. 32KB SRAM using 8KB chips.
3. Interface Interrupt controller 8259 with 8086 Microprocessor and modes of 8259. (10m)
May-2023
1. Interface DMA controller 8257 with 8086 MP. Explain different data transfer modes of
8257 DMAC (10m)
2. Explain the Initialization command words (ICWs) an Operational command word
(OCWs) of the 8259 PIC. (10m)
3. Design an 8086-based microprocessor system with the following specifications:
1. MP 8086 working at 10MHz minimum mode.
2. 32KB ROM using 8KB devices.
3. 16KB RAM using 4KB chips.
4. Explain 8255 with a block diagram and its operating modes. (10m)
December 2022
1. Dra and explain the Master Slave Mode of 8259 Processor with suitable example.
Consider Slave 8259 connected to IR0 and IR4 of master. (10)
2. Design 8086-based system for the following specifications: (10m)
1. MP 8086 working at 10MHz minimum mode.
2. 64KB ROM using 16KB Devices.
3. 32KB RAM using 16KB chips.
3. Explain Mode 2 of 8255 with a neat block diagram. Show the CWR initialization. (10m)
4. Explain the 8257 DMA controller with the help of neat diagram and explain its Control
Register Format. (10m)
December 2019
1. Explain BSR mode of 8255 PPI. (5m)
2. Design 8086-based system for the following requirements: (10m)
1. 8086 working in minimum mode with 8MHz.
2. 64KB EROM using 32KB*8 devices.
3. 128KB RAM using 64KB*8 devices.
3. Draw the block diagram of PIC 8259 and discuss its operation. (10m)
4. Draw and explain the block diagram of PIT 8253. (10m)
5. Explain Strobed Bi-directional I/O Mode 2 operation of 8255 PPI with control word and
timing diagram. (10m)
May-2019
1. Draw and explain the block diagram of 8255 Programmable Peripheral Interface (PPI)
with control word formats. (10m)
2. Design 8086-based system for the following specifications: (10m)
1. 8086 in minimum mode with clock frequency 5MHz.
Vidyavardhini’s College of Engineering & Technology
Computer Engineering Department

2. 128KB EPROM using 32KB*8 chips.


3. 32KB RAM using 16KB*8 chips.
3. Explain the operation of three 8259 PIC in cascaded mode. (10m)
December-2018
1. Give formats of initialization command words (ICWs) of 8259 PIC (5m)
2. Design 8086-based system for the following specifications: (10m)
1. 8086 in minimum mode with clock frequency 5MHz.
2. 64KB EPROM using 16KB*8 chips.
3. 16KB RAM using 8KB*8 chips.
3. Draw and explain the block diagram of 8257 DMA controller. (10m)
4. Explain the I/O mode control word format of 8255 PPI. (5m)
Important Points
➢ Design examples on an 8086-based microprocessor system.
➢ Block diagram of 8255 Programmable Peripheral Interface (PPI) explanation.
➢ I/O Mode and BSR Mode Control Word format of 8255 PPI
➢ I/O Operating Modes Operations – Mode-0, Mode-1 and Mode-2 of 8255 PPI
➢ Block diagram of DMA controller 8257 explanation
➢ Data Transfer Modes of 8257 DMAC
➢ Control Register Format of 8257 DMAC
➢ Block diagram of 8259 Programmable Interrupt Controller (PIC) explanation
➢ Initialization Command Words (ICWs) of 8259 PIC - ICW1 ICW2, ICW3, ICW4.
➢ Operational Command Words (OCWs) of the 8259 PIC – OCW1 OC2, OCW3

Module -4
Dec-2024
1. Discuss in brief the Segment Register of 80386DX. (5m)
2. Explain the implementation of Paging in protected mode of 80386. (10m)
May-2023
1. Discuss in brief the protection mechanism of 80386DX. (5m)
2. Explain the Register organization of 80386. (10m)
December 2022
1. Differentiate between Real Mode, Virtual Mode, and Protected Mode of 80386 Processor.
(5m)
2. Explain the segment descriptor of 80386 processor (10m)
3. Explain the EFLAG REGISTER of 80386 processor. (10m)
December 2019
1. Explain VM, RF, IOPL, NT and TF flags of 80386 microprocessor. (5)
2. Differentiate Real Mode, Protected Mode, and Virtual Mode of 80386 microprocessor.
(5m)
May-2019
1. Explain VM, RF, IOPL, NT and TF flags of 80386 microprocessor. (5m)
2. Differentiate Real Mode, Protected Mode, and Virtual Mode of 80386 microprocessor.
(10m)
Vidyavardhini’s College of Engineering & Technology
Computer Engineering Department

December-2018
1. Explain the FLAG REGISTER of 80386 processor. (5m)
2. Explain the modes of operation of 80386 microprocessor. (10m)

Important Points
➢ Register Organization of 80386
➢ EFLAG REGISTER of 80386 processor
➢ Control Register of 80386 processor
➢ Modes of operation of 80386 microprocessor Real Mode, Protected Mode, & Virtual
Mode.
➢ Protection Mechanism of 80386DX
➢ Segment Descriptor of 80386 processor

Module -5
Dec-2024
1. Explain in brief cache organization of Pentium processor. (5m)
2. Explain MESI protocol. (10m)
May-2023
1. Explain in brief cache organization of Pentium processor. (5m)
2. Explain MESI protocol. (10m)
December 2022
1. Explain the Floating-point pipeline of Pentium processor. (5m)
2. Explain the Branch Prediction Mechanism of Pentium processor. (10m)
December 2019
1. Explain how flushing of pipeline problem is minimized in Pentium architecture. (10m)
May-2019
2. Explain an instruction issue algorithm of Pentium processor. (5m)
3. Explain cache organization of Pentium processor. (10m)
December-2018
1. Explain the Branch Prediction logic used in Pentium processor. (10m)
2. Explain an instruction issue algorithm of Pentium processor. (5m)

Important Points
➢ Floating-point pipeline of Pentium processor
➢ Integer pipeline of Pentium processor
➢ Branch Prediction Mechanism of Pentium processor
➢ Cache Organization of Pentium processor
➢ MESI protocol of Pentium Processor
➢ Flushing of Pipeline Problem is minimized in Pentium architecture
➢ Instruction Issue Algorithm of Pentium processor
Vidyavardhini’s College of Engineering & Technology
Computer Engineering Department

Module -6
Dec-2024
1. Explain Hyper Threading technology and its use in Pentium 4. (10m)
May-2023
2. Explain Hyper Threading technology and its use in Pentium 4. (10m)
3. Compare 80386, Pentium-1, Pentium-2 and Pentium-3 Processor. (10m)
Dec-2025
1. Explain Hyper Threading technology and its use in Pentium 4. (10m)

Important Points
➢ Net burst micro architecture block diagram of Pentium 4.
➢ Hyper Threading technology and its use in Pentium 4
➢ Compare 8086, 80386, Pentium-1, Pentium-2, and Pentium-3 Processor

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