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Pipe Lining

The document outlines the structure and functioning of a CPU, detailing its responsibilities such as fetching, interpreting, and processing instructions and data. It discusses pipelining as a method to enhance instruction execution efficiency, while also addressing various pipeline hazards including resource, data, and control hazards that can impede performance. Solutions to these hazards, such as increasing resources and implementing branch prediction, are also explored.

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eldieblo30
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16 views14 pages

Pipe Lining

The document outlines the structure and functioning of a CPU, detailing its responsibilities such as fetching, interpreting, and processing instructions and data. It discusses pipelining as a method to enhance instruction execution efficiency, while also addressing various pipeline hazards including resource, data, and control hazards that can impede performance. Solutions to these hazards, such as increasing resources and implementing branch prediction, are also explored.

Uploaded by

eldieblo30
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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CPU Structure

• CPU must:
—Fetch instructions
—Interpret instructions
—Fetch data
—Process data
—Write data
Example Register Organizations
Pipelining
• Fetch instruction
• Decode instruction
• Calculate operands (i.e. EAs)
• Fetch operands
• Execute instructions
• Write result

• Overlap these operations


Two Stage Instruction Pipeline
Timing Diagram for
Instruction Pipeline Operation
Six Stage
Instruction Pipeline
Alternative Pipeline Depiction
Pipeline Hazards
• Pipeline, or some portion of pipeline, must
stall
• Also called pipeline bubble
• Types of hazards
—Resource
—Data
—Control
Resource Hazards
• Two (or more) instructions in pipeline need same resource
• Executed in serial rather than parallel for part of pipeline
• Also called structural hazard
• E.g. Assume simplified five-stage pipeline
— Each stage takes one clock cycle
• Ideal case is new instruction enters pipeline each clock cycle
• Assume main memory has single port
• Assume instruction fetches and data reads and writes performed
one at a time
• Ignore the cache
• Operand read or write cannot be performed in parallel with
instruction fetch
• Fetch instruction stage must idle for one cycle fetching I3

• E.g. multiple instructions ready to enter execute instruction phase


• Single ALU

• One solution: increase available resources


— Multiple main memory ports
— Multiple ALUs
Data Hazards
• Conflict in access of an operand location
• Two instructions to be executed in sequence
• Both access a particular memory or register operand
• If in strict sequence, no problem occurs
• If in a pipeline, operand value could be updated so as to
produce different result from strict sequential execution
• E.g. x86 machine instruction sequence:

• ADD EAX, EBX /* EAX = EAX + EBX


• SUB ECX, EAX /* ECX = ECX – EAX

• ADD instruction does not update EAX until end of stage 5,


at clock cycle 5
• SUB instruction needs value at beginning of its stage 2, at
clock cycle 4
• Pipeline must stall for two clocks cycles
• Without special hardware and specific avoidance
algorithms, results in inefficient pipeline usage
Data Hazard Diagram
Types of Data Hazard
• Read after write (RAW), or true dependency
— An instruction modifies a register or memory location
— Succeeding instruction reads data in that location
— Hazard if read takes place before write complete
• Write after read (RAW), or antidependency
— An instruction reads a register or memory location
— Succeeding instruction writes to location
— Hazard if write completes before read takes place
• Write after write (RAW), or output dependency
— Two instructions both write to same location
— Hazard if writes take place in reverse of order intended
sequence
• Previous example is RAW hazard
• See also Chapter 14
Resource Hazard Diagram
Control Hazard
• Also known as branch hazard
• Pipeline makes wrong decision on branch
prediction
• Brings instructions into pipeline that must
subsequently be discarded
• Dealing with Branches
—Multiple Streams
—Prefetch Branch Target
—Loop buffer
—Branch prediction
—Delayed branching

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