Question 1:

Define a binary search tree (BST) and explain its key properties.
Answer:
A Binary Search Tree (BST) is a binary tree in which each node contains a key such that all keys in the
left subtree are less than the node’s key, and all keys in the right subtree are greater. It supports
efficient search, insertion, and deletion operations, typically in O(log n) time for balanced trees.

Question 2:
Explain the difference between a binary tree and a binary search tree (BST). Provide an example of
each.
Answer:
A binary tree is a tree where each node has at most two children. A BST is a binary tree that follows
an order: left child < parent < right child.
Example binary tree: root(5), left(7), right(2)
Example BST: root(5), left(2), right(7)

Question 3:
Discuss the advantages and disadvantages of a singly linked list compared to an array. Provide
specific examples for each.
Answer:
Advantages: Dynamic memory use, efficient insertion/deletion at head (O(1)).
Disadvantages: No direct access (O(n)), extra memory for pointers.
Arrays allow random access (O(1)) but resizing is costly (O(n)).

Question 4:
Explain the concept of enqueue and dequeue operations in a queue.
Answer:
Enqueue adds an element to the rear of the queue, while dequeue removes an element from the
front. Queues follow the First In First Out (FIFO) principle.

Question 5:

CopyEdit

#define f(a,b) a+b

#define g(a,b) a*b

main() {

int m;

m = 2 * f(3, g(4,5));

printf("\n m is %d", m);

What is the value of m?

Answer:
Macro expands as: 2 * 3 + 4 * 5 = 6 + 20 = 26
Question 6:
How many different types of trees that can be realized are with six nodes?
Answer:
Catalan number C₆ = 132 different binary trees

Question 7:
Consider the following C declaration

CopyEdit

struct {

short s[5];

union { float y; long z; } u;

} t;

What is the memory requirement for variable t?

Answer:
s[5] = 10 bytes, union = 4 bytes ⇒ total = 14 bytes. After alignment, may be 16 bytes.

Question 8:
Find the maximum number of binary trees that can be formed with three unlabeled nodes.
Answer:
Catalan number C₃ = 5 trees

Question 9:
Suppose the numbers 7, 5, 1, 8, 3, 6, 0, 9, 4, 2 are inserted into a BST. What is the inorder traversal
sequence?
Answer:
Inorder of BST = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9

Question 10:
Find the number of pointers affected for an insertion operation in a doubly linked list.
Answer:
4 pointers (2 in the new node, 2 in adjacent nodes)

Question 11:
Output of:

CopyEdit

void funx1(struct node* head) {

if (head == NULL) return;

funx1(head->next);

printf("%d ", head->data);

}
Answer:
Prints the linked list in reverse order

Question 12:
Which algorithms among Insertion Sort, Quick Sort, Heap Sort, and Merge Sort can be used to sort a
linked list with minimum time complexity?
Answer:
Merge Sort – O(n log n), efficient for linked lists due to sequential access.

Question 13:
How many stacks are needed to implement a queue (using only stacks)?
Answer:
2 stacks

Question 14:
Direct mapped cache: size = 32KB, block size = 32B, 32-bit addresses. Calculate index and tag bits.
Answer:
Blocks = 32KB / 32B = 1024 ⇒ Index = 10 bits
Offset = 5 bits ⇒ Tag = 32 – 10 – 5 = 17 bits

Question 15:
How many 32K × 1 RAM chips are needed for 256 KB?
Answer:
256KB = 2^18 bits ⇒ Each chip = 2^15 bits ⇒ 2^18 / 2^15 = 8 chips

Question 16:
Point out how DMA can improve I/O speed.
Answer:
DMA bypasses CPU for data transfers between memory and I/O devices, reducing CPU overhead and
increasing I/O speed.

Question 17:
In a 4-way set-associative cache with 16 blocks total, if the access order is given, which block will NOT
be in cache using LRU?
Answer:
Simulate Least Recently Used (LRU) replacement policy. The block that was not recently accessed
within the set will be evicted. Specific answer depends on access sequence.

Question 18:
How many bits are in the tag field of a 256 KB 4-way set-associative cache with 32-byte blocks and
32-bit memory address?
Answer:
Block offset = log₂(32) = 5 bits
Total blocks = 256KB / 32 = 8192
Number of sets = 8192 / 4 = 2048 = 2¹¹
Index bits = 11
Tag bits = 32 - 11 - 5 = 16 bits

Question 19:
Illustrate the advantages of virtual memory.
Answer:
 • Allows processes to use more memory than physically available

• Provides memory protection

• Enables multitasking

• Simplifies memory management for programmers

Question 20:
Define hit ratio.
Answer:
Hit ratio = (Number of cache hits) / (Total memory accesses)

Question 21:
How many address bits are needed to access 1 GB memory with 32-bit word addressing?
Answer:
1 GB = 2³⁰ bytes; each word = 4 bytes ⇒ 2³⁰ / 2² = 2²⁸ words ⇒ 28 address bits

Question 22:
Illustrate memory hierarchy with an example.
Answer:
Registers (fastest, smallest) → Cache → Main Memory → Secondary Storage → Tertiary Storage
E.g., CPU registers (1 ns), L1 cache (2–5 ns), RAM (50–100 ns), SSD/HDD (ms)

Question 23:
Explain page replacement algorithms and their operations.
Answer:
Algorithms: FIFO, LRU, Optimal
Operation: On page fault, choose a page to evict, bring in the required page, and update page table.

Question 24:
Design direct-mapped cache: 16KB size, 256B block, main memory = 128KB
Answer:
Cache blocks = 16KB / 256 = 64
Index bits = log₂(64) = 6
Memory blocks = 128KB / 256 = 512
Tag bits = log₂(512) - 6 = 3
Directory = 64 entries with tag and valid bits

Question 25:
Which data structure is used in DFS traversal of a graph?
Answer:
Stack

Question 26:
Minimum spanning tree weight of G with edge weight 2|i-j|
Answer:
MST connects nodes in a chain ⇒ Total weight = 2(n – 1)

Question 27:
What are the advantages of DBMS over traditional file systems?
Answer:
 • Reduced data redundancy

• Data consistency

• Improved data security

• Easy backup and recovery

• Concurrent access

Question 28:
Differentiate between primary key and unique constraint.
Answer:
Primary key: Uniquely identifies each record, cannot be null
Unique constraint: Enforces uniqueness but allows one null

Question 29:
What is database normalization?
Answer:
Process of structuring a database to reduce redundancy and improve data integrity through various
normal forms (1NF, 2NF, 3NF, etc.)

Question 30:
Differentiate DDL, DML, DCL.
Answer:

• DDL: Data Definition Language (CREATE, ALTER)

• DML: Data Manipulation Language (SELECT, INSERT)

• DCL: Data Control Language (GRANT, REVOKE)

Question 31:
Difference between HAVING and WHERE clause.
Answer:
WHERE filters rows before grouping; HAVING filters groups after aggregation.

Question 32:
SQL query to print duplicate rows from a table.
Answer:

sql

CopyEdit

SELECT column, COUNT(*)

FROM table

GROUP BY column

HAVING COUNT(*) > 1;

Question 33:
What is Identity in SQL?
Answer:
An identity column auto-increments with each insert, providing unique values.

Question 34:
What is a view in SQL? How to create it?
Answer:
A virtual table based on a SELECT query.

sql

CopyEdit

CREATE VIEW view_name AS

SELECT column1, column2 FROM table_name;

Question 35:
What is a trigger?
Answer:
A database object that automatically executes a specified action in response to certain events on a
table (INSERT, UPDATE, DELETE)

Question 36:
What is a stored procedure?
Answer:
A compiled set of SQL statements stored in the database and executed as a program.

Question 37:
What are ACID properties?
Answer:

• Atomicity

• Consistency

• Isolation

• Durability
These ensure reliable and secure transactions in a DBMS.

Question 38:
Compare clustered and non-clustered indexes.
Answer:
Clustered: Sorts data rows physically; one per table
Non-clustered: Separate structure; can be many per table

Question 39:
What is denormalization?
Answer:
The process of introducing redundancy into a database for performance optimization by combining
tables or adding derived columns.

Question 40:
Difference between schema and state in DBMS.
Answer:
Schema: Structure/design of the database
State: Actual content/data at a particular point in time

Question 41:
Explain primary key and foreign key with an example.
Answer:
Primary key uniquely identifies records;
Foreign key links to primary key in another table, ensuring referential integrity.

Question 42:
What is a sub-query?
Answer:
A query nested within another SQL query to perform operations like filtering, computation, or
selection.

Question 43:
Differentiate DROP, TRUNCATE, DELETE.
Answer:

• DROP: Removes table structure and data

• TRUNCATE: Removes all rows, can’t rollback

• DELETE: Removes selected rows, can rollback

Question 44:
Differentiate UNION and UNION ALL.
Answer:

• UNION: Removes duplicates

• UNION ALL: Includes all rows, including duplicates

Question 45:
Explain Entity, Entity Type, and Entity Set.
Answer:

• Entity: Real-world object

• Entity Type: Category of entities

• Entity Set: Collection of entities of the same type

Question 46:
What are levels of abstraction in DBMS?
Answer:

• Physical Level: How data is stored

• Logical Level: What data is stored

• View Level: How users see data

Question 47:
Which statements are true for string w ∈ L(G) defined by S → aS | aSbS | c?
Answer:
(i) w contains more a’s than b’s
(ii) w starts with a and ends with b
(iii) w contains equal number of a’s and b’s
Correct: (iii)

Question 48:
L2: strings of length 4 over {0,1}; L1: strings of form 0(0+1)*0 or 1(0+1)*1
Find L2 ∩ L1.
Answer:
List all 2⁴ = 16 strings and check against both regexes. Count strings matching both.

Question 49:
Find strings of length ≤ 4 not in L(r) or L(s), r = 0* + 1*, s = 01* + 10*
Answer:
List all 2⁴ = 16 strings. Remove those matching either pattern.

Question 50:
Which of the following statements is true?
A. CFLs are not closed under intersection
B. CFLs are not closed under union
C. Regular languages are closed under union
D. CFLs are closed under concatenation
Answer:
Correct statements: A, C, D

Question 51:
Which of the following sets are uncountable?
S1: Set of all recursively enumerable languages
S2: Set of all valid C programs
S3: Set of all languages over {0,1}
S4: Set of non-regular languages over {0,1}
Answer:
S1 and S2 are countable; S3 and S4 are uncountable.
Correct: S3 and S4

Question 52:
Which of the following languages are context-free?
L1 = {aⁿbⁿaⁿ}
L2 = {aⁿbⁿcⁿ | n ≥ 1}
L3 = {aⁿbᵐcⁿ | n, m ≥ 1}
L4 = {aⁿbⁿ | n ≥ 0}
Answer:
L1 and L2 are not context-free
L3 and L4 are context-free
Correct: L3 and L4

Question 53:
Regular expression for strings with even number of a’s and odd number of b’s.
Answer:
Complex RE not practical; not regular due to dependency on parity. Language is not regular.

Question 54:
Define left recursion and how to eliminate it.
Answer:
Left recursion: A → Aα | β
To eliminate:
A → βA’
A’ → αA’ | ε

Question 55:
Grammar for even-length palindromes over {0,1}.
Answer:
S → 0S0 | 1S1 | ε

Question 56:
Grammar for strings of odd length with middle symbol 0.
Answer:
S → 0 | 0S0 | 1S1
Ensure odd length and center 0

Question 57:
Grammar for strings that start and end with the same symbol over {a,b,c}.
Answer:
S → aXa | bXb | cXc | a | b | c
X → aX | bX | cX | ε

Question 58:
Difference between Deterministic PDA and Non-deterministic PDA.
Answer:
DPDA: One possible move per input-symbol and state
NPDA: Multiple possible moves
NPDA can recognize more languages (e.g., palindromes)

Question 59:
Techniques to simplify a grammar.
Answer:

• Remove null (ε) productions

• Remove unit productions

• Remove useless symbols

• Convert to CNF or GNF

Question 60:
What is a unit production and how is it removed?
Answer:
A → B (non-terminal to non-terminal)
Remove by replacing A → RHS of B
Question 61:
Define a useless symbol and how to remove it.
Answer:
A symbol that does not lead to a terminal string or is never reached from the start symbol.
Remove:

1. Identify generating symbols

2. Remove non-generating and unreachable symbols

Question 62:
Compare CNF and GNF.
Answer:

• CNF: A → BC or A → a

• GNF: A → aα (starts with terminal)

GNF used in top-down parsing; CNF in CYK parsing.

Question 63:
How to remove ε-productions from a CFG?
Answer:

1. Identify nullable variables

2. Add new productions without nullable symbols

3. Remove ε-productions except for start symbol

Question 64:
Classify languages in Chomsky hierarchy.
Answer:

• Equal 0s and 1s: CFL

• Each ‘a’ followed by at least one ‘b’: Regular

• Palindromes: CFL

• Number of a’s = 2×b’s: Context-sensitive

Question 65:
Significance of Turing machines and their limitations.
Answer:
TMs can model any algorithm; they define recursively enumerable languages.
Limitations: Can’t solve undecidable problems (e.g., Halting problem)

Question 66:
High-speed memory between CPU and main memory.
Answer:
Cache memory

Question 67:
Memory holding boot sector files.
Answer:
ROM (BIOS)

Question 68:
How is virtual address mapped to physical memory?
Answer:
Through page tables and memory management unit (MMU)

Question 69:
CPU interrupt overhead = 2µs, 9 cycles @ 2MHz.
Answer:
9 cycles = 9 × 0.5µs = 4.5µs
Total overhead = 2 + 4.5 = 6.5µs

Question 70:
Avg. access time = 45ns; T1 = 30ns, T2 = 150ns. What is hit rate?
Answer:
45 = h×30 + (1–h)×150
Solving: h = 0.875

Question 71:
DMA: 16 bytes in 2µs; CPU @ 2MHz ⇒ CPU blocked how much?
Answer:
Time per byte = 0.125µs
CPU blocked for 2µs per 16B ⇒ Total ≈ 0.5% of CPU

Question 72:
DRAM with 16 address lines ⇒ Addressable range?
Answer:
2¹⁶ = 64KB ⇒ Address range: 0000H to FFFFH

Question 73:
Stack after operations: PUSH(10), PUSH(20), POP, etc.
Answer:
Top of stack sequence: 10 → 20 → POP → 10 → etc.

Question 74:
BST insertion order = 7,5,1,8,... ⇒ Inorder traversal?
Answer:
Inorder = 0,1,2,3,4,5,6,7,8,9

Question 75:
Output of C code with static, global, local variables.
Answer:
Depends on initializations, likely prints 115 and 100

Question 76:
Advantages of shared dynamically linked libraries.
Answer:

• Reduced memory usage

• Smaller executables
 • Centralized updates

• Efficient program loading

Question 77:
Recursive function output with static variable i.
Answer:
Function increments i and n recursively
Returns: 21

Question 78:
Prove L = {aⁿ²} is not regular.
Answer:
Use pumping lemma. Pushed string breaks form aⁿ² when pumped ⇒ not regular

Question 79:
Prove regular languages are closed under concatenation.
Answer:
Construct DFA from L1 and L2 using ε-transitions ⇒ Result is regular

Question 80:
What is a dead state in automata?
Answer:
A non-accepting state from which no accepting state is reachable.

Question 81:
What is an instruction cycle?
Answer:
Cycle of fetch → decode → execute → memory access → write-back

Question 82:
Function of ALU.
Answer:
Performs arithmetic and logic operations (add, subtract, AND, OR)

Question 83:
Difference between computer organization and architecture.
Answer:

• Architecture: Features visible to programmer (ISA)

• Organization: Hardware implementation of those features

Question 84:
Differentiate RISC and CISC.
Answer:

• RISC: Few simple instructions, faster

• CISC: Complex instructions, slower

Question 85:
Stages in instruction cycle.
Answer:
Fetch → Decode → Execute → Memory Access → Write-back

Question 86:
What is pipelining?
Answer:
Technique where multiple instruction stages are overlapped for faster execution.

Question 87:
Define cache memory.
Answer:
A small, fast memory storing frequently accessed data close to CPU.

Question 88:
What is virtual memory?
Answer:
A memory abstraction that allows programs to use more memory than physically available using
paging.

Question 89:
Harvard vs Von Neumann architecture.
Answer:

• Harvard: Separate memory for data and instructions

• Von Neumann: Unified memory

Question 90:
What is a Program Counter (PC)?
Answer:
Register holding the address of the next instruction to execute.

Question 91:
Types of addressing modes.
Answer:
Immediate, Direct, Indirect, Register, Indexed, Relative

Question 92:
What is an interrupt?
Answer:
A signal that temporarily halts the current process to handle external/internal events.

Question 93:
Convert (47.625)₁₀ to binary.
Answer:
47 = 101111
0.625 = .101
Result = 101111.101

Question 94:
Find 2’s complement of 110101.
Answer:
Invert: 001010, Add 1 ⇒ 001011
Question 95:
EAT = ? Hit = 90%, Cache = 10ns, Memory = 100ns
Answer:
EAT = 0.9×10 + 0.1×100 = 19 ns

Question 96:
Address lines for 1MB memory.
Answer:
1MB = 2²⁰ ⇒ 20 lines

Question 97:
Physical address if base = 4000H, offset = 200H
Answer:
Physical address = 4200H

Question 98:
Addresses needed for 2540 bytes.
Answer:
log₂(2540) ≈ 12 bits

Question 99:
What is DMA?
Answer:
Direct Memory Access – data transfer between I/O and memory without CPU

Question 100:
Application of Serial Access Memory
Answer:
Used in tape storage, FIFO buffers, and sequential access memory

Question 101:
How to put a microprocessor in a Wait state?
Answer:
A microprocessor enters a Wait state when the READY signal is held low. During this time, the
processor pauses execution until READY is set high again by a slower peripheral or memory device.

Question 102:
Explain the following instructions:
(i) RST
(ii) LXI
Answer:
(i) RST (Restart): Equivalent to a subroutine call to a fixed memory location. For example, RST 1
jumps to address 0008H.
(ii) LXI (Load Register Pair Immediate): Loads a 16-bit immediate value into a register pair. For
example, LXI H, 2050H loads 2050H into HL.

Question 103:
Explain the following instructions:
(i) JMP
(ii) DAA
Answer:
(i) JMP (Jump): An unconditional jump to a specified memory address. For example, JMP 2050H
transfers control to address 2050H.
(ii) DAA (Decimal Adjust Accumulator): Adjusts the contents of the accumulator into BCD after a
binary addition.

Question 104:
What is the sequence of events during a Fetch operation?
Answer:

1. Program Counter places address on address bus

2. Memory decoder selects the memory location

3. Memory places instruction on the data bus

4. Instruction Register loads the instruction

5. Program Counter increments to point to the next instruction

Question 105:
Differentiate between PLA and ROM.
Answer:

• PLA (Programmable Logic Array): Has programmable AND and OR planes; more flexible;
used to implement logic functions.

• ROM (Read-Only Memory): Has fixed AND plane and programmable OR plane; generally
used for storage, not logic flexibility.

• Question 106:
Let T(n) be the number of BSTs on n elements. Analyze the value of T(n).
Answer:
T(n) = Catalan number = (2n)! / ((n+1)!n!)
Used to count the number of structurally unique BSTs.
• Question 107:
Find the postfix form of the expression A + B * (C + D) / E + F * G.
Answer:
Postfix: A B C D + * E / + F G * +
• Question 108:
What is the inorder traversal for a BST built using the postorder:
10,9,23,22,27,25,15,50,95,60,40,2?
Answer:
Build the BST from postorder, then do inorder traversal. Inorder gives: 2, 9, 10, 15,
22, 23, 25, 27, 40, 50, 60, 95
• Question 109:
Evaluate the postfix expression: 8 2 3 ^ / 2 3 * + 5 1 * –
Answer:
 Step-by-step:
23^=8
8/8=1
23*=6
1+6=7
51*=5
7–5=2
• Question 110:
What is the output of the following recursive function working on even/odd logic?
Answer:
Assuming it alternates subtraction and addition based on parity, the result is: Depends
on input, but generally alternates signs.
• Question 111:
What does the recursive function fun(n, *fp) do with Fibonacci logic?
Answer:
Calculates Fibonacci number recursively and stores result via pointer.
For input 5, output is 8 (6th Fibonacci number including 0).
• Question 112:
What correction is needed in binary search code?
Answer:
On line 6, change i = k; to i = k + 1; to avoid infinite loop if i == k.
• Question 113:
Find the postorder traversal from the preorder: 15,10,12,11,20,18,16,19
Answer:
Build BST → postorder = 11,12,10,16,19,18,20,15
• Question 114:
Write an algorithm to reverse a singly linked list.
Answer:
• c
• CopyEdit
• Node* reverse(Node* head) {
• Node* prev = NULL;
• Node* current = head;
• Node* next;
• while(current) {
• next = current->next;
• current->next = prev;
• prev = current;
• current = next;
• }
• return prev;
• }
• Question 115:
Write an algorithm to delete an element from a singly linked list.
Answer:
• c
• CopyEdit
• Node* delete(Node* head, int key) {
• if (!head) return NULL;
• if (head->data == key) return head->next;
• Node* temp = head;
• while (temp->next && temp->next->data != key)
• temp = temp->next;
• if (temp->next) temp->next = temp->next->next;
• return head;
• }
• Question 116:
Algorithm to sort a singly linked list in descending order.
Answer:
Use Merge Sort or Bubble Sort:
Traverse, compare, and swap node values or re-link nodes accordingly.
• Question 117:
Write an algorithm to detect if a circular queue is full or empty.
Answer:
• c
• CopyEdit
• bool isFull() { return (rear + 1) % size == front; }
• bool isEmpty() { return rear == front; }
• Question 118:
If 3 elements are inserted into a hash table with 100 slots using chaining, what is the
probability that the first 3 slots are unfilled?
Answer:
Prob = (97/100) × (96/100) × (95/100) ≈ 0.885
• Question 119:
How many 1024×1 RAM chips are needed to provide 16KB of storage?
Answer:
16KB = 16 × 1024 × 8 = 131072 bits ⇒ 131072 / 1024 = 128 chips
• Question 120:
Cache: 4-way set-associative, 1024 words, block = 4 words. Find number of sets and
index bits.
Answer:
Blocks = 1024 / 4 = 256
Sets = 256 / 4 = 64
Index bits = log₂(64) = 6
• Question 121:
Given T1 = 4ns (hit), main memory = 100ns, VM = 10ms. Hit rate = 70%, second
level hit = 99.5%.
Answer:
Avg access = 0.7×4 + 0.3×(0.995×100 + 0.005×10⁶) =
= 2.8 + 29.85 + 1500 = ~1532.65ns
• Question 122:
In a system with 2GB memory and 2K word cache with 16-word blocks, find number
of sets.
Answer:
Cache blocks = 2048 / 16 = 128
Direct-mapped: 128 sets
Set-associative depends on level of associativity
• Question 123:
Direct mapped cache: 32KB, 32B block, 32-bit address. Find tag bits.
Answer:
Block offset = 5
 Index = log₂(32KB / 32B) = 10
Tag = 32 – 10 – 5 = 17 bits
• Question 124:
How much time is needed to refresh a 4MB DRAM with 100ns/row?
Answer:
4MB = 2²² bits
Rows = 2¹⁰ (assuming 1K×1K structure)
Time = 2¹⁰ × 100ns = 102.4μs
• Question 125:
What are the tag, index, and offset bits for a 4-way 16KB cache with 64B blocks and
32-bit address?
Answer:
Blocks = 16KB / 64 = 256
Sets = 256 / 4 = 64 ⇒ Index = 6
Offset = 6
Tag = 32 – 6 – 6 = 20 bits
• Question 126:
DFA for language L = {w | number of a’s = number of b’s + 1}
Answer:
Language is not regular ⇒ DFA not possible
• Question 127:
DFA accepting strings with even number of 0s and 1s
Answer:
Requires 4 states to track parity: (even, even), (even, odd), etc.
• Question 128:
L(G): S → aSb | X; X → aX | Xb | a | b
Answer:
L(G) = set of strings with equal numbers of a’s and b’s ⇒ Not regular
• Question 129:
DFA for strings not having substring “111”
Answer:
Minimum 4 states: Track last two inputs to reject on third 1
• Question 130:
Which problems are undecidable?
A. L(M₁) = L(M₂)
B. Whether M is regular
C. M accepts all strings
D. M halts in >1073 steps
Answer:
All are undecidable

Question 131:
Give regular expression and CFG for L = {x ∈ {0,1}* | x starts and ends with different symbols}
Answer:
Regular Expression: 0(0+1)*1 + 1(0+1)*0
CFG:
S → 0A1 | 1A0
A → 0A | 1A | ε
Question 132:
Give RE and DFA for language L = strings ending in 1 and not containing “00”
Answer:
Regular Expression: (1 + 01)*1
DFA: 3 states tracking last bit, rejecting “00”

Question 133:
Construct NFA for strings with at least two 1’s.
Answer:
Start → 1 → q1 → 1 → Accept
Allow any combination in between

Question 134:
NFA for strings that start and end with same symbol over {a,b}
Answer:
States for start symbol, allow any number in middle, transition to accepting state if last symbol
matches start.

Question 135:
Closure properties of languages:

Operation Regular CFL CSL RE

Union

Intersection

Concatenation

Kleene Star

Question 136:
Avg read time = 10ns, hit = 90%; memory access = 50ns
Answer:
EAT = 0.9×10 + 0.1×50 = 14ns

Question 137:
DMA controller steals 0.5% CPU cycles, 2MHz CPU. Data rate?
Answer:
0.005 × 2,000,000 = 10,000 bytes/sec

Question 138:
In a direct mapped cache, if TAG = 10 bits and changed to 16-way, what’s the new TAG size?
Answer:
Decrease index bits by 4 (log₂(16)) ⇒ New TAG = 10 + 4 = 14 bits

Question 139:
DMA: 16-bit data @2400cps; CPU @1 MIPS. CPU slowdown?
Answer:
DMA operations = 2400 × 1 = 2400 instructions
Slowdown = 2400 / 1,000,000 = 0.24%
Question 140:
Difference between isolated I/O and memory-mapped I/O
Answer:
Isolated: Separate address space; special instructions
Memory-mapped: I/O uses same address space as memory; standard instructions used

Question 141:
Instruction count = 1 million, CPI = 2, clock = 2ns. Execution time?
Answer:
1M × 2 × 2ns = 4ms

Question 142:
How is cache mapping done?
Answer:
Using techniques like direct mapping, associative mapping, and set-associative mapping.

Question 143:
Give logic to print top 5 customers who spent most in last 6 months.
Answer:

sql

CopyEdit

SELECT customer_id, SUM(amount)

FROM purchases

WHERE date >= CURRENT_DATE - INTERVAL '6 months'

GROUP BY customer_id

ORDER BY SUM(amount) DESC

LIMIT 5;

Question 144:
Explain 8085 architecture
Answer:
8-bit microprocessor with 16-bit address bus, accumulator, ALU, general-purpose registers, program
counter, stack pointer, and control unit.

Question 145:
Discuss RISC design and working
Answer:
Simple instructions, single clock cycle per instruction, load/store architecture, large register set.

Question 146:
Explain memory mapping techniques
Answer:

• Direct mapping

• Associative mapping
 • Set-associative mapping
They define how cache lines are filled and accessed.

Question 147:
Show string pumping beyond FA state count
Answer:
In a DFA with n states, any string of length > n must repeat a state ⇒ can be pumped per the
pumping lemma.

Question 148:
Why is BCNF stricter than 3NF?
Answer:
BCNF requires every non-trivial FD to have a superkey as LHS.
3NF allows non-superkeys if RHS is a prime attribute.

Question 149:
Canonical cover may not be unique – prove with example.
Answer:
FDs: A → B, A → C can be combined to A → BC
Or kept separate. Both are minimal ⇒ multiple canonical covers possible

Question 150:
Given FDs on R(A,B,C,D,E,F,...), find candidate key
Answer:
Use attribute closure method on combinations until full attribute set is covered.

Question 151:
What is instruction format with examples?
Answer:
Defines structure: opcode, operands
Examples:

• 3-address: ADD R1, R2, R3

• 2-address: MOV R1, R2

• 1-address: ADD M

• 0-address: Stack machines

Question 152:
Explain pipelining and hazards
Answer:
Pipelining: overlapping instruction stages
Hazards:

• Data

• Structural

• Control
Handled using forwarding, stalls, prediction
Question 153:
Memory hierarchy
Answer:
Registers > Cache > RAM > SSD > HDD
Higher in hierarchy = faster, smaller, costlier

Question 154:
SRAM vs DRAM
Answer:

• SRAM: Fast, no refresh, costly

• DRAM: Slower, needs refresh, cheaper

Question 155:
Types of ROM
Answer:

• PROM: Programmable once

• EPROM: Erasable via UV

• EEPROM: Electrically erasable

Question 156:
Function of DMA
Answer:
Transfers data directly between I/O and memory, bypassing CPU to improve efficiency.

Question 157:
Types of Buses
Answer:

• Address bus: Sends addresses

• Data bus: Carries data

• Control bus: Carries control signals

Question 158:
In 4GB RAM system, how many addressable locations?
Answer:
4GB = 2³² locations ⇒ 4,294,967,296 addresses

Question 159:
Cache hit = 80%, time = 5ns; memory = 50ns ⇒ avg access?
Answer:
0.8×5 + 0.2×50 = 4 + 10 = 14ns

Question 160:
Disk @ 7200 RPM, avg seek time = 9ms ⇒ avg access time?
Answer:
Rotation = 60/7200 = 8.33ms
Avg rotation delay = 4.17ms
Total = 9 + 4.17 = 13.17ms

Question 161:
16-bit instruction, 32 registers. Opcode bits?
Answer:
Registers = 5 bits each ⇒ 2×5 = 10
Opcode = 16 – 10 = 6 bits

Question 162:
How many 256K × 1 chips to make 2MB memory?
Answer:
2MB = 2 × 1024 × 1024 = 2,097,152 bits
256K = 262,144 bits ⇒ 2,097,152 / 262,144 = 8 chips

Question 163:
Difference: Control vs Data vs Address Registers
Answer:

• Control: Hold status/command (e.g., IR)

• Data: Temporarily hold data

• Address: Hold memory addresses (e.g., MAR)

Question 164:
Address, data, and control bus functions
Answer:

• Address: Carries addresses

• Data: Carries data to/from memory

• Control: Signals for read/write, clock, interrupt

Question 165:
Cache 10× faster than memory, used 90% ⇒ speed gain?
Answer:
Avg = 0.9×1 + 0.1×10 = 1.9 ⇒ Speedup = 10 / 1.9 ≈ 5.26×

Question 166:
Program reads 500 scores, finds frequency > 50 ⇒ how?
Answer:
Use array[101] to store frequency of scores 0–100.
Scan 51–100 to find required count.

Question 167:
Worst-case time for search in BST
Answer:
If unbalanced: O(n)

Question 168:
Priority Queue (Max-Heap): insert 1 and 7 ⇒ final heap?
Answer:
Maintain heap after insertion ⇒ Max-Heap: 10, 8, 7...

Question 169:
Move last node to head in SLL
Answer:
Traverse to second last node, point its next to NULL, set last’s next to head, update head

Question 170:
Parse tree of (7 ↓ 343 ↓ 2), ↓ < ^ precedence
Answer:
Evaluate: 343 ↓ 2 first, then 7 ↓ result
Assuming ↓ = root, expression groups from right to left

Question 171:
Function foo(345,10), foo(513,2) returns sum of digits
Answer:
345 base 10: 3+4+5 = 12
513 base 2: 1000000001 ⇒ sum = 2

Question 172:
Merge sort min and max comparisons for n = power of 2
Answer:
Min = n log₂ n – n + 1
Max = n log₂ n

Question 173:
Canonical cover and use in normalization
Answer:
Minimized set of FDs used to:

• Check decomposition

• Reduce redundancy

• Preserve dependencies

Question 174:
How to find candidate keys?
Answer:
Compute closures of combinations of attributes using FDs until you get full attribute set.

Question 175:
What is lossless join decomposition?
Answer:
Splitting relation into sub-relations so that original relation can be reconstructed by natural join.

Question 176:
Types of addressing modes with examples.
Answer:

• Immediate: Operand is part of instruction (e.g., MOV A, #5)

• Direct: Address is given directly (e.g., MOV A, 2000H)

 • Indirect: Address found via register (e.g., MOV A, @R0)

• Register: Operand in register (e.g., MOV A, R1)

• Indexed: Base + offset (e.g., MOVX A, @DPTR)

Question 177:
How does cache memory work? Describe mapping.
Answer:
Stores frequently accessed data near CPU.
Mappings:

• Direct mapping: One-to-one mapping

• Associative: Any block to any line

• Set-associative: Block to set, then any line within

Question 178:
Difference between hardwired and microprogrammed control.
Answer:

• Hardwired: Uses fixed logic; faster

• Microprogrammed: Uses control memory; flexible

Question 179:
Explain the instruction cycle diagram.
Answer:
Stages:

1. Fetch

2. Decode

3. Execute

4. Memory access

5. Write back

Question 180:
What is pipelining in processor?
Answer:
Executing multiple instructions in overlapping phases. Increases throughput.

Question 181:
Explain memory hierarchy.
Answer:
Registers → Cache → RAM → SSD → HDD
Trade-off: Speed vs Size vs Cost

Question 182:
Difference between SRAM and DRAM.
Answer:
 • SRAM: Fast, no refresh, costly, used in cache

• DRAM: Slower, needs refresh, used in main memory

Question 183:
Different types of ROM.
Answer:

• PROM: Programmable once

• EPROM: Erasable via UV

• EEPROM: Electrically erasable

Question 184:
What is DMA and its role?
Answer:
DMA = Direct Memory Access; allows devices to access memory directly without CPU involvement.

Question 185:
Types of buses and their functions.
Answer:

• Address bus: Carries memory addresses

• Data bus: Carries data

• Control bus: Carries control signals

Question 186:
In a 4GB RAM system, how many addressable locations exist?
Answer:
4GB = 2³² ⇒ 4,294,967,296 addressable locations

Question 187:
Hit ratio = 80%, cache access = 5ns, MM = 50ns ⇒ Avg time?
Answer:
EAT = 0.8×5 + 0.2×50 = 4 + 10 = 14ns

Question 188:
Disk @7200 RPM, seek time = 9ms ⇒ Avg access time?
Answer:
Rotational latency = 60/7200 = 8.33ms ⇒ half = 4.17ms
Total = 9 + 4.17 = 13.17ms

Question 189:
Instruction = 16 bits, 32 registers ⇒ Bits for opcode?
Answer:
Register = 5 bits each ⇒ 2×5 = 10
Opcode = 16 – 10 = 6 bits

Question 190:
256K × 1 bit RAM ⇒ How many chips needed for 2MB?
Answer:
2MB = 16,777,216 bits
Chips = 16,777,216 / 262,144 = 64 chips

Question 191:
Differences: Control, Data, Address registers
Answer:

• Control: Manage processor states

• Data: Store values being processed

• Address: Store memory addresses

Question 192:
Functions of address, data, and control buses.
Answer:

• Address: Identifies memory location

• Data: Carries actual data

• Control: Manages operations (read/write)

Question 193:
Cache 10× faster than memory, used 90% ⇒ speedup?
Answer:
Access = 0.9×1 + 0.1×10 = 1.9 units
Speedup = 10 / 1.9 ≈ 5.26×

Question 194:
Program reads 500 scores, range 0–100 ⇒ find frequency > 50
Answer:
Use array of size 101; increment index by value.
Count sum from index 51–100.

Question 195:
Worst-case search time in BST.
Answer:
O(n) for skewed (unbalanced) BST

Question 196:
Max-Heap insert 1, then 7. Final heap (level order)?
Answer:
Maintain max-heap after insert:
Heap → 10, 8, 7...

Question 197:
Move last node to head in singly linked list.
Answer:
Traverse to last and second-last, set second-last’s next to NULL, last’s next to head, head = last

Question 198:
Parse tree of (7 ↓ 343 ↓ 2); ↓ precedence < ^
Answer:
Evaluate 343 ↓ 2 first, then apply ↓ to 7 and result (right associative)

Question 199:
foo(345,10), foo(513,2): returns sum of digits
Answer:
foo(345,10): 3 + 4 + 5 = 12
foo(513,2): Binary = 1000000001 ⇒ Sum = 2

Question 200:
Merge sort comparisons when n is power of 2
Answer:

• Min: n log₂n – n + 1

• Max: n log₂n

Question 201:
Postorder from preorder: 30,20,10,15,25,23,39,35,42
Answer:
Build BST → postorder = 15,10,23,25,20,35,42,39,30

Question 202:
Prove sum of degrees = 2×edges in graph
Answer:
Each edge contributes 1 to degree of both vertices ⇒ total = 2 × E

Question 203:
Preorder from postorder: 3,5,7,9,4,17,16,20,18,15,14 (BST)
Answer:
Rebuild BST, then traverse ⇒ Preorder = 14,4,3,5,9,7,15,18,16,17,20

Question 204:
Construct FA for substrings 101 and 00101
Answer:
Create 2 separate DFAs and combine with union for either substring acceptance.

Question 205:
Design FA substring search algorithm.
Answer:
Use KMP prefix function; build automaton that matches substring characters in sequence.

Question 206:
DFA accepting strings ending with 01
Answer:
3 states: start → 0 → q1 → 1 → Accept

Question 207:
Convert NFA for “ends with 01” to DFA
Answer:
Use subset construction method on states to build equivalent DFA
Question 208:
DFA: ≥ two 0s
Answer:
3 states: q0 (0s=0), q1 (1 zero), q2 (≥2 zeros)

Question 209:
DFA: strings not ending in 01
Answer:
4 states tracking last two bits; reject if ends in 01

Question 210:
DFA: even number of 0s and even number of 1s
Answer:
States = 4: (even0, even1), (odd0, even1), (even0, odd1), (odd0, odd1)

Question 211:
DFA for aⁿb where n ≥ 0
Answer:
Start: loop on a, one transition to accepting state on b

Question 212:
DFA for strings divisible by 3
Answer:
Track mod 3 values with 3 states: (0,1,2)

Question 213:
NFA for (0+1)*010(0+1)*101 + ...
Answer:
Use alternation and concatenation, with intermediate states for substring tracking

Question 214:
Show closure under reversal of regular languages
Answer:
Reverse transitions and final/start states → New NFA accepts reversed language

Question 215:
FA for x#y where x ∈ L(M₁), y ∈ L(M₂)
Answer:
Build FA that accepts x in M₁, then transitions via '#' to simulate M₂ on y

Question 216:
Prove regular languages are closed under intersection
Answer:
Build product automaton: state = (state_M₁, state_M₂)

Question 217:
SQL to list employees in >1 project and those earning above dept. avg.
Answer:
(a)

sql

CopyEdit
SELECT e.name

FROM employee e

JOIN project p ON e.id = p.emp_id

GROUP BY e.id

HAVING COUNT(p.id) > 1;

(b)

sql

CopyEdit

SELECT e.name

FROM employee e

WHERE e.salary > (SELECT AVG(salary) FROM employee WHERE dept = e.dept);

Question 218:
SQL: Top 5 customers who spent most in 6 months
Answer:

sql

CopyEdit

SELECT customer_id, SUM(amount)

FROM orders

WHERE order_date >= CURDATE() - INTERVAL 6 MONTH

GROUP BY customer_id

ORDER BY SUM(amount) DESC

LIMIT 5;

Question 219:
Explain 8085 architecture
Answer:
8-bit microprocessor, 16-bit address bus, accumulator, flags, ALU, registers, PC, SP

Question 220:
RISC processor architecture
Answer:
Reduced instruction set, single-cycle execution, load/store model, large register file

Question 221:
Memory mapping techniques
Answer:

• Direct mapping
 • Associative mapping

• Set-associative mapping

Question 222:
Show strings longer than DFA states are pumpable
Answer:
By pigeonhole principle, some state repeats ⇒ Loop can be pumped ⇒ pumping lemma holds

Question 223:
Why is BCNF stricter than 3NF?
Answer:
3NF allows non-superkey determinants if RHS is prime
BCNF requires superkey determinants only

Question 224:
Prove canonical cover may not be unique
Answer:
FDs: A→B, A→C vs A→BC → Both are valid minimal covers

Question 225:
Candidate key in R with multiple FDs
Answer:
Compute closures; smallest attribute set that gives full attribute set is candidate key

Question 226:
Candidate key in R = {A,B,C,D,E,H}, given multiple FDs
Answer:
Compute closure of combinations (e.g., AH+, AEH+) ⇒ key = AEH

Question 227:
Table with FDs: F1→F3, F2→F4, (F1,F2)→F5. Highest normal form?
Answer:
Partial dependency exists ⇒ violates 2NF ⇒ 1NF

Question 228:
Is Student_Performance relation in 3NF?
Answer:
If student name depends only on rollNo ⇒ partial dependency ⇒ Not in 3NF

Question 229:
Different keys in DBMS with example
Answer:

• Primary: Unique + not null (e.g., ID)

• Candidate: All possible PKs

• Foreign: Refers PK in another table

• Super: PK + extra fields

• Unique: Ensures uniqueness (nullable)

Question 230:
Algorithm to compute attribute closure
Answer:

1. Start with attribute set

2. Add RHS of any FD whose LHS ⊆ closure

3. Repeat until no new attributes added

Question 231:
What is canonical cover?
Answer:
Minimal equivalent set of FDs with no extraneous attributes or redundancy

Question 232:
When is dense index preferred over sparse?
Answer:
When data is accessed frequently or blocks are small

Question 233:
Different I/O techniques
Answer:

• Programmed I/O: CPU handles all

• Interrupt I/O: Device interrupts CPU

• DMA: Direct memory access without CPU

Question 234:
Instruction formats and examples
Answer:

• 3-address: ADD A,B,C

• 2-address: MOV A,B

• 1-address: ADD A

• 0-address: stack (ADD)

Question 235:
What is pipeline processing and performance?
Answer:
Overlapping instruction stages increases throughput.
Speedup ≈ n for n-stage pipeline (ideal case)

Question 236:
Difference between paging and segmentation
Answer:
Paging: Fixed-size blocks
Segmentation: Variable-sized logical units
Paging simplifies memory management; segmentation is user-view aligned
Question 237:
RAID levels and case study
Answer:

• RAID 0: Striping (no redundancy)

• RAID 1: Mirroring

• RAID 5: Striping + parity

Case study: RAID 5 used in DB servers for performance + redundancy

Question 238:
Multiprocessor system design
Answer:
Multiple CPUs with shared memory (SMP) or distributed memory
Improves speed, scalability, and fault tolerance

Question 239:
64KB system using 8KB chips ⇒ how many chips?
Answer:
64 / 8 = 8 chips
Address lines = log₂(64KB) = 16 ⇒ 3 bits for chip select

Question 240:
4-way set-associative cache: 16KB, 64B block, 32-bit address
Answer:
Blocks = 16KB / 64 = 256
Sets = 256 / 4 = 64
Offset = 6, Index = 6, Tag = 32 – 6 – 6 = 20 bits

Question 241:
CPI calc: Load(5,30%), Store(4,20%), Arith(2,40%), Branch(3,10%)
Answer:
CPI = 0.3×5 + 0.2×4 + 0.4×2 + 0.1×3 = 3.1

Question 242:
Secondary storage + 400 FP ops, 40ns cycle ⇒ time?
Answer:
400 × 40ns = 16,000ns = 16μs

Question 243:
Program Counter + 200 ops @ 50ns
Answer:
200 × 50ns = 10μs

Question 244:
EPROM + 200 ops @ 10ns
Answer:
200 × 10ns = 2μs