SeeYA Technology SeeYA 1.

03” Micro-OLED

SeeYA 1.03”Micro-OLED（2560×2560RGB）
Specification

Model Name：SY103WAM01

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SeeYA Technology SeeYA 1.03” Micro-OLED

Revision
Version Date Description
V1.0 2021.4.15 Initial release

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SeeYA Technology SeeYA 1.03” Micro-OLED

Contents
1 General Description ..........................................................................................................................................................4
2 General Feature................................................................................................................................................................5
3 Optical Specification .........................................................................................................................................................6
4 Pixel Arrangement ............................................................................................................................................................8
5 System block ....................................................................................................................................................................9
6 Module Diagram .............................................................................................................................................................10
7 Pin Description ...............................................................................................................................................................11
7.1 Pin Description .............................................................................................................................................................. 11
7.2 Application circuit ......................................................................................................................................................... 14
8 Electrical Characteristics .................................................................................................................................................16
8.1 Absolute Maximum Ratings .......................................................................................................................................... 16
8.2 DC Characteristic ........................................................................................................................................................... 16
8.3 DSI DC/AC Characteristic ............................................................................................................................................... 17
8.4 Timing Characteristics ................................................................................................................................................... 19
8.5 Reset Timing Characteristics ......................................................................................................................................... 23
9 Power Sequence .............................................................................................................................................................24
9.1 Power Generation Scheme ........................................................................................................................................... 24
9.2 Power Sequence ........................................................................................................................................................... 24
10 Interface .............................................................................................................................................................................26
10.1 I2C Interface .................................................................................................................................................................. 26
10.1.1 I2C-Bus Protocol .................................................................................................................................................. 27
10.1.2 Write Sequence ................................................................................................................................................... 27
10.1.3 Read Sequence .................................................................................................................................................... 28
10.2 MIPI Interface ............................................................................................................................................................... 28
10.2.1 DSI System Configuration .................................................................................................................................... 29
11 User Command ...............................................................................................................................................................30
Command list ................................................................................................................................................................ 30
SWRESET(0100h): Software Reset ................................................................................................................................ 31
CMODE(0300h): Compression Mode ............................................................................................................................ 32
SLPIN (1000h): Sleep In ................................................................................................................................................. 33
SLPOUT (1100h): Sleep Out ........................................................................................................................................... 34
ALLPOFF (2200h): All Pixels OFF .................................................................................................................................... 35
ALLPON (2300h): All Pixel ON ....................................................................................................................................... 36
TCON (2500h): Temperature Sensor Enable ................................................................................................................. 37
DISPON (2900h): Display ON ......................................................................................................................................... 39
CASET (2A00h): Column Address Set ............................................................................................................................ 40
RASET (2B00h): Row Address Set .................................................................................................................................. 41
MADCTL (3600h): Set Address Mode ............................................................................................................................ 42
IDMOFF (3800h): Idle Mode Off.................................................................................................................................... 44
IDMON (3900h): Idle Mode On ..................................................................................................................................... 45
WRDISBV (5100h): Write Display Brightness ................................................................................................................ 46
SCACTRL (6900h): Scaling Up Control ........................................................................................................................... 47
IFCONF (6B00h): Interface Configure ............................................................................................................................ 48
RESCTRL1 (8000h): Resolution Control1 ....................................................................................................................... 49
12 Reliability .......................................................................................................................................................................50
13 Handling Precautions ......................................................................................................................................................51
13.1 Mounting Method ......................................................................................................................................................... 51
13.2 Caution of Against Static Charge ................................................................................................................................... 51
13.3 Packing .......................................................................................................................................................................... 51
13.4 Caution for Operation ................................................................................................................................................... 51
13.5 Storage .......................................................................................................................................................................... 51
13.6 Safety Precautions ........................................................................................................................................................ 52
13.7 Precautions before use ................................................................................................................................................. 52
14 Warranty ........................................................................................................................................................................53
15 Packing ...........................................................................................................................................................................54

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SeeYA Technology SeeYA 1.03” Micro-OLED

1 General Description
This display is a 1.03 inch diagonal, 2560(RGB) × 2560 dots active matrix color OLED panel module based on single-
crystal silicon transistors. This panel integrates panel driver and logic driver, and realizes small size, light weight, low
power consumption and high resolution.
Applications: View finders, Head mounted displays, etc.

• 2560 x 2560 Real RGB Resolution

• AP Operated Resolution
-- 2560 x 2560: (8 x M, M=160~320) x RGB x (8 x N, N=90~320)
• Frame rate:
-- 1920 x1920 input, x1.33scaling up to 2560 x2560, VESA DSC on, maximum 90Hz
-- 2560 x2560, input, x1scaling up , VESA DSC on, maximum 75Hz
• Normal operation supports full color mode: 16.7M colors
• Interface
-- MIPII + I2C
-- MIPI DPHY v1.2 with one / two port (4 / 8 lanes), 1.0Gbps/Lane
-- MIPI DSI v1.01 R11 Video mode
-- Support VESA-DSC v1.1 in-chip decoder (3X compression ratio)
-- Support scaling up 1.33x (1920x1920 to 2560 x 2560) and 2x (1280x1280 to 2560 x 2560)
• Scan direction selection, up or down and right or left
• Orbit supported
• Wide range Brightness adjustment
• Sequential/Global emission
• Temperature compensation

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SeeYA Technology SeeYA 1.03” Micro-OLED

2 General Feature

Parameter Specification

Resolution 2560(H) x 2560 (V)

Number of dots 19.66M (2560x2560x3)

Pixel Size 7.2μm x 7.2μm

Pixel Arrangement RGB π type

Useable Display Area 18.432mm x 18.432mm / 1.03'' diagonal

Luminance 1800cd/m² typical

Contrast Ratio 500,000:1 typical

Uniformity > 85%

VDDI=1.8V
Operating Voltage AVDD=5.8V~6V
AVEE=-4V~-5.5V
Power Consumption
(1800nits，100%duty_1920
1600mW
×1920input_1.33scaling
up_No DSC_72Hz)
Gray Levels 256

Interface MIPI (1 or 2-port D-PHY)

Frame Rate 60HZ~90HZ

Weight 2g

Operating Temperature -20°C to +70°C

Storage Temperature -40°C to +80°C

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SeeYA Technology SeeYA 1.03” Micro-OLED

3 Optical Specification

Item Description Min. Typ. Max. Unit

Brightness Tpanel=30℃ 1800 cd/m2

Tpanel=10℃
Brightness 1350 1800 2250 cd/m2
~70℃
white to Black
CR 200,000:1 500,000:1
Contrast Ratio
End to end
Uniformity large-area 85 %
uniformity
CIE-x 0.635 0.655 0.675
CIE Red
CIE-y 0.315 0.335 0.355

CIE-x 0.197 0.232 0.267

CIE Green
CIE-y 0.675 0.695 0.715

CIE-x 0.141 0.161 0.181

CIE Blue
CIE-y 0.045 0.065 0.085

CIE-x 0.298 0.313 0.328

CIE White
CIE-y 0.314 0.329 0.344

Color Gamut DCI-P3 80% 90%

View angle Luminance
35°
(White) decay to 50%
Frame rate 60 90 HZ
1800nits，
100%duty_1920×
Power consumption 1920input_1.33sca 1600 2000 mW
ling up_No
DSC_72Hz
Note1: If there is no specified, the specification of optical is specified at 30 degree Celsius.

Note2: Definition of optical measurement system.

The optical characteristics should be measured in dark room. Brightness is measured as peak luminance at full white
pattern (Gray level=255);

Photo detector

Field

Micro-OLED
Module

The center of the screen

Fig.1

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SeeYA Technology SeeYA 1.03” Micro-OLED

Note3: Definition of Uniformity at highest gray level( 255) and 100%duty emission.
Active area is divided into 9 measuring areas (Refer Fig. 2). Every measuring point is placed at the center of
each measuring area.
Luminance Uniformity (U) = Lmin/ Lmax
L-------Active area length; W----- Active area width

Lmax: The measured maximum luminance of all measurement position.

Lmin: The measured minimum luminance of all measurement position.

1/6W 1/3W

L1
1/3L
L4

L7
1/6L
Fig. 2

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SeeYA Technology SeeYA 1.03” Micro-OLED

4 Pixel Arrangement

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SeeYA Technology SeeYA 1.03” Micro-OLED

5 System block
VDD VSS

MIPI Source Driver

MVSS VDD
Voltage Gamma
MVDD Regulator
Gen

DATA3N_PTA
DATA3P_PTA
DATA0N_PTA Data Path
DATA0P_PTA
CLKN_PTA
CLKP_PTA
DATA1N_PTA Gate
DATA1P_PTA Driver 2560RGB*2560
DATA2N_PTA
DATA2P_PTA

DATA3N_PTB
DATA3P_PTB
DATA0N_PTB
DATA0P_PTB
MIPI I/F
& I/O
CLKN_PTB Timing
CLKP_PTB
Control
DATA1N_PTB
DATA1P_PTB
DATA2N_PTB Register
DATA2P_PTB Decode

IM[0]
SDA
SCL_WRX
IF_SEL MIPI Regulator
EN_EXT_VDD Voltage OSC
EN_AOI Gen

OTP_VDD2 OVDD OVSS VRF E1 VRFE2 VRFE3 VGMP VGSP ELVDD_L ELVDD_R VCOM_L VCOM_R

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SeeYA Technology SeeYA 1.03” Micro-OLED

6 Module Diagram

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SeeYA Technology SeeYA 1.03” Micro-OLED

7 Pin Description
7.1 Pin Description
Pin
Symbol Type Description
No.
Regulator output for common electrode voltage.
1 VCOM Output
connect a capacitor for stabilization, connect a TVS diode to GND.
-4.0V~-6.0V Power supply for OLED cell.
2 AVEE Power
connect a capacitor for stabilization.
-4.0V~-6.0V Power supply for OLED cell.
3 AVEE Power
then connect a capacitor for stabilization.
Power supply for OLED cell.
4 ELVDD Output
connect a capacitor for stabilization.
5 VSS Power System GND for internal digital system.
6 VSS Power System GND for internal digital system.
7 VDD Output Connect a capacitor for stabilization.
OTP program power.
8 OTP_PWR Input
If not use, please connect to GND or OPEN.
Regulator output for MTP analog system power.
9 OTP_VDD2 Output
Connect a capacitor for stabilization.
5.8V~6.0VPower supply for analog system.
10 AVDD Power
connect a capacitor for stabilization.
5.8V~6.0VPower supply for analog system.
11 AVDD Power
connect a capacitor for stabilization.
12 AVSS Power System GND for analog system.
13 AVSS Power System GND for analog system.
14 OVSS Power System GND for oscillator.
Regulator output for common electrode voltage.
15 OVDD Output
Connect a capacitor for stabilization.
Input/
16 MIPI_TEST Test pin for MIPI.
Output
17 VDDI Power Power supply for interface system except for the interface.

18 VDDI Power Power supply for interface system except for the interface.

19 MVSS Power System GND for MIPI interface.

This pin is DSI D3+ signal if MIPI Port A interface is used.
Input/Ou
20 DATA3P_PTA DATA3P/N_PTA is differential small amplitude signals.
tput
If not used, please keep it open.
This pin is DSI D3- signal if MIPI Port A interface is used.
Input/Ou
21 DATA3N_PTA DATA3P/N_PTA is differential small amplitude signals.
tput
If not used, please keep it open.
22 MVSS Power System GND for MIPI interface.
This pin is DSI D0+ signal if MIPI Port A interface is used.
Input/Ou
23 DATA0P_PTA DATA0P/N_PTA is differential small amplitude signals.
tput
If not used, please keep it open.
This pin is DSI D0- signal if MIPI Port A interface is used.
Input/Ou
24 DATA0N_PTA DATA0P/N_PTA is differential small amplitude signals.
tput
If not used, please keep it open.
25 MVSS Power System GND for MIPI interface.
This pin is DSI CLK+ signal if MIPI Port A interface is used.
26 CLKP_PTA Input CLKP/N_PTA is differential small amplitude signals.
If not used, please keep it open.
This pin is DSI CLK- signal if MIPI Port A interface is used.
27 CLKN_PTA Input CLKP/N_PTA is differential small amplitude signals.
If not used, please keep it open.
28 MVSS Power System GND for MIPI interface.
This pin is DSI D1+ signal if MIPI Port A interface is used.
29 DATA1P_PTA Input/Ou DATA1P/N_PTA is differential small amplitude signals.
tput If not used, please keep it open.

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This pin is DSI D1- signal if MIPI Port A interface is used.

30 DATA1N_PTA Input/Ou DATA1P/N_PTA is differential small amplitude signals.
tput If not used, please keep it open.
31 MVSS Power System GND for MIPI interface.
This pin is DSI D2+ signal if MIPI Port A interface is used.
32 DATA2P_PTA Input/Ou DATA2P/N_PTA is differential small amplitude signals.
tput If not used, please keep it open.
This pin is DSI D2- signal if MIPI Port A interface is used.
33 DATA2N_PTA Input/Ou DATA2P/N_PTA is differential small amplitude signals.
tput If not used, please keep it open.
34 MVSS Power System GND for MIPI interface.
This pin is DSI D3+ signal if MIPI Port B interface is used.
35 DATA3P_PTB Input/Ou DATA3P/N_PTB is differential small amplitude signals.
tput If not used, pleased keep it open.
This pin is DSI D3- signal if MIPI Port B interface is used.
36 DATA3N_PTB Input/Ou DATA3P/N_PTB is differential small amplitude signals.
tput If not used, pleased keep it open.
37 MVSS Power System GND for MIPI interface.
This pin is DSI D0+ signal if MIPI Port B interface is used.
38 DATA0P_PTB Input/Ou DATA0P/N_PTB is differential small amplitude signals.
tput If not used, pleased keep it open.
This pin is DSI D0- signal if MIPI Port B interface is used.
39 DATA0N_PTB Input/Ou DATA0P/N_PTB is differential small amplitude signals.
tput If not used, pleased keep it open.
40 MVSS Power System GND for MIPI interface.
This pin is DSI CLK+ signal if MIPI Port B interface is used.
41 CLKP_PTB Input CLKP/N_PTB is differential small amplitude signals.
If not used, pleased keep it open.
This pin is DSI CLK- signal if MIPI Port B interface is used.
42 CLKN_PTB Input CLKP/N_PTB is differential small amplitude signals.
If not used, please keep it open.
43 MVSS Power System GND for MIPI interface.
This pin is DSI D1+ signal if MIPI Port B interface is used.
Input/
44 DATA1P_PTB DATA1P/N_PTB is differential small amplitude signals.
Output
If not used, please keep it open.
This pin is DSI D1- signal if MIPI Port B interface is used.
45 DATA1N_PTB Power DATA1P/N_PTB is differential small amplitude signals.
If not used, please keep it open.
Input/
46 MVSS System GND for MIPI interface.
Output
This pin is DSI D2+ signal if MIPI Port B interface is used.
Input/
47 DATA2P_PTB DATA2P/N_PTB is differential small amplitude signals.
Output
If not used, please keep it open.
This pin is DSI D2- signal if MIPI Port B interface is used.
Input/
48 DATA2N_PTB DATA2P/N_PTB is differential small amplitude signals.
Output
If not used, please keep it open.
49 MVSS Power System GND for MIPI interface.
Regulator output for MIPI digital system power.
50 MVDD Output
Connect a capacitor for stabilization.
51 VDD Output Connect a capacitor for stabilization.
52 VDD Output Connect a capacitor for stabilization.
53 VSS Power System GND for internal digital system.
54 VSS Power System GND for internal digital system.
55 VDDI Power power supply for interface system except for MIPI interface.
56 VDDI Power power supply for interface system except for MIPI interface.
Regulator output for gamma high voltage generation.
57 VGMP Output
Connect a capacitor for stabilization.
Regulator output for gamma low voltage generation.
58 VGSP Output
Connect a capacitor for stabilization.
59 EN_EXT_VDD Input Connect to GND.
60 GPIO Output Digital global purpose in/out test pin
61 OCP_OUT Output Over current protect output flag.

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Input/ Synchronous clock signal in I2C I/F.

62 SCL_WRX
Output If this pin is not used, please connect to VDDI.
Input/ Bi-direction data PIN in I2C I/F.
63 SDA
Output If this pin is not used, please connect to VDDI.
64 EN_AOI Input Connect to GND.
65 IF_SEL Input Connect to GND.
Use to select the Interface type.
IM[0] Command Display Data
66 IM[0] Input
0V MIPI MIPI
1.8V I2C or MIPI MIPI
This signal will reset the device and must be applied to properly initialize the chip. Signal is
67 RESX Input
active low.
Regulator output for internal reference voltage.
68 VREF1 Output
Connect a capacitor for stabilization.
Regulator output for internal reference voltage.
69 VREF3 Output Connect a capacitor for stabilization.
Connect a Schottky diode to GND
Regulator output for internal reference voltage.
70 VREF2 Output
Connect a capacitor for stabilization.
71 AVSS Power System GND for analog system.
72 AVSS Power System GND for analog system.
73 AVSS Power System GND for analog system.
5.8V~6.0VPower supply for analog system.
74 AVDD Power
connect a capacitor for stabilization.
5.8V~6.0VPower supply for analog system.
75 AVDD Power
connect a capacitor for stabilization.
5.8V~6.0VPower supply for analog system.
76 AVDD Power
connect a capacitor for stabilization.
Power supply for OLED cell.
77 ELVDD Power
connect a capacitor for stabilization.
-4.0V~-6.0V Power supply for OLED cell.
78 AVEE Power
connect a capacitor for stabilization.
-4.0V~-6.0V Power supply for OLED cell.
79 AVEE Power
connect a capacitor for stabilization.
-4.0V~-6.0V Power supply for OLED cell.
80 AVEE Power
connect a capacitor for stabilization.
Regulator output for common electrode voltage.
81 VCOM Output
connect a capacitor for stabilization, connect a TVS diode to GND.

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7.2 Application circuit

Below table is the instruction of peripheral circuit. Regarding power supply capacitor connections, mount an
appropriate capacitor for each power supply.

No. Signal Name Typical Value Maximum Rated Voltage Note

1 VDDI Cap, 2.2uF 6.3V -

2 AVDD Cap, 1.0uF 10V -
3 ELVDD Cap, 2.2uF 10V -
4 AVEE Cap, 1uF 10V -
5 VDD Cap, 4.7uF 6.3V -
6 MVDD Cap, 1uF 6.3V -
7 VGMP Cap, 1uF 10V -
8 VGSP Cap, 1uF 10V -
9 VREF1 Cap, 1uF 6.3V -
10 VREF2 Cap, 1uF 6.3V -
Cap, 1uF
11 VREF3 Schottky Diode 6.3V
Cap, 2.2uF Recommend: TVS VBR
12 VCOM TVS 10V min>8V
13 OTP_VDD2 Cap, 1uF 6.3V -
14 OVDD Cap, 1uF 6.3V -

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Below circuit is one of typical example for reference to drive the module with D-PHY.

TVS

1 VCOM 2.2uF
VCOM GND
2
AVEE
3 AVEE 1uF
AVEE GND
4 ELVDD
ELVDD GND
5 2.2uF
VSS
6
VSS 4.7uF GND
7 VDD
VDD GND
8
OTP_PWR 1uF GND
9
OTP_VDD2 GND
10
AVDD
11 AVDD 1uF
AVDD GND
12
AVSS
13
AVSS
14
OVSS 1uF GND
15
OVDD GND
16
MIPI_TEST
17
VDDI 2.2uF
18
VDDI GND
19
MVSS GND
20 D3P_PTA
DATA3P_PTA
21 D3N_PTA
DATA3N_PTA
22
MVSS GND
23 D0P_PTA
DATA0P_PTA
24 D0N_PTA
DATA0N_PTA
25
MVSS GND
26 CLKP_PTA
CLKP_PTA
27 CLKN_PTA
CLKN_PTA
28
MVSS GND
29 D1P_PTA
DATA1P_PTA
30 D1N_PTA
DATA1N_PTA
31
MVSS GND
32 D2P_PTA
DATA2P_PTA
33 D2N_PTA
DATA2N_PTA
34
MVSS GND
35 D3P_PTB
DATA3P_PTB
36 D3N_PTB
DATA3N_PTB
37
MVSS GND
38 D0P_PTB
DATA0P_PTB
39 D0N_PTB
DATA0N_PTB
40
MVSS GND
41 CLKP_PTB
CLKP_PTB
42 CLKN_PTB
CLKN_PTB
43
MVSS GND
44 D1P_PTB
DATA1P_PTB
45 D1N_PTB
DATA1N_PTB
46
MVSS GND
47 D2P_PTB
DATA2P_PTB
48 D2N_PTB
DATA2N_PTB
49
MVSS 1uF GND
50
MVDD GND
51
VDD
52 VDD
VDD
53
VSS
54
VSS GND
55
VDDI
56 VDDI
VDDI 1uF
57
VGMP GND
58 1uF
VGSP GND
EN_EXT_VDD
59
GND
Notes:
60
GPIO
61
OCP_OUT
SCL_WRX
62 SCL I2C Bus:Pin62 SCL and Pin63 SDA.
63 SDA
SDA
64 If I2C is not used,please connect to VDDI.
EN_AOI
65
IF_SEL GND
66 IM[0]
IM[0] 1uF IM[0]:Use to select the interface type.
67 RESET
RESX 1uF GND
68
VREF1
69 (If you connect this pin to GND,only MIPI can
VREF3 GND
VREF2
70 Schottky execute command .If you connect this pin to
71 1uF
AVSS
72
GND VDDI,MIPI or I2C can execute command.)
AVSS
73
AVSS GND
74
AVDD
AVDD
75 Schottky:RB521CS30L
76 AVDD
AVDD
77 ELVDD
ELVDD
AVEE
78 TVS:DY2L5A0C0L1
79
AVEE
80 AVEE
AVEE
81 VCOM
VCOM
SY103_81pin

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8 Electrical Characteristics
8.1 Absolute Maximum Ratings
The absolute maximum rating is listed on the below table. When this Micro-OLED product is used beyond the
absolute maximum ratings, it may be permanently damaged. It is strongly recommended use this Micro-OLED
product within the following specified limits for normal operation. If these electrical characteristic conditions are
exceeded during normal operation, this Micro-OLED product will malfunction and cause poor reliability.

Item Symbol Value Unit

Power Supply Voltage (1) VDDI 5.5 V
AVDD-AVSS 6.6 V
Power Supply Voltage (2)
AVEE-AVSS 6.6 V
VDDI 1.32 V
Power Supply Voltage in
AVDD-AVSS 6.6 V
AOI mode
AVEE-AVSS 6.6 V
CLKP_PTA/B, CLKN_PTA/B
DATAP0_PTA/B, DATAN0_PTA/B
MIPI Differential Input DATAP1_PTA/B, DATAN1_PTA/B 1.32 V
DATAP2_PTA/B, DATAN2_PTA/B
DATAP3_PTA/B, DATAN3_PTA/B
Input Voltage of Interface Vin -0.3 ~ VDDI+0.3 V
Output Voltage of Interface Vo -0.3 ~ VDDI+0.3 V
Operating temperature Topr -20 ~ 70 °C
Storage temperature Tstg -40 ~ 80 °C

8.2 DC Characteristic
Parameter Symbol Condition Min. Typ. Max. Unit
Power & Operation Voltage
AVDD Input Level AVDD - 5.8 6.0 V
Digital I/O Power
Supply (non-MIPI VDDI -
1.8 V
I/O)
Digital I/O Input Level 0.7*VD
VIH VDDI=1.65V ~ 1.95V VDDI
@Logic High DI - V
Digital I/O Input Level 0.3*VD
VIL VDDI=1.65V ~ 1.95V 0
@Logic Low - DI V
Digital I/O Output Level 0.8*VD
VOH Iout = -1mA VDDI
@Logic High DI - V
Digital I/O Output Level 0.2*VD
Iout = +1mA 0
@Logic Low VOL - DI V
Digital I/O Input leakage
Vin = VDDI uA
@Logic High IIHD 1
Digital I/O Input leakage
Vin = 0 -1 uA
@Logic Low IILD
MIPI I/O Power Supply MVDD - - 1.2 - V
MIPI Input leakage
IIHMD Vin = MVDD
@Logic High 1 uA
MIPI Input leakage
IILMD Vin = 0
@Logic Low -1 uA

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8.3 DSI DC/AC Characteristic

8.3.1 Receiver characteristic

High speed receiver characteristic

Parameter Description Min Typ. Max Unit

Common-mode voltage HS receive
VCMRX(DC) 70 - 330 mV
mode
ZID Differential input impedance 80 100 125 Ω
VIDTH Differential input high threshold - - 70 mV
VIDTL Differential input low threshold -70 - - mV
VIHHS Single-ended input high voltage - - 460 mV
VILHS Single-ended input low voltage -40 - - mV
CCM Common-mode termination - - 60 pF

Low power receiver characteristic

Parameter Description Min Typ. Max Unit

VIH Logic 1 input voltage 880 - - mV
VIL Logic 0 input voltage, not in ULP state - - 550 mV
VIL_ULPS Logic 0 input voltage, ULP state - - 300 mV
VHYST Input hysteresis 25 - - mV
eSPIKE Input pulse rejection - - 300 V·ps
TMIN-RX Minimum pulse width response 20 - -

2*TLPX 2*TLPX

eSPIKE
VIH
Input

VIL
eSPIKE
TMIN-RX TMIN-RX

Output

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8.3.2 Transmitter Characteristics

High-Speed Transmitter Characteristics

Parameter Description Min Typ. Max Unit
HS transmit static common-mode voltage 150 200 250 mV
VCMTX
|VOD| HS transmit differential voltage 140 200 270 mV

VOHHS HS output high voltage - - 360 mV

ZOS Single ended output impedance 40 50 62.5 Ω

- - 0.3 UI
tR and tF (note1,2) 20%-80%rise time and fall time
- - 0.35 UI

Note:

1. Applicable when supporting maximum HS bitrates ≤ 1Gbps (UI≥1ns)

Low-Power Transmitter Characteristics

Parameter Description Min Ty Ma Unit

p. x
VOH The output high level 1.1 1.2 1.3 V
VOL The output low level -50 - 50 mV
ZOLP Output impedance of LP 110 - - Ω
transmitter
VIHCD Logic1 contention threshold 450 - - mV
VILCD Logic0 contention threshold - - 200 mV

VOH,MAX

LP-TX
Output High LP-RX
Input High

VOH,MIN
LP-CD
VIL,MIN Input High

LP-RX
Threshold
Region

VIL,MAX

VIHCD,MIN

LP-CD LP-RX
Threshold Region Input Low

VILCD,MAX

VOL,MAX LP-CD
Input Low
LP-TX
GND
Output Low
VOL,MIN

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8.4 Timing Characteristics

8.4.1 High Speed Mode Characteristics

Parameter Symbol Min Typ. Max Unit

UI instantaneous UIINST 1 - 3 ns
T Data to Clock Skew TSKEW -0.15 - 0.15 UIHS
RX Data to Clock Setup Time Tolerance TSETUP 0.15 - - UIHS
RX Data to Clock Hold Time Tolerance THOLD 0.15 - - UIHS

TSETUP THOLD

0.5UIINST+TSKEW

CLKP

CLKN
1UIINST
1Clock Period

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8.4.2 Low Power Mode Characteristics

Parameter Description Min Typ. Max Unit

Transmitted length of any Low-Power state
TLPX(M) period (MCU to display module) 50 - - ns
Transmitted length of any Low-Power state
TLPX(D) period (display module to MCU) 50 - - ns
Time that the new transmitter waits after
the LP-10 state before transmitting the
TTA-SURE Bridge state(LP-00) during a Link TLPX 2*TLPX
-
Turnaround
Time that the new transmitter drives the Bridge state
TTA-GET (LP-00) after accepting control during a Link 5* TLPX
Turnaround
Time that the transmitter drives the Bridge
TTA-GO state(LP-00) before releasing control during a 4* TLPX
Link Turnaround

⚫ Bus Turnaround from MPU to display module

TLPX(M) TLPX(M) TLPX(M) Driver Overlop

D0+

D0-
LP-11 LP-10 LP-00 LP-10 LP-00 LP-00 LP-00 LP-10 LP-11
TTA- TTA-GET(D) TLPX(D) TLPX(D)
SU RE(D)

⚫ Bus Turnaround from MPU to display module

TTA-GO(D)
TLPX(D) TLPX(D) TLPX(D) Driver Overlop
D0+

D0-
LP-11 LP-10 LP-00 LP-10 LP-00 LP-00 LP-00 LP-10 LP-11
TTA- TLPX(M) TLPX(M)
SU RE(M)

8.4.3 High Speed Mode Operation Timing Characteristics

Parameter Ty Un
Description Min Max
p. it
Time that the transmitter continues to send HS
clock after the last associated Data Lane has 60ns+52*U
transitioned to LP Mode. Interval is defined as the - -
I
TCLK-POST period from the end of THS-TRAIL to the beginning
ns

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of TCLK-TRAIL

Time that the HS clock shall be driven by the

transmitter prior to any associated Data Lane 8 - -
TCLK-PRE beginning the transition from LP to HS mode UI

Time that the transmitter drives the Clock Lane

LP-00 Line state immediately before the HS-0 38 95
TCLK-PREPARE n
Line state starting the HS transmission -
s

Time interval during which the HS receiver

should ignore any Clock Lane HS transitions, 95 300
TCLK-SETTLE n
starting from the beginning of TCLK-PREPARE -
s

Time for the Clock Lane receiver to enable the

HS line termination, starting from the time - 38
TCLK-TERM_EN n
point when Dn crosses VIL,MAX -
s
Time that the transmitter drives the HS-0 state
after the last payload clock bit of a HS
n
TCLK-TRAIL transmission burst 60 - -
s
t
TCLK-PREPARE + time that the transmitter
TCLK-PREPARE+TCLK- drives the HS-0 state prior to starting the Clock 300 - - n
ZERO s
Time that the transmitter drives LP-11 n
THS-EXIT 100 - -
following a HS burst s
Time for the Data Lane receiver to enable the
35ns+4* n
HS line termination, starting from the time - -
TD-TERM_EN UI s
point when Dn crosses VIL,MAX
Time that the transmitter drives the Data Lane
LP-00 Line state immediately before the HS-0 40ns+4* 85ns+6* n
-
THS-PREPARE Line state starting the HS transmission UI UI s

THS-PREPARE + time that the transmitter

drives the HS-0 state prior to transmitting the
THS-PREPARE+THS- 145ns+1 n
ZERO
Sync sequence - -
0*UI s

Time interval during which the HS receiver

shall ignore any Data Lane HS transitions,
starting from the beginning of THS-PREPARE.
The HS receiver shall ignore any Data Lane 85ns+6* 145ns+1 n
transitions before the minimum value, and the UI 0*UI s
HS receiver shall respond to any Data Lane
THS-SETTLE
transitions after the maximum value. -
value.

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CLK+/CLK-

DN+/DN- THS-PREPARE THS-ZERO

-VIH(min)
-VIL(max)
Dn-
0 0 0 1 1 1 0 1
LP-11 LP-01 LP-00 Dn+ HS-0 Start of Transmission High-Speed data EoT LP-11
TLPX THS-SETTLE
THS-TRAIL

TCLK-POST

-VIH(min)
-VIL(max)
CLK+/CLK-

TCLK-TRAIL THS-EXIT TLPX TCLK-PREPARE TCLK-ZERO TCLK-PRE THS-PREPARE

TLPX

-VIH(min)
-VIL(max)
DN+/DN-
Dn-

Dn+

8.4.4 I2C-Bus Interface Timing

Parameter Symbol Min. Typ. Max. Unit Conditio

n
I2C Clock Frequency Fclk - - 400 kH
z
I2C Clock Low Tclkl 130 - - ns
0
I2C Clock High Tclkh 600 - - ns
I2C Data Rising Time Tdr - - 300 ns
I2C Data Falling Time Tdf - - 300 ns
I2C Data Setup Time Tdsu 100 - - ns
I2C Data Hold Time Tdhd - - TBD ns
I2C Setup Time (Start Condition) Tsu_sta 600 - - ns
I2C Hold Time (Start Condition) Thd_sta 600 - - ns
I2C Setup Time (Stop Condition) Tsu_stp 600 - - ns
I2C Bus Free Time (Stop Condition) Tbuf_stp 130 - - ns
0

Tf Tr Tdsu Tbuf_stp

70% 70% 70%

I2C_SDA
30% 30% 30%
Tsu_sta Tclkh
Thd_sta Tdhd Tsu_stp

70% 70% 70% 70% 70% 70%

I2C_SDL 30% 30% 30% 30% 30% 30%
30%

S 1/Fclk
Tclkl P S
1st Clock cycle
START STOP START
condition condition condition

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8.5 Reset Timing Characteristics

When Reset happens in Sleep-out mode, this Micro-OLED product will enter blanking sequence with the
maximum time 120 msec. Then this Micro-OLED product will remain in blanking state and return \ default state.
During reset complete time (tRT), data in OTP will be re-loaded and latched to internal registers. This data re-
load is done every time when there is an H/W reset and completes within 20 msec after the rising edge of RESX.
Therefore, it is necessary to wait at least 20 msec after releasing the RESX before sending commands. Moreover,
the Sleep-out command cannot be sent in 120 msec. Spike (less than 20ns width) Rejection can also be applied
during a valid reset pulse.

Invalid reset(when low

pulse width<15μs 15μs
tRW

RESX
tRT

During a valid reset pulse, positive

20ns spike(less than 20ns width)will be rejected

Display
Normal Operation Resetting Default state
status

Reset time @VDDI=1.65V to 1.95V, AVSS = VSS = MVSS = 0V, Ta=-40°C to 85°C

Signal Symbol Parameter Min Typ. Max Uni Description

. . t
Reset low pulse
tRW 15 us
width
When reset applied at sleep-in
20 ms
RESX mode
tRT Reset Complete
time When reset applied at sleep-out
120 ms
mode

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9 Power Sequence
9.1 Power Generation Scheme

AVDD=5.8v~6.0v

ELVDD
VGMP

VREF1

VGSP
VDDI=1.65v~1.95v

VDD
MVDD

DVSS=VSSR=AVSS=VSSAM=0V

VREF2，VREF3
Vcom

AVEE=-4v~-5.5V

9.2 Power Sequence

Power on sequence

Command
STATE Unknown RESET MTP Power On Display Off Display on
Input

VDDI
T1

AVDD T2

AVEE
T3 T4

RESET
T6

MIPI I/F
T5

Power off sequence

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STATE Display On Display Off Power Off Reset Unknown

VDDI
T11

AVDD
T9

AVEE

RESET

T7 T8 T10

MIPI I/F

Symbol Min. Typ. Max. Unit Description

T1 1 - - ms Power on time between VDDI and AVDD

T2 2 - - ms Power on time between AVDD and AVEE

T3 1 - - ms Effective hardware reset period

T4 20 - - ms OTP reload time

The time is between initial code finished and sleep-out

T5 0 - - ms
command

T6 2 - 8 uS Power on sequence, the period can be modified

T7 1 - - uS Blanking region

T8 - 1 - uS Power off sequence, the period can be modified

T9 2 - - ms Power off time between AVEE and AVDD

T10 1 - - ms Effective hardware reset period

T11 1 - - ms Power off time between AVDD and VDDI

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10 Interface
This Micro-OLED product supports MIPI interface and inter-integrated circuit interface (I2C). 1 port MIPI or 2
port MIPI is selected by register, and I2C is selected by IM0, the detail interface selection by IM0 pin and register
of PORT1_2_SEL shows in below table.

IM0 PORT1_2_SEL Command Execute Image Write

0 0 MIPI MIPI 1port

0 1 MIPI MIPI 2 port

1 0 I2C or MIPI MIPI 1port

1 1 I2C or MIPI MIPI 2 port

This Micro-OLED product supports MIPI interface with D-PHY and C-PHY which is selected by IF_SEL pin.

DPHY+DSI
0
Data Path
CPHY+DSI
1

HW pin: IF_SEL
(Default=0 is DPHY)

10.1 I2C Interface

The I2C-bus is for bi-directional, two-line communication between different ICs or modules. The two lines are
the Serial Data Line (I2C_SDA) and Serial Clock Line (I2C_SCL). Both lines must be connected to a positive power
supply via pull-up resistors. Data transfer can be initiated only when the bus is not busy. The acknowledge takes
place after every byte. The acknowledge bit allows the receiver to signal the transmitter that the byte was
successfully received and another byte maybe sent. The master generates all clock pulses, including the ninth
acknowledge clock pulse.

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10.1.1 I2C-Bus Protocol

Before any data is transmitted on the I2C-bus, the device which should response is addressed first. There are
several slave addresses can be selected by MCU. The slave addressing is always carried out with the first byte
transmitted after the START procedure.

Definition

− Transmitter: The device which sends the data to the bus.

− Receiver: The device which receives the data from the bus.
− Master: The device which initiates a transfer generates clock signals and terminates a transfer.
− Slave: The device addressed by a master.
− Multi-master: More than one master can attempt to control the bus at the same time without corrupting the
message.
− Arbitration: Procedure to ensure that. If more than one master simultaneously tries to control the bus, only
one is allowed to do so and the message is not corrupted.
− Synchronization: Procedure to synchronize the clock signals of two or more devices.

Master Slave Master

Slave Receiver Slave Receiver
Transmitter/Receiver Transmitter/Receiver Transmitter/Receiver

I2C_SDA

I2C_SCL

10.1.2 Write Sequence

This Micro-OLED product supports register write sequence via I2C-bus transfer. The register writing supports single
register write mode. The detailed transfer sequences are illustrated and described as below.
(1) Data transfer for register writing should follow the format shown as below.
(2) After the START condition, a slave address is sent. R/W̅ bit is setting to “0” for Write.
(3) The slave issues an ACK to the master.
(4) 8-bits register address transfer first then transfer the register data parameter.
(5) A data transfer is always terminated by a STOP condition.
(6) The chip SA [6:0] =1001100.

SA SA SA SA SA SA SA ADD ADD ADD ADD ADD ADD ADD ADD ADD ADD ADD ADD ADD ADD ADD ADD
[1] [0] W ACK ACK D[15] D[14] D[13] D[12] D[11] D[10] D[9] D[8]] ACK D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]]
[6] [5] [4] [3] [2] [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0]

Register Address Register DATA Register Data

Slave Address SA[6:0] W ACK Register Address
ADD[15:8]

W: Write Bit, W= “1” here, R: Read Bit, R= “0” here

ACK: Acknowledge Bit, ACK= “0” here
SA[6:0]: Slave Address
ADD[15:0]: Register Address
D[15:0]: Register Data

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10.1.3 Read Sequence

This Micro-OLED product supports register read sequence via I2C-bus transfer. The register reading supports single
register read mode. The register data reading transfer are shown as below.

I2C_SDA
ADD ADD
W ACK ACK ACK
[1] [0]

W ACK ACK ACK

START

R ACK ACK D[5]

[0]

ACK ACK
STOP

W: Write Bit, W= “0” here, R: Read Bit,R= “1” here

ACK: Acknowledge Bit, ACK= “0” here
SA[6:0]: Slave Address
ADD[15:0]: Register Address
D[15:0]: Register Data
NACK: Negative Acknowledge Bit, NACK= “1” here

10.2 MIPI Interface

Display serial interface (DSI) specifies the interface between a host processor and a peripheral such as a display
module. It builds on existing MIPI Alliance specification by adoption pixel formats and command set. The detail Lane
configuration for DPHY and CPHY are listed below.

[DPHY]

For DPHY, there are one Clock Lane and 1~4 Data Lane. The configuration for DPHY between host and this Micro-
OLED product shows as the table below.

Lane Pair Available Operation Mode

Forward High-Speed Clock
Clock Lane Unidirectional Lane Escape Mode (ULPS only)
Forward High-Speed Data Bi-
Data Lane 0 Bi-directional Lane directional Escape Mode Bi-
directional LPDT
Forward High-Speed Data No LPDT
Data Lane 1 Unidirectional Lane Escape Mode (ULPM only)
Forward High-Speed Data No LPDT
Data Lane 2 Unidirectional Lane Escape Mode (ULPM only)
Forward High-Speed Data No LPDT
Data Lane 3 Unidirectional Lane Escape Mode (ULPM only)

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[DPHY]

For CPHY, there is no Clock Lane since it’s embedded clock in Data Lane. There are 1~3 Trio (Lane) in CPHY. The
configuration for CPHY between host and this Micro-OLED product shows as the table below.

Trio Available Operation Mode

Forward High-Speed Data
Trio 0 Bi-directional Lane Bi-directional Escape Mode
Bi-directional LPDT
Forward High-Speed Data
Trio 1 Unidirectional Lane No LPDT
Escape Mode (ULPM only)
Forward High-Speed Data
Trio 2 Unidirectional Lane No LPDT
Escape Mode (ULPM only)

10.2.1 DSI System Configuration

[DPHY]

This Micro-OLED product supports MIPI 2 port with 2, 3 or 4 lane configurations for DPHY. The system configuration
is shown as the figure below. There are HW pin(IM, IF_SEL, PORTSWAP) and registers (Lane_num_cfg, PSWAP,
DSWAP) which can set the interface and lane related configuration.

RSEX Display Driver

DSIA_D0P/D0N HSSIA_D0P/D0N

DSIA_D1P/D1N HSSIA_D1P/D1N
PORT-A

HSSIA_D2P/D2N
DSIA_D2P/D2N
HSSIA_D3P/D3N
DSIA_D2P/D2N
HSSIA_CLKP/CLKN
Host DSIA_CLKP/CLKN

DSIB_D0P/D0N
HSSIB_D0P/D0N
DSIB_D1P/D1N HSSIB_D1P/D1N
PORT-B

DSIB_D2P/D2N HSSIB_D2P/D2N
DSIB_D2P/D2N HSSIB_D3P/D3N
DSIB_CLKP/CLKN HSSIB_CLKP/CLKN

IM

IF_SEL

PORTSWAP

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11 User Command
Command list
Address
Instruction R/W D7 D6 D5 D4 D3 D2 D1 D0 Default
MIPI Non-MIPI

SWRESET W 01h 0100h No Parameter N/A

CMODE R/W 03h 0300h slice2_sel - - - - - - CMODE 80h

SLPIN W 10h 1000h No Parameter N/A

SLPOUT W 11h 1100h No Parameter N/A

ALLPOFF W 22h 2200h No Parameter N/A

ALLPON W 23h 2300h No Parameter N/A

TCON R/W 25h 2500h - - - - - - - TC_ENABLE 00h

DSPOFF W 28h 2800h No Parameter N/A

DSPON W 29h 2900h No Parameter N/A

R/W 2A00h XS[15:8] 00h

CASET 2Ah
R/W 2A01h XS[7:0] 00h

R/W 2B00h YS[15:8] 00h

RASET 2Bh
R/W 2B01h YS[7:0] 00h

TEON R/W 35h 3500h - - - - - - - M 00h

MADCTL R/W 36h 3600h - - - - RGB - RSMX RSMY 00h

IDMOFF R/W 38h 3800h No Parameter N/A

IDMON R/W 39h 3900h No Parameter N/A

SCACTRL W 69h 6900h SC_MOD_SEL[1:0] 00h

PORT1_2_S
IFCONFG R/W 6Bh 6B00h - - - - - - - 10h
EL_ CMD1
OSC_FRE
8000h - - - - - - - 01h
Q_SEL

8001h NC[7:0] 40h

RESCTRL1 R/W 80h
8002h NL[7:0] 40h

8003h - - - NC[8] - - - NL[8] 11h

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SWRESET(0100h): Software Reset

0100H SWRESET
Address Parameter
Instructio R/W D
n MI Oth D7 D6 D5 D4 D3 D2 D1 D0
1
PI er
SWRESET W 01 0100 -5 No Parameter
h h -
When the Software Reset command is executed, all related register and parameters are reset to their S/W Reset default
Descriptio D
values. 8
n
It is necessary to wait 10m sec to send any command following the S/W Reset.
If S/W Reset is executed in Sleep-out mode, it is necessary to wait 120m sec to send Sleep-Out command. The
Restriction
Software Reset command cannot be sent during Sleep-Out sequence. Any new command cannot be sent within 8-
frame until device enters Sleep-In mode.
Status Default Value
Power On Sequence 0100h N/A
Default
SW Reset The same as above
HW Reset The same as above

Flow
Chart

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CMODE(0300h): Compression Mode

0400H RDID123
Address Parameter
Instructio R/W D
n MI Oth D7 D6 D5 D4 D3 D2 D1 D0
1
PI er
5
CMODE R/W 03h 0300h -- D7 D0
D
These commands are used for compression
8 mode
Descriptio Bit Symbol Description Comment
n 0=1 slice
D7 slice_sel Compression slice selection
1=2 slice

0=Disable
D0 CMODE Enable/Disable compression mode
1=Enable

Restriction -
Status Default Value
Power On Sequence 0300h 80h
SW Reset The same as above
Default
HW Reset The same as above

Flow
Chart

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SLPIN (1000h): Sleep In
1000H SLPIN
Address Parameter
Instructio R/W D
n MI Othe D7 D6 D5 D4 D3 D2 D1 D0
1
PI r
SLPIN W 10 1000 -5 No Parameter
h h -
This command force display module to enter Sleep-In mode. Under Sleep-In mode, internal display oscillator, and
D
panel scanning are all stopped. The
8 interface and related registers are still working and keeps its values.

Descriptio
n

Restriction -
Status Default Value
Power On Sequence 1000h Sleep In Mode
Default SW Reset The same as above
HW Reset The same as above

Flow
Chart

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 SLPOUT (1100h): Sleep Out
1100H SLPOUT
Address Parameter
Instructio R/W D
n MI Othe D7 D6 D5 D4 D3 D2 D1 D0
1
PI r
SLPOUT W 11 1100 -5 No Parameter
h h -
This command force display module D to exit Sleep-In mode. Under Sleep-out mode regulator, internal display
oscillator, and panel scanning are8all enabled.

Descriptio
n

Restriction -
Status Default Value
Power On Sequence 1100h Sleep In Mode
Default SW Reset The same as above
HW Reset The same as above

Flow chart

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 ALLPOFF (2200h): All Pixels OFF
2200H ALLPOFF
Address Parameter
Instructio R/W D
n MI Othe D7 D6 D5 D4 D3 D2 D1 D0
1
PI r
ALLPOFF W 22 2200 -5 No Parameter
h forceshthe display -module to display black image in Display-On Mode.
This command
D
8

Descriptio
n

Restriction -
Status Default Value
Power On Sequence 2200h All Pixel Off
Default SW Reset The same as above
HW Reset The same as above

Flow
Chart

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 ALLPON (2300h): All Pixel ON
2300H ALLPON
Address Parameter
Instructio R/W D
n MI Othe D7 D6 D5 D4 D3 D2 D1 D0
1
PI r
ALLPON W 23 2300 -5 No Parameter
h forceshthe display -module to display white image in Display-On Mode.
This command
D
8

Descriptio
n

Restriction -
Status Default Value
Power On Sequence 2300h All Pixel Off
Default
SW Reset The same as above
HW Reset The same as above

Flow Chart

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 TCON (2500h): Temperature Sensor Enable
2300H ALLPON
Address Parameter
R/W D
Instruction MI Othe D7 D6 D5 D4 D3 D2 D1 D0
1
PI r
ALLPON R/W 25 2500 -5 - - - - - - - D0
h to turn on -temperature sensor.
h is used
This command
D
8
Bit Symbol Description Comment
Description
0=Temperature sensor off
D0 TC_ENABLE Temperature sensor enable
1=Temperature sensor on

Restriction -
Status Default Value
Power On Sequence 2500h 00h
Default SW Reset The same as above
HW Reset The same as above

Flow Chart

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permission of SeeYA. Please handle the information based on Non-Disclosure Agreement.
 DISPOFF (2800h): Display OFF
2800H DISPOFF
Address Parameter
Instructio R/W D
n MI Othe D7 D6 D5 D4 D3 D2 D1 D0
1
PI r
DISPOFF W 28 2800 -5 No Parameter
h h -
Descriptio This command forces the display Dmodule to stop displaying image data.
n 8
Restriction This command has no effect when display driver is already in DISPLAY-OFF mode
Status Default Value
Power On Sequence 2800h Display Off
Default SW Reset The same as above
HW Reset The same as above
Flow Chart

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permission of SeeYA. Please handle the information based on Non-Disclosure Agreement.
 DISPON (2900h): Display ON
2900H DISPON
Address Parameter
Instructio R/W D
n MI Othe D7 D6 D5 D4 D3 D2 D1 D0
1
PI r
DISPON W 29 2900 -5 No Parameter
h h -
Descriptio This command forces the display Dmodule to start displaying image data.
n 8
Restriction This command has no effect when display driver is already in DISPLAY-ON mode.
Status Default Value
Power On Sequence 2900h Display Off
Default SW Reset The same as above
HW Reset The same as above

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permission of SeeYA. Please handle the information based on Non-Disclosure Agreement.
 CASET (2A00h): Column Address Set
2A00H CASET
Address Parameter
Instructio R/W D
n MI Othe D7 D6 D5 D4 D3 D2 D1 D0
1
PI r
2A00 -5 XS[15:8]
CASET R/W 2A h -
2A01 - XS[7:0]
h D
Description This command indicates h display start position of display module in columns.
8
XS[15:0]: Display line start position.

1. XS= 0 + 2N, N=integer

2. Display content can be adjusted by XS, YS, PIXEL_SHIFT_X_COUNT, and PIXEL_SHIFT_Y_COUNT. The constraint
is that display content can’t exceed display area. XS should follow the rule as below: PIXEL_SHIFT_X_DIR=0(Left)
Parameter range= 0 ≤ XS[15:0] + NC[7:0]*8 - PIXEL_SHIFT_X_COUNT*2 ≤ 2568 (A08h)
Restriction
PIXEL_SHIFT_X_DIR=1(Right)
Parameter range= 0 ≤ XS[15:0] + NC[7:0]*8 + PIXEL_SHIFT_X_COUNT*2 ≤ 2568 (A08h)

Status Default Value

2A00h 00h
Power On Sequence 2A01h
Default 00h
SW Reset The same as above
HW Reset The same as above

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permission of SeeYA. Please handle the information based on Non-Disclosure Agreement.
 RASET (2B00h): Row Address Set
2A00H CASET
Address Parameter
Instructio R/W D
n MI Othe D7 D6 D5 D4 D3 D2 D1 D0
1
PI r
2B00 -5 YS[15:8]
RASET R/W 2B h -
2B01 - YS[7:0]
h D
Description This command indicates h display start position of display module in rows.
8
XS[15:0]: Display line start position.

1. YS= 0 + 2N, N=integer

2. Display content cane be adjusted by XS, YS, PIXEL_SHIFT_X_COUNT, and PIXEL_SHIFT_Y_COUNT. The constraint
is that display content can’t exceed display area. YS should follow the rule as below: PIXEL_SHIFT_Y_DIR=0(Up)
Parameter range= 0 ≤ YS[15:0] + NL[7:0]*8 - PIXEL_SHIFT_Y_COUNT*2 ≤ 2568 (A08h)
Restriction
PIXEL_SHIFT_Y_DIR=1(Down)
Parameter range= 0 ≤ YS[15:0] + NL[7:0]*8 + PIXEL_SHIFT_Y_COUNT*2 ≤ 2568 (A08h)

Status Default Value

2B00h 00h
Power On Sequence
Default 2B01h 00h
SW Reset The same as above
HW Reset The same as above

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permission of SeeYA. Please handle the information based on Non-Disclosure Agreement.
 MADCTL (3600h): Set Address Mode
3600H MADCTL
Address Parameter
Instructio R/W D
n MI Othe D7 D6 D5 D4 D3 D2 D1 D0
1
PI r
MADCTL R/W 36 3600 -5 - - - - D3 - D1 D0
h direction -of source and gate and data order.
h set scan
This command
D
Bit Symbol 8 Description Comment
D3] RGB Color Order of sub-pixel of true 1=BGR
RGB type 0=RGB
D1 RSMX Horizontal Flip 1=Normal Display
0= Horizontal Flip
D0 RSMY Vertical Flip 1= Normal Display
0= Vertical Flip

Input image RSMX RSMY Display

F F
B B

F
E E
0 0

E E

E
0 1

F
B
Descriptio
n
1 0 E

1 1
F E

Input Data order RGB Panel Display Color Order

Restrictio -
n
Status Default Value
Power On Sequence 3600h 00h
Default
SW Reset The same as above
HW Reset The same as above

Attachment is the exclusive property of SeeYA and shall not be reproduced or copied or transformed to any other format without prior
permission of SeeYA. Please handle the information based on Non-Disclosure Agreement.
 Flow Chart

Attachment is the exclusive property of SeeYA and shall not be reproduced or copied or transformed to any other format without prior
permission of SeeYA. Please handle the information based on Non-Disclosure Agreement.
 IDMOFF (3800h): Idle Mode Off
3800H IDMOFF
Address Parameter
Instructio R/W D
n MI Othe D7 D6 D5 D4 D3 D2 D1 D0
1
PI r
IDMOFF W 38 3800 -5 No Parameter
h h -
Descriptio This command cause display module
D to exit Idle mode.
n 8
Restriction This command has no effect when display module is not in Idle mode.
Status Default Value
Power On Sequence 3800h Idle mode off
Default SW Reset The same as above
HW Reset The same as above

Flow
Chart

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permission of SeeYA. Please handle the information based on Non-Disclosure Agreement.
 IDMON (3900h): Idle Mode On
3900H IDMON
Address Parameter
Instructio R/W D
n MI Othe D7 D6 D5 D4 D3 D2 D1 D0
1
PI r
IDMON W 39 3900 -5 No Parameter
h h -
This command cause display module
D to enter Idle mode. In the idle mode, color expression is reduced.
Input Image 8 Display

Descriptio
n

Restriction This command has no effect when display module is already in Idle mode.
Status Default Value
Power On Sequence 3900h Idle mode off
Default SW Reset The same as above
HW Reset The same as above

Flow
Chart

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permission of SeeYA. Please handle the information based on Non-Disclosure Agreement.
 WRDISBV (5100h): Write Display Brightness
5100H WRDISBV
Address Parameter
Instructio R/W D
n MI Othe D7 D6 D5 D4 D3 D2 D1 D0
1
PI r
5100 -5 DBV[7:0]
WRDISBV W 51 h - D
h 5101 -D - - - - - - -
B
h 8 V
Descriptio This command is used to adjust brightness. [
n 8
Restrictio - ]
n
Status Default Value
5100h 00h
Power On Sequence
5101h 00h
Default
SW Reset The same as above
HW Reset The same as above

Flow
Chart

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permission of SeeYA. Please handle the information based on Non-Disclosure Agreement.
 SCACTRL (6900h): Scaling Up Control
6900H SCACTRL
Address Parameter
Instructio R/W D
n MI Othe D7 D6 D5 D4 D3 D2 D1 D0
1
PI r
SCACTRL R/W 69 6900 -5 - - - - - - D[1:0]
h h -
This command sets operation mode
D of MIPI clock lane during porch time.
Bit Symbol 8 Description Comment
0= off
Descriptio Scaling up ratio 1= 2x scaling up
D[1:0] SC_MOD_SEL
n selection 2=1.33x scaling up
3= reserved

Restrictio -
n
Status Default Value
Power On Sequence 6900h 00h
Default
SW Reset The same as above
HW Reset The same as above

Flow
Chart

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permission of SeeYA. Please handle the information based on Non-Disclosure Agreement.
 IFCONF (6B00h): Interface Configure
6900H IFCONFG
Address Parameter
Instructio R/W D
n MI Othe D7 D6 D5 D4 D3 D2 D1 D0
1
PI r
IFCONFG R/W 6B 6B00 -5 - - - D4 - - - -
h h -
PORT_1_2_SEL_CMD1: Set MIPI Port1
D or Port2 selection. XOR with PORT1_2_SEL (CMD2 page0 B102 D7).
Bit Symbol 8 Description Comment
PORT1_2_SEL_C MIPI 1 port or 2 port
D4 Refer to the table below
MD1 selection

Descriptio PORT_1_2_SEL_CMD1 (CMD1) PORT1_2_SEL (CMD2 p0) MIPI Port Selection

n 0h 0h 1-Port
0h 1h 2-Port
1h 0h 2-port
1h 1h 1-port

Restrictio -
n
Status Default Value
Power On Sequence 6B00h 10h
Default SW Reset The same as above
HW Reset The same as above
Flow
Chart

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permission of SeeYA. Please handle the information based on Non-Disclosure Agreement.
 RESCTRL1 (8000h): Resolution Control1
8000H RESCTRL1
Address Parameter
Instructio R/W D
n MI Othe D7 D6 D5 D4 D3 D2 D1 D0
1
PI r
8000 -5 - - - - - - - D0
h -
8001 - NC[7:0]
RESCTR R/W 80 D
h
8002 -8 NL[7:0]
L1 h
h
8003 - - - - NC[8 - - - NL[8
h to set panel type and display resolution.
This command is used ] ]

Bit Symbol Description Comment

D0 OSC_FREQ_SEL OSC frequency selection 0= 69.75MHz
1= 93MHz
Descriptio
n D[8:0] NC[8:0] X-axis resolution X-axis resolution= NC[8:0]*8

D[8:0] NL[8:0] Y-axis resolution Y-axis resolution= NL[8:0]*8

Restrictio Resolution switch is only valid in SLPIN mode.

n
Status Default Value
8000h 01h
8001h 40h
Power On Sequence 8002h 40h
Default
8003h 11h
SW Reset The same as above
HW Reset The same as above

Flow
Chart

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permission of SeeYA. Please handle the information based on Non-Disclosure Agreement.
12 Reliability

No. Item Condition Judgement Criterion

High Temperature
1 80℃ 240hrs
Storage

High Temperature
2 70℃ 240hrs
Operating

Low Temperature
3 -40℃ 240hrs
After testing
Storage
1.No clearly visible defects or remarkable deterioration
Low Temperature
4 -20℃ 240hrs of display quality.
Operating
2.No function-related abnormalities
High Temperature
5 60℃/90%RH 240hrs *The results must be checked after 2hours later under
/ Humidity Storage room temperature

High Temperature
6 60℃/90%RH 240hrs
/ Humidity Operating

-30℃ ←→ 80℃, 0.5hr,

7 Thermal Shock Change time <1min,
100cycles

After testing
Air discharge ±2kv 1.Hard defect should not happen
8 ESD
Contact discharge ±1kv 2.If it would be recovered to normal state after
resetting, it would be judged as a good state.

Attachment is the exclusive property of SeeYA and shall not be reproduced or copied or transformed to any other format without prior
permission of SeeYA. Please handle the information based on Non-Disclosure Agreement.
13 Handling Precautions
13.1 Mounting Method
This Micro-OLED product consists of one silicon backplane and one cover glass, which can easily get damaged.
Extreme care should be used when handling the MICRO-OLED.

13.2 Caution of Against Static Charge

For this Micro-OLED, use C-MOS drivers, do not input and signals before power is turned on, and ground your body,
work/assembly areas, assembly equipment to protect against static electricity. It could occur static electricity when
taping off the film which protects Micro-OLED. Against static charge, you should make sure that the product is safe
or not by experiment in advance.

13.3 Packing
The packing principle is that Micro-OLED module should keep its packing condition at the time of delivery. For safety
& avoiding the module damage, Carton box must stack the below 4 boxes.

When storing the Micro-OLED after unpacking, note the followings. Micro-OLED module is consisted of GLASS and
assemblies. It should avoid pressure, strong impact, and being dropped from a height.

To prevent modules from degradation, do not operate or store them in a place where they are directly exposed to
sunlight or high temperature/humidity.

13.4 Caution for Operation

If you do not follow normal POWER ON, OFF sequence or abnormal operating, then Micro-OLED module can be
damaged electro-optically and does not recover. Do not change software without SeeYA confirmation.

Micro-OLED module may not display normally when twisting power or pressing power is added. Therefore, you
should secure Micro-OLED module maximum thickness at set assembly not to have any pressure affect Micro-OLED
module.

Electro-chemical reaction may occur when there is humidity on pad, therefore, you should use MICRO-OLED Module
below maximum operating humidity.

Micro-OLED may not display normally when it is interfered by surrounding elements, therefore you should consider
setting design not to damage Micro-OLED module by surrounding elements.

To satisfy EMI standards, you should plan your design after considering emitting energy. We can’t guarantee display
characteristics outside viewing area, therefore your set window should be fixed into viewing area. Image-sticking
may occur if Micro-OLED displays same image for a long time, so you need to make a change for Micro-OLED.

13.5 Storage
Place in a dark place where neither exposure to direct sunlight or any fluorescent light is permitted and keep at room
temperature & room humidity. Store with no contact with polarizer surface. It is recommended to store them as they
have been contained in the inner container when we delivered them.

Attachment is the exclusive property of SeeYA and shall not be reproduced or copied or transformed to any other format without prior
permission of SeeYA. Please handle the information based on Non-Disclosure Agreement.
13.6 Safety Precautions
Disassembly or modification may cause electric shock, damages to sensitive part inside of the AMICRO-OLED module,
dust adhesion, or scratches on the display part. In the event that the contents of AMICRO-OLED module are on skin,
wipe them with a paper towel or gauge and wash the part well, and receive medical attention if necessary. Do not
use the AMICRO-OLED module for the special purpose besides display units. Be careful of the glass chips that may
cause injury to fingers of skin, when the display part is broken. For keeping safe quality from outer exposure or
contamination, modules should be consumed within 2 months after unpacking.

13.7 Precautions before use

You should discuss the following case with SeeYA:

➢ in case of any questions about contents of this "Specification for Approval".

➢ in case of occurring new problems not mentioned at this "Specification for Approval".
➢ in case of your request about income inspection specification change.
➢ in case of occurring new problem at your driving test.

*If SeeYA has to change the conditions specified in the specification, previously shall be held and decided.

Attachment is the exclusive property of SeeYA and shall not be reproduced or copied or transformed to any other format without prior
permission of SeeYA. Please handle the information based on Non-Disclosure Agreement.
14 Warranty

Basically, warranty term is 12 months of reliability characteristics of quality level after the outgoing date in SeeYA, could
compensate for defectives which happens within warranty term under condition that the products should be stored or be used
as specified under normal condition within the contents of specification.

Otherwise, it is impossible to compensate for defectives when they happen by customer's mistake such as careless handing or
circuit change, etc.

Attachment is the exclusive property of SeeYA and shall not be reproduced or copied or transformed to any other format without prior
permission of SeeYA. Please handle the information based on Non-Disclosure Agreement.
15 Packing

Adhesive Tape

a bag of desiccant

Put it into
Vacuum Bag

E
EP

E
EP

Attachment is the exclusive property of SeeYA and shall not be reproduced or copied or transformed to any other format without prior
permission of SeeYA. Please handle the information based on Non-Disclosure Agreement.