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COA LAB-pages

The document outlines a series of experiments focused on logic gates, Boolean functions, adders, subtractors, and multiplexers/demultiplexers. Each experiment includes an aim, learning objectives, required components, theoretical background, procedures, and viva questions. The experiments aim to deepen understanding of digital logic design and the practical application of various integrated circuits.

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0% found this document useful (0 votes)
16 views21 pages

COA LAB-pages

The document outlines a series of experiments focused on logic gates, Boolean functions, adders, subtractors, and multiplexers/demultiplexers. Each experiment includes an aim, learning objectives, required components, theoretical background, procedures, and viva questions. The experiments aim to deepen understanding of digital logic design and the practical application of various integrated circuits.

Uploaded by

gbdarkfreak7
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EXPERIMENT: 1 LOGIC GATES

AIM: To study and verify the truth table of logic gates

LEARNING OBJECTIVE:
 Identify various ICs and their specification.

COMPONENTS REQUIRED:
 Logic gates (IC) trainer kit.
 Connecting patch chords.
 IC 7400, IC 7408, IC 7432, IC 7406, IC 7402, IC 7404, IC 7486

THEORY:
The basic logic gates are the building blocks of more complex logic circuits. These logic
gates perform the basic Boolean functions, such as AND, OR, NAND, NOR, Inversion,
Exclusive-OR, Exclusive-NOR. Fig. below shows the circuit symbol, Boolean function,
and truth. It is seen from the Fig that each gate has one or two binary inputs, A and B, and
one binary output, C. The small circle on the output of the circuit symbols designates the
logic complement. The AND, OR, NAND, and NOR gates can be extended to have more
than two inputs. A gate can be extended to have multiple inputs if the binary operation it
represents is commutative and associative.

These basic logic gates are implemented as small-scale integrated circuits (SSICs) or as part
of more complex medium scale (MSI) or very large-scale (VLSI) integrated circuits. Digital
IC gates are classified not only by their logic operation, but also the specific logic-circuit
family to which they belong. Each logic family has its own basic electronic circuit upon
which more complex digital circuits and functions are developed. The following logic
families are the most frequently used.

TTL Transistor-transistor logic


ECL Emitter-coupled logic
MOS Metal-oxide semiconductor
CMOS Complementary metal-oxide semiconductor

TTL and ECL are based upon bipolar transistors. TTL has a well established popularity among
logic families. ECL is used only in systems requiring high-speed operation. MOS and CMOS,
are based on field effect transistors. They are widely used in large scale integrated circuits
because of their high component density and relatively low power consumption. CMOS logic
consumes far less power than MOS logic. There are various commercial
Logic Design Laboratory Manual 2

integrated circuit chips available. TTL ICs are usually distinguished by numerical
designation as the 5400 and 7400 series.

PROCEDURE:
1. Check the components for their working.
2. Insert the appropriate IC into the IC base.
3. Make connections as shown in the circuit diagram.
4. Provide the input data via the input switches and observe the output on output LEDs
Logic Design Laboratory Manual 3

VIVA QUESTIONS:

1. Why NAND & NOR gates are called universal gates?


2. Realize the EX – OR gates using minimum number of NAND gates.
3. Give the truth table for EX-NOR and realize using NAND gates?
4. What are the logic low and High levels of TTL IC’s and CMOS IC’s?
5. Compare TTL logic family with CMOS family?
6. Which logic family is fastest and which has low power dissipation?

EXPERIMENT: 2 REALIZATION OF A BOOLEAN FUNCTION.

AIM: To simplify the given expression and to realize it using Basic gates
and Universal gates

LEARNING OBJECTIVE:
To simplify the Boolean expression and to build the logic circuit.
Given a Truth table to derive the Boolean expressions and build the logic circuit
to realize it.

COMPONENTS REQUIRED:
IC 7400, IC 7408, IC 7432, IC 7406, IC 7402, Patch Cords & IC Trainer Kit.

THEORY:
Canonical Forms (Normal Forms): Any Boolean function can be written in disjunctive
normal form (sum of min-terms) or conjunctive normal form (product of max-terms).
A Boolean function can be represented by a Karnaugh map in which each cell corresponds
to a minterm. The cells are arranged in such a way that any two immediately adjacent cells
correspond to two minterms of distance 1. There is more than one way to construct a map
with this property.
Karnaugh Maps

For a function of two variables, say, f(x, y),

For a function of three variables, say, f(x, y, z)

For a function of four variables: f(w, x, y, z)


Logic Design Laboratory Manual 5

2) For the given Truth Table, realize a logical circuit using basic gates and NAND gates

Inputs Output
A B C D Y
0 0 0 0 1
0 0 0 1 1
0 0 1 0 0
0 0 1 1 0
0 1 0 0 1
0 1 0 1 1
0 1 1 0 0
0 1 1 1 0
1 0 0 0 0
1 0 0 1 0
1 0 1 0 0
1 0 1 1 0
1 1 0 0 0
1 1 0 1 1
1 1 1 0 0
1 1 1 1 1

PROCEDURE:
Check the components for their working.
Insert the appropriate IC into the IC base.
Make connections as shown in the circuit diagram.
Provide the input data via the input switches and observe the output on output
LEDs Verify the Truth Table

RESULT: Simplified and verified the Boolean function using basic gates and universal gates

VIVA QUESTIONS:
1) What are the different methods to obtain minimal expression?
2) What is a Min term and Max term
3) State the difference between SOP and POS.
EXPERIMENT: 3 ADDERS AND SUBTRACTORS

AIM: To realize
i) Half Adder and Full Adder
ii) Half Subtractor and Full Subtractor by using Basic gates and NAND gates

LEARNING OBJECTIVE:
To realize the adder and subtractor circuits using basic gates and universal
gates To realize full adder using two half adders
To realize a full subtractor using two half subtractors

COMPONENTS REQUIRED:
IC 7400, IC 7408, IC 7486, IC 7432, Patch Cords & IC Trainer Kit.

THEORY:
Half-Adder: A combinational logic circuit that performs the addition of two data bits, A and
B, is called a half-adder. Addition will result in two output bits; one of which is the sum bit, S,
and the other is the carry bit, C. The Boolean functions describing the half-adder are:
S =A ⊕ B C=AB

Full-Adder: The half-adder does not take the carry bit from its previous stage into account.
This carry bit from its previous stage is called carry-in bit. A combinational logic circuit that
adds two data bits, A and B, and a carry-in bit, Cin , is called a full-adder. The Boolean
functions describing the full-adder are:
S = (x ⊕ y) ⊕ Cin C = xy + Cin (x ⊕ y)

Half Subtractor: Subtracting a single-bit binary value B from another A (i.e. A -B ) produces a
difference bit D and a borrow out bit B-out. This operation is called half subtraction and the
circuit to realize it is called a half subtractor. The Boolean functions describing the half-
Subtractor are:
S =A ⊕ B C = A’ B

Full Subtractor: Subtracting two single-bit binary values, B, Cin from a single-bit value A
produces a difference bit D and a borrow out Br bit. This is called full subtraction. The
Boolean functions describing the full-subtracter are:
D = (x ⊕ y) ⊕ Cin Br= A’B + A’(Cin) + B(Cin)
Logic Design Laboratory Manual 10

ii) To Realize the Full subtractor using NAND Gates only

PROCEDURE:
 Check the components for their working.
 Insert the appropriate IC into the IC base.
 Make connections as shown in the circuit diagram.
 Verify the Truth Table and observe the outputs. RESULT:

The truth table of the above circuits is verified. VIVA

QUESTIONS:

1) What is a half adder?


2) What is a full adder?
3) What are the applications of adders?
4) What is a half subtractor?
5) What is a full subtractor?
6) What are the applications of subtractors?
7) Obtain the minimal expression for above circuits.
8) Realize a full adder using two half adders
9) Realize a full subtractors using two half subtractors
EXPERIMENT: 4 PARALLEL ADDER AND SUBTRACTOR

AIM: To design and set up the following circuit using IC 7483.


i) A 4-bit binary parallel adder.
ii) A 4-bit binary parallel subtractor.

LEARNING OBJECTIVE:
To learn about IC 7483 and its internal structure.
To realize a subtractor using adder IC 7483

COMPONENTS REQUIRED:
IC 7483, IC 7486, Patch Cords & IC Trainer Kit.

THEORY:
The Full adder can add single-digit binary numbers and carries. The largest sum that can be
obtained using a full adder is 112. Parallel adders can add multiple-digit numbers. If full adders
are placed in parallel, we can add two- or four-digit numbers or any other size desired. Figure
below uses STANDARD SYMBOLS to show a parallel adder capable of adding two, two-digit
binary numbers The addend would be on A inputs, and the augend on the B inputs. For this
explanation we will assume there is no input to C0 (carry from a previous circuit)

To add 102 (addend) and 012 (augend), the addend inputs will be 1 on A2 and 0 on A1. The
augend inputs will be 0 on B2 and 1 on B1. Working from right to left, as we do in normal
addition, let’s calculate the outputs of each full adder. With A1 at 0 and B1 at 1, the output of
adder1 will be a sum (S1) of 1 with no carry (C1). Since A2 is 1 and B2 is 0, we have a sum
(S2) of 1 with no carry (C2) from adder1. To determine the sum, read the outputs (C2, S2, and
S1) from left to right. In this case, C2 = 0, S2 = 1, and S1 = 1. The sum, then, of 10 2 and 012
Logic Design Laboratory Manual 12

is 0112. To add four bits we require four full adders arranged in parallel. IC 7483 is a 4- bit
parallel adder whose pin diagram is shown.

MSB LSB
Cin
INPUTS A3 A2 A1 A0
3 2 1 0

OUTPUT Cout S3 S2 S1 S0

IC 7483 pin diagram

i) 4-Bit Binary Adder

An Example: 7+2=11 (1001)

 7 is realized at A3 A2 A1 A0 = 0111
 2 is realized at B3 B2 B1 B0 = 0010
Sum = 1001

ADDER CIRCUIT:
Logic Design Laboratory Manual 13

PROCEDURE:
 Check all the components for their working.
 Insert the appropriate IC into the IC base.
 Make connections as shown in the circuit diagram.
 Apply augend and addend bits on A and B and cin=0.
 Verify the results and observe the outputs.
i) 4-BIT BINARY SUBTRACTOR.
Subtraction is carried out by adding 2’s complement of the subtrahend.
Example: 8 – 3 = 5 (0101)

 8 is realized at A3 A2 A1 A0 = 1000
 3 is realized at B3 B2 B1 B0 through X-OR gates = 0011
 Output of X-OR gate is 1’s complement of 3 = 1100
 2’s Complement can be obtained by adding Cin =1

Therefore
Cin = 1
A3 A2 A1 A0 = 1 0 0 0
B 3 B2 B1 B0 = 1 1 0 0
S3 S2 S1 S0 = 0 1 0 1
Cout = 1 (Ignored)
Logic Design Laboratory Manual 14

PROCEDURE:
 Check all the components for their working.
 Insert the appropriate IC into the IC base.
 Make connections as shown in the circuit diagram.
 Apply Minuend and subtrahend bits on A and B and cin=1.
 Verify the results and observe the outputs.

RESULTS: Verified the working of IC 7483 as adder and subtractor.


BCD adder using two 7483 IC chip

• A BCD adder adds two BCD digits and produces output as a BCD digit. A BCD or
Binary Coded Decimal digit cannot be greater than 9.
• The two BCD digits are to be added using the rules of binary addition. If sum is less than
or equal to 9 and carry is 0, then no correction is needed. The sum is correct and in true
BCD form.
• But if sum is greater than 9 or carry =1, the result is wrong and correction must be done.
The wrong result can be corrected adding six (0110) to it.
• For implementing a BCD adder using a binary adder circuit IC 7483, additional
combinational circuit will be required, where the Sum output S3−S0

• is checked for invalid values from 10 to 15. The truth table and K-map for the same is as
shown:
• • The BCD adder is shown below. The output of the combinational circuit should be 1 if Cout
of adder-1 is high. Therefore Y is ORed with Cout of adder 1.

• The output of combinational circuit is connected to B1B2 inputs of adder-2 and B3=B1+0

as they are connected to ground permanently. This makes B3B2B1B0

• = 0110 if Y' = 1.

• The sum outputs of adder-1 are applied to A3A2A1A0

• of adder-2. The output of combinational circuit is to be used as final output carry and the
carry output of adder-2 is to be ignored.

Operations of: (011)BCD+(1001)BCD


Thus,

Cout = 1

S3S2S1S0=0000

Hence, for adder, inputs will be A3A2A1A0=0000

and B3B2B1B0=0110

This will give final output as Cout S3S2S1S0=10110

Therefore, (0111)BCD+(1001)BCD

= (00010110)BCD
EXPERIMENT: 7 MULTIPLEXER AND DEMULTIPLEXER

AIM: To design and set up the following circuit


1) To design and set up a 4:1 Multiplexer (MUX) using only NAND gates.
2) To design and set up a 1:4 Demultiplexer(DE-MUX) using only NAND gates.
3) To verify the various functions of IC 74153(MUX) and IC 74139(DEMUX).
4) To set up a Half/Full Adder and Half/Full Subtractor using IC 74153.

LEARNING OBJECTIVE:
To learn about various applications of multiplexer and de-multiplexer
To learn and understand the working of IC 74153 and IC 74139
To learn to realize any function using Multiplexer

THEORY:
Multiplexers are very useful components in digital systems. They transfer a large number of
information units over a smaller number of channels, (usually one channel) under the
control of selection signals. Multiplexer means many to one. A multiplexer is a circuit with
many inputs but only one output. By using control signals (select lines) we can select any
input to the output. Multiplexer is also called as data selector because the outputn bit
depends on the input data bit that is selected. The general multiplexer circuit has 2 input
signals, n control/select signals and 1 output signal.
De-multiplexers perform the opposite function of multiplexers. They transfer a small
number of information units (usually one unit) over a larger number of channels under the
control of selection signals.n The general de-multiplexer circuit has 1 input signal, n
control/select signals and 2 output signals. De-multiplexer circuit can also be realized
using a decoder circuit with enable.

COMPONENTS REQUIRED:
IC 7400, IC 7410, IC 7420, IC 7404, IC 74153, IC 74139, Patch Cords & IC Trainer Kit.

i) 4:1 MULTIPLEXER

4:1
Inputs MUX
Y

E’
Select
inputs
Output Y= E’S1’S0’I0 + E’S1’S0I1 + E’S1S0’I2 + E’S1S0I3
Logic Design Laboratory Manual 26

FULL SUBTRACTOR USING MUX:

DESIGN:
DIFFERENCE BORROW
I0 I1 I2 I3 I0 I1 I2 I3
0 1 2 3 0 1 2 3
4 5 6 7 4 5 6 7
A A’ A’ A 0 A’ A’ 1
TRUTH TABLE
Inputs Outputs
A B C D Br
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

PROCEDURE:
 Check all the components for their working.
 Insert the appropriate IC into the IC base.
 Make connections as shown in the circuit diagram.
 Verify the Truth Table and observe the outputs.

RESULT: Adder and subtractor circuits are realized using multiplexer IC 74153.

VIVA QUESTIONS:

1) What is a multiplexer?
2) What is a de-multiplexer?
3) What are the applications of multiplexer and de-multiplexer?
4) Derive the Boolean expression for multiplexer and de-multiplexer.
5) How do you realize a given function using multiplexer
6) What is the difference between multiplexer & demultiplexer?
EXPERIMENT: 9 DECODERS

AIM: To realize a decoder circuit using basic gates and to verify IC 74LS139

LEARNING OBJECTIVE:
To learn about working principle of decoder
To learn and understand the working of IC 74LS139
To realize using basic gates as well as universal gates

COMPONENTS REQUIRED:
IC74LS139, IC 7400, IC 7408, IC 7432, IC 7404, IC 7410, Patch chords, & IC Trainer Kit

THEORY:

A decoder is a combinational circuit that connects the binary information from ‘n’ input lines to
n
a maximum of 2 unique output lines. Decoder is also called a min-term generator/max-term
generator. A min-term generator is constructed using AND and NOT gates. The appropriate
output is indicated by logic 1 (positive logic). Max-term generator is constructed using NAND
gates. The appropriate output is indicated by logic 0 (Negative logic).
The IC 74139 accepts two binary inputs and when enable provides 4 individual active low
outputs. The device has 2 enable inputs (Two active low).

CIRCUIT DIAGRAM:

2:4 DECODER (MIN TERM GENERATOR):

TRUTH TABLE:

INPUT OUTPUT
A B Y0 Y1 Y2 Y3
0 0 1 0 0 0
0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 0 0 1

BOOLAEN EXPRESSIONS:
Y 0 = AB
Y1 = AB
Y 2 = AB
Y 3 = AB
PROCEDURE:
1. Make the connections as per the circuit diagram.
2. Change the values of G1, G2A, G2B, A, B, and C, using switches.
3. Observe status of Y0, to Y7 on LED’s.
4. Verify the truth table.

RESULT: Verified the Operation of 3 to 8 Decoder

VIVA QUESTIONS:
1. What are the applications of decoder?
2. What is nthe difference between decoder & encoder?
3. For n- 2 decoder how many i/p lines & how many o/p lines?
4. What are the different codes & their applications?
5. What are code converters?
6. Using 3:8 decoder and associated logic, implement a full adder?
7. Implement a full subtractor using IC 74138?
8. What is the difference between decoder and de-mux?
EXPERIMENT: 10 BCD TO 7-SEGMENT DECODER/DRIVER

AIM: To set up and test a 7-segment static display system to display numbers 0 to 9.

LEARNING OBJECTIVE:
To learn about various applications of decoder
To learn and understand the working of IC 7447
To learn about types of seven-segment display

COMPONENTS REQUIRED:
IC7447, 7-Segment display (common anode), Patch chords, resistor (1K ) & IC Trainer Kit

THEORY:

The Light Emitting Diode (LED) finds its place in many applications in these modern electronic
fields. One of them is the Seven Segment Display. Seven-segment displays contains the
arrangement of the LEDs in “Eight” (8) passion, and a Dot (.) with a common electrode, lead
(Anode or Cathode). The purpose of arranging it in that passion is that we can make any
number out of that by switching ON and OFF the particular LED's. Here is the block diagram of
the Seven Segment LED arrangement.

The Light Emitting Diode (LED), finds its place in many applications in this modern electronic
fields. One of them is the Seven Segment Display. Seven-segment displays contains the
arrangement of the LEDs in “Eight” (8) passion, and a Dot (.) with a common electrode, lead
(Anode or Cathode). The purpose of arranging it in that passion is that we can make any
number out of that by switching ON and OFF the particular LED's. Here is the block diagram of
the Seven Segment LED arrangement.

LED‟s are basically of two types-


Common Cathode (CC) -All the 8 anode legs uses only one cathode, which is common.
Common Anode (CA)-The common leg for all the cathode is of Anode type.

A decoder is a combinational circuit that connects the binary information from „n‟ input lines
n
to a maximum of 2 unique output lines. The IC7447 is a BCD to 7-segment pattern converter.
The IC7447 takes the Binary Coded Decimal (BCD) as the input and outputs the relevant 7
segment code.
Logic Design Laboratory Manual 35

CIRCUIT DIAGRAM:

TRUTH TABLE:

Decimal
BCD Inputs Output Logic Levels from IC 7447 to 7-segments number
display
D C B A a b c d e f g
0 0 0 0 0 0 0 0 0 0 1 0
0 0 0 1 1 0 0 1 1 1 1 1
0 0 1 0 0 0 1 0 0 1 0 2
0 0 1 1 0 0 0 0 1 1 0 3
0 1 0 0 1 0 0 1 1 0 0 4
0 1 0 1 0 1 0 0 1 0 0 5
0 1 1 0 1 1 0 0 0 0 0 6
0 1 1 1 0 0 0 1 1 1 1 7
1 0 0 0 0 0 0 0 0 0 0 8
1 0 0 1 0 0 0 1 1 0 0 9

PROCEDURE:
 Check all the components for their working.
 Insert the appropriate IC into the IC base.
 Make connections as shown in the circuit diagram.
 Verify the Truth Table and observe the outputs.

VIVA QUESTIONS:
1. What are the different types of LEDs?
2. Draw the internal circuit diagram of an LED.
3. What are the applications of LEDs?
Logic Design Laboratory Manual 36

EXPERIMENT: 11 ENCODERS

AIM:
1. To set up a circuit of Decimal-to-BCD Encoder using IC 74147.
2. To design and set up a circuit of Hexadecimal-to-Binary Encoder using IC
3. 74148 Encoders and IC 74157 Multiplexer

LEARNING OBJECTIVE:
To learn about various applications of Encoders
To learn and understand the working of IC 74147 , IC 74148 & IC 74157
To learn to do code conversion using encoders

COMPONENTS REQUIRED:
IC 74147, IC 74148, IC 74157, Patch chords & IC Trainer Kit

THEORY:
An encoder performs a function that is the opposite of decoder. It receives one or more signals
in an encoded format and output a code that can be processed by another logic circuit. One of
the advantages of encoding data, or more often data addresses in computers, is that it reduces
the number of required bits to represent data or addresses. For example, if a memory has 16
different locations, in order to access these 16 different locations, 16 lines (bits) are required if
the addressing signals are in 1 out of n format. However, if we code the 16 different addresses

into a binary format, then only 4 lines (bits) are required. Such a reduction improves the speed
of information processing in digital systems.

CIRCUIT DIAGRAM:

1) DECIMAL-TO BCD ENCODER USING IC 74147.


TRUTH TABLE
INPUTS OUTPUTS
I1 I2 I3 I4 I5 I6 I7 I8 I9 A3 A2 A1 A0
1 1 1 1 1 1 1 1 0 0 1 1 0
X X X X X X X 0 1 0 1 1 1
X X X X X X 0 1 1 1 0 0 0
X X X X X 0 1 1 1 1 0 0 1
X X X X 0 1 1 1 1 1 0 1 0
X X X 0 1 1 1 1 1 1 0 1 1
X X 0 1 1 1 1 1 1 1 1 0 0
X 0 1 1 1 1 1 1 1 1 1 0 1
0 1 1 1 1 1 1 1 1 1 1 1 0
1 1 1 1 1 1 1 1 1 1 1 1 1
Logic Design Laboratory Manual 38

TRUTH TABLE

INPUTS OUTPUTS
I0 I1 I2 I3 I4 I5 I6 I7 I8 I9 I10 I11 I12 I13 I14 I15 Y3 Y2 Y1 Y0
1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 0 0 0
1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 0 0 1
1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 0 1 0
1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1
1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0
1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1
1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0
0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0
1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 0 0 1
1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 0 0 1 0
1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 0 0 1 1
1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 0 1 0 0
1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 0 1 0 1
1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 0 1 1 0
1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 0 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PROCEDURE:
 Check all the components for their working.
 Insert the appropriate IC into the IC base.
 Make connections as shown in the circuit diagram.
 Verify the Truth Table and observe the outputs.

VIVA QUESTIONS:
1. What is a priority encoder?
2. What is the role of an encoder in communication?
3. What is the advantage of using an encoder?
4. What are the uses of validating outputs?

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